Apparatus, system, and method for frequency-dependent signal modulation

Abstract

The present application relates to apparatuses, systems, and methods for frequency dependent signal modulation. Apparatuses, systems, and methods for high pass filter pre-emphasis circuitry. A device can provide a multi-level signal based on a plurality of binary signals using a pre-emphasis driver. The pre-emphasis driver includes a main driver coupled in parallel with at least one equalizer path, each equalizer path including an equalizer driver and a filter element. The filter element can be an AC filter element, such as a capacitor. The equalizer path can contribute an equalized signal having a high pass filter behavior. The pre-emphasis circuitry can combine a main signal from the main driver and the equalized signal to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver can be a pulse amplitude modulation (PAM) driver, such as a PAM4 driver of a multi-level driver having four levels.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more particularly to apparatus, systems and methods for frequency-dependent signal modulation in electronic devices. Background Technology

[0002] Electronic devices can be coupled together and can transmit data back and forth along the physical channel that couples them. The amount of data inside some electronic devices may be greater than the amount of data inside the physical channel. To increase the bandwidth and transmission speed along the channel, internal binary signals can be combined to form a multi-level signal provided along the channel. For example, a multi-level signal can have different levels representing each possible state of different binary signals (e.g., 2^N levels of N binary signals).

[0003] The level of a multi-bit signal can be represented by voltage, where a first voltage represents a first level, a second voltage represents a second level, and so on. When a multi-level signal changes level, the voltage of the conductive element may need to change rapidly between different levels. However, when the level of a multi-bit signal changes over time, the driver may find it difficult to rapidly change the voltage level along the conductive element. Summary of the Invention

[0004] One aspect of this disclosure provides an apparatus comprising: a main drive circuit configured to receive a plurality of binary signals and provide a first multi-level signal; an equalizer path including an equalizer driver and a capacitor, wherein the equalizer path is configured to receive the plurality of binary signals and provide a second multi-level signal; and a summing node configured to combine the first multi-level signal and the second multi-level signal into an output multi-level signal.

[0005] Another aspect of this disclosure provides an apparatus comprising: a main drive circuit configured to receive a plurality of binary signals and provide a main multilevel signal; a plurality of selectable equalizer paths, each of the plurality of selectable equalizer paths including an equalizer driver and a high-pass filter, wherein a selected equalizer path among the plurality of equalizer paths is configured to receive the plurality of binary signals and provide a filtered multilevel signal; and a summing node configured to provide an equalized output multilevel signal based on the main multilevel signal and the filtered multilevel signal.

[0006] Another aspect of this disclosure provides a system comprising: a first device including a pre-emphasis driver configured to provide a multi-level signal based on a plurality of binary signals of the first device; and a second device configured to receive the multi-level signal, wherein the pre-emphasis driver includes: a main drive circuit configured to receive the plurality of binary signals and provide a first multi-level signal; an equalizer path including an equalizer driver and a capacitor, wherein the equalizer path is configured to receive the plurality of binary signals and provide a second multi-level signal; and a summing node configured to combine the first multi-level signal and the second multi-level signal into an output multi-level signal. Attached Figure Description

[0007] Figure 1 This is a block diagram of an apparatus according to an embodiment of the present disclosure.

[0008] Figure 2 This is a block diagram of an apparatus for a multilevel communication architecture according to embodiments of the present disclosure.

[0009] Figure 3 This is a schematic diagram of a pre-emphasis driver according to some embodiments of the present disclosure.

[0010] Figure 4 This is a diagram illustrating exemplary operation of a pre-emphasis driver according to some embodiments of this disclosure.

[0011] Figure 5 This is a schematic diagram of a pre-emphasis driver according to some embodiments of the present disclosure.

[0012] Figure 6 This is a graph showing the transfer function of a pre-emphasis driver based on different capacitor values ​​according to some embodiments of this disclosure.

[0013] Figure 7A C is a set of graphs illustrating exemplary effects of increasing the number of activation balancing paths according to some embodiments of this disclosure. Detailed Implementation

[0014] The following description of certain embodiments is merely exemplary in nature and is not intended to limit the scope of this disclosure or its application or use in any way. In the following detailed description of embodiments of the systems and methods, reference is made to the accompanying drawings, which form part of the invention, and illustrate specific embodiments of the described systems and methods by way of illustration. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the systems and methods currently disclosed, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be discussed where they are obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of this disclosure is defined only by the appended claims.

[0015] Semiconductor devices (such as memory devices) may require conversion between binary and multilevel signals. For example, in the case of two coupled devices, the number of connections between the two devices may be limited, but each device may use a greater number of signals internally. To alleviate the bottleneck represented by a limited number of inter-device connections, some internal binary signals can be combined to form a multilevel signal, which is then provided through the inter-device connections. The receiving device can then decode the multilevel signal back into different binary signals. The driving circuitry on the transmitting device can generate voltages along the connections based on the received internal binary signals. Since various internal binary signals can change states rapidly, it can be useful for the driving circuitry that generates the multilevel signal to be able to quickly switch between different levels of the multilevel signal.

[0016] Various driving techniques can be used to control the levels of multilevel signals. For example, a pre-emphasis driver can be placed within the transmitter of a multilevel signal. A pre-emphasis driver can amplify certain characteristics of the signal to maintain rapid signal transitions. However, it may be difficult to rapidly change the voltage of a multilevel signal (e.g., between levels) because the driver may have limited bandwidth to produce rapid changes in the associated voltage.

[0017] This disclosure relates to apparatus, systems, and methods for frequency-dependent signal modulation. Frequency-dependent signal modulation can be used as part of a pre-emphasis driver. The pre-emphasis driver may include a master driver, an equalizer path, and a summing node. The master driver may receive multiple binary signals and provide a multi-level signal to the summing node. The equalizer path may include a secondary driver (e.g., an equalizer driver) that also receives binary signals along with the master driver and may provide a multi-level signal. The equalizer path may have frequency-dependent behavior. For example, the equalizer path may include filtering elements. Filtering elements may be AC ​​circuit components, such as capacitors. The equalizer path may provide a frequency-modulated multi-level signal to the summing node, which in turn may add the master multi-level signal and the frequency-modulated multi-level signal to provide a composite multi-level signal at the output. In some embodiments, the frequency dependence of the equalizer path may take the form of high-pass filtering behavior. For example, the equalizer path may include a high-pass filtering element, such as a capacitor, and the frequency-modulated signal provided by the equalizer path may be a high-pass filtered signal.

[0018] In summary, when the equalizer path is active, the pre-emphasis driver can provide frequency modulation behavior (e.g., high-pass filtering behavior). The pre-emphasis driver of this disclosure can provide advantages such as continuous-time performance (e.g., due to the AC characteristics of the frequency modulation component), minimal sensitivity to process, voltage, and temperature (PVT) variations, relatively high signal swing (e.g., compared to deemphasis methods), and / or relatively low power and layout size compared to other methods (e.g., by using lower-power sub-drivers and / or capacitors as filtering elements).

[0019] In some embodiments, the pre-emphasis driver may include multiple equalizer paths. For example, the equalizer paths may be coupled in parallel with the main driver. Each of the multiple equalizer paths may provide a frequency-modulated (e.g., filtered) multilevel signal to the summing node. In some embodiments, the multiple equalizer paths are selectable, and the device may include one or more settings that determine how many equalizer paths are active. Increasing the number of active equalizer paths can provide enhanced equalization at the cost of increased power consumption. For example, enhanced equalization can provide improved high-frequency response, which can reduce inter-symbol interference (ISI).

[0020] Figure 1This is a block diagram of an apparatus according to embodiments of the present disclosure. Apparatus 100 may include a first device 110 communicating with a second device 120 via an input / output (I / O) bus. The first device 110 may include I / O interface circuitry 112, which includes a signal driver 114 for communication via the I / O bus and a receiver and decoder circuitry 116. The second device 120 may include I / O interface circuitry 122, which includes a signal driver 124 for communication via the I / O bus and a receiver and decoder circuitry 126. The I / O bus may support a multi-level communication architecture including multiple channels. In some embodiments, each channel may be single-ended and may include a single signal line. In other embodiments, each channel may include more than one signal line. In one embodiment, the first device 110, the second device 120, and the I / O bus may support a channel including the conversion of M binary signals into N multi-level signals, where M is greater than N.

[0021] In some embodiments, binary signals can be organized into one or more bit streams. A bit stream comprises a plurality of bits provided serially, wherein each bit of the bit stream is provided at a time interval, which may be referred to as a data interval. For example, a first bit is provided for a first interval, a second bit is provided for a second interval following the first interval, a third bit is provided for a third interval following the second interval, and so on. Successive bits provided in this serial manner represent a bit stream. The corresponding bit of each bit stream within a data interval represents M-bit wide data. In some embodiments, binary signals can be provided in parallel with each other and can be received simultaneously at I / O interface circuitry 112. For example, a first bit can be received along a first conductive element during a data interval, and a second bit can be received along a second conductive element during the same data interval. In some embodiments, a combination of serial and parallel transmission can be used.

[0022] Multilevel signals can have one of three or more voltage levels (unlike binary signals, which can have one of two voltage levels to represent a data value), where the voltage levels of a multilevel signal represent data values. These N multilevel signals can be transmitted via an I / O bus. Each multilevel signal is provided within a data interval having a voltage corresponding to one of multiple voltage levels (e.g., 2 different voltage levels, 4 different voltage levels, 8 different voltage levels, etc.), where each of the multiple voltage levels represents a different data value. In one example, three binary signals can be converted into two three-level signals. In another example, pulse amplitude modulation (PAM) can be used to convert two, three, or four bit streams into a single multilevel signal with 4 levels, 8 levels, 16 levels, etc.

[0023] For example, in a memory device with eight input / output (I / O) terminals, a total of 64 bits of data can be accessed (e.g., read or written) in column operations. That is, each of the eight I / O terminals can be provided with 8 bits of serialized data, resulting in a total of 64 bits of data (e.g., eight I / O terminals multiplied by 8 bits (serialized) per I / O terminal). In a memory device, since there are eight I / O terminals (not 64), a time-division multiplexing method using first-in-first-out (FIFO) circuit coupling is used to serialize a set of 8 bits of data. In embodiments of this disclosure, for example, where 2 bits are converted into multi-level signals (e.g., having one of four different voltage levels to represent a 2-bit value), eight serialized data can be converted into four serialized data, or eight I / O terminals can be reduced to four I / O terminals (where each of the four I / O terminals is provided with 8 bits of serialized data).

[0024] In some instances, the first device 110 may include a memory controller or processing system, and / or the second device 120 may include memory, including volatile memory and / or non-volatile memory. In some instances, the second device 120 may include dynamic random access memory (DRAM), such as dual data rate (DDR) DRAM or low-power DDR DRAM. However, it should be noted that memory is not an essential component of this disclosure. Rather, this disclosure can be applied to any two or more (on-chip or off-chip) devices communicating with each other using multi-level signaling.

[0025] Signal driver 114 may include circuitry for converting a set of M binary signals to generate N multilevel signals, and signal driver 114 may drive the N multilevel signals onto a channel of the I / O bus. Similarly, signal driver 124 may include circuitry for converting a set of M binary signals to generate N multilevel signals, and drive the N multilevel signals onto a channel of the I / O bus. Signal driver 114 (and / or 124) may act as a pre-emphasis driver to amplify (e.g., amplify) certain aspects of the multilevel signals along the I / O bus. For example, the rising and falling edges of the signal may become sharper (e.g., the signal may rise or fall faster). Signal driver 114 (and / or 124) may, for example, include one or more equalizer paths that can be selectively activated to give the pre-emphasis driver frequency modulation behavior, such as activating the characteristics of a high-pass filter. This, in turn, can help equalize the high-frequency aspects of the channel on the signal, such as when the channel prohibits multilevel signal changes between one level and another. In some embodiments, device 110 may include setting logic (not shown) to determine how many equalizer paths are active.

[0026] Driver 114 (and / or 124) can convert M binary signals into N multilevel signals using various techniques now known or developed hereafter. For example, in some embodiments of this disclosure, PAM4 technology can be used to convert two bits of data into a multilevel signal having one of four different voltage levels. In other embodiments of this disclosure, PAM8 technology can be used to convert three bits of data into a multilevel signal having one of eight different voltage levels. Other conversion techniques may also be used without departing from the scope of this disclosure.

[0027] For each channel, receiver and decoder circuit 116 may include a decoder configured to recover the set of M binary signals by decoding N multi-level signals received via the channel through the I / O bus provided by signal driver 124. Further, receiver and decoder circuit 126 may include a decoder configured to recover the set of M binary signals by decoding N multi-level signals received via the channel through the I / O bus provided by signal driver 114. In some embodiments, receiver and decoder circuits 116 and 126 may include comparators and decoding logic to recover the set of M binary signals.

[0028] In operation, the first device 110 and the second device 120 can communicate via an I / O bus to transmit information such as data, addresses, and commands. Although the I / O bus is shown as bidirectional, it can also be unidirectional. I / O interface circuits 112 and 122 can implement a multi-level communication architecture. In a multi-level communication architecture, data can be transmitted through the channel during data intervals. Data can include a single value on the signal lines of the channel, or it can be a combination of values ​​provided on multiple signal lines of the channel. Data can represent the channel state. The receiver can determine the output signal value based on the values ​​transmitted on the signal lines of the channel. In a single-ended architecture, the signal line value can be compared with one or more reference values ​​to determine the output signal value. The receiver determines and latches the output signal value based on the time interval from the time the output signal transitions to the current value to the time the output signal transitions to the next value. The transition time can be determined based on a clock signal, and the setup and hold time can be determined based on the transition from one value to another. In addition to mitigating frequency-dependent signal degradation imposed by the channel (e.g., ISI), inherent jitter can occur in multilevel communication architectures with fixed slew rates or fixed rise / fall times due to varying amplitude offsets. The amount of jitter can be based on the slew rate, rise / fall time, multilevel amplitude values, or combinations thereof. In some instances, the slew time may also be affected by variations in process technology, voltage, and temperature. Using pre-emphasis techniques and equalizer paths in signal drivers 114 (and / or 124) can help mitigate one or more of these effects.

[0029] In one example, signal driver 114 can generate data for a channel by converting bits from each of M binary signals into N multi-level signals during a data interval. The data can be transmitted to receiver and decoder circuitry 126 via N signal lines of the I / O bus. Receiver and decoder circuitry 126 can detect the levels on the N signal lines and decode the levels to retrieve bits from each of the M streams. More data can be transmitted during the data interval by using multi-level signal lines compared to using binary signal line levels. In one example, M is 2, N is 1, and the I / O bus signal lines can be driven to four independent voltage levels (e.g., in a PAM implementation such as a four-level signal PAM4). The communication protocol between signal driver 124 and receiver and decoder circuitry 116 can be similar to the communication protocol between signal driver 114 and receiver and decoder circuitry 126. Signal driver 114 may include a DRAM driver that has been segmented to drive multiple (e.g., more than two) voltage levels on the signal lines.

[0030] Figure 2 This is a block diagram of an apparatus for a multilevel communication architecture according to embodiments of the present disclosure. The apparatus may include a signal driver 214 coupled to a receiver 226 via an I / O bus. The signal driver 214 may be... Figure 1 The signal driver 114 and / or signal driver 124 are implemented, and the receiver 226 can be implemented in the signal driver 114 and / or signal driver 124. Figure 1 Implemented in receiver and decoder circuits 116 and / or receiver and decoder circuits 126.

[0031] The signal driver 214 may include a driving circuit 240. The driving circuit 240 can receive the bit stream IN. <1> and bitstream IN <0> , and serve as the response to drive the output signal OUT. IN <1> Bitstream and IN <0> A bit stream can represent a two-bit data stream. The output signal OUT, driven by the driver circuit 240, is based on IN. <1> Bitstream and IN <0> Bit stream. For example, input signal IN. <0> and input signal IN <1> These can be considered as the least significant bit (LSB) and most significant bit (MSB) of a binary number. The output signal OUT can be a multi-level signal with different levels to represent IN. <0> and IN <1> The four possible values ​​of IN. In some embodiments of this disclosure, PAM4 technology can be used to convert IN to IN. <1> Bitstream and IN <0> The two bits of data in the bitstream are converted into a multilevel signal with one of four different voltage levels.

[0032] Receiver 226 may include comparator block 250 coupled to decoder 260. Comparator block 250 may be configured to receive signals from the I / O bus and provide Z0-Zn signals (n is an integer) to decoder 260. Comparator block 250 may include circuitry configured to compare signals from the I / O bus with a reference signal to provide Z0-Zn signals. Figure 2 (Not shown in the diagram). For example, comparator block 250 may include a comparator that compares the OUT signal from the I / O bus with various reference signals to provide the Z0-Zn signals. Decoder 260 may include generating a bit stream RX based on the Z0-Zn signals from comparator block 250. <0> and bitstream RX <1> The logic. RX <0> Bitstream and RX <1> Bit streams can be generated by IN <0> Bitstream and IN <1> The logical equivalent of bitstream transmitted data. RX <0> Bitstream and RX <1> A bitstream can represent a two-bit received data stream.

[0033] During operation, IN <0> and IN <1> This can be a bit stream transmitted via the I / O bus. The signal driver 214 can use multi-level signals based on the IN value to be transmitted on the signal line. <0> Bitstream and IN <1> Instead of sending each bit stream on a separate signal line, bit streams are used to provide signals. For example, signal driver 214 can receive IN. <0> Bitstream and IN <1> The bit stream, and during each data interval, the drive circuit 240 can be used with the RX provided by the receiver 226. <0> Bitstream and RX <1> The voltage of the bit stream drives the signal lines of the I / O bus. Multi-level signals can be used to represent I / O using fewer signal lines than one signal line per bit stream. <0> Bitstream and IN <1> Bitstream data. For example, as in Figure 2 In embodiments where fewer than two signal lines are used (e.g., one signal on the I / O bus instead of for IN), <0> One signal line of the bit stream and used for IN <1> On another signal line of the bit stream, IN will be... <0> Bitstream and IN <1> The bitstream data is provided to receiver 226.

[0034] although Figure 2 This demonstrates the use of bit stream IN <0> and bitstream IN <1> To provide bitstream RX <0> and bitstream RX <1> The operation is the same, but in other embodiments of this disclosure, the number of bit streams can be different. For example, in some embodiments of this disclosure, besides IN... <0> Bitstream and IN <1> In addition to the bit stream, a third bit stream IN can also be provided to the signal driver 214. <2> Furthermore, multi-level signals can be represented by signals from IN. <0> Bitstream, IN <1> Bitstream and IN <2> An I / O bus for bitstream data is provided. Such embodiments are within the scope of this disclosure.

[0035] Figure 3This is a schematic diagram of a pre-emphasis driver according to some embodiments of the present disclosure. In some embodiments, the pre-emphasis driver 300 may include... Figure 1 Signal drivers 114 / 124 and / or Figure 2 In the driving circuit 240. Figure 3 An exemplary pre-emphasis driver 300 is shown configured for a PAM4 signal architecture, wherein two binary input signals, MSB and LSB, are converted into multi-level signals with four levels. Other signal architectures may be used in other embodiments.

[0036] The pre-emphasis driver 300 includes a main driver 302 as part of the main signal path, and multiple equalizer paths 304a-c. Figure 3 The exemplary embodiment illustrates three equalizer paths 304a-c, although more or fewer equalizer paths may be used in other exemplary embodiments. In some embodiments, only a single equalizer path (e.g., 304a) may be used. In some embodiments, additional equalizer paths (not shown) may be used. The master driver 302 and each equalizer path 304a-c have input nodes that are commonly coupled to the signal MSB and signal LSB. The master driver 302 and each equalizer path 304a-c also have output nodes that are commonly coupled to the summing node 310. Therefore, the master driver 302 may represent a master driver path parallel to all equalizer paths 304a-c between the input signals MSB and LSB and the summing node 310. The summing node 310 directs traffic to the channel (e.g., Figure 1 (The I / O channel) provides signals.

[0037] The main driver 302 can receive the MSB and LSB signals and generate a multi-level signal based on these input signals. Each equalizer path 304a-c includes an equalizer driver 306 and frequency modulation elements. Figure 3 In this embodiment, filter element 308 (especially a capacitor) is used as a frequency modulation element. In other exemplary embodiments, other types of frequency modulation elements and other types of filter elements may be used.

[0038] When activated, equalizer driver 306 receives the input signal MSB and input signal LSB and provides a multi-level output signal in a manner similar to that of main driver 302. In some embodiments, equalizer driver 306 may be smaller than main driver 302 (e.g., lower power, smaller component transistors). For example, equalizer driver 306 may be approximately 0.1 times the size of main driver 302. Each equalizer path 304a-c also includes a filter element 308, which may act as a high-pass filter for the signal provided by equalizer driver 306. Figure 5The exemplary details of the master driver and equalizer driver are discussed in more detail below.

[0039] Filter element 308 can be an AC circuit element, such as a capacitor. The use of an AC circuit element decouples the filtering effect from the length of the signaling interval and allows the pre-emphasis filter to operate continuously. The capacitor can be coupled between the output node of the correlated equalizer driver 306 and the summing node 310. Due to the filter element 308 (e.g., a capacitor), each equalizer path 304a-c can have a transfer function that acts as a high-pass filter. For example, each equalizer path 304a-c can have a separate equivalent resistance R. EQ and series capacitor C EQ As illustrated in the illustration, in some embodiments, these may have an inherent resistance R from the capacitor. Via and edge capacitance C 边缘 (For example, between the metal layers of the chip) contribution. The first equalizer path 304a may have a first resistor R. EQ a and capacitance C EQ a. The second path 304b can have a second resistor R. EQ b and capacitor C EQ b, and the third path 304c can have a third resistor R EQ c and capacitor C EQ c. In some embodiments, each path 304a-c has a corresponding resistance R EQ and capacitor C EQ They can have the same value.

[0040] Therefore, when at least one equalizer path is active, capacitor 308 can be based on C EQ and R EQ The value of gives the behavior of the high-pass filter for the active paths a cutoff frequency. This provides an effective resistance Reff and an effective capacitance Ceff for the entire driver 300, which in turn gives the overall high-pass filter behavior. The number of active equalizer paths 304a-c determines the total value of Reff and Ceff. For example, the values ​​of Ceff and Reff can vary between a minimum (e.g., no equalizer paths 304a-c are active) and a maximum (e.g., all equalizer paths 304a-c are active).

[0041] In other instances, different types of filter elements 308 can be used to implement high-pass filtering (or different forms of frequency modulation response). For example, in some embodiments, the inductance of equalizer paths 304a-c can be based on the passive or active inductance of equalizer driver 306 (e.g., based on the way transistors of equalizer driver 306 are coupled together). In some embodiments, filter element 308 may include a resistor in series with a capacitor. In some embodiments, filter element 308 may include a resistor and a shunt inductor. Other forms of filter element 308 are possible in other instances.

[0042] Activating equalizer paths 304a-c can contribute an equalized (e.g., high-pass filtered) signal to summing node 310, which can provide enhanced performance to the overall output signal during high-frequency (e.g., fast switching) behavior. The equalized signal can decay over time (e.g., due to capacitors), which can provide a strong response to the total output signal after the levels of the multi-level signals (e.g., both from the equalized signal and the main signal) have changed, and the levels of the multi-level signals decay over time to the level of only the main signal (e.g., when the equalized signal drops to a negligible level). Figure 6 The text discusses different types of capacitors and different C values ​​in more detail. EQ Value and R EQ The choice of value. Figure 7A The activation of different numbers of equalizer paths 304a-c is discussed in more detail in section C.

[0043] Different types of capacitors 308 can provide different benefits and disadvantages to the overall performance of the pre-emphasized driver 300. In some embodiments, a metal-oxide-semiconductor capacitor (MOScap) can be used as capacitor 308. For example, a MOScap can be formed between the gate of a transistor and the short-circuited source-drain of the transistor. MOScaps can provide advantages such as relatively area-efficient and relatively high bandwidth, as well as relatively low cost for implementation on memory devices. In some embodiments, capacitor 308 can be implemented using edge capacitance, such as capacitance formed by interlacing metal wirings on multiple layers of a chopper and relying on the proximity of the traces (e.g., in the horizontal and / or vertical dimensions) to generate capacitance. In some embodiments, capacitor 308 can be a reused memory cell capacitor or a metal-insulator-metal capacitor (MIMcap).

[0044] The summing node 310 can receive multilevel signals from the main driver 302 and any active path among the multiple equalizer paths 304a-c, and combine them into an output multilevel signal. In some embodiments, the summing node 310 may be a conductive node that is commonly coupled to the outputs of the main driver 302 and the equalizer paths 304a-c.

[0045] Compared to the main driver 302, each equalizer path 304a-c has a transfer function that amplifies high-frequency components due to capacitor 308. The capacitor also causes the equalizer paths to decay over time, allowing equalizer paths 304a-c to contribute to the output signal after changes in the input signal MSB and LSB, and the contribution from paths 304a-c can then decay over time. Therefore, the overall transfer function of the pre-emphasis circuit can have an increased response to high-frequency components, such as rapid voltage changes when the output multi-level signal changes level. This allows the pre-emphasis driver to respond more quickly to level changes, with a more pronounced swing from the first level to the second. This, in turn, can improve the detection of different levels of the multi-level signal.

[0046] The response of the pre-emphasis circuit 300 can be altered by selecting more or fewer equalizer paths 304a-c. When a path is selected, each equalizer path 304a-c can provide only an equalized multilevel signal. For example, a selection signal (not shown) can be used to activate the equalizer driver 306 (e.g., by powering the equalizer driver 306). Other methods can also be used to adjust the equalizer response, such as by adjusting the drive strength (inverter size) in the equalizer path, and / or by enabling / disabling the capacitors in the equalizer path.

[0047] Figure 4 This is a diagram illustrating exemplary operation of a pre-emphasis driver according to some embodiments of this disclosure. In some embodiments, diagram 400 may represent, for example... Figure 3 The operation of the pre-emphasis driver 300. The graph shows the voltage change over time. While some values ​​for voltage and time are shown, it should be understood that these are merely examples and higher or lower voltages and slower or faster speeds may be used in other exemplary embodiments.

[0048] The first trace 402 shows the main drive (e.g., Figure 3 The output of 302). The second trace 404 shows the equalizer path (e.g., ). Figure 3 The output of 304a-c). The third trace 406 shows the combined output multi-level signal (e.g., provided by summing node 310).

[0049] At an initial time t0, the pre-emphasis driver is activated. For example, the pre-emphasis driver can receive a binary signal, which allows it to provide a multi-level signal at a certain level (e.g., approximately 0.5 V). It can be seen that the output of the main driver 402 rises to this level but does not exceed it. The output of the equalizer path 404 shows an immediate rise to a lower level, then due to the filtering elements (e.g., ...). Figure 3 The capacitor C of 308)EQ The output of equalizer path 404 exhibits an exponential decay due to the AC-based high-pass filtering of the filtering elements. As can be seen from the total output 406, the total output demonstrates both the strong initial response of equalizer path 404 and then equalization to the high voltage level provided by the main driver. The total output signal 406 can rise faster than signal 402 (e.g., faster than when the equalizer path is not activated) and can exceed the output level, making it easier to detect changes in the multi-level output signal 406. For example, this can allow for an increase in data rate due to this edge enhancement, compensating for channel loss.

[0050] At the first time t1, the signal ends, and the pre-emphasis driver returns to providing the initial voltage level. It can be seen that the equalizer path 404 exhibits a large initial response that decays over time, which causes a strong response throughout the output trace 406.

[0051] Figure 5 This is a schematic diagram of a pre-emphasis driver according to some embodiments of the present disclosure. In some embodiments, the pre-emphasis driver 500 may include... Figure 3 In the pre-emphasis driver 300. The pre-emphasis driver 500 includes a main driver 502 (e.g., Figure 3 The main driver 302) and the equalizer path, the equalizer path including the equalizer driver 506 and the capacitor 508 (e.g., Figure 3 (equalizer driver 306 and filter element 308).

[0052] The main driver 502 includes four transistors 510-513 and four resistors R1-R4. These work together to generate an output signal with one of four voltage levels (e.g., a multi-level signal) based on the states of two binary input signals MSB and LSB. Specifically, the two binary input signals can be represented in binary as values ​​between 0 and 3, with MSB being the most significant bit and LSB being the least significant bit (e.g., 00, 01, 10, and 11). In some instances, the output voltage can be the lowest level when the value is 00, the next lowest level when the value is 01, and so on. The main driver 502 can use transistor 510 as a switch to configure a voltage divider using two of the resistors R1-R4.

[0053] The first transistor 510 is a p-type transistor, with its source coupled to the first system voltage Vdd, its gate coupled to the MSB signal, and its drain coupled to the output node through R1. The second transistor 512 is an n-type transistor, with its source coupled to a second system voltage Vss (such as ground) lower than Vdd, its gate coupled to the MSB signal, and its drain coupled to the output node through R2. The third transistor 511 is a p-type transistor, with its source coupled to Vdd, its gate coupled to the LSB signal, and its drain coupled to the output node through R3. The fourth transistor 513 is an n-type transistor, with its source coupled to Vss, its gate coupled to the LSB signal, and its drain coupled to the output node through R4.

[0054] In operation, when both the MSB and LSB signals are low (e.g., value 00), transistors 512 and 513 can be inactive, while transistors 510 and 511 are active, and output node 509 can have a voltage Vdd. When the LSB signal is high and the MSB is low (e.g., value 01), transistors 510 and 513 can be active, and the output node can be coupled to Vdd via R1 and to Vss via R4. Resistors R1 and R4 can therefore act as voltage dividers, and the output node can have a voltage based on the ratio of R1 and R4. Similarly, when the MSB signal is high and the LSB is low (e.g., value 10), resistors R2 and R3 can act as voltage dividers, and the voltage of the output node can be based on the ratio of R2 and R3. When both the MSB and LSB signals are active, transistors 512 and 513 can both be active, and the output node is coupled to Vss. The output of the main driver 502 is coupled to a summing node 509, which provides the total output voltage (e.g., a multi-level signal). In some embodiments, the multi-bit data may be pre-encoded before the multi-level signal is transmitted, such that the final decoded data within the receiver may not follow the allocation just described. For example, when Gray code can be integrated into a signaling scheme.

[0055] The equalizer driver 506 can generally be similar to the main driver 502, and for the sake of brevity, the operation of the equalizer driver 506 will not be described in detail. The equalizer driver 506 includes resistors R5-R8, which can selectively couple between voltages Vdd and Vss to the output node of the equalizer driver 506 (which is coupled to the summing node 509 via capacitor 508). In some embodiments, resistors R5-R8 can be selected to have different values ​​than their associated resistors R1-R4. In some embodiments, resistors R5-R8 can be selected such that the output of the equalizer driver 506 is generally lower than the output of the main driver 502. In some embodiments, transistors 510-513 (and / or 520-523) can have resistances that contribute to the total Reeff of the driver. In some embodiments, the resistances of the transistors can be tuned to different values, and resistors R1-R4 (and / or R5-R8) can be omitted.

[0056] Figure 6 This is a graph showing the transfer function of a pre-emphasis driver based on different capacitor values ​​according to some embodiments of this disclosure. Graph 600 shows the transfer function H as a function of frequency, representing two different resistors R. EQ Value and two different capacitors C EQ Values. Specifically, Figure 600 shows the resistance R for 10 Ω and 40 Ω. EQ The values ​​and capacitances C of 2.0 pF and 0.5 pF. EQ .

[0057] As shown in Figure 600, the overall transfer function H(f) acts as a high-pass filter, where frequencies below the cutoff have lower transfer function values ​​than frequencies above the cutoff. Increasing the capacitor lowers the frequency used as the cutoff, while increasing the resistor reduces the difference in transfer function values ​​before and after the cutoff. Therefore, as more equalizer paths are activated (e.g., and more capacitors are coupled in parallel), the overall C... EQ It may increase, and the cutoff frequency may decrease.

[0058] Figure 7A C is a set of graphs illustrating exemplary effects of increasing the number of activation balancing paths according to some embodiments of this disclosure. Figure 7A Figures 700a-700c to C illustrate different ways of characterizing the behavior of the pre-emphasis circuit when more or fewer equalizer paths (e.g., paths 304a-c) are activated, where more activated equalizer paths represent increased equalizer (EQ) strength. Although figures 700a-c show various values ​​for time, frequency, decibels, etc., these should be understood as merely examples, and other values ​​may be used in other exemplary embodiments.

[0059] Figure 700a shows the frequency response of the circuit. When no equalizer path is activated, the circuit may have a flat frequency response (e.g., 0 dB). As the equalizer strength increases (as indicated by the arrows), the slope of the response increases.

[0060] Figure 700b shows the time-domain response of the pre-emphasis driver, as the driver outputs different levels over time (levels 3, 4, 2, and 1 as shown). The arrows indicate the increase in equalization strength during the transition between levels from 0 dB (no equalizer path active) to 2.1 dB (all equalizer paths active). It can be seen that as the equalization level increases, the multi-level signal has sharper "corners" when transitioning between levels. It also changes levels more quickly. For example, this can make it easier for the receiving circuitry to determine the transitions between levels.

[0061] Figure 700c shows a data eye diagram of data transmitted using a pre-emphasis driver at three different equalization levels (e.g., more or fewer equalizer path activations). The leftmost portion of Figure 700c shows no equalization (e.g., no equalizer path activation), the middle portion shows under-equalization (e.g., one equalizer path activation), and the rightmost portion shows optimal equalization (e.g., three equalizer path activations). While the example in Figure 700c shows that three equalizer paths are optimal, it should be understood that more or fewer equalizer paths may be optimal in other cases. Figure 700c shows a multi-level output signal with four levels (e.g., a PAM4 signal). It can be seen that as the number of activated equalizer paths increases, the data eye opens, showing a faster (and more concise) transition between different levels of the multi-level signal.

[0062] Devices including pre-emphasis drivers can have an optional number of active equalizer paths (e.g., Figure 3 (Paths 304a-c). In some embodiments, the number of active paths can be device-configurable. The number of active equalizer paths can be permanently set, for example, by blowing one or more fuses on the device. For example, device testing (e.g., during packaging or assembly) can measure the response of the pre-emphasized driver and can be used to determine the optimal number of active equalizer paths, and fuses can be blown to set that optimal number to active.

[0063] In some embodiments, the number of active equalizer paths can be user-configurable. For example, in some cases, a user may determine that they prefer to improve the performance of the pre-emphasis circuitry (at the cost of greater power consumption) and can activate all equalizer paths by, for example, by blowing a fuse or setting a feature of the mode register. In other cases, a user may prefer lower power consumption and select fewer equalizers to be active.

[0064] In some embodiments, the device may use a training process to determine how many equalizer paths to activate. For example, during initialization, the device may provide a test signal to the pre-emphasis driver and measure one or more characteristics of the response to the multilevel signal. The device may then determine the optimal number of equalizer paths and save that setting (e.g., as a value in a mode register). In some embodiments, the training process may be iterative, and the device may adjust the number of activated equalizer paths until the performance of the multilevel signal is within acceptable tolerances. In some embodiments, the device may continuously monitor the multilevel signal during operation and may update the number of activated equalizer paths continuously and / or intermittently based on this monitoring.

[0065] Of course, it should be understood that any of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and / or processes, or may be separated and / or performed between separate devices or device parts, based on this system, device and method.

[0066] Finally, the foregoing discussion is intended to illustrate the system only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system has been specifically described with reference to exemplary embodiments, it should be understood that various modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and contemplated spirit and scope of the system as set forth in the appended claims. Thus, the specification and drawings are considered illustrative and are not intended to limit the scope of the appended claims.

Claims

1. An apparatus for signal modulation, the apparatus comprising: The main drive circuit is configured to receive multiple binary signals and provide a first multi-level signal; Multiple selectable equalizer paths, each of the multiple selectable equalizer paths including an equalizer driver and a capacitor, wherein a selected equalizer path is configured to receive the multiple binary signals and provide a second multi-level signal, wherein the main drive circuit and the equalizer driver of each of the multiple selectable equalizer paths are co-coupled to a signal line carrying the multiple binary signals; and A summing node, configured to combine the first multilevel signal and the second multilevel signal into an output multilevel signal.

2. The apparatus of claim 1, wherein the selected equalizer path is selectively activated.

3. The apparatus of claim 1, wherein the main drive circuit and the equalizer path are connected in parallel between the input node and the summing node.

4. The apparatus of claim 1, wherein the capacitor comprises an edge capacitor, a metal oxide semiconductor capacitor (MOScap), a reused memory cell capacitor, or a metal-insulator-metal capacitor (MIMcap).

5. The apparatus of claim 1, wherein the main drive circuit and the equalizer driver are pulse amplitude modulation (PAM) drivers, wherein the plurality of binary signals include a first binary signal and a second binary signal, and wherein the output multilevel signal has four levels.

6. The apparatus of claim 1, wherein the equalizer driver is smaller than the main driver.

7. An apparatus for signal modulation, the apparatus comprising: The main drive circuit is configured to receive multiple binary signals and provide a main multi-level signal; Multiple selectable equalizer paths, each of which includes an equalizer driver and a high-pass filter, wherein a selected equalizer path is configured to receive the plurality of binary signals and provide a filtered multi-level signal, wherein the equalizer driver and the main drive circuit in each of the plurality of selectable equalizer paths are co-coupled to a signal line carrying the plurality of binary signals; and A summing node configured to provide a balanced output multilevel signal based on the main multilevel signal and the filtered multilevel signal.

8. The apparatus of claim 7, wherein the selected equalizer path among the plurality of selectable equalizer paths is selected based on a measurement of the output multilevel signal.

9. The apparatus of claim 7, wherein the main driver and the equalizer driver are pulse amplitude modulation (PAM) drivers.

10. The apparatus of claim 9, wherein the output multilevel signal has four voltage levels.

11. The apparatus of claim 7, wherein the high-pass filter comprises a capacitor.

12. The apparatus of claim 11, wherein the capacitor comprises an edge capacitor, a metal oxide semiconductor capacitor (MOScap), a reused memory cell capacitor, or a metal-insulator-metal capacitor (MIMcap).

13. A system for signal modulation, the system comprising: A first device, comprising a pre-emphasis driver configured to provide a multi-level signal based on a plurality of binary signals of the first device; and A second device, configured to receive the multi-level signal. The pre-emphasis driver includes: The main drive circuit is configured to receive multiple binary signals and provide a first multi-level signal; An equalizer path, comprising an equalizer driver and a capacitor, wherein the equalizer path is configured to receive the plurality of binary signals and provide a second multi-level signal, wherein the main drive circuit and the equalizer driver are coupled together to a signal line carrying the plurality of binary signals; as well as A summing node, configured to combine the first multilevel signal and the second multilevel signal into an output multilevel signal.

14. The system of claim 13, wherein the second device comprises a receiver and a decoder configured to reconstruct the plurality of binary signals based on the multilevel signal.

15. The system of claim 13, wherein the pre-emphasis driver comprises a plurality of equalizer paths, each of the plurality of equalizer paths comprising an equalizer driver and a capacitor.

16. The system of claim 15, wherein the first device includes an equalizer setting, and wherein a plurality of the equalizer paths are selectively activated based on the equalizer setting.

17. The system of claim 13, wherein the second multilevel signal is high-pass filtered compared to the first multilevel signal.

18. The system of claim 13, wherein the second multilevel signal has a lower voltage than the first multilevel signal.

19. The system of claim 13, wherein the capacitor comprises a metal oxide semiconductor capacitor (MOScap).

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