Level shifter

Abstract

This application is entitled "Level Shifter". In one example, a device (100) includes a level shifting circuit (114) and a ramp detector (112). The level shifting circuit has a current choke and a transistor coupled across the current choke, and the level shifting circuit is adapted to be coupled to a first voltage source (108). The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, and the ramp detector is adapted to be coupled to a second voltage source (110).

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Indian Provisional Patent Application No. 202041026732, filed on June 24, 2020, the entire contents of which are incorporated herein by reference. Background Technology

[0003] A level shifter is a circuit, component, or device that converts a received input signal from a first voltage domain or logic level to a second voltage domain or logic level to provide an output signal. The value of the output signal can be greater than or less than the value of the input signal. Level shifters can be unidirectional or bidirectional and can facilitate compatibility between components or devices that might otherwise be incompatible based on their respective voltage specifications (e.g., the corresponding voltage domain in which each component operates). Summary of the Invention

[0004] In one example, a device includes a level shifting circuit and a ramp detector. The level shifting circuit has a current choke and a transistor coupled across the current choke, and the level shifting circuit is adapted to be coupled to a first voltage source. The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, and the ramp detector is adapted to be coupled to a second voltage source.

[0005] In one example, a device includes a ramp detector and a level shifting circuit. The ramp detector is configured to detect the slew rate of a voltage source, determine whether the slew rate of the voltage source exceeds a programmed value, and provide an output signal with an asserted value in response to the slew rate exceeding the programmed value. The level shifting circuit is coupled to the voltage source and the ramp detector. The level shifting circuit is configured to limit the quiescent current of the level shifting circuit through a current choke when the slew rate of the voltage source does not exceed the programmed value, and to bypass the current choke in response to the output signal having an asserted value.

[0006] In one example, a system includes a first component, a second component, and a level shifter. The first component has a first component input and is configured to operate in a first voltage domain defined according to a first voltage source. The second component has a second component output and is configured to operate in a second voltage domain defined according to a second voltage source. The level shifter includes a ramp detector and a level shifting circuit. The ramp detector is configured to detect the slew rate of the first voltage source, determine whether the slew rate of the first voltage source exceeds a programmed amount, and provide an output signal with an assertion value in response to the slew rate of the first voltage source exceeding the programmed amount. The level shifting circuit has a level shifting circuit input coupled to the output of the second component and a level shifting circuit output coupled to the input of the first component, and the level shifting circuit is also coupled to the first voltage source and the ramp detector. The level shift circuit is configured to convert a signal provided by the second component from a second voltage domain to a first voltage domain and provide a signal according to the second voltage domain to the first component, limit the quiescent current of the level shift circuit by a current choke when the slew rate of the first voltage source does not exceed the programmed amount, and bypass the current choke in response to the output signal having an assertion value.

[0007] In one example, a device includes a level shifting circuit and a ramp detector. The level shifting circuit includes a first arm and a second arm. The first arm includes a first portion of a cross-coupled latch, a first diode-coupled transistor stack, and a first input transistor. The second arm includes a second portion of a cross-coupled latch, a second diode-coupled transistor stack, and a second input transistor. The level shifting circuit also includes a first current choke adapted to be coupled between the first input transistor and ground, and a second current choke adapted to be coupled between the second input transistor and ground. The level shifting circuit also includes a first short-circuit transistor adapted to be coupled across the first current choke between the first input transistor and ground, and a second short-circuit transistor adapted to be coupled across the second current choke between the second input transistor and ground. The ramp detector has a capacitor coupled to the first and second short-circuit transistors via a current mirror. The ramp detector also has a ground gate transistor coupled to the capacitor. Attached Figure Description

[0008] Figure 1 This is a block diagram of the example system.

[0009] Figure 2 This is a schematic diagram of an example rising edge detector.

[0010] Figure 3 This is a schematic diagram of an example falling edge detector.

[0011] Figure 4 This is a schematic diagram of an example ramp detector.

[0012] Figure 5 This is a schematic diagram of an example level shifting circuit. Detailed Implementation

[0013] As mentioned above, level shifters can facilitate voltage compatibility between components that might otherwise operate in incompatible voltage domains or ranges. In some examples, these voltage domains are low-voltage and high-voltage domains, respectively. For example, the low-voltage domain may have an upper limit of less than or equal to about 5 volts (V), while the high-voltage domain may have upper and lower limits respectively ranging from about 2.5V to about 70V, due to potential voltage transients in the high-voltage domain. In various other examples, other suitable voltage ranges are possible for the low-voltage and / or high-voltage domains. For example, the low-voltage domain may have an upper limit of less than or equal to about 1.2V, 1.8V, 3.3V, or any other suitable amount. Some trade-offs may occur when designing level shifters that can be used in the high-voltage domain. For example, the level shifter may be designed to facilitate an output (OUT) signal with a lower limit that swings between multiple values ​​to account for the gate oxide voltage of the level shifter's transistor. Level shifters can also be designed to have low current consumption, such as less than about 100 nanoamps (nA), to reduce the quiescent current (IQ) of the level shifter, which may involve a trade-off in limiting the slew rate of the OUT signal. Level shifters can also be designed to account for the relatively large parasitic values ​​(e.g., capacitance and / or inductance) of components operating in the high-voltage domain, which may involve a trade-off in reducing the transient performance of the level shifter. To accommodate operation in both low-voltage and high-voltage domains, level shifters can receive low-source voltages and high-source voltages, respectively. The low-source voltage can have any suitable value within the low-voltage domain. The high-source voltage can have any suitable value within the high-voltage domain but may also experience transient events where the value of the high-source voltage may unpredictably or unexpectedly change to any other value within the high-voltage domain. Without compensation, these transient events may damage the level shifter and / or may alter its preset function or operation.

[0014] The level shifter according to this specification at least partially mitigates and / or compensates for the effects of these transient events. In at least one embodiment, the level shifter includes a current choke to limit the IQ of the level shifter and includes a component (e.g., a transistor) coupled across the current choke to short-circuit the current choke, which increases the transient response of the level shifter in response to detecting a voltage transient in the voltage source of the level shifter exceeding a voltage transient threshold. For example, the level shifter may modify its operation (e.g., operation relating to providing an OUT signal) based on the value of a high source voltage. Such modified operation can maintain the voltage across at least one transistor coupled to the level shifter (e.g., such as one driven by the level shifter) within a specified operating tolerance of the transistor. For example, the modified operation of the level shifter can maintain the voltage supplied by the level shifter to a transistor coupled to and receiving the output of the level shifter within a specified tolerance of the transistor's gate oxide voltage, while also providing reduced IQ operation of the level shifter. The modified operation can also control the pull-down strength of the level shifter (e.g., provided by a current source) to modify the discharge rate of the OUT signal (e.g., increase the response time in the presence of certain voltage transients). The level shifter may include a ramp detector that monitors the rate of change of the value of the high source voltage. In some examples, this monitoring provides an indication or relevant information about voltage transients present in the high source voltage. In at least some examples, the ramp detector includes both a rising value or rising edge detector and a falling value or falling edge detector. In response to the rate of change of the value of the high source voltage (e.g., slew rate) exceeding a programmed amount in the positive or negative direction, the level shifter may increase the pull-down current to increase the discharge rate of the OUT signal, increase the falling slew rate of the OUT signal or OUTBAR (e.g., the inverted phase of the OUT signal), increase the falling slew rate of the OUTBAR, and thus increase the charging rate of the OUT signal. Conversely, in response to the slew rate of the high source voltage not exceeding a programmed amount, the pull-down current of the level shifter may be limited to a programmed value to reduce and / or control the IQ of the level shifter. In at least some examples, whether the slew rate of the high source voltage exceeds the programmed value is determined by comparing the current representing the slew rate of the high source voltage with a reference current representing the programmed value.

[0015] Figure 1A block diagram of an example system 100 is shown. In at least some examples, system 100 represents an automotive or other vehicle environment where certain components can operate in or according to a first voltage domain, while other components can operate in or according to a second voltage domain. For example, system 100 may include component 102, level shifter 104, and component 106. System 100 may also include or be adapted to be coupled to a first power source 108 and a second power source 110. In at least some examples, component 102 receives power from the first power source 108 and operates in the first voltage domain. Similarly, component 106 receives power from the second power source 110 and operates in the second voltage domain. In some embodiments, the second power source 110 is a vehicle battery. Typically, components 102 and 106 may not be interoperable with each other due to their operation in different voltage domains. For example, a digital output signal provided by component 102 having a first value may be interpreted by component 106 as having a value other than the first value generated by components 102 and 106 operating in different voltage domains.

[0016] To provide interoperability between components 102 and 106, in at least some examples, a level shifter 104 is adapted to be coupled between components 102 and 106, and adapted to be coupled to a first power supply 108 and a second power supply 110. The level shifter 104 can switch between a first voltage domain and a second voltage domain. For example, in some embodiments, the level shifter 104 receives an input signal from component 102 having a value specified according to a first voltage domain and provides an output signal to component 106 having a value specified according to a second voltage domain. In this way, if the value specified according to the first voltage domain is a first digital value, then the value specified according to the second voltage domain is also a first digital value. Similarly, if the value specified according to the first voltage domain is a second digital value, then the value specified according to the second voltage domain is also a second digital value.

[0017] In some examples, the second power supply 110 is susceptible to voltage transients, such as when the second power supply 110 is a battery in a vehicle environment. For example, the second power supply 110 may be susceptible to voltage transients ranging from about 2.5V to about 70V or any other suitable value (e.g., negative), such as those caused by loads on the second power supply 110. To mitigate the effects of these voltage transients on the operation of the level shifter 104, the level shifter 104 may include a ramp detector 112 and a level shifting circuit 114. In some examples, the ramp detector 112 detects the slew rate of the signal received from the second power supply 110 and, in response to determining that the slew rate exceeds a programmed amount, provides an output signal with an asserted / valid pulse to the level shifting circuit 114. To reduce the IQ of the level shifting circuit 114 and thus increase the energy efficiency of the level shifting circuit 114 and the level shifter 104, the level shifting circuit 114 may include a current-limiting component (not shown) configured to limit the current flowing through the level shifting circuit 114. In at least some examples, in response to receiving a signal with an assertion pulse from ramp detector 112, level shift circuit 114 bypasses or shunts the current limiting component. In some examples, the IQ of level shift circuit 114 and level shifter 104 increases approximately during the period when the current limiting component is shunt, relative to the IQ of level shift circuit 114 and level shifter 104 when the current limiting component is not shunt. In at least some examples, shunting the current limiting component increases the discharge rate of the output signal (e.g., OUT signal) of level shift circuit 114. By increasing the discharge rate of the output signal of level shift circuit 114, the effects of transient components of the second power supply 110 on the operation of level shifter 104 and system 100 are mitigated.

[0018] Figure 2 A schematic diagram of an example falling edge detector 200 is shown. In at least some examples, the falling edge detector 200 is Figure 1 The ramp detector 112 or Figure 1 The components of the ramp detector 112. For example, the falling edge detector 200 can detect the falling slew rate of the received signal and provide a signal with an assertion pulse in response to the falling slew rate exceeding a programmed amount. In at least some examples, the falling edge detector 200 includes a diode 202, a transistor 204, a transistor 206, a capacitor 208, a current mirror 210 including transistors 212 and 214, a current mirror 216 including transistors 218 and 220, a current source 222, a transistor 224, a transistor 226, and a transistor 228. In at least some examples, the diode 202 is a Zener diode. In some examples, the capacitor 208 is a high-voltage capacitor. In some examples, both transistors 204 and 206 are extended-drain transistors or other high-voltage process technology transistors.

[0019] In the example architecture of the falling edge detector 200, diode 202 has an anode adapted to be coupled to a first voltage source (not shown) and to receive a first voltage signal (Vl). Diode 202 also has a cathode coupled to node 230. Transistor 204 has a gate coupled to the anode of diode 202, a source coupled to node 230, and a drain coupled to node 232. Transistor 206 has a drain coupled to node 230 and a gate and source adapted to be coupled to ground 234. Capacitor 208 is coupled between node 230 and ground 234. Current mirror 210 is coupled between the drain of transistor 204 and current mirror 216. For example, transistor 212 has a gate and drain coupled to the drain of transistor 204 and a source adapted to be coupled to ground 234. Transistor 214 has a gate coupled to the gate of transistor 212 and a source adapted to be coupled to ground 234. A current mirror 216 is coupled between current mirror 210 (e.g., at the drain of transistor 214) and node 236. For example, transistor 218 has a gate and drain coupled to the drain of transistor 214, and a source adapted to be coupled to a second voltage source (not shown) and receive a second voltage signal (V2). Transistor 220 has a gate coupled to the gate of transistor 218, a source adapted to be coupled to the second voltage source and receive V2, and a drain coupled to node 236. Current source 222 is adapted to be coupled between node 236 and ground 234 and conducts current between node 236 and ground 234. Transistors 224, 226, and 228 are each adapted to be coupled in series in a diode configuration between node 236 and ground 234. In at least some examples, any one or more of transistors 224, 226, and / or 228 may be omitted from the falling edge detector 200 or replaced by any other suitable safety or voltage clamping component or circuitry.

[0020] In an example of the operation of the falling edge detector 200, V1 is received at the anode of diode 202. A current in V1 flows through diode 202 and provides a signal (V1_int) at node 230. In at least some examples, during the falling transient of V1, the value of V1_int follows the value of V1 minus the voltage drop across diode 202. Otherwise, the gate-source voltage (Vsg) of transistor 204 increases, thereby increasing the pull-down strength of transistor 204. Transistor 206 is coupled in such a configuration to provide parasitic capacitance in parallel with capacitor 208, thereby increasing the effective capacitance at node 230. In at least some examples, transistor 206 is referred to as a ground-gate transistor, or a transistor coupled in a ground-gate configuration. Capacitor 208 is charged based on V1_int and provides a current (Icap) during the falling transient of V1, the value of which is approximately equal to the capacitance (C) of capacitor 208 multiplied by the rate of change of V1 with respect to time. Icap is mapped from current mirror 210 to current mirror 216. In at least some examples, current mirror 216 is a 1:n current mirror, such that the size of transistor 220 is n times that of transistor 218. Current mirror 216 maps Icap to node 236 to provide n*Icap at node 236. Current source 222 is configured to draw a programmed amount of current (Itail) from node 236 to ground 234. In response to a value greater than Itail, a ramp detection signal (RAMP_DETECT) is provided at node 236, with a voltage approximately equal to V2 minus the voltage drop provided by transistor 220. In response to a value less than Itail, RAMP_DETECT is provided at node 236, with a voltage approximately equal to the voltage provided at ground 234. In at least some examples, transistors 224, 226, and 228 clamp the voltage value of RAMP_DETECT to approximately the sum of the threshold voltages of transistors 224, 226, and 228. In at least some examples, by increasing the value of n, the value of C can be decreased, thereby reducing the physical size of the falling edge detector 200 compared to a falling edge detector 200 with a smaller n value and a larger C value.

[0021] Figure 3 A schematic diagram of an example rising edge detector 300 is shown. In at least some examples, the rising edge detector 300 is Figure 1 The ramp detector 112 or Figure 1 The components of the ramp detector 112. For example, the rising edge detector 300 can detect the rising slew rate of the received signal and provide a signal with an assertion pulse in response to the rising slew rate exceeding a programmed amount. In at least some examples, the rising edge detector 300 includes a capacitor 302, a current mirror 304 including transistors 306 and 308, a current mirror 310 including transistors 312 and 314, a current source 316, transistors 318, 320, and 322. In some examples, the capacitor 302 is a high-voltage capacitor.

[0022] In an example architecture of the rising edge detector 300, capacitor 302 has a first terminal adapted to be coupled to a first voltage source (not shown) and receive V1, and a second terminal coupled to node 324. Current mirror 304 is coupled between node 324 and current mirror 310. For example, transistor 306 has a gate and drain coupled to node 324 and a source adapted to be coupled to ground 326. Transistor 308 has a gate coupled to the gate of transistor 306 and a source adapted to be coupled to ground 326. Current mirror 310 is coupled between current mirror 304 (e.g., at the drain of transistor 308) and node 328. For example, transistor 312 has a gate and drain coupled to the drain of transistor 308 and a source adapted to be coupled to a second voltage source (not shown) and receive V2. Transistor 314 has a gate coupled to the gate of transistor 312, a source adapted to be coupled to the second voltage source and receive V2, and a drain coupled to node 328. Current source 316 is adapted to be coupled between node 328 and ground 326 and to conduct current between node 328 and ground 326. Transistors 318, 320, and 322 are all adapted to be coupled in series in a diode configuration between node 328 and ground 326. In at least some examples, any one or more of transistors 318, 320, and / or 322 may be omitted from rising edge detector 300 or replaced by any other suitable safety or voltage clamping component or circuitry.

[0023] In an example of the operation of the rising edge detector 300, capacitor 302 is charged based on V1 and provides Icap at node 324 during the rising transient of V1. The value of Icap is approximately equal to the capacitance (C) of capacitor 302 multiplied by the rate of change of V1 with respect to time. Icap is mapped from current mirror 304 to current mirror 310. In at least some examples, current mirror 310 is a 1:n current mirror, such that the size of transistor 314 is n times that of transistor 312. Current mirror 310 maps Icap to node 328 to provide n*Icap at node 328. Current source 316 is configured to draw a programmed current (Itail) from node 328 to ground 326. In response to a value of n*Icap greater than Itail, RAMP_DETECT is provided at node 328, with a voltage approximately equal to V2 minus the voltage drop provided by transistor 314. In response to a value of n*Icap less than Itail, RAMP_DETECT is provided at node 328, with a voltage approximately equal to the voltage provided at ground 326. In at least some examples, transistors 318, 320, and 322 clamp the voltage value of RAMP_DETECT to approximately the sum of the threshold voltages of transistors 318, 320, and 322. In at least some examples, by increasing the value of n, the value of C can be decreased, thereby reducing the physical size of the rising edge detector 300 compared to a rising edge detector 300 with a smaller n value and a larger C value.

[0024] Figure 4 A schematic diagram of an example ramp detector 112 is shown. In at least some examples, the ramp detector 112 is combined with... Figure 2 Falling edge detector 200 and Figure 3The rising edge detector 300 enables the ramp detector 112 to detect and provide a signal in response to rising and / or falling transients in V1. For example, the ramp detector 112 includes components of the falling edge detector 200 and a current mirror 304 (including transistors 306 and 308) of the rising edge detector 300. In at least some examples, capacitors 208 and 302 are shared as identical components, current mirror 216 including transistors 218 and 220 is shared as identical components with current mirror 310 including transistors 312 and 314, current sources 222 and 316 are shared as identical components, and transistors 224, 226, and 228 are shared as identical components with transistors 318, 320, and 322, respectively. In at least some embodiments, the ramp detector 112 also includes a current source 402 adapted to be coupled between the second voltage source and the gate of transistor 306, and a current source 404 adapted to be coupled between the second voltage source and the drain of transistor 214. Both current sources 402 and 404 provide their respective bias currents to ramp detector 112 to mitigate the presence of floating nodes in ramp detector 112. In at least some examples, the outputs of current mirrors 210 and 304 are summed at current mirror 216, for example, by shorting the current pull-down arm of current mirror 210 (e.g., at the drain of transistor 214) and the current pull-down arm of current mirror 304 (e.g., at the drain of transistor 308) at the current pull-up arm of current mirror 216 (e.g., at the drain of transistor 220). This document does not include information about... Figure 4 For a further description of the ramp detector 112, please refer to the above description. Figure 2 and Figure 3 The architecture and operation description.

[0025] Figure 5A schematic diagram of an example level shift circuit 114 is shown. In at least some examples, the level shift circuit 114 is configured to receive an input signal (IN) in a first voltage domain defined according to V2 and provide an OUT signal in a second voltage domain defined according to V1. In at least some examples, the level shift circuit 114 includes transistors 502, 504, 506, 508, current sources 510, 512, 514, 516, 518, 520, 522, 524, 526, 528, diodes 530 and 532, capacitors 534 and 536, and an inverter 538. In some embodiments, transistors 506 and 508 are both drain-extended transistors. In some embodiments, diodes 530 and 532 are both Zener diodes. In at least some examples, current sources 510 and 512 are both referred to as current chokes.

[0026] In the example architecture of level shift circuit 114, transistors 502 and 504 form a cross-coupled latch, such that level shift circuit 114 includes two complementary arms. For example, transistor 502 has a source adapted to be coupled to a voltage source (not shown) providing V1, a gate coupled to node 540, and a drain coupled to node 542. Transistor 504 has a source adapted to be coupled to a voltage source providing V1, a gate coupled to node 542, and a drain coupled to node 540. Transistor 506 has a drain coupled to node 540, a source coupled to node 544, and a gate configured to receive IN. Inverter 538 has an input terminal coupled to the gate of transistor 506 and an output terminal coupled to the gate terminal of transistor 508, and operates in a first voltage domain based on receiving V2. Transistor 508 also has a drain coupled to node 540 and a source coupled to node 548. Current source 510 is adapted to be coupled between node 544 and ground 550. Current source 512 is adapted to be coupled between node 548 and ground 550. Transistor 514 has a drain coupled to the source of transistor 506, a source adapted to be coupled to ground 550, and a gate configured to receive RAMP_DETECT as described above. Transistor 516 has a drain coupled to the source of transistor 508, a source adapted to be coupled to ground 550, and a gate configured to receive RAMP_DETECT as described above. In at least some examples, nodes 540 and 542 are adapted to be coupled to ground 550 such that a parasitic capacitance (not shown) of transistor 506 exists between the drain of transistor 506 and ground 550, and a parasitic capacitance (not shown) of transistor 508 exists between the drain of transistor 508 and ground 550. Transistors 518, 520, and 522 are all adapted to be configured in series coupling in a diode configuration between the voltage source and node 540. Transistors 524, 526, and 528 are all adapted to be coupled in series in a diode configuration between the voltage source and node 542. Diode 530 has a cathode adapted to be coupled to the voltage source and an anode coupled to node 540. Diode 532 has a cathode adapted to be coupled to the voltage source and an anode coupled to node 542. Capacitor 534 is adapted to be coupled between the voltage source and node 540. Capacitor 536 is adapted to be coupled between the voltage source and node 542. In at least some examples, any one or more of transistors 518, 520, and / or 522 can be omitted from the level shifting circuit 114, or additional diode-coupled transistors can be added in series with transistors 518, 520, and 522. In at least some examples, any one or more of transistors 524, 524, and / or 528 can be omitted from the level shifting circuit 114, or additional diode-coupled transistors can be added in series with transistors 524, 526, and 528.In some examples, diodes 530 and 532 can be omitted from level shift circuit 114. In some examples, capacitors 534 and 536 can be omitted from level shift circuit 114.

[0027] In an example of the operation of level shift circuit 114, in response to receiving an IN with a value sufficient to conduct current between transistor 506's drain and source, transistor 506 pulls down node 540 with a current approximately equal to the current absorbed by current source 510, and transistor 508 is non-conducting. When node 540 is pulled down by transistor 506, the voltage provided at node 540 can be approximately equal to V1 minus the voltage drop provided by transistors 518, 520, and 522 (e.g., the sum of the threshold voltages of transistors 518, 520, and 522). In response to node 540 being pulled down, transistor 504 becomes on and pulls up node 542 to provide an OUT signal, the value of which is approximately V1 minus the voltage drop provided by transistor 504. In response to receiving an IN with a value insufficient to conduct current between transistor 506's drain and source, transistor 506 is non-conducting, and transistor 508 pulls down node 542 with a current approximately equal to the current absorbed by current source 512. When node 542 is pulled down by transistor 508, the voltage provided at node 542 as the OUT signal can be approximately equal to V1 minus the voltage drop provided by transistors 524, 526, and 528 (e.g., the sum of the threshold voltages of transistors 524, 526, and 528). In response to node 542 being pulled down, transistor 502 becomes on and pulls node 540 up to a value having approximately V1 minus the voltage drop provided by transistor 502.

[0028] In at least some examples, the IQ of the level shift circuit 114 can be limited to a programmed value, and current sources 510 and 512 are configured to draw current to ground 550 at that programmed value. In some cases, such as when a transient exists in V1, the parasitic capacitances of transistors 506 and 508 hold the values ​​of nodes 540 and 542 as provided before the transient in V1. In some examples, this may cause the OUT signal to have an incorrect value relative to IN, potentially altering the function or operation of a system (e.g., system 100), a circuit (e.g., level shifter 104), or a device including the level shift circuit 114. In at least some examples, as described above, RAMP_DETECT is asserted in response to a transient in V1 exceeding the programmed amount. In response to the RAMP_DETECT assertion, current sources 510 and 512 are bypassed or shunt, thereby eliminating the IQ limit imposed on the level shift circuit 114 by the current sources 510 and 512. Eliminating the IQ limit applied to the level shift circuit 114 by current sources 510 and 512 increases the rate of discharge of the parasitic capacitance of transistors 506 and / or 508, thereby preventing the OUT signal from having an incorrect value relative to IN due to transients in V1 as described above. In at least some examples, the transients in V1 have a slew rate of approximately 1 V per microsecond (µs) (1V / µs). In at least some examples, both current sources 510 and 512 are configured to draw currents less than or equal to approximately 20 nA.

[0029] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: (a) in the first example, device A is directly coupled to device B; or (b) in the second example, if the intervening component C does not substantially alter the functional relationship between device A and device B, then device A is indirectly coupled to device B through the intervening component C, and therefore device B is controlled by device A through the control signals provided by device A.

[0030] A device "configured" to perform a task or function can be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform the function and / or can be configured (or reconfigured) by the user after manufacturing to perform that function and / or other additional or alternative functions. This configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0031] A circuit or device described herein as including certain components may be modified to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may be modified to include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be modified to be coupled to at least some passive elements and / or sources to form the described structure (e.g., by an end user and / or a third party) during or after manufacturing.

[0032] While some components may be described herein as having a specific process technology, these components can be interchanged with components of other process technologies. The circuits described herein can be reconfigured to include the replaced components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can be replaced with multiple resistors or capacitors, each coupled in parallel between the same nodes. Similarly, a resistor or capacitor shown and described herein as a single component can be replaced with multiple resistors or capacitors, each coupled in series between the same two nodes as the single resistor or capacitor.

[0033] The phrase "ground voltage potential" as used in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, "approximately," "about," or "basically" preceding a numerical value means + / - 10% of the stated value.

[0034] Within the scope of the claims, modifications may be made to the described examples, and other examples are possible.

Claims

1. A level shifter, comprising: A level shifting circuit having a current source and a transistor coupled across the current source, the level shifting circuit being adapted to be coupled to a first voltage source; as well as A ramp detector having a ramp detector input adapted to be coupled to a first voltage source and a ramp detector output coupled to the transistor, the ramp detector being adapted to be coupled to a second voltage source.

2. The level shifter according to claim 1, wherein the current source is a first current source, the transistor is a first transistor, and the level shifting circuit comprises: The first arm includes a second transistor as a first part of a cross-coupled latch, a first current source, a first transistor, a third transistor, and a first diode-coupled transistor stack; as well as The second arm includes a fourth transistor, a second current source, a fifth transistor, a sixth transistor, and a second diode-coupled transistor stack, which are the second part of the cross-coupled latch.

3. The level shifter of claim 2, wherein the second transistor has a source adapted to be coupled to the first voltage source, the fourth transistor has a source adapted to be coupled to the first voltage source, a gate coupled to the drain of the second transistor, and a drain coupled to the gate of the second transistor, the third transistor has a drain coupled to the drain of the second transistor, the fifth transistor has a drain coupled to the drain of the fourth transistor, the first current source is adapted to be coupled between the source of the third transistor and ground, the second current source is adapted to be coupled between the source of the fifth transistor and ground, the first transistor has a drain coupled to the source of the third transistor and a source adapted to be coupled to ground, and the sixth transistor has a drain coupled to the source of the fifth transistor and a source adapted to be coupled to ground.

4. The level shifter of claim 3, wherein both the first transistor and the sixth transistor are configured to receive a signal having an assertion value in response to the slew rate of the first voltage source exceeding a programmed amount, the assertion value being sufficient to allow the first transistor and the sixth transistor to conduct current.

5. The level shifter of claim 1, wherein the current source is a first current source, and wherein the ramp detector comprises: A diode having an anode adapted to be coupled to the first voltage source and having a cathode; A seventh transistor having a gate coupled to the anode of the diode, a source coupled to the cathode of the diode, and a drain; The eighth transistor has a gate and a source adapted to be coupled to ground and a drain coupled to the cathode of the diode; A capacitor having a first terminal coupled to the cathode of the diode; A first current mirror has a first current mirror input coupled to the drain of the seventh transistor and a first current mirror output; A second current mirror has a second current mirror input coupled to the output of the first current mirror and a second current mirror output, the second current mirror being adapted to be coupled to the second voltage source; as well as A second current source is coupled between the output of the second current mirror and ground, and the output of the second current mirror is coupled to the transistor.

6. The level shifter of claim 5, wherein the capacitor has a second terminal and the ramp detector includes a third current mirror having a third current mirror input coupled to the second terminal of the capacitor and a third current mirror output coupled to the second current mirror input.

7. The level shifter of claim 1, wherein the current source is a first current source, and wherein the ramp detector comprises: A capacitor having a first terminal adapted to be coupled to the first voltage source and having a second terminal; A first current mirror has a first current mirror input coupled to the second terminal of the capacitor and a first current mirror output; A second current mirror has a second current mirror input coupled to the output of the first current mirror and a second current mirror output, the second current mirror being adapted to be coupled to the second voltage source; as well as A second current source is coupled between the output of the second current mirror and ground, and the output of the second current mirror is coupled to the transistor.

8. A level shifter comprising: The ramp detector is configured as follows: Detect the slew rate of the voltage source; Determine whether the slew rate of the voltage source exceeds the programmed value; as well as In response to the slew rate of the voltage source exceeding the programmed amount, an output signal with an assertion value is provided; as well as A level shifting circuit, coupled to the voltage source and the ramp detector, is configured such that: When the slew rate of the voltage source does not exceed the programmed value, the static current of the level shifting circuit is limited by the current source; as well as In response to the output signal having the assertion value, the current source is bypassed.

9. The level shifter of claim 8, wherein the current source is a first current source, and the level shifting circuit comprises: The first arm includes a first transistor, a second transistor, a first current source, a third transistor, and a first diode-coupled transistor stack as a first part of a cross-coupled latch. as well as The second arm includes a fourth transistor, a fifth transistor, a second current source, a sixth transistor, and a second diode-coupled transistor stack, which are the second part of the cross-coupled latch.

10. The level shifter of claim 9, wherein the first transistor has a source adapted to be coupled to the voltage source, the fourth transistor has a source adapted to be coupled to the voltage source, a gate coupled to the drain of the first transistor, and a drain coupled to the gate of the first transistor, the second transistor has a drain coupled to the drain of the first transistor, the fifth transistor has a drain coupled to the drain of the fourth transistor, the first current source is adapted to be coupled between the source of the second transistor and ground, the second current source is adapted to be coupled between the source of the fifth transistor and ground, the third transistor has a drain coupled to the source of the second transistor and a source adapted to be coupled to ground, and the sixth transistor has a drain coupled to the source of the fifth transistor and a source adapted to be coupled to ground.

11. The level shifter of claim 10, wherein both the third transistor and the sixth transistor are configured to receive a signal having an assertion value in response to the slew rate of the voltage source exceeding a programmed amount, the assertion value being sufficient to cause the third transistor and the sixth transistor to conduct current to bypass the first current source and the second current source.

12. The level shifter of claim 9, wherein the current source is a first current source, the voltage source is a first voltage source, and the ramp detector comprises: A diode having an anode coupled to the first voltage source and having a cathode; A seventh transistor having a gate coupled to the anode of the diode, a source coupled to the cathode of the diode, and a drain; The eighth transistor has a gate and a source adapted to be coupled to ground and a drain coupled to the cathode of the diode; A capacitor having a first terminal coupled to the cathode of the diode; A first current mirror has a first current mirror input coupled to the drain of the seventh transistor and a first current mirror output; A second current mirror has a second current mirror input coupled to the output of the first current mirror and a second current mirror output, the second current mirror being adapted to be coupled to the second voltage source; as well as A second current source is coupled between the output of the second current mirror and ground, and the output of the second current mirror is coupled to the third transistor.

13. The level shifter of claim 12, wherein the capacitor has a second terminal and the ramp detector includes a third current mirror having a third current mirror input coupled to the second terminal of the capacitor and a third current mirror output coupled to the second current mirror input.

14. The level shifter of claim 9, wherein the current source is a first current source, the voltage source is a first voltage source, and the ramp detector comprises: A capacitor having a first terminal adapted to be coupled to the first voltage source and having a second terminal; A first current mirror has a first current mirror input coupled to the second terminal of the capacitor and a first current mirror output; A second current mirror has a second current mirror input coupled to the output of the first current mirror and a second current mirror output, the second current mirror being adapted to be coupled to the second voltage source; as well as A second current source is coupled between the output of the second current mirror and ground, and the output of the second current mirror is coupled to the third transistor.

15. An electrical system having multiple voltage domains, comprising: A first component having a first component input, the first component being configured to operate in a first voltage domain defined according to a first voltage source; A second component having a second component output, the second component being configured to operate in a second voltage domain defined according to a second voltage source; as well as A level shifter, comprising: The ramp detector is configured as follows: Detect the slew rate of the first voltage source; Determine whether the slew rate of the first voltage source exceeds the programmed value; and In response to the slew rate of the first voltage source exceeding the programmed amount, an output signal with an assertion value is provided; and A level shifting circuit having a level shifting circuit input coupled to the output of the second component and a level shifting circuit output coupled to the input of the first component, the level shifting circuit also being coupled to the first voltage source and the ramp detector, and the level shifting circuit being configured as follows: The signal provided by the second component is converted from the second voltage domain to the first voltage domain, and the signal according to the second voltage domain is provided to the first component; When the slew rate of the first voltage source does not exceed the programmed value, the quiescent current of the level shifting circuit is limited by the current source; and In response to the output signal having the assertion value, the current source is bypassed.

16. The electrical system of claim 15, wherein the current source is a first current source, and the level shifting circuit comprises: The first arm includes a first transistor, a second transistor, a first current source, a third transistor, and a first diode-coupled transistor stack as a first part of a cross-coupled latch; as well as The second arm includes a fourth transistor, a fifth transistor, a second current source, a sixth transistor, and a second diode-coupled transistor stack, which are the second part of the cross-coupled latch.

17. The electrical system of claim 16, wherein the first transistor has a source adapted to be coupled to the voltage source, the fourth transistor has a source adapted to be coupled to the voltage source, a gate coupled to the drain of the first transistor, and a drain coupled to the gate of the first transistor, the second transistor has a drain coupled to the drain of the first transistor, the fifth transistor has a drain coupled to the drain of the fourth transistor, the first current source is adapted to be coupled between the source of the second transistor and ground, the second current source is adapted to be coupled between the source of the fifth transistor and ground, the third transistor has a drain coupled to the source of the second transistor and a source adapted to be coupled to ground, the sixth transistor has a drain coupled to the source of the fifth transistor and a source adapted to be coupled to ground, and both the third transistor and the sixth transistor are configured to receive a signal having an assertion value in response to a slew rate of the voltage source exceeding a programmed amount, the assertion value being sufficient to cause the third transistor and the sixth transistor to conduct current to bypass the first current source and the second current source.

18. The electrical system of claim 16, wherein the current source is a first current source, the voltage source is a first voltage source, and the ramp detector comprises: A diode having an anode coupled to the first voltage source and having a cathode; A seventh transistor having a gate coupled to the anode of the diode, a source coupled to the cathode of the diode, and a drain; The eighth transistor has a gate and a source adapted to be coupled to ground and a drain coupled to the cathode of the diode; A capacitor having a first terminal coupled to the cathode of the diode; A first current mirror has a first current mirror input coupled to the drain of the seventh transistor and a first current mirror output; A second current mirror has a second current mirror input coupled to the output of the first current mirror and a second current mirror output, the second current mirror being adapted to be coupled to the second voltage source; as well as A second current source is coupled between the output of the second current mirror and ground, and the output of the second current mirror is coupled to the third transistor.

19. The electrical system of claim 18, wherein the capacitor has a second terminal and the ramp detector includes a third current mirror having a third current mirror input coupled to the second terminal of the capacitor and a third current mirror output coupled to the second current mirror input.

20. The electrical system of claim 16, wherein the current source is a first current source, the voltage source is a first voltage source, and the ramp detector comprises: A capacitor having a first terminal adapted to be coupled to the first voltage source and having a second terminal; A first current mirror has a first current mirror input coupled to the second terminal of the capacitor and a first current mirror output; A second current mirror has a second current mirror input coupled to the output of the first current mirror and a second current mirror output, the second current mirror being adapted to be coupled to the second voltage source; as well as A second current source is coupled between the output of the second current mirror and ground, and the output of the second current mirror is coupled to the third transistor.

21. A level shifter, comprising: A level shifting circuit has the following characteristics: The first arm includes a first portion of a cross-coupled latch, a first diode-coupled transistor stack, and a first input transistor; The second arm includes a second portion of the cross-coupled latch, a second diode-coupled transistor stack, and a second input transistor; A first current source is adapted to be coupled between the first input transistor and ground; A second current source is adapted to be coupled between the second input transistor and ground; A first short-circuit transistor is adapted to be coupled across the first current source between the first input transistor and ground; as well as A second short-circuit transistor is adapted to be coupled across the second current source between the second input transistor and ground; as well as A ramp detector having a capacitor coupled to the first short-circuit transistor and the second short-circuit transistor via a current mirror, the ramp detector also having a ground gate transistor coupled to the capacitor.

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