Flash memory block retirement strategy

Abstract

Apparatuses and techniques for flash memory block retirement policies are disclosed herein. In an example embodiment, a first memory block is de-commissioned in response to encountering read errors exceeding a first error threshold in the first memory block. Recoverable data is copied from the first memory block to a second memory block. During each of a plurality of iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to the page exhibiting no read errors exceeding a second error threshold during the plurality of iterations, the first memory block is returned to a use state.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Application No. 15 / 690,903, filed August 30, 2017, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile memory and non-volatile memory.

[0004] Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM).

[0005] Non-volatile memory can retain stored data when no power is supplied, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistive variable memory (e.g., phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM)) or 3D XPoint. TM Memory, etc.

[0006] Flash memory is used as a non-volatile memory for a wide range of electronic applications. Flash memory devices typically contain one or more groups of single-transistor floating-gate or charge-trapping memory cells that allow for high memory density, high reliability, and low power consumption.

[0007] Two common types of flash memory array architectures include NAND architecture and NOR architecture, named after the logical form in which the corresponding basic memory cell configurations are arranged. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each floating-gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in series (source to drain) between the source line and the bit line.

[0008] Both NOR and NAND architecture semiconductor memory arrays are accessed via a decoder, which activates a specific memory cell by selecting a word line coupled to its gate. In a NOR architecture semiconductor memory array, once the selected memory cell is activated, its data value is placed on the bit line, causing different current flows depending on the programming state of the specific cell. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the drain-side select gate (SGD) line. A specified voltage (e.g., Vpass) drives the word line coupled to the gate of each group of unselected memory cells to operate each group of unselected memory cells as a pass transistor (e.g., to pass current regardless of its stored data value). The current then flows from the source line to the bit line through each series-coupled group, limited only by the selected memory cell in each group, placing the currently encoded data value of the selected memory cell on the bit line.

[0009] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be individually or collectively programmed into one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), which represents a data bit.

[0010] However, flash memory cells can also represent one of more than two programmed states, which allows for the manufacture of higher-density memory without increasing the number of memory cells, because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some instances, MLC can refer to a memory cell that can store two data bits per cell (e.g., one of four programmed states), three-level cells (TLCs) can refer to a memory cell that can store three data bits per cell (e.g., one of eight programmed states), and four-level cells (QLCs) can store four data bits per cell. MLC is used herein in its broader context and can refer to any memory cell that can store more than one data bit per cell (i.e., can represent more than two programmed states).

[0011] Traditional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor substrate. To increase memory capacity for a given area and reduce cost, the size of individual memory cells has been reduced. However, there are technological limitations to the reduction in the size of individual memory cells and therefore the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures (such as 3D NAND architecture semiconductor memory devices) are being developed to further increase memory density and reduce memory costs.

[0012] Such 3D NAND devices often comprise strings of memory cells series-coupled (e.g., drain-to-source) between one or more source-side select gates (SGS) near the source and one or more drain-side select gates (SGD) near the bit lines. In examples, the SGS or SGD may comprise one or more field-effect transistor (FET) or metal-oxide-semiconductor (MOS) structure devices, etc. In some examples, the string extends vertically through multiple vertically spaced layers containing corresponding word lines. Semiconductor structures (e.g., polysilicon structures) may extend near the string memory cells to form channels for the memory cells of the string. In examples of vertical strings, the polysilicon structure may take the form of vertically extending pillars. In some examples, the string may be “folded” and thus arranged relative to U-shaped pillars. In other examples, multiple vertical structures may be stacked on top of each other to form a stacked array of memory cell strings.

[0013] Memory arrays or devices can be combined to form the storage volume of a memory system, such as solid-state drives (SSDs) and universal flash memory (UFS). TM Multimedia Card (MMC) solid-state storage device, embedded MMC device (eMMC) TM SSDs, in particular, can be used as the primary storage device for computers, offering advantages over traditional hard drives with moving parts in areas such as performance, size, weight, robustness, operating temperature range, and power consumption. For example, SSDs can have reduced search times, latency, or other delays associated with disk drives (e.g., electromechanical latency). SSDs use non-volatile memory cells, such as flash memory cells, to eliminate the need for an internal battery supply, thus allowing for more versatile and compact disk drives.

[0014] An SSD may contain a number for a memory device (including a number for a die or logical cell (e.g., a logical cell number or LUN)) and may contain one or more processors or other controllers that perform the logical functions required to operate the memory device or interface with an external system. Such an SSD may contain one or more flash memory dies with memory arrays and peripheral circuitry on them. A flash memory array may contain blocks of memory cells organized into physical pages. In many instances, the SSD will also contain DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands from the host associated with memory operations (e.g., read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data) between the memory device and the host, or erase operations to erase data from the memory device).

[0015] Flash memory devices can exhibit data errors for several reasons. For example, a memory cell may fail to retain its previously programmed state over an extended period (e.g., when exposed to high temperatures). These types of errors are often referred to as "data retention" errors and are distinct from other data retention errors, where a number of program / erase (P / E) cycles have exceeded a certain expected maximum. In other cases, if the temperature of the memory cell differs significantly from the temperature of the cell during programming, the state of the memory cell may be read incorrectly. This type of error is called a "cross-temperature" error, which may occur when the cell temperature during a programming cycle is significantly higher or lower than the cell temperature during a subsequent read cycle. Such errors can be common in varying and challenging environmental conditions, such as those encountered in mobile and automotive applications that may involve a wide range of operating temperatures.

[0016] Other errors can occur when reading memory cells, causing threshold voltage shifts in nearby memory cells and potentially affecting the ability to read those nearby cells. These "read interference" errors have become more problematic due to the increased density and speed of flash memory devices.

[0017] The aforementioned errors, as well as other errors not explicitly discussed herein, can be considered inherent because they typically occur due to a variety of conditions that can be expected during the use of the memory device. In contrast, other memory cell errors (such as memory cell defects that occur during the manufacture of the memory device) are inherently more unexpected or non-inherent, and therefore tend to be more permanent than inherent errors. Attached Figure Description

[0018] In diagrams that are not necessarily drawn to scale, similar numbers can describe similar components in different views. Similar numbers with different letter subscripts can represent different examples of similar components. The diagrams generally illustrate the various embodiments discussed in this document by way of example rather than limitation.

[0019] Figure 1 Describe an example of an environment that includes a memory device.

[0020] Figures 2 to 3 A schematic diagram illustrating an example of a 3D NAND architecture semiconductor memory array.

[0021] Figure 4 Illustrate the block diagram of the example memory module.

[0022] Figure 5 A flowchart illustrating an example method for implementing a block scrapping strategy for a memory array.

[0023] Figure 6 Explanation in Figure 5The flowchart shows the test method for memory blocks in the instance block scrapping policy method.

[0024] Figure 7 It is a block diagram illustrating an example of a machine on which one or more embodiments may be implemented. Detailed Implementation

[0025] In at least some of the example embodiments described below, a memory block may be tested to determine whether read errors exhibited by the memory block are temporary or more permanent. If read errors encountered in the memory block exceed a certain threshold or level, at least some data from the memory block may be stored elsewhere, and the memory block may be tested by repeatedly erasing, programming, and reading it to determine at the source whether the read errors are more temporary (and therefore potentially mitigated during the testing process) or more permanent. Based on this determination, the memory block may be returned to a usable state or permanently scrapped. In some example embodiments, a memory controller incorporated within a memory device containing the memory block may perform these operations, and thus the controller may be configured to have more control over one or more parameters of the erasure, programming, and reading processes of the memory device compared to a host device employing the memory device.

[0026] Electronic devices (such as mobile electronic devices (e.g., smartphones, tablets, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected electrical appliances or devices (e.g., Internet of Things (IoT) devices, etc.)) have storage requirements that vary particularly depending on the type of electronic device, the environment in which it is used, and performance expectations.

[0027] Electronic devices can be broken down into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); memory (e.g., one or more volatile or non-volatile random access memory (RAM) devices, such as dynamic RAM (DRAM), mobile or low-power double data rate synchronous DRAM (DDR SDRAM), etc.); and storage devices (e.g., non-volatile memory (NVM) devices, such as flash memory, read-only memory (ROM), SSD, MMC, or other memory card structures or combinations, etc.). In some instances, electronic devices may include a user interface (e.g., a display, touchscreen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor, or one or more transceiver circuits, etc.

[0028] Figure 1The description includes an example of an environment 100 containing a host device 105 and a memory device 110 configured to communicate via a communication interface. The host device 105 or the memory device 110 may be included in a variety of products 150 (e.g., Internet of Things (IoT) devices, such as refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.)) to support the processing, communication, or control of the product 150.

[0029] Memory device 110 includes a memory controller 115 and a memory array 120 comprising, for example, a plurality of individual memory dies (e.g., a three-dimensional (3D) NAND die stack). In 3D architecture semiconductor memory technology, stacking vertical structures increases the number of layers, physical pages, and therefore the density of memory devices (e.g., storage devices). In one example, memory device 110 may be a discrete memory or storage device component of host device 105. In other examples, memory device 110 may be a portion of an integrated circuit (e.g., a system-on-a-chip (SoC) etc.) stacked or otherwise incorporated with one or more other components of host device 105.

[0030] Data can be transferred between the memory device 110 and one or more other components of the host device 105 using one or more communication interfaces, such as Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Fast (PCIe) interface, Universal Serial Bus (USB) interface, Universal Flash Storage (UFS) interface, and eMMC. TM An interface or one or more other connectors or interfaces. Host device 105 may include a host system, electronic devices, a processor, a memory card reader, or one or more other electronic devices external to memory device 110. In some instances, host 105 may be equipped with... Figure 7 The machine 700 is a machine of some or all of the components described.

[0031] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array to, for example, transfer data to (e.g., write or erase) or from one or more memory cells, planes, sub-blocks, blocks, or pages of the memory array (e.g., read data). The memory controller 115 may include circuitry or firmware, comprising one or more components or integrated circuits. For example, the memory controller 115 may include one or more memory control units, circuitry, or components configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110. The memory controller 115 may include one or more input / output (I / O) circuitry, lines, or interfaces for transferring data to or from the memory array 120. The memory controller 115 may include a memory manager 125 and an array controller 135.

[0032] The memory manager 125 may include, in particular, circuitry or firmware, such as components or integrated circuits associated with various memory management functions. For the purposes of this description, example memory operation and management functions will be described within the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling (e.g., waste item collection or recycling), error detection or correction, block scrapping, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from the host) into device commands (e.g., commands associated with the operation of the memory array, etc.), or generate device commands for the array controller 135 or one or more other components of the memory device 110 (e.g., to perform various memory management functions).

[0033] The memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of the memory device 110 (e.g., various information associated with the memory array or one or more memory cells coupled to the memory controller 115). For example, management table 130 may contain information about block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) of one or more blocks of memory cells coupled to the memory controller 115. In some instances, a bit error may be referred to as an uncorrectable bit error if the number of detected errors in one or more of the error counts exceeds a threshold. Management table 130 may maintain counts of correctable or uncorrectable bit errors, etc.

[0034] The array controller 135 may include, in particular, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing data from the memory devices 110 coupled to the memory controller 115. Memory operations may be based on host commands received, for example, from the host 105 or generated internally by the memory manager 125 (e.g., in conjunction with wear leveling, error detection, or correction, etc.).

[0035] The array controller 135 may include an error correction code (ECC) component 140, which may in particular include an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells coupled to the memory controller 115. The memory controller 115 may be configured to proactively detect and repair errors associated with various operations or storage of data (e.g., bit errors, operational errors, etc.), while maintaining the integrity of data transferred between the host 105 and the memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., scrap) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0036] The memory array 120 may contain several memory cells arranged, for example, in devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and four or more planes per device. As another example, a 32GB MLC memory device (where each cell stores two data bits (i.e., four programmable states)) may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and four planes per device, but with half the required write time and twice the program / erase (P / E) cycles of a corresponding TLC memory device. Other examples may contain other numbers or arrangements. In some instances, the memory device or a portion thereof may selectively operate in SLC mode or in the desired MLC mode (e.g., TLC, QLC, etc.).

[0037] During operation, data is typically written to or read from the NAND memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as needed. The data transfer size of the NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a segment.

[0038] Although a data page may contain several bytes of user data (e.g., a data payload containing several data segments) and its corresponding metadata, the page size often refers only to the number of bytes used to store the user data. For example, a data page with a page size of 4KB may contain 4KB of user data (e.g., eight segments of 512B segment size) and several bytes of metadata corresponding to the user data (e.g., 32B, 54B, 224B, etc.), such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0039] Different types of memory cells or memory arrays 120 can provide different page sizes, or may require different amounts of metadata associated with them. For example, different memory device types may have different bit error rates, which can result in different amounts of metadata necessary to ensure the integrity of data pages (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data compared to a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than its corresponding single-level cell (SLC) NAND flash device. Therefore, an MLC device may require more metadata bytes for error data compared to its corresponding SLC device.

[0040] Figure 2 This is an example schematic diagram illustrating a 3D NAND architecture semiconductor memory array 200, which includes blocks (e.g., block A 201A, block B 201B, etc.) and sub-blocks (e.g., sub-block A0 201A0, sub-block A...). n 201A n Sub-block B0 201B0, Sub-block B n 201B n Several strings of memory units (e.g., the first to the third A0 memory strings 205A0 to 207A0, the first to the third A0, etc.) n Memory String 205A n To 207A n The first to third B0 memory strings 205B0 to 207B0, the first to third B n Memory String 205B n To 207Bn (etc.). Memory array 200 represents a large number of similar structures that would typically exist in other cells of a block, device, or memory device.

[0041] Each string of memory cells contains a Z-direction (source to drain) stacked on the source line (SRC) 235 or the source-side select gate (SGS) (e.g., first to third A0 SGS 231A0 to 233A0, first to third A0...). n SGS 231A n To 233A n First to third B0 SGS 231B0 to 233B0, first to third B n SGS 231B n To 233B n (etc.) and drain-side selection gates (SGD) (e.g., first to third A0 SGD 226A0 to 228A0, first to third A n SGD 226A n To 228A n First to third B0SGD 226B0 to 228B0, first to third B n SGD 226B n To 228B n Several layers of charge storage transistors (e.g., floating gate transistors, charge trapping structures, etc.) between the array. Each string of memory cells in the 3D memory array can be arranged as data lines (e.g., bit lines (BL) BL0 to BL2 220 to 222) along the X direction and as physical pages along the Y direction.

[0042] Within a physical page, each level represents a row of memory cells, and each string of memory cells represents a column. A sub-block may contain one or more physical pages. A block may contain several sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although described herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having eight levels of memory cells, in other instances, the memory array 200 may contain more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or levels. For example, each string of memory cells may contain more or fewer levels as needed (e.g., 16, 32, 64, 128, etc.) and one or more additional levels of semiconductor material above or below charge storage transistors (e.g., select gates, data lines, etc.). As an example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data per page (16,384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0043] Each memory cell in the memory array 200 includes control gates (CGs) coupled to (e.g., electrically or otherwise operably connected to) access lines (e.g., word lines (WL) WL00 to WL70 210A to 217A, WL01 to WL71 210B to 217B, etc.), which, as needed, jointly couple control gates (CGs) across a specific level or portion of a level. Specific levels and therefore specific memory cells in the 3D memory array can be accessed or controlled using appropriate access lines. Various select lines can be used to access select gate groups. For example, the A0 SGD line SGDA0 225A0 can be used to access the first to third A0SGD 226A0 to 228A0, and A... n SGD line SGDA n 225A n To access the first to third A n SGD 226A n To 228A n You can use B0 SGD lines SGDB0 225B0 to access the first to third B0 SGD lines 226B0 to 228B0, and you can use B n SGD line SGDB n 225B n To access the first to third B n SGD 226B n To 228B n The first to third A0, SGS 231A0 to 233A0, and the first to third A0 can be accessed using gate select lines SGS0 230A, SGS 231A0 to 233A0, and SGS 231A0 to 233A0.n SGS 231A n To 233A n Furthermore, the gate select lines SGS1230B can be used to access the first to third B0, SGS 231B0 to 233B0, and the first to third B0. n SGS 231B n To 233B n .

[0044] In an example, memory array 200 may include several layers of semiconductor material (e.g., polysilicon, etc.) configured to couple control gates (CGs) or select gates (or portions of CGs or select gates) for each memory cell of a corresponding level of the array. A combination of bit lines (BLs) and select gates, etc., can be used to access, select, or control a specific string of memory cells in the array, and one or more access lines (e.g., word lines) can be used to access, select, or control a specific memory cell at one or more levels within a specific string.

[0045] Figure 3 This is a schematic diagram illustrating a portion of a NAND architecture semiconductor memory array 300, which includes a plurality of memory cells 302 arranged in strings (e.g., first to third strings 305 to 307) and layers (e.g., illustrated as corresponding word lines (WL) WL0 to WL7 310 to 317, drain-side select gate (SGD) line 325, source-side select gate (SGS) line 330, etc.) in a two-dimensional array, and a sense amplifier or device 360. For example, the memory array 300 may illustrate, for example... Figure 2 This is a schematic diagram illustrating an example of a portion of a physical page of a memory cell in a 3D NAND architecture semiconductor memory device.

[0046] Each memory cell is coupled to a source line (SRC) 335 using a corresponding source-side select gate (SGS) (e.g., first to third SGS 331 to 333) and to a corresponding data line (e.g., first to third bit lines (BL) BL0 to BL2 320 to 322) using a corresponding drain-side select gate (SGD) (e.g., first to third SGD 326 to 328). Although in Figure 3 The example is described as having 8 levels (e.g., using word lines (WL) WL0 to WL7 310 to 317) and three data lines (BL0 to BL2 320 to 322), but other examples may contain strings of memory cells with more or fewer levels or data lines as needed.

[0047] In a NAND architecture semiconductor memory array, such as instance memory array 300, the state of a selected memory cell can be accessed by sensing a change in current or voltage associated with a specific data line containing a selected memory cell 302. One or more drivers can be used to access (e.g., via control circuitry, one or more processors, digital logic, etc.) memory array 300. In an example, one or more drivers can activate a specific memory cell or group of memory cells by driving a specific potential to one or more data lines (e.g., bit lines BL0 to BL2), access lines (e.g., word lines WL0 to WL7), or select gates (depending on the type of operation desired to be performed on the specific memory cell or group of memory cells).

[0048] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses, etc.) may be applied to a selected word line (e.g., WL4) and thus to the control gates (e.g., the first to third control gates (CGs) 341 to 343 of the memory cell coupled to the selected word line). The programming pulse may begin, for example, at or near 15V, and in some instances may be increased by a large value during each programming pulse application. When the programming voltage is applied to the selected word line, a potential (e.g., a ground potential (e.g., Vss)) may be applied to the data line (e.g., bit line) and substrate (and thus the channel between the source and drain) of the target memory cell for programming, resulting in charge transfer from the channel to the floating gate of the target memory cell (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0049] In contrast, a pass voltage (Vpass) can be applied to one or more word lines having target non-programmable memory cells, or a suppressor voltage (e.g., Vcc) can be applied to data lines (e.g., bit lines) having target non-programmable memory cells to, for example, suppress charge transfer from the channel to the floating gate of such non-target memory cells. The pass voltage can be variable, depending, for example, on the proximity of the applied pass voltage to the target programmable word line. The suppressor voltage can comprise a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external source or power supply (e.g., a battery, an AC-to-DC converter, etc.).

[0050] As an example, if a programming voltage (e.g., 15V or higher) is applied to a specific word line (e.g., WL4), then a 10V pass voltage can be applied to one or more other word lines (e.g., WL3, WL5, etc.) to suppress programming of non-target memory cells, or to preserve values ​​stored on such memory cells that are not intended for programming. As the distance between the applied programming voltage and the non-target memory cell increases, the pass voltage required to avoid programming the non-target memory cell can decrease. For example, when a 15V programming voltage is applied to WL4, a 10V pass voltage can be applied to WL3 and WL5, an 8V pass voltage to WL2 and WL6, a 7V pass voltage to WL1 and WL7, etc. In other examples, the pass voltage or the number of word lines can be higher or lower, more or fewer.

[0051] The sensing amplifier 360, coupled to one or more of the data lines (e.g., the first, second, or third bit lines (BL0 to BL2) 320 to 322), can detect the state of each memory cell in the corresponding data line by sensing the voltage or current on the specific data line.

[0052] Between the application of one or more programming pulses (e.g., Vpgm), a verification operation can be performed to determine whether the selected memory cell has reached its intended programming state. If the selected memory cell has reached its intended programming state, further programming of it can be suppressed. If the selected memory cell has not yet reached its intended programming state, additional programming pulses can be applied. If the selected memory cell has not reached its intended programming state after a certain number of programming pulses (e.g., a maximum number), the selected memory cell or the string, block, or page associated with this selected memory cell can be marked as defective.

[0053] To erase a memory cell or group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) may be applied to the substrate of the target memory cell to be erased (and thus the channel between the source and drain) (e.g., using one or more bit lines, select gates, etc.), while the word line of the target memory cell is held at a potential such as ground (e.g., Vss), resulting in charge transfer from the floating gate of the target memory cell to the channel (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0054] Figure 4An example block diagram illustrating a memory device 400 includes a memory array 402 having a plurality of memory cells 404 and one or more circuits or components providing communication with the memory array 402 or performing one or more memory operations on the memory array 402. The memory device 400 may include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, input / output (I / O) circuitry 426, and a memory control unit 430.

[0055] The memory cells 404 of the memory array 402 can be arranged in blocks, such as first and second blocks 402A and 402B. Each block can contain sub-blocks. For example, the first block 402A can contain first and second sub-blocks 402A0 and 402A0. n Furthermore, the second 402B block may include the first and second sub-blocks 402B0 and 402B. n Each sub-block may contain several physical pages, and each page may contain several memory cells 404. Although described herein as having two blocks, each block having two sub-blocks, and each sub-block having several memory cells 404, in other instances, the memory array 402 may contain more or fewer blocks, sub-blocks, memory cells, etc. In other instances, the memory cells 404 may be arranged in rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, access lines 406, first data lines 410, or one or more select gates, source lines, etc.

[0056] The memory control unit 430 can control the memory operation of the memory device 400 based on one or more signals or instructions received on the control line 432 (including one or more clock signals or control signals indicating the operation to be performed, such as write, read, erase, etc.) or address signals (A0 to AX) received on one or more address lines 416. One or more devices external to the memory device 400 can control the values ​​of the control signals on the control line 432 or the address signals on the address lines 416. Examples of devices external to the memory device 400 may include (but are not limited to) a host, a memory controller, a processor, or Figure 4 One or more circuits or components not specified in the text.

[0057] The memory device 400 may use access lines 406 and first data lines 410 to transfer (e.g., write or erase) data to or from one or more memory cells 404 (e.g., read) data. Row decoder 412 and column decoder 414 may receive and decode address signals (A0 to AX) from address lines 416 to determine which memory cells 404 to access, and may provide signals to one or more of the access lines 406 (e.g., one or more of a plurality of word lines (WL0 to WLm)) or the first data lines 410 (e.g., one or more of a plurality of bit lines (BL0 to BLn), as described above.

[0058] The memory device 400 may include sensing circuitry, such as a sense amplifier 420, configured to determine (e.g., read) the value of data on memory cell 404, or to determine the value of data to be written to memory cell 404, using a first data line 410. For example, in a selected string of memory cells 404, one or more of the sense amplifiers 420 may read the logic level in the selected memory cell 404 in response to a read current flowing through the selected string to the data line 410 in the memory array 402.

[0059] One or more devices external to memory device 400 may communicate with memory device 400 using I / O lines (DQ0 to DQN) 408, address lines 416 (A0 to AX), or control lines 432. Input / output (I / O) circuitry 426 may use I / O lines 408 to transfer data values ​​into or out of memory device 400, for example, into or out of page buffer 422 or memory array 402, according to, for example, control lines 432 and address lines 416. Page buffer 422 may store data received from one or more devices external to memory device 400 before data is programmed into a relevant portion of memory array 402, or may store data read from memory array 402 before data is transferred to one or more devices external to memory device 402.

[0060] Column decoder 414 receives address signals (A0 to AX) and decodes them into one or more column select signals (CSEL1 to CSELn). Selector 424 (e.g., selector circuitry) receives the column select signals (CSEL1 to CSELn) and selects data in page buffer 422 representing the value of data to be read from or programmed into memory cell 404. The selected data can be transferred between page buffer 422 and I / O circuitry 426 using a second data line 418.

[0061] The memory control unit 430 may receive positive and negative supply signals from an external source or power source (e.g., an internal or external battery, an AC-to-DC converter, etc.), such as a supply voltage (Vcc) 434 and a negative supply (Vss) 436 (e.g., ground potential). In some instances, the memory control unit 430 may include a regulator 428 for providing positive or negative supply signals internally.

[0062] Figure 5 A flowchart illustrating an example method 500 for implementing a block scrapping strategy for a memory array (e.g., memory array 120). In the example embodiment described below, memory array 120 is a NAND flash memory array, as discussed in detail above. However, method 500 and other methods described below can be applied to other memory arrays, devices, or systems.

[0063] In an example embodiment where a NAND flash memory array is used, method 500 may be executed by memory controller 115 through operations performed in either or both of memory manager 125 and array controller 135 of memory device 110, and / or by memory control unit 430 of memory device 400. Other modules or structures besides those explicitly described herein may execute method 500 and other methods described below in other example embodiments.

[0064] In an example embodiment of method 500, a first memory block (e.g., memory blocks 201, 402) is read (operation 502), and a determination is made regarding whether one or more read errors exceeding a first error threshold are encountered (operation 504). In some example embodiments, operation 502 is initiated by a read command (or similar command) received from host 105 by memory controller 115. In other example embodiments, operation 502 may be initiated by memory controller 115 or another unit within the memory device (e.g., memory device 110, 400). For example, memory controller 115 may perform operation 502 as part of a memory "scrubbing" process, wherein memory controller 115 may read a previously written memory block to determine whether read errors found in the memory block exceed a certain threshold, and if so, the memory block may be erased and rewritten to reduce the number of read errors encountered during subsequent read operations. In some example embodiments, the memory controller 115 may perform one or more error handling techniques (e.g., changing the read voltage of one or more memory cells of the first memory block (e.g., control gate (CG) voltage), retrying read operations multiple times, and the like) to recover the data.

[0065] Also in method 500, if the number of read errors does not exceed a first error threshold, the remaining operations of method 500 can be omitted because the first memory block can be considered to have an acceptable number of read errors. Conversely, if the number of read errors exceeds the first error threshold, then processing of the first memory block continues, as described below. In an example embodiment, the first error threshold is an error threshold or level at which all errors in the memory block are correctable. In another example embodiment, the first error threshold is an error threshold or level at which at least one of the errors in the first memory block is uncorrectable. In an example embodiment, the ECC component 140 of the array controller 135 can be used to determine whether read errors in the first memory block are correctable or uncorrectable, as discussed above.

[0066] Assuming the number of read errors exceeds a first error threshold, memory controller 115 may (e.g., using memory manager 125) copy recoverable (e.g., correctable) data from the first memory block to a second memory block (e.g., memory blocks 201, 402) (operation 506). For example, if all data in the first memory block is correctable, then all data may be copied to the second memory block. If less than all data in the first memory block is correctable, then only a portion of the correctable data (e.g., less than the data in all pages of the first memory block) may be copied to the second memory block. In other example embodiments, all data in the first memory block may be copied to the second memory block, even if some data is uncorrectable. In some example embodiments, this information may be tracked through management table 130 of memory manager 135.

[0067] In an example embodiment, memory manager 125 may retrieve the second memory block from a “free set” of memory blocks (e.g., a set or group of memory blocks not currently assigned to be accessed by host 105) before copying recoverable data from the first memory block to the second memory block. Also in an example embodiment, memory manager 125 may temporarily or temporarily decommission the first memory block, or otherwise deactivate it (operation 508), thus preventing access to the first memory block via host 105.

[0068] After copying recoverable data from the first memory block (operation 506) and deactivating the first memory block (operation 508), the array controller 135 may repeatedly test the first memory block (operation 510) to determine whether the first memory block should be scrapped (operation 512). In an example embodiment described in more detail below, the array controller 135 may determine during testing whether any page in the first memory block exhibits several read errors exceeding a second error threshold (operation 512). Figure 3 Examples of at least a portion of the pages of the first memory block are depicted, as described above. The following text, in conjunction with... Figure 6 Some example embodiments of repeatedly testing a first memory block are described. In some example embodiments, the second error threshold may be an error threshold at which all read errors are correctable. In various example embodiments, the second error threshold may be the same as or different from the first error threshold.

[0069] If none of the pages of the first memory block exhibit a number of read errors exceeding the second error threshold, then the memory controller 115 may (e.g., using the memory manager 125) make the memory block available for use, for example, by returning the first memory block to the free set 514 (operation 514). Conversely, if one or more of the pages of the first memory block exhibit a number of read errors exceeding the second error threshold, then the memory controller 115 may permanently invalidate the first memory block (operation 516), thus preventing access to the first memory block via the host 105.

[0070] Although Figure 5 Operations 502 to 516 are presented in a specific order, but other execution orders of operations 502 to 516 are possible, including simultaneous, parallel, or overlapping execution of two or more of operations 502 to 516. For example, copying data from a first memory block to a second memory block (operation 506) may occur after or simultaneously with deactivating the first memory block (operation 508).

[0071] In the example implementation, Figure 5 Operations 506 to 516 can be performed as background operations, or in a background mode while the memory device 110 is operating and not processing an access request to the memory array 120 from the host 105. For example, in which the memory device 110 supports eMMC... TM In a standard example implementation, operations 506 to 516 can be performed as background operations (BKOPS).

[0072] Figure 6 Explanation in Figure 5 The flowchart shows the instance method 600 for testing memory blocks in the instance block scrapping policy method 500. In the example embodiment, Figure 6 Operations 602 to 614 are used as instances of repeatedly testing the first memory block (e.g., memory blocks 201, 402). Figure 5 Operation 510).

[0073] In method 600, at the beginning of each of one or more repetitions, memory controller 115 may (e.g., via array controller 135) cause an erase of the first memory block (operation 602) and then program or write to the first memory block (operation 604). In some exemplary embodiments, erasing the first memory block is performed as a single block-level erase. Also in exemplary embodiments, although each byte, word, or other individually addressable location of the first memory block may carry individual data, the actual write operation may occur on a page-by-page basis or even on an entire block basis. In other exemplary embodiments, the write data may occur in other increments of the first memory block. As indicated above, the pages written to the first memory block may also include: writing ECC data to facilitate the reading and associated correction of bit errors associated with said pages.

[0074] In exemplary embodiments, the data written to each page of the first memory block can take any number of forms. For example, since erasing data can result in all data being read as 1, the data written to each page can be all 0, alternating between 1 and 0, or any other type. Furthermore, in some exemplary embodiments, the data written to each page can vary over time.

[0075] During each iteration, after programming the first memory block 604 (operation 604), the array controller 135 may read each page of the first memory block (operation 606) and may use the ECC code stored in the page to correct bit errors in the read data (e.g., using ECC component 140). In one example embodiment, a page may be read once using a nominal or default read voltage (e.g., control gate (CG) voltage) that is generally expected to provide a significant voltage threshold margin to present the lowest raw bit error rate (RBER). In other example embodiments, the page may employ an enhanced read mode, during which each page may be read one or more times during each iteration using one or more different read voltages. For example, a page may be read multiple times using different read voltages with respect to a certain nominal or default read voltage level, such that a specific read voltage providing the maximum read window budget (RWB) and therefore the lowest RBER can be used when determining whether the first memory block should be scrapped or retained.

[0076] Based on each page read, the memory controller 115 can determine, via the array controller 135 and ECC component 140, whether the page read error exceeds a second error threshold (operation 608). In an example embodiment where each page is read only once during a repetition, the memory controller 115 can determine that the page read error exceeds the second error threshold during the single read operation. In an example embodiment where each page is read multiple times, for example using one or more read voltages, if the second error threshold is exceeded for each read operation during a particular repetition, then the memory controller 115 can determine that the page read error exceeds the second error threshold. This example can help prevent excessive scrapping of memory blocks (sometimes referred to as "overkill"), which unnecessarily limits the number of memory blocks available to the host 105. In other examples, if the second error threshold is exceeded during at least a minimum number (e.g., one, two, etc.) of read operations during a particular repetition, then the memory controller 115 can determine that the page read error exceeds the second error threshold.

[0077] Based on the determination during the current iteration that at least one page of the first memory block contains read errors exceeding the second error threshold, the memory controller 115 may determine that the first memory block should be permanently scrapped (operation 610) and continue until... Figure 5 Operation 512. Otherwise, based on the determination that none of the pages of the first memory block contain read errors exceeding the second error threshold, the memory controller 115 may then determine whether any further iterations should be performed (operation 612). If so, then the memory controller 115 may continue erasing (operation 602) and programming (operation 604) the first memory block, and continue as described above. Otherwise, if no further iterations should be performed, then the memory controller 115 may determine that the first memory block is ready for use (operation 614). In some example embodiments, upon continuing to... Figure 5 Before operation 512 of method 500, the memory controller 115 can erase the first memory block again. Figure 6 Method 600 employs any number of repetitions (e.g., once, twice, five times, ten times, etc.).

[0078] Therefore, by employing at least some of the exemplary embodiments described above, memory blocks exhibiting a specific level of read errors can be deactivated (at least temporarily) and tested during background operating modes, for example. Based on these tests, it can be determined whether the read errors are more likely to be non-inherent (and therefore less likely to be remediable) or inherent (and therefore do not represent a permanent or chronic failure mode). Correspondingly, memory blocks primarily with inherent errors can be recovered (e.g., via erasure) and returned to an active operating state, while memory blocks primarily with non-inherent errors can be permanently scrapped to improve the overall RBER and performance level of the memory device 110. Such exemplary embodiments are particularly beneficial for memory devices used in harsh environmental conditions typically encountered, such as those in mobile and automotive applications, by distinguishing between read errors that may be a temporary result of a particular operating environment and those that may be more chronic.

[0079] Figure 7 The block diagram illustrating instance machine 700 shows any or more of the techniques (e.g., methodologies) discussed herein that can be executed on instance machine 700. In alternative embodiments, machine 700 may operate as a standalone device or be connectable (e.g., networked) to other machines. In a network deployment, machine 700 may operate as a server machine, a client machine, or both in a server-client network environment. In an instance, machine 700 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 700 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, IoT device, automotive system, or any machine capable of executing instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while only a single machine is illustrated, the term "machine" should also be considered as any collection of machines that individually or jointly execute sets of instructions (or multiple sets of instructions) to perform any or more of the methodologies discussed herein, such as cloud computing, Software as a Service (SaaS), and other computer cluster configurations.

[0080] The examples described herein may include logic, components, devices, packages, or mechanisms or operable thereof. A circuit system is a collection (e.g., set) of circuits implemented in a tangible physical body containing hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system may vary over time and with the variability of its underlying hardware. A circuit system contains components that can perform specific tasks individually or in combination during operation. In some examples, the hardware of a circuit system may be designed immutably to perform specific operations (e.g., hardwired). In some examples, the hardware of a circuit system may contain variablely connected physical components (e.g., execution units, transistors, simple circuits, etc.) containing computer-readable media that are physically modified (e.g., magnetically, electrically, movable placement of particles in an immutable concentration, etc.) to encode instructions for specific operations. When connecting physical components, the basic electrical properties of the hardware composition, for example, change from insulator to conductor, or vice versa. Instructions enable the components of the participating hardware (e.g., execution units or loading mechanisms) to establish the circuit system within the hardware via variable connections to perform specific tasks during operation. Thus, the computer-readable media is communicatively coupled to other components of the circuit system during device operation. In this example, any of the physical components can be used in more than one part of more than one circuit system. For instance, under operation, the execution unit can be used in a first circuit of a first circuit at one point in time and reused by a second circuit in the first circuit, or reused by a third circuit in the second circuit at a different time.

[0081] Machine (e.g., computer system) 700 may include a hardware processor 702 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), main memory 704, and static memory 706, some or all of which may communicate with each other via interconnect (e.g., bus) 708. Machine 700 may further include a display unit 710, an alphanumeric input device 712 (e.g., a keyboard), and a user interface (UI) navigation device 714 (e.g., a mouse). In an example, the display unit 710, the input device 712, and the UI navigation device 714 may be a touch screen display. Machine 700 may additionally include a storage device (e.g., a drive unit) 716, a signal generation device 718 (e.g., a speaker), a network interface device 720, and one or more sensors 716, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 700 may include an output controller 728 (e.g., serial (e.g., Universal Serial Bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC) etc.)) connected) to communicate with or control one or more peripheral devices (e.g., printer, card reader, etc.).

[0082] Storage device 716 may include machine-readable medium 722 thereon storing one or more sets of data structures or instructions 724 (e.g., software) that embody or utilize any or more of the techniques or functions described herein. Instructions 724 may also reside wholly or at least partially within main memory 704, static memory 706, or hardware processor 702 during execution by machine 700. In an example, one or any combination of hardware processor 702, main memory 704, static memory 706, or storage device 716 may constitute machine-readable medium 722.

[0083] Although machine-readable media 722 is described as a single medium, the term "machine-readable media" may include a single medium or multiple media (e.g., a centralized or distributed database or associated cache and server) configured to store one or more instructions 724.

[0084] The term "machine-readable medium" may include any or more of the technologies capable of storing, encoding, or carrying instructions to be executed by machine 700 and causing machine 700 to perform the present invention, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory as well as optical and magnetic media. In examples, concentrated machine-readable media includes machine-readable media having a plurality of particles with invariant (e.g., rest) mass. Therefore, concentrated machine-readable media is not a transient propagation of signals. Specific examples of concentrated machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0085] Instructions 724 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage device 721, which can be accessed by memory 704 for use by processor 702. Memory 704 (e.g., DRAM) is typically fast but volatile, and therefore a different type of storage than storage device 721 (e.g., SSD), which is suitable for long-term storage, including when in a "shutdown" state. Instructions 724 or data used by the user or machine 700 are typically loaded into memory 704 for use by processor 702. When memory 704 is full, virtual space from storage device 721 can be allocated to supplement memory 704; however, because storage device 721 is typically slower than memory 704, and its write speed is typically less than half that of its read speed, using virtual memory can significantly degrade the user experience (as opposed to memory 704 (e.g., DRAM) due to storage device latency). Furthermore, using storage device 721 for virtual memory can significantly reduce the available lifespan of storage device 721.

[0086] In contrast to virtual memory, virtual memory compression (e.g., The core feature, "ZRAM," uses a portion of memory as compressed block memory to avoid paging of storage device 721. Paging occurs within the compressed block until it is necessary to write the data to storage device 721. Virtual memory compression increases the available size of memory 704 while reducing wear and tear on storage device 721.

[0087] Storage devices optimized for mobile electronic devices or mobile storage traditionally include MMC solid-state storage devices (e.g., microSD cards). TM (e.g., cards, etc.) MMC devices contain several parallel interfaces to the host device (e.g., 8-bit parallel interfaces) and are typically removable and detachable components from the host device. In contrast, eMMC... TM The device is attached to the circuit board and is considered a component of the host device; its read speed is comparable to that based on Serial ATA. TM Comparable to SSDs with (Serial ATA (Advanced Technology) or SATA) interfaces. However, the demand for mobile device performance continues to grow, such as fully enabling virtual or augmented reality devices and taking advantage of ever-increasing network speeds. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices, which include the controller and firmware, use a Low Voltage Differential Signaling (LVDS) serial interface with a dedicated read / write path to communicate with the host device, thereby further advancing read / write speeds.

[0088] Furthermore, instructions 724 can be transmitted or received via communication network 726 using any of several transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) through network interface device 720 using a transmission medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), simple old-style telephone (POTS) networks, and wireless data networks (e.g., referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as The network interface device 720 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 726. In an example, the network interface device 720 may include multiple antennas to wirelessly communicate using at least one of Single-Input Multiple-Output (SIMO), Multiple-Input Multiple-Output (MIMO), or Multiple-Input Single-Output (MISO) technologies. The term "transmission medium" should be considered to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 700, and containing digital or analog communication signals or other intangible media to facilitate communication of the software.

[0089] The detailed description above includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate that only examples of the elements shown or described are provided herein. Furthermore, the inventors also contemplate examples using any combination or arrangement of the elements (or aspects thereof) shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0090] In this document, any other examples or uses independent of "at least one" or "one or more," such as the terms "(a)" or "an" commonly found in patent documents, are used to include one or more. In this document, the term "or" is used to refer to a non-exclusive "or," such that "A or B" may include "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "comprising" and "wherein" are used as concise English equivalents to the corresponding terms "including" and "wherein." Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process comprising elements other than those listed after this term in a claim is still considered within the scope of the claimed claim. Additionally, in the appended claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objectives.

[0091] In various instances, the components, controllers, processors, units, engines, or tables described herein may particularly include physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuitry, including processor groups or multi-core devices.

[0092] As used in this document, the term "horizontal" is defined as a plane parallel to, for example, a conventional plane or surface of a substrate that lies beneath a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction orthogonal to the horizontal as defined above. For example, the prepositions "on," "above," and "below" refer to conventional planes or surfaces defined on the top or exposed surface of a substrate, regardless of the substrate's orientation; and "on" is intended to indicate direct contact between a structure and another structure located "on" it (in the absence of an explicit indication of the contrary); the terms "above" and "below" are intended to identify the relative placement of structures (or layers, features, etc.), which explicitly includes, but is not limited to, direct contact between the identified structures unless so explicitly identified. Similarly, the terms "above" and "below" are not limited to horizontal orientation, because if a structure is the outermost part of the construction under discussion at a given point in time, then the structure may be "above" a reference structure, even if this structure extends vertically relative to the reference structure rather than being horizontally oriented.

[0093] In this document, the terms "wafer" and "substrate" are used to generally refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit fabrication. Therefore, the following specific embodiments should not be construed as limiting, and the scope of the various embodiments is defined only by the full scope of the appended claims, together with their equivalents.

[0094] Various embodiments of the present invention, and described herein, include memories utilizing vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives will be considered relative to the surface of the substrate on which the memory cells are formed (i.e., the vertical structure will be considered as extending away from the substrate surface, the bottom end of the vertical structure will be considered as the end closest to the substrate surface and the top end of the vertical structure will be considered as the end furthest from the substrate surface).

[0095] As used herein, directional adjectives such as horizontal, vertical, normal, parallel, orthogonal, etc., may refer to relative orientation and do not necessarily require strict adherence to specific geometric properties, unless otherwise specified. For example, as used herein, a vertical structure does not need to be strictly orthogonal to the surface of the substrate, but may alternatively be approximately orthogonal to the surface of the substrate, and may form an acute angle with the surface of the substrate (e.g., between 60 and 120 degrees, etc.).

[0096] In some embodiments described herein, different doping configurations may be applied to source-side selected gates (SGS), control gates (CG), and drain-side selected gates (SGD), each of which in this example may be formed of or at least contain polysilicon, resulting in these layers (e.g., polysilicon, etc.) having different etch rates when exposed to an etch solution. For example, in the process of forming a monolithic pillar in a 3D semiconductor device, SGS and CG may form recesses, while SGD may retain less or no recess. Thus, these doping configurations can be selectively etched into different layers (e.g., SGS, CG, and SGD) in the 3D semiconductor device using an etch solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0097] As used herein, operating a memory cell includes reading from a memory cell, writing to a memory cell, or erasing a memory cell. The operation of placing a memory cell in a desired state is referred to herein as “programming” and may include both writing to and erasing from a memory cell (e.g., a memory cell may be programmed to an erase state).

[0098] According to one or more embodiments of the present invention, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside the memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, count them when the operation of the memory device occurs, track the memory device operation that started it, evaluate the memory device characteristics corresponding to the wear state, etc.).

[0099] According to one or more embodiments of the present invention, the memory access means may be configured to provide wear cycle information to the memory device for each memory operation. The memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0100] It will be understood that when a component is referred to as "on another component," "connected to another component," or "coupled to another component," it may be directly on, connected to, or coupled to another component, or there may be an intermediary component. In contrast, when a component is referred to as "directly on another component," "directly connected to another component," or "directly coupled to another component," there is no intermediary component or layer. If two components are shown in a diagram as having a line connecting them, then the two components may be coupled or directly coupled, unless otherwise indicated.

[0101] The methods described herein may be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, higher-level language code, or the like. This code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored, for example, during execution or at other times, on one or more volatile or non-volatile tangible computer-readable media. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical discs and digital video discs), magnetic tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSDs), universal flash storage (UFS) devices, embedded MMC (eMMC) devices, and the like.

[0102] Example 1 is a method for implementing a memory block scrapping strategy for a flash memory array, the method comprising: in response to encountering a read error exceeding a first error threshold in a first memory block of the flash memory array; temporarily deactivating the first memory block, the first memory block comprising a plurality of memory pages; copying recoverable data of the first memory block to a second memory block of the flash memory array; after deactivating the first memory block and copying the recoverable data of the first memory block to the second memory block, during each of a plurality of repetitions: erasing the first memory block; programming the first memory block after erasing the first memory block; reading the plurality of memory pages of the first memory block after programming the first memory block; and determining, during the reading of the plurality of memory pages, whether at least one of the plurality of memory pages exhibits a read error exceeding a second error threshold; and returning the first memory block to a usable state in response to the plurality of memory pages not exhibiting a read error exceeding the second error threshold during the reading of the plurality of memory pages during the plurality of repetitions.

[0103] In Example 2, the object of Example 1 optionally includes: permanently rendering the first memory block unusable in response to at least one of the plurality of memory pages exhibiting a read error exceeding the second error threshold during the plurality of repetitions.

[0104] In Example 3, the object of any or more of Examples 1 to 2 optionally includes: wherein the second memory block comprises a memory block from a free memory block set region, and the method further includes: returning the second memory block to a usable state after copying the recoverable data of the first memory block to the second memory block.

[0105] In Example 4, the object of any or more of Examples 1 to 3 optionally includes: wherein returning the first memory block to a used state includes: returning the first memory block to a free memory block set area.

[0106] In Example 5, the subject matter of any or more of Examples 1 to 4 optionally includes: wherein the first error threshold includes a correctable error threshold, and the recoverable data of the first memory block includes all data of the first memory block.

[0107] In Example 6, the subject matter of any or more of Examples 1 to 5 optionally includes: wherein the first error threshold includes an uncorrectable error threshold, and the recoverable data of the first memory block includes less than all the data of the first memory block.

[0108] In Example 7, the subject matter of any or more of Examples 1 to 6 optionally includes: wherein the read error encountered in the first memory block occurs during a read operation employing the default read voltage of the control gate of each memory cell of the first memory block.

[0109] In Example 8, the subject matter of any or more of Examples 1 to 7 optionally includes: wherein the read error encountered in the first memory block occurs during a read operation employing a read voltage offset from the default read voltage of the control gate of each memory cell of the first memory block.

[0110] In Example 9, the object of any or more of Examples 1 to 8 optionally includes: wherein reading the plurality of memory pages of the first memory block includes: changing the read voltage of at least one of the plurality of memory pages during the plurality of repeated iterations.

[0111] In Example 10, the subject of Example 9 optionally includes: wherein the change in the read voltage is used to increase the read window budget during the multiple repetitions.

[0112] In Example 11, the object of any or more of Examples 1 to 10 optionally includes: receiving a read command from a host device to read the first memory block; performing a read operation on the first memory block in response to receiving the read command, wherein the encounter of the read error occurs during the read operation.

[0113] In Example 12, the subject matter of any or more of Examples 1 to 11 optionally includes: wherein the encounter with the read error occurs during an error cleanup process performed on the first memory block.

[0114] In Example 13, the subject matter of any or more of Examples 1 to 12 optionally includes: wherein the multiple repetitions occur during one or more time periods during which no command from the host for accessing the flash memory array is processed.

[0115] Example 14 is a data storage system comprising: a flash memory array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of memory pages; one or more hardware processors; and a memory storing instructions that, when executed by at least one of the one or more hardware processors, cause the data storage system to perform operations including: in response to encountering a read error exceeding a first error threshold in a first memory block of the flash memory array; deactivating the first memory block, the first memory block including a plurality of memory pages; copying recoverable data from the first memory block to a second memory block of the flash memory array; and deactivating the first memory block... After copying the recoverable data of the first memory block to the second memory block, during each of the multiple repetitions: erasing the first memory block; programming the first memory block after erasing the first memory block; reading the plurality of memory pages of the first memory block after programming the first memory block; determining whether at least one of the plurality of memory pages exhibits a read error exceeding a second error threshold during the reading of the plurality of memory pages; and returning the first memory block to a use state in response to the fact that the plurality of memory pages do not exhibit a read error exceeding the second error threshold during the reading of the plurality of memory pages during the multiple repetitions.

[0116] In Example 15, the subject matter of Example 14 optionally includes: the first error threshold includes an uncorrectable error threshold; and the encounter of the read error in the first memory block continues after an error handling process is performed on the first memory block.

[0117] In Example 16, the object of any or more of Examples 14 to 15 optionally includes: wherein reading the plurality of memory pages of the first memory block includes: changing the read voltage of at least one of the plurality of memory pages during the plurality of repeated iterations.

[0118] In Example 17, the subject matter of Example 16 optionally includes: wherein reading the plurality of memory pages of the first memory block comprises: reading each of the plurality of memory pages multiple times during the multiple repetitions while changing the read voltage.

[0119] In Example 18, the subject matter of any or more of Examples 14 to 17 optionally includes: wherein the flash memory array comprises a multilevel cell NAND memory array.

[0120] In Example 19, the subject matter of any or more of Examples 14 to 18 optionally includes: the flash memory array comprising a three-dimensional NAND memory array; and each of the plurality of memory pages of the three-dimensional NAND memory array comprising a vertically oriented two-dimensional memory cell array.

[0121] Example 20 is a non-transitory computer-readable data storage device that stores instructions, when executed by one or more hardware processors of a data storage system, causes the data storage system to perform operations including: in response to encountering a read error exceeding a first error threshold in a first memory block of a flash memory array: deactivating the first memory block, the first memory block comprising a plurality of memory pages; copying recoverable data of the first memory block to a second memory block of the flash memory array; after deactivating the first memory block and copying the recoverable data of the first memory block to the second memory block, during each of a plurality of repetitions: erasing the first memory block; programming the first memory block after erasing the first memory block; reading the plurality of memory pages of the first memory block after programming the first memory block; and determining, during the reading of the plurality of memory pages, whether at least one of the plurality of memory pages exhibits a read error exceeding a second error threshold; and returning the first memory block to a usable state in response to the plurality of memory pages not exhibiting a read error exceeding the second error threshold during the reading of the plurality of memory pages during the plurality of repetitions.

[0122] The foregoing description is intended to be illustrative and non-limiting. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the foregoing description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the detailed description above, various features may be grouped together to simplify the invention. This should not be construed as an expectation that the undisclosed features are essential to any claim. Rather, the subject matter of the invention may consist of fewer than all the features of the specifically disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and such embodiments are contemplated to be combined or arranged in various ways. The scope of the invention should be determined with reference to the appended claims together with the full scope of the equivalents granted by these claims.

Claims

1. A method for implementing a memory block scrapping strategy for a flash memory array, the method comprising: In response to a read error exceeding a first error threshold encountered in the first memory block of the flash memory array: Temporarily deactivate the first memory block, which includes multiple memory pages; Copy the recoverable data from the first memory block to the second memory block of the flash memory array; During each of the multiple repetitions following the removal of the first memory block from use and the copying of the recoverable data from the first memory block to the second memory block: Erase the first memory block; The first memory block is programmed after the first memory block is erased; After programming the first memory block, read the plurality of memory pages of the first memory block; and During the reading of the plurality of memory pages, it is determined whether at least one of the plurality of memory pages exhibits a read error exceeding a second error threshold; and In response to the fact that none of the plurality of memory pages exhibited a read error exceeding the second error threshold during the reads of the plurality of memory pages during the multiple repetitions, the first memory block was returned to the use state. During each of the multiple iterations, the programming of the first memory block after erasing the first memory block includes changing the data programmed into each of the multiple memory pages during each of the multiple iterations.

2. The method for implementing a memory block scrapping strategy for a flash memory array according to claim 1, further comprising: The first memory block is permanently rendered unusable in response to at least one of the plurality of memory pages exhibiting a read error exceeding the second error threshold during the plurality of repetitions.

3. The method for implementing a memory block scrapping strategy for a flash memory array according to claim 1, wherein the second memory block comprises a memory block from a free memory block set region, and the method further comprises: After the recoverable data of the first memory block is copied to the second memory block, the second memory block is returned to a usable state.

4. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, wherein returning the first memory block to a usable state comprises: The first memory block is returned to the free memory block set area.

5. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, wherein the first error threshold includes a correctable error threshold, and the recoverable data of the first memory block includes all data of the first memory block.

6. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, wherein the first error threshold includes an uncorrectable error threshold, and the recoverable data of the first memory block includes less than all the data of the first memory block.

7. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, wherein the encounter of the read error in the first memory block occurs during a read operation employing the default read voltage of the control gate of each memory cell of the first memory block.

8. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, wherein the encounter of the read error in the first memory block occurs during a read operation employing a read voltage offset from the default read voltage of the control gate of each memory cell of the first memory block.

9. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, wherein reading the plurality of memory pages of the first memory block comprises: During the repeated iterations, the read voltage of at least one of the plurality of memory pages is changed.

10. The method of claim 9 for implementing a memory block scrapping strategy for a flash memory array, wherein the change of read voltage is used to increase the read window budget during the multiple repetitions.

11. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, further comprising: Receive a read command from the host device to read the first memory block; A read operation is performed on the first memory block in response to receiving the read command, wherein the read error is encountered during the read operation.

12. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, wherein the encounter of the read error occurs during an error cleanup process performed on the first memory block.

13. The method for implementing a memory block scrapping strategy for a flash memory array according to any one of claims 1 to 3, wherein the multiple repetitions occur during one or more time periods during which no command from the host for accessing the flash memory array is processed.

14. A data storage system, comprising: A flash memory array comprising multiple memory blocks, each of which comprises multiple memory pages; One or more hardware processors; and A memory that stores instructions, which, when executed by at least one of the one or more hardware processors, cause the data storage system to perform operations including: In response to a read error exceeding a first error threshold encountered in the first memory block of the flash memory array: Release the first memory block from use; the first memory block includes multiple memory pages. Copy the recoverable data from the first memory block to the second memory block of the flash memory array; During each of the multiple repetitions following the removal of the first memory block from use and the copying of the recoverable data from the first memory block to the second memory block: Erase the first memory block; The first memory block is programmed after the first memory block is erased; After programming the first memory block, read the plurality of memory pages of the first memory block; and During the reading of the plurality of memory pages, it is determined whether at least one of the plurality of memory pages exhibits a read error exceeding a second error threshold; and In response to the fact that none of the plurality of memory pages exhibited a read error exceeding the second error threshold during the reads of the plurality of memory pages during the multiple repetitions, the first memory block was returned to the use state. During each of the multiple iterations, the programming of the first memory block after erasing the first memory block includes changing the data programmed into each of the multiple memory pages during each of the multiple iterations.

15. The data storage system according to claim 14, wherein: The first error threshold includes an uncorrectable error threshold; and The occurrence of the read error in the first memory block continues after the error handling process is performed on the first memory block.

16. The data storage system according to any one of claims 14 to 15, wherein reading the plurality of memory pages of the first memory block comprises: During the repeated iterations, the read voltage of at least one of the plurality of memory pages is changed.

17. The data storage system of claim 16, wherein reading the plurality of memory pages of the first memory block comprises: During the repeated cycles, the read voltage is changed while each of the plurality of memory pages is read multiple times.

18. The data storage system according to any one of claims 14 to 15, wherein the flash memory array comprises a multilevel cell NAND memory array.

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