Wafer sensitivity determination and communication

Abstract

The present disclosure relates to wafer sensitivity determination and communication. For example, a method includes receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method also includes generating, by the one or more processors, sensitivity information based on determining that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with a write mask that is written for the IC chip design.

Description

Technical Field

[0001] This invention relates to generating mask design files that include wafer sensitivity information for photolithography manufacturing systems. Background Technology

[0002] Integrated circuit (IC) chips are manufactured using photolithography systems and corresponding manufacturing processes. Mask synthesis tools are used to generate mask designs for use during the photolithography process. Mask writing tools generate physical masks based on the mask designs. The physical masks are used during IC chip manufacturing based on the mask designs generated by the mask synthesis tools. The mask synthesis tools implement processes such as optical proximity correction (OPC) and inverse lithography (ILT) to generate the mask designs. The mask writing tools generate one or more masks that are used by the photolithography scanner to manufacture the IC chips. In one example, a set of masks is generated by the mask writing tool (device), where each mask defines a different layer within the IC chip. Masks can be generated by exposing or writing patterns onto a photoresist-coated mask blank. The mask writing tool exposes the mask blank to a pattern of light to form a pattern within a photosensitive material on the mask blank. Mask writing tools include deformable beam (VSB) or multi-beam mask writer (MBMW). The exposed mask blank is developed to generate the physical mask. Summary of the Invention

[0003] In one example, a method includes receiving an integrated circuit (IC) chip design and generating a wafer image and a wafer target based on the IC chip design using one or more processors. The method further includes generating sensitivity information based on determining the convergence of the wafer image and the wafer target using one or more processors, and outputting the sensitivity information. The sensitivity information is associated with a write mask that is written for use in the IC chip design.

[0004] In one example, a non-transitory computer-readable medium includes stored instructions that, when executed by a processor, cause the processor to receive an integrated circuit (IC) chip design and generate a wafer image and a wafer target based on the IC chip design. The processor further generates sensitivity information based on determining the convergence of the wafer image and the wafer target, and outputs the sensitivity information to a mask writing device.

[0005] In one example, a lithography system includes a memory and a processor coupled to the memory. The processor is configured to receive an integrated circuit (IC) chip design and generate a wafer image and a wafer target based on the IC chip design. The processor is further configured to generate sensitivity information based on determining the convergence of the wafer image and the wafer target, and output the sensitivity information to a mask writing device. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of embodiments thereof. The drawings are provided to give knowledge and understanding of embodiments of this disclosure and are not intended to limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0007] Figure 1 An example block diagram of a lithography system based on one or more examples is shown.

[0008] Figure 2 A flowchart illustrating a method for determining sensitivity information based on one or more examples is shown.

[0009] Figure 3 A flowchart illustrating a method for determining sensitivity information based on one or more examples is shown.

[0010] Figure 4 A flowchart illustrating a method for determining a sensitivity band based on one or more examples is shown.

[0011] Figure 5 Example sensitivity bands based on one or more examples are shown.

[0012] Figure 6 A flowchart illustrating a method for determining a sensitivity quantity based on one or more examples is shown.

[0013] Figure 7 Example sensitivity values ​​are shown based on one or more examples.

[0014] Figure 8 A flowchart is shown for a method for determining a sensitivity gradient based on one or more examples.

[0015] Figure 9 Example sensitivity gradients based on one or more examples are shown.

[0016] Figure 10 Flowcharts of various processes used during the design and manufacture of integrated circuits according to some embodiments of this disclosure are shown.

[0017] Figure 11 An abstract diagram of an example computer system operable according to embodiments of the present disclosure is shown. Detailed Implementation

[0018] This disclosure relates to aspects of chip sensitivity determination and communication.

[0019] Photolithography is a manufacturing process used to fabricate integrated circuit (IC) chips by exposing a mask (e.g., a photomask) placed on a substrate to a pattern of light. The mask is generated using a mask combining engine and a mask writing device. The photolithography process is performed by a photolithography system to manufacture IC chips. The photolithography system implements mask combining engines and mask writing devices during the manufacturing process. The mask combining engine performs processes such as optical proximity correction (OPC) and inverse lithography (ILT) to generate the mask. The mask combining engine generates the mask design based on the circuit design of the IC chip. For example, the mask combining engine determines the polygons (e.g., geometry) of the mask based on the IC chip's circuit design, which define a pattern of apertures (or openings or holes) within the mask.

[0020] During the mask writing process, a mask is generated based on a mask design. Mask writing equipment includes deformable beam (VSB) tools or multi-beam mask writer (MBMW) tools. During the manufacturing process, a mask is placed on a wafer (or substrate). Ultraviolet or other types of light are applied to the wafer. The mask blocks light in areas that do not correspond to an aperture, and allows light to pass through areas that correspond to the aperture. As light passes through the aperture, it exposes the photosensitive material on the wafer in the corresponding area. The exposed (or unexposed) areas are developed to remove some of the photoresist material, creating a pattern on the wafer. The patterned wafer is then exposed to etching and / or deposition processes to fabricate an IC chip.

[0021] In many lithography manufacturing systems, the separation between the mask synthesis engine and the mask writing device makes it difficult to achieve tight coupling between them, as both are implemented independently. In many instances, during the mask design-to-wafer manufacturing process, the mask synthesis engine generates a mask design and transmits a file containing that design to the mask writing device. For example, lithography information is transmitted from the mask synthesis engine to the mask writing device. The mask writing device uses this lithography information to write a physical mask that replicates the mask shape indicated by the mask geometry in the mask design file. During the mask writing process, errors may occur within the physical mask. These errors can negatively impact the final IC chip. However, because the mask synthesis engine and the mask writing device are independent, and the mask writing device is unaware of the IC chip design details, it is unaware of the impact of errors introduced during the mask writing process on the final IC chip.

[0022] The following describes an improved photolithography manufacturing process. For example, during the mask design phase, corresponding sensitivities (e.g., mask or wafer sensitivities) are determined. Sensitivity indicates the relative importance of different regions of the mask on the final IC chip. The sensitivity is transmitted from the mask synthesis engine to the mask writing device. For example, the mask synthesis engine packages the sensitivity information into a compressed file format, which is then transmitted to the mask writing device. Therefore, compared to other mask generation processes, the mask writing device can utilize the sensitivity information during mask generation to create masks with higher-quality wafers, thereby reducing computation and runtime impact.

[0023] Mask writing devices use sensitivity information to determine the relative importance of different parts of the mask. They determine which parts of the mask will be formed using a more precise writing algorithm and which parts can be formed using a faster and simplified but less precise algorithm. The mask writing device uses sensitivity information to determine the impact of the mask writing process on the manufactured IC chip and optimizes the mask for wafer quality (additionally or alternatively, mask quality). In various examples, determining and transmitting sensitivity information (enabling its use during the mask writing process) achieves higher yields and more successful production launches compared to IC chip manufacturing processes that do not specify and use sensitivity information.

[0024] Figure 1 A lithography system 100 according to one or more examples is shown. The lithography system 100 includes a mask synthesis engine 110 and a mask writing device 120. Furthermore, the lithography system 100 may also include a lithography scanning device 130. The lithography scanning device 130 is optional, and in some examples, the lithography scanning device 130 is omitted. The lithography system 100 includes one or more processing devices (e.g., Figure 11 Processing device 1102) and one or more memory devices (e.g., Figure 11 The main memory 1104 and / or machine-readable storage medium 1124). One or more processing devices execute instructions stored in one or more memory devices (e.g., main memory 1104 and / or machine-readable storage medium 1124). Figure 11 Instruction 1126) is used to receive IC chip designs, process IC chip designs to determine sensitivity, and generate physical masks.

[0025] The lithography system 100 receives an IC chip design and generates a mask design and sensitivity information based on the IC chip design. In addition, the lithography system 100 generates a physical mask based on the mask design and sensitivity information, and uses the physical mask to manufacture a printed wafer (substrate).

[0026] The mask compositing engine 110 receives an IC chip design (e.g., an IC chip design digital file). The IC chip design is received from a system connected to the lithography system 100 or an input device connected to the lithography system 100. In another example, the mask compositing engine 110 receives the IC chip design from memory. For example, the mask compositing engine 110 accesses memory to obtain the IC chip design. The mask compositing engine 110 processes the IC chip design to generate a mask design and sensitivity information. Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 8 Methods 200, 300, 400, 600 and 800 further describe the processes used to generate sensitivity information.

[0027] The mask compositing engine 110 transmits mask design and sensitivity information to the mask writing device 120. The mask compositing engine 110 transmits this information via a network (e.g., ...). Figure 11 The network 1120 transmits mask design and sensitivity information. In one example, the mask synthesis engine 110 includes one or more processors (e.g., processing device 1102) of a computer system (e.g., computer system 1100) and is coupled to the mask writing device 120 via a network (e.g., network 1120). In this example, the computer system of the mask synthesis engine 110 is physically separated from the mask writing device 120 and connected to the mask writing device 120 via a network. Furthermore, the computer system of the mask synthesis engine 110 and the mask writing device 120 are located in different physical locations from each other.

[0028] Mask design and sensitivity information can be transmitted in a common mask file or in a separate file. In one example, the mask compositing engine 110 packages the sensitivity information into a compressed file format, which is then transmitted to the mask writing device 120. Additionally or alternatively, the mask compositing engine 110 may transmit the mask design file and / or sensitivity information to the memory of the lithography system 100.

[0029] Mask compositing engine 110 includes one or more processing devices (e.g., Figure 11 Processing device 1102), which executes data stored in a memory device (e.g., Figure 11 Instructions in main memory 1104 and / or machine-readable storage medium 1124 (e.g., Figure 11 The instruction 1126) is used to receive IC chip design files and generate mask design files and sensitivity information.

[0030] Mask writing device 120 receives mask design files and sensitivity information. In one example, mask writing device 120 receives mask design files and sensitivity information from mask synthesis engine 110. In another example, mask writing device 120 accesses the memory device of lithography system 100 to obtain mask design files and sensitivity information.

[0031] The mask writing device 120 determines the relative importance of different parts of the mask based on sensitivity information. Furthermore, the mask writing device 120 generates a printing mask based on the mask design file and the sensitivity information. In one example, the relative importance of different parts of the mask corresponds to the precision of the operations used when generating the printing mask. For example, the mask writing device 120 determines which parts of the mask will be formed using writing operations with higher precision, and which parts of the mask can be formed using writing operations with lower precision. Using higher precision writing operations reduces errors in the printing mask compared to using lower precision writing operations. However, higher precision writing operations require more processing time and computational power compared to lower precision writing operations. Therefore, to mitigate errors within the printing mask and reduce the processing time and computational power used during the mask writing process, higher precision writing operations are selectively applied when generating the printing mask.

[0032] A printing mask can be generated from a mask blank (or substrate). The mask blank can be a silicon dioxide blank, etc. During the printing process, apertures (e.g., holes or openings) are formed in the mask blank based on polygon and sensitivity information from the mask design document. The mask blank is coated with a photoresist material. The photoresist material is exposed to an energy beam that interacts with it. The photoresist exposed to the energy beam becomes sensitive or insensitive to the chemical reactions of the following development processes (depending on the type of photoresist). Photoresist sensitive to the chemical reactions of the development process is removed during the development process, while photoresist insensitive to the chemical reactions of development is not removed to form the mask.

[0033] The energy beam applied to the photoresist can be an electron beam or a photon beam. An electron beam is applied by an electron beam writer, which focuses the electron beam onto the blank. A photon beam is applied by a laser writer. The energy beam is controlled based on the write operation. For example, mask writing device 120 uses write operations to control the position and energy of the photon beam to control which parts of the mask are exposed to the electron beam and the amount of energy applied to different parts of the mask. The accuracy of the write operation can be measured based on the degree to which the write operation reproduces the mask shape specified in the mask design document. In one example, different write operations determine different amounts of energy applied to different locations on the mask. Different amounts of energy correspond to different amounts of photoresist removed, creating shapes with different dimensions and / or orientations within the mask. Therefore, the write operation that generates a mask that most closely matches the mask shape specified in the mask design document can be considered to have the highest accuracy.

[0034] The mask is etched to remove the blank portion from which the photoresist coating has been removed. The etching process may include a liquid (e.g., wet) etching process or a plasma (e.g., dry) etching process. The etching process removes the blank portion from which the photoresist coating has been removed, forming an aperture (e.g., a hole or opening) within the mask blank.

[0035] Mask writing device 120 includes one or more processing devices (e.g., Figure 11 Processing device 1102), which executes data stored in a memory device (e.g., Figure 11 Instructions in main memory 1104 and / or machine-readable storage medium 1124 (e.g., Figure 11 The instruction 1126) is used to receive mask design documents and sensitivity information and generate a printing mask. In addition, the mask writing device 120 includes a mask writing tool (such as an electron beam writer or a laser writer) that applies an energy beam to the mask blank.

[0036] The photolithography scanning apparatus 130 receives a printed mask from the mask writing apparatus 120 to fabricate an IC chip. The photolithography scanning apparatus 130 positions the printed mask over a substrate and applies light to the substrate through the printed mask. The light passing through an aperture of the printed mask alters the properties of a corresponding portion of the photoresist material on the substrate. The light can be ultraviolet (UV) light or light of another wavelength. The altered portion of the photoresist material is then removed from the substrate during a subsequent development process. The developed substrate (e.g., a substrate on which a patterned mask is disposed) is exposed to etching and / or deposition processes during the IC chip fabrication process. In one example, multiple different patterned masks are applied to the substrate at different times during the IC chip fabrication process.

[0037] Different parts of an IC chip design may be more sensitive to photolithography processes than other parts. To indicate which parts of the IC chip design are more sensitive than others, sensitivity information is determined by the mask composition engine 110 and transmitted to the mask writing device 120. The sensitivity information provides an indication of the relative sensitivity of mask writing errors to different parts (e.g., polygons) of the IC chip design. The sensitivity information corresponds to the dimensional tolerances of different polygons within the IC chip design. During mask writing and wafer fabrication processes, polygons associated with lower tolerances are more prone to errors than polygons associated with higher tolerances. The sensitivity identified by the sensitivity information is used by the mask writing device 120 to determine the level of precision used when writing different areas of the mask. For example, the type of write operation used by the mask writing device 120 may be based on the sensitivity information. Therefore, areas associated with higher sensitivity can be written with more precise process control than those used to write areas associated with lower sensitivity, thereby saving processing time and computational power, while improving the accuracy of the printed mask compared to mask writing processes that use either high-precision or low-precision process control to write the entire mask.

[0038] Figure 2 A flowchart of a method 200 for generating sensitivity information according to one or more examples is shown. Method 200 is performed by a mask synthesis engine 110. At block 210, an IC chip design is received. For example, the mask synthesis engine 110 receives the IC chip design from another processing system, input device, or memory device. The chip design may be in a vector format (e.g., OASIS or GDS file format) or other file formats.

[0039] At box 220, the IC chip design is converted into a wafer image and a wafer target. In one example, mask compositing engine 110 converts the IC chip design into a wafer image and a wafer target. Converting the IC chip design into a wafer image includes converting the IC chip design into a mask representation and simulating the mask representation to generate a simulated mask and generate a corresponding wafer image from the simulated mask. The mask representation may include a level set format, a bitmap file format, or a polygon file format, etc. Converting the IC chip design into a wafer target includes identifying design polygons from the IC chip design and processing the design polygons to generate the wafer target. Processing the design polygons includes smoothing the polygons to form a printable representation, rasterizing the polygons, creating a level set interface representation of the polygons, and selecting one or more points or metrics on the wafer where the wafer image will be monitored.

[0040] At box 230, sensitivity information is generated based on determining that the wafer image and the wafer target converge. For example, mask synthesis engine 110 compares the wafer image and the wafer target to determine whether the wafer image converges with the wafer target, and determines sensitivity information based on the convergence of the wafer image and the wafer target. Comparing the wafer image with the wafer target includes: generating a pixelated representation of the wafer image and comparing the pixelated representation of the wafer image with the wafer target. The wafer image and the wafer target are determined to converge based on the difference between the pixelated representation of the wafer image and the wafer target being less than a threshold. In another example, comparing the wafer image with the wafer target includes sampling the wafer image. The sample is compared with a corresponding point within the wafer target, comparing the intensity of the sample with the corresponding point within the wafer target. The wafer image and the wafer target are determined to converge based on the intensity difference being less than a threshold. In one example, comparing the wafer image with the wafer target includes: comparing the width and / or spacing information of the wafer image within a corresponding threshold. The convergence of the wafer image and the wafer target is determined based on the width and / or spacing of the wafer image satisfying the corresponding threshold.

[0041] The mask synthesis engine 110 generates sensitivity information based on the determined mask image and mask target convergence. The sensitivity information indicates the relative sensitivity of different parts of the chip design to mask write errors. The sensitivity information can be represented by maps, tables, or other representations.

[0042] At box 240, sensitivity information is output to a mask writing device. For example, mask synthesis engine 110 transmits sensitivity information to mask writing device 120. The sensitivity information may be output as a vector file and / or as part of a vector file that includes the mask design.

[0043] Figure 3 A flowchart of a method 300 for generating sensitivity information according to one or more examples is shown. A mask synthesis engine 110 executes method 300. At block 310, an IC chip design is received. For example, the mask synthesis engine 110 receives the IC chip design from another processing system, an input device, or a memory device. The chip design may be in a vector format (e.g., OASIS or GDS file format).

[0044] At box 312, the IC chip design is converted into a wafer target. The wafer target can be a bitmap file or a polygon file, etc. The mask compositing engine 110 converts the IC chip design into a wafer target. In one example, converting the IC chip design into a wafer target includes: identifying design polygons within the IC chip design and processing the design polygons to generate the wafer target. Processing the design polygons includes: smoothing the polygons to create a printable representation, rasterizing the polygons, creating a level set interface representation of the polygons, and selecting one or more points or metrics within the IC chip design where the wafer image will be monitored.

[0045] At box 314, a mask representation is generated based on the IC chip design. The mask synthesis engine 110 generates the mask representation based on the IC chip design. In one example, generating the mask representation produces an initial mask representation, which can be optimized. A mask representation is generated based on the design polygons of the IC chip design. For example, the size of the design polygons is based on geometric rules and / or converted to other geometric representations. Alternative geometric representations include level set masks or rasterized masks.

[0046] At box 316, a mask representation is simulated to generate a wafer image. Mask compositing engine 110 simulates the mask representation to generate the wafer image. For example, the mask representation generated at box 314 is used to simulate a manufacturing process to generate a simulated manufactured wafer represented as a wafer image.

[0047] Complete box 312 is completed during a period that at least partially overlaps with one or more periods of complete box 314 and / or 316. In one example, complete box 312 is completed during a period that does not overlap with one or more periods of complete box 314 and / or 316.

[0048] At box 318, the wafer image is compared with a wafer target. For example, mask compositing engine 110 compares the wafer image and the wafer target. Comparing the wafer image with the wafer target includes generating a pixelated representation of the wafer image and comparing the pixelated representation of the wafer image with the wafer target. In another example, comparing the wafer image with the wafer target includes sampling the wafer image. The sample is compared with a corresponding point within the wafer target, and the intensity of the sample is compared with the intensity of the corresponding point within the wafer target. In one example, comparing the wafer image with the wafer target includes comparing the width and / or spacing of the wafer image with a corresponding threshold determined based on the wafer target.

[0049] At box 320, it is determined whether the wafer image and the target wafer will converge. Mask compositing engine 110 determines whether the wafer image and the target wafer will converge. In one example, convergence is determined based on the difference between the pixelated representation of the wafer image and the wafer target being less than a threshold. In another example, convergence is determined based on the intensity difference between the wafer image and the wafer target being less than a threshold. In yet another example, convergence is determined based on the width and / or spacing of the wafer image satisfying a corresponding threshold.

[0050] At box 322, the mask representation is modified based on the fact that the wafer image and the wafer target do not converge. The mask synthesis engine 110 modifies the mask representation based on the fact that the wafer image and the wafer target do not converge. Modifying the mask representation includes applying one or more of gradient-based optimization methods, perturbation (e.g., numerical gradient) optimization methods, and rule-based modifications. The purpose of these modifications is to converge the wafer image and the target. Modifications may also consider other constraints, such as mask rules. Mask rules may include minimum width and space, and the corresponding lithography or fabrication target of the lithography fabrication system and / or processing method. At box 316, the mask synthesis engine 110 simulates the optimized mask representation to generate an updated wafer image, which is compared with the wafer target at box 318. At box 318, the mask synthesis engine 110 determines whether the updated wafer image converges with the wafer target. Based on the determination that the updated wafer image does not converge with the wafer target, the loop including boxes 322, 316, 318, and 320 is repeated until it is determined that the updated wafer image converges with the wafer target.

[0051] At box 324, sensitivity information is generated based on determining the convergence of the wafer image and the wafer target. In one example, the mask synthesis engine 110 generates sensitivity information based on determining the convergence of the wafer image and the wafer target. A sensitivity image is determined based on the wafer image determined to converge with the wafer target. The sensitivity information indicates the relative sensitivity of different parts of the IC chip design to errors that may occur when writing the corresponding mask. Figure 4 , Figure 6 and Figure 8 Methods 400, 600, and 800 provide further details on generating sensitivity information.

[0052] At box 326, sensitivity information is output to a mask writing device. For example, mask compositing engine 110 transmits sensitivity information to mask writing device 120. The sensitivity information may be output as a vector file and / or a portion of a vector file including the mask design.

[0053] Methods 200 and 300 can correspond to Figure 10 The mask data preparation process involves 1032 steps. For example, when in... Figure 10 During the mask data preparation process 1032, when preparing the mask data, methods 200 and / or 300 are executed.

[0054] In one example, generating sensitivity information includes generating sensitivity bands. Based on one or more examples, Figure 4 A flowchart of a method 400 for generating sensitivity bands is shown, and Figure 5 An example sensitivity band is shown. Method 400 corresponds to... Figure 3Method 300, box 324. At box 410, sensitivity values ​​at one or more polygonal points of the wafer image are determined based on the determined convergence of the wafer image and the wafer target. Mask synthesis engine 110 determines the sensitivity values ​​by simulating a mask representation used to generate the wafer image determined to converge with the wafer target. During the simulation of the mask representation, mask edges are determined and perturbed to generate multiple images. Wafer generation metrics are compared for each image. For example, one or more edge placement errors and processor variation bandwidth are compared for each image. In one example, the image contour may cover one or more of the multiple images. The width of the outer envelope of the contour, adjacent to (e.g., close to) the perturbed location of the mask representation, can be measured. Sensitivity values ​​are determined based on a comparison of each edge of each polygon and assigned to each edge. In one example, sensitivity values ​​may be stored as offset values ​​along the corresponding points of the polygon. Offset values ​​are determined for each point along each polygon.

[0055] Sensitivity values ​​are expressed in units of change of perturbation applied to the mask representation based on the wafer image profile position reference. For example, a change in the wafer image profile can be represented in nanometers, and a change in mask perturbation (e.g., the distance the mask edge moves) can also be represented in nanometers. Therefore, a sensitivity value of 1 corresponds to a 1 nm change in the wafer image profile based on a 1 nm movement of the mask edge when the mask representation is perturbed. In one example, the sensitivity value may range from about 0 to about 10. In one or more instances, the sensitivity value may be greater than 10. As the sensitivity value increases, the likelihood of errors occurring within the printed mask increases. To mitigate errors within the printed mask and improve the accuracy of the mask manufacturing process, in examples using process variation bands, the envelope width, expressed in nanometers, is the sensitivity value.

[0056] At box 420, the size of the polygons represented by the mask is changed based on the sensitivity values. For example, the mask compositing engine 110 adjusts the size of the polygons represented by the mask outwards and inwards based on the corresponding sensitivity values ​​to determine the sensitivity band for each polygon. Example sensitivity bands are shown below. Figure 5 As shown. Each polygon point of each polygon has an associated sensitivity value. The sensitivity value can be a positive scalar value. The size of the polygons in the mask pattern is locally adjusted using a variable-size operation, such that each polygon point is offset from its corresponding original position by the corresponding sensitivity value in the outward normal direction. The size of the polygons in the mask pattern is further locally adjusted using a variable-size operation, such that each polygon point is offset from its corresponding original position by the corresponding sensitivity value in the inward normal direction. Sensitivity bands are generated by the inward and outward-sized polygons to generate sensitivity information.

[0057] In one example, during box 410, multiple offset values ​​(i.e., distances) are determined along each point of the polygon. In such an example, at box 420, the polygon is resized inwards and outwards based on each offset value. A sensitivity band can be determined for each polygon resized inwards and outwards. Alternatively, the sensitivity band can be determined based on the maximum, minimum, or average value of each polygon resized inwards and outwards.

[0058] Figure 5 Example sensitivity information for a mask design is shown. Sensitivity information can be transmitted using a vector-based format (e.g., OASIS or GDS file format). Region 510 of mask design 500 includes sensitivity bands 520-526 surrounding each mask polygon. Sensitivity bands 520-526 indicate the relative sensitivity of the corresponding region of the IC chip design to variations that may occur during the mask writing process and / or manufacturing of the IC chip. For example, sensitivity bands 520-526 indicate the sensitivity of different regions (e.g., polygons) of the mask to changes made during the mask writing process. The distance between sensitivity bands 520-526 can indicate different relative sensitivities. In one example, a larger distance corresponds to a region of lower sensitivity, while a smaller distance corresponds to a region of higher sensitivity. In one example, for a given mask perturbation, the sensitivity can be expressed as the edge placement error of the wafer image relative to the target image. Furthermore, the process variation band generated by the perturbation image can be used as mask sensitivity. The process variation band includes the outer envelope of the image contour overlaid with process variations, including images from out-of-focus conditions, overexposure, or underexposure conditions, and / or global bias mask conditions. In one or more examples, a sensitivity function that decreases with increasing sensitivity can be used to determine the width or offset of the sensitivity band relative to the mask edges (e.g., the edges of the polygon represented by the mask). Therefore, higher sensitivity corresponds to lower bandwidth.

[0059] Mask fabrication results that violate sensitivity band relationships include violations of wafer design parameters. Tighter bands (e.g., smaller distances between sensitivity bands) indicate that the wafer is more sensitive to mask variations in these regions. Looser bands (e.g., larger distances between sensitivity bands) indicate that the wafer is less sensitive to mask variations in these regions. Figure 5 As shown, the distance between sensitivity bands 524 and 525 is smaller than the distance between sensitivity bands 522 and 523 and the distance between sensitivity bands 520 and 521. Therefore, sensitivity bands 524 and 525 indicate areas of higher sensitivity than those indicated by sensitivity bands 520, 521, 522, and 523.

[0060] In one example, transmitting sensitivity information to the mask writing device 120 includes: sending information including, for example... Figure 5The example shows a mask design file for the sensitivity band, or the sensitivity band is sent in addition to the mask design file. However, in other embodiments, the distance between sensitivity bands 520-525 is transmitted as a vector file format (e.g., OASIS or GDS file format, etc.) instead of the sensitivity band itself to reduce the amount of information transmitted between the mask synthesis engine 110 and the mask writing device 120. The file size used to transmit the distance is smaller than the file size used to transmit the sensitivity band along with the mask design file. In one or more embodiments, uniform sensitivity values ​​are determined for polygon vertices that are adjacent to each other. In these embodiments, in addition to generating the complete outline of the polygon, sensitivity bandwidths at several specific key points along the polygon edge path can also be determined.

[0061] In one example, generating sensitivity information involves generating a change in the amount of change for different points along the polygon of the mask pattern. Figure 6 A flowchart of a method 600 for generating the amount of change is shown, and Figure 7 A mask pattern with example variations is shown. At block 610 of method 600, sensitivity at one or more polygon points is determined based on the determined convergence of the wafer image and the wafer target. Mask synthesis engine 110 determines the sensitivity values ​​by simulating a mask representation used to generate a wafer image determined to converge with the wafer target. During the simulation of the mask representation, mask edges are determined and perturbed to generate multiple images. Wafer generation metrics are compared for each image. For example, one or more of the following are compared: mask edge placement error and processor variation bandwidth. Sensitivity values ​​are determined based on the comparison performed on each polygon edge and assigned to each polygon edge. Sensitivity values ​​can be stored as offset values ​​along the corresponding points of the polygon. Offset values ​​are determined for each point along each polygon.

[0062] At box 620, an output file is generated that includes mask polygon points and associated sensitivity values. For example, in one example, the mask compositing engine 110 generates an output file that includes mask polygon points and associated sensitivity values. The output file can be a vector file. Alternatively, the output file can be in tabular format. In this example, the coordinates of points along the polygon are associated with the corresponding sensitivity values. The vector output file can be an OASIS file or a GDS vector file format, etc.

[0063] Figure 7 A mask design is shown that has associated local sensitivity values ​​(e.g., local variations) at different points along a polygonal pattern of the mask. The sensitivity values ​​can be indicated by the length of a line at each different point along the polygonal path (e.g., the mask edge). In one or more examples, the length of the line perpendicular to the mask edge is determined in relation to how it is referenced. Figure 4The method 400 determines the offset similarly, and is determined by... Figure 5 The sensitivity is indicated by a band. Regions of a mask pattern indicated by larger changes have lower sensitivity compared to regions indicated by smaller changes. In other examples, regions of a mask pattern indicated by larger changes have higher sensitivity compared to regions indicated by smaller changes. Figure 7 An example mask pattern 700 is shown. Region 710 of mask pattern 700 includes geometries (e.g., polygons) 712 and 714. Geometry 712 is associated with a variation 720, and geometry 714 is associated with a variation 722. In one example, because variation 722 is smaller than variation 720, geometry 714 is associated with higher sensitivity compared to geometry 712.

[0064] In one example, the sensitivity information generated by method 400 includes information similar to that generated by method 600. Furthermore, in one example, the sensitivity information generated by method 600 may include additional information compared to the sensitivity information generated by method 400. For example, the sensitivity information generated by method 600 can be determined using multiple lithographic metrics (e.g., edge placement errors and process variation bands). Therefore, multiple information sources can be stored for each point location along the polygon. For example, offset values ​​of bands for a specific metric can be stored, and / or multiple offset distances can be stored for each lithographic metric.

[0065] In one example, generating sensitivity information involves generating an image file with gradients that describe the sensitivity information. Figure 8 A flowchart of method 800 for generating image files and gradients is shown. Figure 9Example image file 900 shows a mask design with example gradients for different shadows and cross shadows shown in region 910. At block 810 of method 800, sensitivity values ​​at one or more polygon points are determined based on the wafer image and the determination of wafer target convergence. Mask synthesis engine 110 determines the sensitivity by simulating a mask representation used to generate a wafer image determined to converge with the wafer target. The mask representation of the converged wafer image is converted into a function representation of an image file (e.g., a bitmap file or other raster image file). For example, the mask representation is converted into a rasterized mask representation or a level set function representation. A level set function that represents an interface or polygon in two dimensions is a two-dimensional pixelated representation, where the location of the interface is defined as the location of the pixel value being a specific scalar value (such as 0). The interior of the polygon will have positive pixels, and the exterior will have negative pixels, and vice versa. Level set methods include fast travel and fast scan, etc. Level set methods generate level sets based on polygons within the mask representation. Each image file, represented by an image file function, is perturbed in the pixel domain, and a mask representation generated by the perturbed pixels is simulated to generate multiple images. Metrics are generated for each image and compared to produce a sensitivity value for each pixel. For example, this might involve comparing one or more edge placement errors and processor bandwidth variations for each image. This can be similar to... Figure 4 Method 400 describes the determination of one or more errors. In another example, one or more errors can be determined by comparing pixelated representations of the wafer image with each other and finding a range of values ​​at each pixel. This range will be larger if the wafer image is more sensitive to mask changes, and smaller if the wafer image is less sensitive to mask changes. In another example, the image is converted to a level set distance function, and then the ranges of these level set functions are used at each pixel. Furthermore, a sensitivity value is determined based on the comparison at each pixel and assigned to each pixel.

[0066] At box 820, an image file including gradients indicating sensitivity values ​​is generated. For example, mask compositing engine 110 generates an image file and corresponding gradients based on the sensitivity value of each pixel. The image file can be a bitmap or other rasterized image file type. Figure 9 Example image file 900 is shown with the gradient shown in region 910. The gradient is represented by different shades and crossshading. Each level of the gradient indicates a different sensitivity. The number of gradients corresponds to the level of precision. For example, for higher precision, more gradients are used compared to lower precision using fewer gradients. Fewer gradients use fewer data bits to convey the sensitivity representation for each pixel compared to more gradients. Figure 9As shown, the gradient within region 910 of image file 900 indicates the sensitivity value of the corresponding polygon. In one example, the number of gradient levels represents different sensitivity values. Regions associated with higher sensitivity values ​​are indicated by gradients having a greater number of gradient levels than regions associated with lower sensitivity values.

[0067] The above describes an improved photolithography manufacturing process. This improved process involves generating sensitivity information that indicates the relative importance of different regions of the mask on the final IC chip. This sensitivity information is transmitted from a mask synthesis engine to a mask writing device. For example, the mask synthesis engine packages the sensitivity information into a compressed file format, which is then transmitted to the mask writing device. Therefore, compared to other mask generation processes, the mask writing device can utilize the sensitivity information during mask generation to increase yield and wafers, thereby reducing computation and runtime impacts.

[0068] Figure 10 An example set of processes 1000 used during the design, verification, and manufacturing of articles of manufacture, such as integrated circuits, is shown to transform and verify design data and instructions representing integrated circuits. Each of these processes can be constructed and enabled as multiple modules or operations. The term "EDA" stands for "Electronic Design Automation." These processes begin with the creation of a product idea 1010 using information provided by a designer, which is then transformed to create an article of manufacture using a set of EDA processes 1012. When the design is complete, it is put into production 1034, where the artwork of the integrated circuit (e.g., a geometric pattern) is sent to a manufacturing prefabrication facility to create a mask set, which is then used to manufacture the integrated circuit. After production, semiconductor dies are manufactured 1036, and packaging and assembly processes 1038 are performed to manufacture the finished integrated circuit 1040.

[0069] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. Using Hardware Description Languages ​​(HDLs) (such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera), high-level abstractions are used to design circuits and systems. HDL descriptions can be translated into logic-level register-transfer-level (RTL) descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of abstraction (i.e., the less abstract description) adds more useful details to the design description, such as including more details about the described modules. Lower levels of abstraction (i.e., the less abstract descriptions) can be computer-generated, derived from design libraries, or created by another design automation process. An example of a specification language used to specify lower levels of abstraction for more detailed descriptions is SPICE, used for detailed descriptions of circuits with many analog components. Descriptions at each level of abstraction can be used by the corresponding tools at that layer (e.g., formal verification tools). Design processes can use... Figure 10 The sequence is shown in the diagram. The described process can be enabled by EDA products (or tools).

[0070] During system design phase 1014, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. The design can be divided into different types of modules or components at this stage.

[0071] During logic design and functional verification 1016, modules or components in a circuit are specified using one or more description languages, and the functional accuracy of that specification is checked. For example, components of a circuit can be verified to generate outputs that match the requirements of the specifications for the designed circuit or system. Functional verification can be performed using simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components referred to as a “simulator” or “prototype system” is used to accelerate functional verification.

[0072] During the synthesis and design process 1018 used for testing, HDL code is converted into a netlist. In some embodiments, the netlist can be a graphical structure, where the edges of the graphical structure represent components of the circuit, and the nodes of the graphical structure represent how the components are interconnected. Both HDL code and netlist are hierarchical manufactured goods that can be used by EDA products to verify that the integrated circuit performs according to a specified design during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Furthermore, the completed integrated circuit can be tested to verify that the integrated circuit meets specification requirements.

[0073] During netlist verification (1020), the netlist is checked to ensure it meets timing constraints and corresponds to the HDL code. During design planning (1022), the overall planar diagram of the integrated circuit is constructed, and timing and top-level routing are analyzed.

[0074] During layout or physical implementation 1024, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connection of circuit components via multiple conductors) occur, and cells can be selected from a library to enable specific logic functions. As used herein, the term "cell" can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be called modules or components and can be enabled in both physical structure and simulation. Parameters (such as size) are specified for the selected cells (based on "standard cells") and made available in the database for EDA products.

[0075] During the analysis and extraction phase 1026, circuit functionality is verified at the layout level, allowing for refinement of the layout design. During physical verification 1028, the layout design is checked to ensure that manufacturing constraints are correct (such as DRC constraints, electrical constraints, and lithographic constraints) and that the circuit functionality matches the HDL design specifications. During resolution enhancement 1030, the geometry of the layout is transformed to improve the fabrication of the circuit design.

[0076] During the production phase, data is created for the production of photolithography masks (if appropriate, after applying photolithography enhancement). During mask data preparation 1032, the "production" data is used to produce photolithography masks for manufacturing finished integrated circuits. In one example, based on... Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 8 Methods 200, 300, 400, 600, or 800 are used to generate a lithography mask. For example, generating a lithography mask includes determining mask design and sensitivity information through a mask synthesis engine 110, and writing a mask (e.g., a lithography mask) based on the mask design and sensitivity information.

[0077] Computer systems (such as) Figure 10 The storage subsystem of the computer system 1100 can be used to store programs and data structures used in some or all of the EDA products described herein, as well as the products developed using the physical and logical design of libraries and the use of libraries.

[0078] Figure 11 An example machine of computer system 1100 is shown, in which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate on the capabilities of a server or client machine in a client-server network environment, a peer-to-peer (or distributed) network environment, or a server or client machine in a cloud computing infrastructure or environment.

[0079] A machine can be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) specifying actions to be performed by that machine. Furthermore, while a single machine is shown, the term "machine" should also include a collection of machines that individually or jointly execute a set (or more) of instructions to perform any of the methods discussed herein.

[0080] Example computer system 1100 includes processing device 1102, main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), static memory 1106 (e.g., flash memory, static random access memory (SRAM)) and the like), and data storage device 1118, which communicate with each other via bus 1130.

[0081] Processing device 1102 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 1102 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1102 may be configured to execute instructions 1126 for performing the operations and steps described herein.

[0082] Computer system 1100 may also include a network interface device 1108 for communication via network 1120. Computer system 1100 may also include a video display unit 1111 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1112 (e.g., a keyboard), a cursor control device 1114 (e.g., a mouse), a graphics processing unit 1122, a signal generation device 1116 (e.g., a speaker), a video processing unit 1128, and an audio processing unit 1132.

[0083] Data storage device 1118 may include machine-readable storage medium 1124 (also referred to as non-transitory computer-readable medium) on which one or more sets of instructions 1126 or software embodying any one or more of the methods or functions described herein are stored. During execution by computer system 1100, the instructions 1126 may also reside wholly or at least partially in main memory 1104 and / or processing device 1102, which also constitute machine-readable storage media.

[0084] In some implementations, instruction 1126 includes instructions for implementing functions corresponding to this disclosure. Although machine-readable storage medium 1124 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine and processing device 1102 to perform any one or more methods of this disclosure. The term "machine-readable storage medium" should accordingly be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0085] Some of the parts described in detail above have already been given regarding the algorithms and symbolic representations of data bit manipulation within computer memory. These algorithmic descriptions and representations are methods used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm can be a series of operations that lead to a desired result. These operations require physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise processed. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0086] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise specified as is obvious from this disclosure, it should be understood that throughout the description, specific terms refer to the actions and processes of a computer system or similar electronic computing device that process and convert data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the memory or registers or other such information storage devices of the computer system.

[0087] This disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specifically constructed for the intended purpose, or may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each medium being connected to a computer system bus.

[0088] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used in conjunction with the programs taught herein, or it may be demonstrated that more specialized devices can be constructed to execute the methods. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0089] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform the process according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0090] In the foregoing disclosure, embodiments of this disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made thereto without departing from the broader spirit and scope of this disclosure as set forth in the following claims. Where elements are represented in the singular tense in this disclosure, more than one element may be shown in the drawings, and the same elements may be labeled with the same numerals. Therefore, the disclosure and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method comprising: Receiver integrated circuit (IC) chip design; A wafer image and wafer target are generated based on the IC chip design using one or more processors. Based on the fact that the difference between the wafer image and the wafer target is less than a threshold, it is determined that the wafer image and the wafer target converge. Sensitivity information is generated by the one or more processors based on determining the convergence of the wafer image and the wafer target; as well as The sensitivity information is output, wherein the sensitivity information is associated with a write mask that is written for use in the IC chip design.

2. The method according to claim 1, further comprising: Determine the mask design document based on the IC chip design; as well as The mask design file is output from the mask synthesis engine to the mask writing device, wherein the sensitivity information indicates the sensitivity of one or more polygons of the IC chip design to mask writing errors.

3. The method according to claim 1, further comprising: Generate a mask representation based on the IC chip design; as well as The mask representation is simulated to generate the wafer image.

4. The method according to claim 3, further comprising: The mask representation is modified based on the determination that the wafer image and the wafer target will not converge.

5. The method according to claim 1, wherein generating the sensitivity information comprises: Sensitivity values ​​at one or more points along a polygon within the IC chip design are determined by perturbing one or more edges within a mask representation corresponding to the wafer image.

6. The method according to claim 5, wherein generating the sensitivity information further comprises: The size of the polygon is changed based on the sensitivity value.

7. The method of claim 1, wherein generating the sensitivity information comprises: Determine one of the following within the IC chip design: the sensitivity band of the polygon, the amount of variation of the polygon, and the gradient level of the polygon.

8. A non-transitory computer-readable medium comprising stored instructions that, when executed by a processor, cause the processor to: Receiver integrated circuit (IC) chip design; Generate wafer images and wafer targets based on the IC chip design; Based on the fact that the difference between the wafer image and the wafer target is less than a threshold, it is determined that the wafer image and the wafer target converge. Sensitivity information is generated based on determining the convergence of the wafer image and the wafer target; as well as The sensitivity information is output to the mask writing device.

9. The non-transitory computer-readable medium of claim 8, wherein the processor further: Determine the mask design document based on the IC chip design; and The mask design file is output from the mask synthesis engine to the mask writing device.

10. The non-transitory computer-readable medium of claim 8, wherein the processor further: Generate a mask representation based on the IC chip design; and The mask representation is simulated to generate the wafer image.

11. The non-transitory computer-readable medium of claim 10, wherein the processor further modifies the mask representation based on determining that the wafer image and the wafer target will not converge.

12. The non-transitory computer-readable medium of claim 8, wherein generating the sensitivity information comprises: Sensitivity values ​​at one or more points along a polygon within the IC chip design are determined by perturbing one or more edges within a mask representation corresponding to the wafer image.

13. The non-transitory computer-readable medium of claim 12, wherein generating the sensitivity information further comprises: The size of the polygon is changed based on the sensitivity value.

14. The non-transitory computer-readable medium of claim 8, wherein generating the sensitivity information comprises: Determine one of the following within the IC chip design: the sensitivity band of the polygon, the amount of variation of the polygon, and the gradient level of the polygon.

15. A photolithography system, comprising: Memory; as well as A processor, coupled to the memory, is configured to: Receiver integrated circuit (IC) chip design; Generate wafer images and wafer targets based on the IC chip design; Based on the fact that the difference between the wafer image and the wafer target is less than a threshold, it is determined that the wafer image and the wafer target converge. Sensitivity information is generated based on determining the convergence of the wafer image and the wafer target; as well as The sensitivity information is output to the mask writing device.

16. The lithography system of claim 15, wherein the processor is further configured to: Determine the mask design document based on the IC chip design; and The mask design file is output to the mask writing device.

17. The lithography system of claim 15, wherein the processor is further configured to: Generate a mask representation based on the IC chip design; and The mask representation is simulated to generate the wafer image.

18. The lithography system of claim 17, wherein the processor is further configured to modify the mask representation based on determining that the wafer image and the wafer target will not converge.

19. The lithography system of claim 15, wherein generating the sensitivity information comprises: Sensitivity values ​​at one or more points along a polygon within the IC chip design are determined by perturbing one or more edges within a mask representation corresponding to the wafer image.

20. The lithography system of claim 15, wherein generating the sensitivity information comprises: Determine one of the following within the IC chip design: the sensitivity band of the polygon, the amount of variation of the polygon, and the gradient level of the polygon.

Images