An efficient method, system and storage medium for detecting floating gate defects in a memory array

Abstract

The application relates to the technical field of memories, and discloses a high-efficiency detection method and system for floating gate defects in a memory array and a storage medium, the method comprising the following steps: after performing an erasing operation on the memory array, writing data according to a chessboard algorithm; performing a voltage acceleration test; comparing threshold voltages of the memory cells with reference threshold voltages after the test; and determining whether defects exist according to a comparison result; and the application can effectively detect potential defects between adjacent memory cell floating gates in a word line of a memory array of a flash memory chip, and further improves the reliability of flash memory data.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and specifically to an efficient method, system, and storage medium for detecting floating gate defects in memory arrays. Background Technology

[0002] Data retention capability, durability, and interference immunity are important parameters for evaluating the reliability of flash memory chips. Among them, data retention capability refers to the ability of the data stored in the flash memory to be effectively read after a period of time without distortion or loss.

[0003] Figure 2 This is a structural diagram of adjacent memory cells on a word line. Due to the unavoidable defects in flash memory chips during the manufacturing process, such as... Figure 3 The image shows a cross-sectional view where, due to a manufacturing defect, the floating gates of two adjacent memory cells on the word line are not electrically completely isolated by the dielectric layer. Currently, the technical solution for detecting this type of manufacturing defect is to use CKBD (Checkerboard Pattern) test patterns to screen out abnormal chips. However, this solution can only detect some obvious defects, and the detected chips are then repaired or discarded. But for some defects, refer to... Figure 4 This is a potential defect between adjacent floating gates on the word line, which cannot be detected quickly and accurately using existing technologies. During subsequent use, it manifests due to repeated readings, writing, or high-temperature baking, causing data variation. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an efficient method, system, and storage medium for detecting floating gate defects in memory arrays. This method can effectively detect potential defects between floating gates of adjacent memory cells on word lines of flash memory chip arrays, greatly improving the reliability of Flash data.

[0005] The present invention solves the technical problem by adopting the following technical solution:

[0006] This invention provides an efficient method for detecting floating gate defects in a memory array, comprising:

[0007] After performing an erase operation on the storage array, data is written according to the chessboard algorithm;

[0008] Perform voltage acceleration testing, specifically including:

[0009] Select all word lines in the memory array and apply a preset voltage parameter.

[0010] Ground the source, drain, and substrate;

[0011] After the test, the threshold voltage of the storage cell is compared with the reference threshold voltage, and the result of the comparison is used to determine whether there is a defect.

[0012] Preferably, comparing the threshold voltage of the memory cell with a reference threshold voltage and determining whether there is a defect based on the comparison result specifically includes:

[0013] The threshold voltage of the storage cell with stored data of 0 is compared with the first reference threshold voltage, and the threshold voltage of the storage cell with stored data of 1 is compared with the second reference threshold voltage, respectively.

[0014] If the threshold voltage of a storage cell with 0 stored data is lower than the first reference threshold voltage, or the threshold voltage of a storage cell with 1 stored data is higher than the second reference threshold voltage, then the cell is considered defective.

[0015] Preferably, the preset parameter voltage is not less than 5V and the width is not less than 1s.

[0016] Preferably, the first reference threshold voltage is 8-12V, and the second reference threshold voltage is 2-6V.

[0017] Preferably, the preset parameter voltage is 9V and the width is 5s.

[0018] Preferably, the floating grid defect specifically includes leakage current caused by adhesion between adjacent floating grids on the word line.

[0019] The present invention also provides a system for efficiently detecting floating gate defects in a memory array, the system comprising a main control module, a controlled data input module, a controlled voltage input module, and a data comparison module that are matched and configured with each other;

[0020] The controlled data input module is configured to write target data to the storage array according to the control signal of the main control module;

[0021] The controlled voltage input module is configured to apply a target parameter voltage to the word lines of the storage array according to the control signal of the main control module.

[0022] The data comparison module is configured to compare the threshold voltage of the storage cell with stored data of 0 with the first reference threshold voltage, and the threshold voltage of the storage cell with stored data of 1 with the second reference threshold voltage, and output the comparison results to the main control module.

[0023] The main control module is configured to determine the received comparison results: if the threshold voltage of the storage cell with stored data of 0 is lower than the first reference threshold voltage or the threshold voltage of the storage cell with stored data of 1 is higher than the second reference threshold voltage, then the floating gate of the storage array is determined to be defective.

[0024] The present invention also provides an electronic device, comprising:

[0025] At least one processor; and

[0026] A memory communicatively connected to the at least one processor; wherein,

[0027] The memory stores instructions that can be executed by the at least one processor, which enables the at least one processor to perform the aforementioned efficient method for detecting floating gate defects in the memory array.

[0028] The present invention also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the aforementioned efficient detection method for floating gate defects in a storage array.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention provides an efficient method for detecting floating gate defects in a memory array, which can effectively detect potential defects between floating gates of adjacent memory cells on word lines of a flash memory chip memory array, reduce the occurrence of potential defects between word lines due to cyclic erasure, read, and high-temperature baking, and prevent data reading errors, thereby further improving the reliability of FLASH data.

[0031] The method provided by this invention amplifies and aggravates potential defects by enhancing the leakage current between adjacent floating gates on the word line, thereby enabling effective detection during the detection stage. The method is simple and fast, requires no additional circuit structure, is low in cost and high in efficiency, and has wide application value.

[0032] Other outstanding substantive features and significant advancements of this invention compared to the prior art are further described in detail in the Embodiments section. Attached Figure Description

[0033] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0034] Figure 1 This is a flowchart of the efficient detection method in Example 1;

[0035] Figure 2 This is a structural diagram of adjacent memory cells on a word line;

[0036] Figure 3 This is a cross-sectional view showing that the floating gates are not completely isolated by the dielectric layer.

[0037] Figure 4 A cross-sectional view of potential defects between adjacent floating grids on a word line;

[0038] Figure 5 This is a cross-sectional view of the charge leakage caused by the defect;

[0039] Figure 6 This is a schematic diagram of the system structure in Embodiment 2. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] It should be noted that certain names are used in the specification and claims to refer to specific components. It should be understood that those skilled in the art may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on substantial differences in function. As used in this specification and claims, "comprising" or "including" is an open-ended term and should be interpreted as "comprising but not limited to" or "including but not limited to". The embodiments described in the Detailed Description section are preferred embodiments of the present invention and are not intended to limit the scope of the invention.

[0042] Example 1

[0043] like Figure 1-5 As shown, this embodiment provides an efficient method for detecting floating gate defects in a memory array. Specifically, the floating gate defect is leakage current caused by adhesion between adjacent floating gates on the word line. Please refer to [reference needed]. Figure 5These are potential defects between adjacent floating gates on the word line, which cannot be detected quickly and accurately using existing technologies. Specifically, the charge stored in the floating gate of Cell-1 gradually decreases, leading to a lower threshold voltage for Cell-1. When the charge in the floating gate of Cell-1 decreases to a certain value, it becomes difficult to identify the data 0 in Cell-1. Simultaneously, the charge stored in the floating gate of Cell-2 gradually increases, leading to a higher threshold voltage for Cell-2. When the charge in the floating gate of Cell-2 increases to a certain value, it becomes difficult to identify the data 1 in Cell-2, thus causing data misreads during read operations and reducing the reliability of the flash memory. Current technologies can only detect relatively obvious defects in the floating gates of adjacent memory cells on the word line, allowing for the repair or replacement of the detected memory array. However, existing technologies cannot effectively detect potential defects between the floating gates of adjacent memory cells on the word line. Consequently, these potential defects manifest during subsequent use due to cyclic read / write operations and high-temperature baking, leading to data read errors.

[0044] In this embodiment, only the innovative design of the present invention is described in detail. As for the technical features that are the same as those in the prior art, they are not described in detail. Those skilled in the art can choose them as needed.

[0045] Please refer to Figure 1-5 This embodiment provides an efficient method for detecting floating gate defects in a memory array, comprising:

[0046] After performing an erase operation on the storage array, data is written according to the checkerboard algorithm. The checkerboard algorithm is a traditional memory testing method that is simple and fast, but has low coverage. Its basic process is to assign values ​​to the storage cells, ensuring that each storage cell has a different value from its adjacent storage cells. This divides the entire storage array into two parts: storage cells storing data 0 and storage cells storing data 1.

[0047] Perform voltage acceleration testing, specifically including:

[0048] Select all word lines in the memory array and apply a preset parameter voltage. The preset parameter voltage should be no less than 5V and the duration should be no less than 1s. The preferred parameter voltage is 9V and the duration is 5s.

[0049] Ground the source, drain, and substrate;

[0050] After the test, the threshold voltage of the storage cell is compared with the reference threshold voltage. The comparison result is used to determine whether there is a defect. Specifically, the threshold voltage of the storage cell is compared with the reference threshold voltage. The comparison result is used to determine whether there is a defect. Specifically, the threshold voltage of the storage cell with stored data of 0 is compared with the first reference threshold voltage, and the threshold voltage of the storage cell with stored data of 1 is compared with the second reference threshold voltage. The first reference threshold voltage is 8-12V, and the second reference threshold voltage is 2-6V.

[0051] If the threshold voltage of a storage cell with 0 stored data is lower than the first reference threshold voltage, or the threshold voltage of a storage cell with 1 stored data is higher than the second reference threshold voltage, then the cell is considered defective.

[0052] More specific explanation:

[0053] After erasing the storage array, CKBD (Checkerboard) data is written. After the CKBD data is written to the storage array, as follows... Figure 4 As shown, at this time, data 0 is written into storage cell Cell-1, and data 1 is written into storage cell Cell-2.

[0054] Select all word lines in the memory array, provide a high level with a voltage of 9V and a pulse width of 5s, while grounding the source, drain, and substrate, and perform voltage acceleration testing on the word lines.

[0055] like Figure 4 As shown, there is a small potential adhesion between the floating gates of memory cells Cell-1 and Cell-2. At this time, the charge in the floating gate of cell-1 is greater than the charge in the floating gate of cell-2. The different charges in the floating gates create a potential difference, and electrons will move from the floating gate of cell-1 to the floating gate of cell-2. Since there is only a very small adhesion between Cell-1 and Cell-2, the leakage current between the floating gates of Cell-1 and Cell-2 is very small. Using the existing detection methods, direct reading will show that the data stored in Cell-1 is still 0, and the data stored in Cell-2 is still 1. This kind of potential defect between adjacent floating gates on the word line cannot be detected.

[0056] This embodiment increases the potential difference between memory cells Cell-1 and Cell-2 by applying a 9V high-level voltage with a 5s pulse width to the word line. This increases the leakage current between adjacent floating gates on the word line, gradually aggravating and exposing potential defects between adjacent floating gates on the word line. Figure 5 As shown.

[0057] After applying a high-level voltage of 9V and a pulse width of 5s to the word line, the threshold voltage for storing data 1 in the memory array is compared with a standard threshold voltage one. If the threshold voltage of the memory cell storing data 0 is lower than the first threshold voltage, it indicates that charge has been lost in the floating gate, and this chip is marked as defective. The threshold voltage for storing data 1 in the memory array is compared with a standard threshold voltage two. If the threshold voltage of the memory cell storing data 1 is higher than the second threshold voltage, it indicates that charge has increased in the floating gate, and this chip is marked as defective.

[0058] Example 2

[0059] Please refer to Figure 6 This embodiment provides a system for efficiently detecting floating gate defects in a memory array, comprising: a main control module, a controlled data input module, a controlled voltage input module, and a data comparison module that are configured to be mutually matched, wherein:

[0060] The controlled data input module is configured to write target data to the storage array according to the control signals of the main control module;

[0061] The controlled voltage input module is configured to apply target parameter voltage to the word lines of the memory array according to the control signal from the main control module;

[0062] The data comparison module is configured to compare the threshold voltage of the storage cell with stored data of 0 with the first reference threshold voltage, and the threshold voltage of the storage cell with stored data of 1 with the second reference threshold voltage, and output the comparison results to the main control module.

[0063] The main control module is configured to judge the received comparison results: if the threshold voltage of the storage cell with stored data of 0 is lower than the first reference threshold voltage or the threshold voltage of the storage cell with stored data of 1 is higher than the second reference threshold voltage, then the floating gate of the storage array is determined to be defective.

[0064] Example 3

[0065] This embodiment provides an electronic device, including:

[0066] At least one processor; and

[0067] A memory communicatively connected to the at least one processor; wherein,

[0068] The memory stores instructions that can be executed by the at least one processor, which enables the at least one processor to perform the efficient detection method for floating gate defects in the memory array described in Embodiment 1.

[0069] Example 4

[0070] This embodiment provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the efficient detection method for floating gate defects in the storage array described in Embodiment 1.

[0071] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0072] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A highly efficient method for detecting floating gate defects in a memory array, characterized in that, The method includes: After performing an erase operation on the storage array, data is written according to the chessboard algorithm; Perform voltage acceleration testing, specifically including: Select all word lines in the memory array and apply a preset voltage parameter. Ground the source, drain, and substrate; After the test, the threshold voltage of the storage cell is compared with the reference threshold voltage, and the result of the comparison is used to determine whether there is a defect. The threshold voltage of the memory cell is compared with a reference threshold voltage, and the determination of whether there is a defect based on the comparison result specifically includes: The threshold voltage of the storage cell with stored data of 0 is compared with the first reference threshold voltage, and the threshold voltage of the storage cell with stored data of 1 is compared with the second reference threshold voltage, respectively. If the threshold voltage of a storage cell with 0 stored data is lower than the first reference threshold voltage, or the threshold voltage of a storage cell with 1 stored data is higher than the second reference threshold voltage, then the cell is considered defective.

2. The efficient detection method for floating gate defects in a memory array according to claim 1, characterized in that, The preset parameters are a voltage of not less than 5V and a width of not less than 1s.

3. The efficient detection method for floating gate defects in a memory array according to claim 1, characterized in that, The first reference threshold voltage is 8-12V, and the second reference threshold voltage is 2-6V.

4. The efficient detection method for floating gate defects in a memory array according to claim 2, characterized in that, The preset parameters are a voltage of 9V and a width of 5s.

5. The efficient detection method for floating gate defects in a memory array according to claim 1, characterized in that, The aforementioned floating grid defects specifically include leakage current caused by adhesion between adjacent floating grids on the word line.

6. A system for efficiently detecting floating gate defects in a memory array, characterized in that, The system includes a main control module, a controlled data input module, a controlled voltage input module, and a data comparison module that are matched and configured with each other. The controlled data input module is configured to write target data to the storage array according to the control signal of the main control module; The controlled voltage input module is configured to apply a target parameter voltage to the word lines of the storage array according to the control signal of the main control module. The data comparison module is configured to compare the threshold voltage of the storage cell with stored data of 0 with the first reference threshold voltage, and the threshold voltage of the storage cell with stored data of 1 with the second reference threshold voltage, and output the comparison results to the main control module. The main control module is configured to determine the received comparison results: if the threshold voltage of the storage cell with stored data of 0 is lower than the first reference threshold voltage or the threshold voltage of the storage cell with stored data of 1 is higher than the second reference threshold voltage, then the floating gate of the storage array is determined to be defective.

7. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which enables the at least one processor to perform the efficient detection method for floating gate defects in the memory array according to any one of claims 1-5.

8. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the efficient detection method for floating gate defects in the memory array according to any one of claims 1-5.

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