A method for fabricating an image sensor

Abstract

The present invention provides a method for fabricating an image sensor, comprising: providing a substrate, the substrate including a pixel region and a logic region located around the pixel region, wherein an interconnect structure is formed in the logic region of the substrate; forming a metal layer on a first surface of the substrate, the metal layer including a first portion covering the pixel region and a second portion covering the logic region, the second portion being electrically connected to the interconnect structure; etching the first portion to form a plurality of through-holes; conformally forming a passivation layer on the metal layer, and etching the passivation layer of the logic region to thin the passivation layer of the logic region; performing a planarization process on the passivation layer, wherein the passivation layer of the logic region is etched before the planarization process to reduce the thickness of the passivation layer of the logic region, improve the uniformity of the planarization process of the passivation layer, and thereby improve the uniformity of the image sensor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for fabricating an image sensor. Background Technology

[0002] Image sensors are back-illuminated sensors that convert optical images into electrical signals. Back-illuminated image sensors receive incident light from the back without wiring layers, avoiding the obstruction of incident light by metal lines and transistor structures. Compared with front-illuminated image sensors, they have higher dynamic range, faster data throughput, and better low-light imaging capabilities, and have become the mainstream image sensor.

[0003] With the development of technology, the application of far-infrared imaging is becoming increasingly widespread, such as in security monitoring, iris scanners, and time-of-flight (ToF) sensors. Back-illuminated image sensors are also becoming more widely used in industrial applications. Industrial applications require larger pixel units, but back-illuminated large-pixel image sensors suffer from poor device uniformity. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating an image sensor, thereby solving the problem of poor uniformity in image sensors.

[0005] To achieve the above objectives, the present invention provides a method for fabricating an image sensor, comprising:

[0006] A substrate is provided, the substrate including a pixel region and a logic region located around the pixel region, wherein an interconnect structure is formed in the logic region of the substrate;

[0007] A metal layer is formed on a first surface of the substrate, the metal layer comprising a first portion covering the pixel region and a second portion covering the logic region, the second portion being electrically connected to the interconnect structure;

[0008] The first portion is etched to form a plurality of through-hole first grooves;

[0009] A passivation layer is formed conformally on the metal layer, and the passivation layer of the logic region is etched to thin the passivation layer of the logic region;

[0010] The passivation layer is subjected to a planarization process;

[0011] A lens structure is formed on the passivation layer.

[0012] Optionally, before forming the metal layer on the first surface of the substrate, the method further includes:

[0013] The substrate is etched to form several deep trenches;

[0014] A reflective layer is formed on the substrate, the reflective layer at least filling the deep trench.

[0015] Optionally, a photodiode is formed within the substrate between two adjacent deep trenches.

[0016] Optionally, the lateral width of the first groove is greater than 5 μm.

[0017] Optionally, the passivation layer of the pixel region has a second groove corresponding to the first trench, the depth of the second groove being...

[0018] Optionally, the thickness of the passivation layer is greater than 10 μm.

[0019] Optionally, the passivation layer of the pixel region has a second groove corresponding to the first trench. After etching the passivation layer of the logic region to thin the passivation layer of the logic region, the top surface height of the portion of the passivation layer located in the logic region is higher than the bottom surface height of the second groove.

[0020] Optionally, after etching the passivation layer of the logic region to thin it, the height difference between the top surface of the passivation layer in the logic region and the bottom surface of the second groove is greater than [missing information].

[0021] Optionally, after etching the passivation layer of the logic region to thin it, the thickness of the portion of the passivation layer located in the logic region is greater than...

[0022] Optionally, before forming the metal layer on the first surface of the substrate, the method further includes:

[0023] A metal interconnect layer is formed on the second surface of the substrate, and the metal interconnect layer is electrically connected to the interconnect structure.

[0024] This invention provides a method for fabricating an image sensor, comprising: providing a substrate, the substrate including a pixel region and a logic region located around the pixel region, wherein an interconnect structure is formed in the logic region of the substrate; forming a metal layer on a first surface of the substrate, the metal layer including a first portion covering the pixel region and a second portion covering the logic region, the second portion being electrically connected to the interconnect structure; etching the first portion to form a plurality of through-holes; conformally forming a passivation layer on the metal layer, and etching the passivation layer of the logic region to thin the passivation layer of the logic region; performing a planarization process on the passivation layer; and forming a lens structure on the passivation layer. This invention etches the passivation layer of the logic region before the planarization process, reducing the thickness of the passivation layer of the logic region, improving the uniformity of the planarization process of the passivation layer, and thus improving the uniformity of the image sensor. Attached Figure Description

[0025] Figures 1a-1b This is a schematic diagram of the structure corresponding to the steps in a method for fabricating an image sensor.

[0026] Figure 2 A flowchart illustrating a method for fabricating an image sensor provided by the present invention;

[0027] Figures 3a-3e This is a schematic diagram of the structure corresponding to the steps of the image sensor fabrication method provided by the present invention;

[0028] The accompanying diagram is described as follows:

[0029] 100, 200 - Substrate; a, A - Logic region; b, B - Pixel region; 101, 201 - Metal interconnect layer; 102, 202 - Deep trench; 104, 204 - Reflective layer; 206 - Metal layer; 107, 207 - Second part; 108, 208 - First part; 109, 209 - First groove; 110, 210 - Passivation layer; 111, 211 - Second groove. Detailed Implementation

[0030] Figures 1a-1b This is a schematic diagram of the structure corresponding to the steps in a method for fabricating an image sensor, as shown below. Figure 1aAs shown, a substrate 100 is provided, the substrate 100 including a pixel region a and a logic region b located around the pixel region a, an interconnect structure is formed in the logic region b of the substrate 100; a first surface of the substrate 100 is etched to form a plurality of deep trenches 102; a reflective layer 104 is formed on the substrate 100, the reflective layer 104 at least filling the deep trenches 102; a metal layer is formed on the first surface of the substrate 100, the metal layer including a first portion 108 covering the pixel region a and a second portion 107 covering the logic region b, the second portion 107 being electrically connected to the interconnect structure; the first portion 108 is etched to form a plurality of through first grooves 109; a passivation layer 110 is formed conformally on the metal layer, since the first portion 108 on the pixel region b has the first grooves 109, the passivation layer 110 on the pixel region b has second grooves 111.

[0031] like Figure 1b As shown, a planarization process is performed on the passivation layer 110, which can be a chemical mechanical polishing (CMP) process. During the CMP process on the passivation layer 110, because the passivation layer 110 above the pixel region b has the second groove 111, while the passivation layer 110 on the logic region a does not have the second groove 111, the polishing speeds of the passivation layers 110 above the pixel region b and the logic region a are different. The polishing speed of the passivation layer 110 above the pixel region b is faster. When the second groove 111 is removed and the passivation layer 110 above the pixel region b reaches the preset thickness H2, the passivation layer 110 on the logic region a, due to its slower polishing speed, does not reach the preset thickness H2. Furthermore, because the polishing head used in CMP has a certain degree of elasticity, the passivation layer 110 on the logic region a will form a shape such as... Figure 1b The slope structure shown has a thickness H1 greater than the preset thickness H2; typically, H1 is twice the thickness H2. This slope structure affects the uniformity of the image sensor, thereby impacting the sensor's performance.

[0032] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0033] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the steps presented herein are not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described in the text may be added to the method.

[0034] Figure 2 This is a flowchart of a method for fabricating an image sensor provided in this embodiment, as shown below. Figure 2 As shown, the present invention provides a method for fabricating an image sensor, comprising:

[0035] Step S1: Provide a substrate, the substrate including a pixel area and a logic area located around the pixel area, and an interconnect structure is formed in the logic area of ​​the substrate;

[0036] Step S2: A metal layer is formed on the first surface of the substrate, the metal layer comprising a first portion covering the pixel area and a second portion covering the logic area, the second portion being electrically connected to the interconnect structure;

[0037] Step S3: Etch the first portion to form a plurality of through-hole first grooves;

[0038] Step S4: Form a passivation layer conformally on the metal layer, and etch the passivation layer of the logic region to thin the passivation layer of the logic region;

[0039] Step S5: Perform a planarization process on the passivation layer;

[0040] Step S6: Form a lens structure on the passivation layer.

[0041] Figures 3a-3e The following is a schematic diagram of the corresponding steps in a method for fabricating an image sensor, in conjunction with the attached diagram. Figures 3a-3e A more detailed description of the method for fabricating an image sensor provided in this embodiment is given, wherein a preferred embodiment of the invention is illustrated.

[0042] like Figure 3a As shown, a substrate 200 is provided, the substrate 200 having a pixel region B and a logic region A, the logic region A being located on the periphery of the logic region A, the pixel region B being used to form various device structures of an image sensor, and various interconnect structures being formed within the logic region A.

[0043] A metal interconnect layer 201 is formed on the second surface of the substrate 200. The metal interconnect layer 201 can be manufactured using conventional methods, such as forming a dielectric layer and then patterning the dielectric layer to form openings and filling the openings with a conductive material, thereby sequentially forming various metal interconnect structures and vias to form the metal interconnect layer 201. The metal interconnect layer 201 is electrically connected to the interconnect structure of the logic region A.

[0044] Furthermore, the first surface of the substrate 200 is etched to form a plurality of deep trenches 202 on the pixel region B. The depths of the plurality of deep trenches 202 may be different or the same. In this embodiment, the plurality of deep trenches 202 with different depths are arranged alternately.

[0045] A photodiode is formed in the substrate 200 between two adjacent deep trenches 202 to achieve photoelectric conversion.

[0046] A reflective layer 204 is formed on the substrate 200. The reflective layer 204 fills the deep trench 202 and extends to cover the surface of the dielectric layer to form a deep trench isolation structure. The deep trench structure can suppress optical and electrical crosstalk of the image sensor and effectively enhance pixel isolation.

[0047] As an optional embodiment, the reflective layer 204 may also be filled only in the deep trench 202.

[0048] The reflective layer 204 can be a planarized film layer, thereby further ensuring the device uniformity of the image sensor.

[0049] A metal layer 206 is formed on the reflective layer 204, and the metal layer 206 covers the reflective layer 204. The metal layer 206 includes a first portion 208 covering the pixel area A and a second portion 207 covering the logic area B.

[0050] The width of the second portion 207 is greater than 1000 μm, and the second portion 207 is electrically connected to the interconnect structure.

[0051] The metal layer 206 can be made of metals such as tungsten, nickel, or titanium. The deposition method for the metal layer 206 can be metal-organic chemical vapor deposition or low-pressure chemical vapor deposition.

[0052] like Figure 3b As shown, photoresist is spin-coated onto the metal layer 206 and then exposed and developed to form a patterned photoresist. The first portion 208 is etched using the patterned photoresist as a mask to form a plurality of through-holes 209; finally, the photoresist is removed by ashing.

[0053] The first groove 209 exposes a portion of the reflective layer 204. Since this embodiment requires a large number of pixels for the back-illuminated image sensor, the width of the first groove 209 is greater than 5 μm to provide the larger pixels required in industry. At the same time, the first groove 209 makes the first portion 208 grid-like, which can effectively reduce the optical crosstalk of the image sensor.

[0054] like Figure 3c As shown, a passivation layer 210 is formed conformally on the metal layer 206. The passivation layer 210 fills the first groove 209 and extends to cover the second portion 207. The thickness of the passivation layer 210 is greater than 10 μm. Since the passivation layer 210 needs to fill the first groove 209, the passivation layer 210 within the pixel region B will form a second groove 211. The depth of the second groove 211 is...

[0055] Because the passivation layer 210 of pixel region B has a second groove 211, if a planarization process is directly performed on the passivation layer 210, the etching rate of the passivation layer 210 located in logic region A and pixel region B will differ. The thickness of the passivation layer 210 above logic region A will be greater than the thickness of the passivation layer 210 above pixel region B. This, in turn, affects the device uniformity of the image sensor.

[0056] Based on this, such as Figure 3d As shown, photoresist is spin-coated onto the passivation layer 210 and exposed and developed to form a patterned photoresist. The patterned photoresist is used as a mask for etching to remove part of the thickness of the passivation layer 210 of the logic region A, thereby thinning the passivation layer 210 of the logic region A. Finally, the photoresist is removed by ashing.

[0057] After etching the passivation layer 210 of the logic region A to thin it, the height of the top surface of the portion of the passivation layer 210 located in the logic region A is higher than the height of the bottom surface of the second groove 211; the height difference between the top surface of the portion of the passivation layer 210 located in the logic region A and the bottom surface of the second groove 211 is greater than... The passivation layer 210 located in the portion of the logic region A has a thickness greater than [missing information].

[0058] First, a portion of the thickness of the passivation layer 210 in the logic region A is removed to make the thickness distribution of the passivation layer 210 more uniform after the planarization process.

[0059] Since the passivation layer 210 will be thinned in the subsequent planarization process, in order to prevent the passivation layer 210 above the logic region A from being too thin, the depth difference between the second groove 213 and the second groove 211 needs to be less than [missing information].

[0060] It should be understood that the depth of the second groove 213 should be adjusted according to the actual situation of the second groove 211 and the preset thickness of the passivation layer 210.

[0061] like Figure 3e As shown, the passivation layer 210 is subjected to a planarization process to achieve a preset thickness H4. The planarization process can be a chemical mechanical polishing process.

[0062] After the planarization process, the thickness H3 of the passivation layer 210 on the logic region A is basically equal to the thickness H4 of the passivation layer 210 on the pixel region B.

[0063] A lens structure is formed on the passivation layer 210 after the planarization process.

[0064] In summary, the present invention provides a method for fabricating an image sensor, comprising: providing a substrate 200, the substrate 200 including a pixel region B and a logic region A located around the pixel region B, wherein an interconnect structure is formed in the logic region A of the substrate 200; forming a metal layer 206 on a first surface of the substrate 200, the metal layer 206 including a first portion 208 covering the pixel region B and a second portion 207 covering the logic region A, the second portion 207 being electrically connected to the interconnect structure; etching the first portion 208 to form a plurality of through first grooves 209; conformally forming a passivation layer 210 on the metal layer 206, and etching the passivation layer 210 of the logic region A to thin the passivation layer 210 of the logic region A; performing a planarization process on the passivation layer 210; and forming a lens structure on the passivation layer 210. The present invention etches the passivation layer 210 of the logic region A before the planarization process, reduces the thickness of the passivation layer 210 of the logic region A, improves the uniformity of the planarization process of the passivation layer 210, and thereby improves the uniformity of the image sensor.

[0065] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating an image sensor, characterized in that, include: A substrate is provided, the substrate including a pixel region and a logic region located around the pixel region, wherein an interconnect structure is formed in the logic region of the substrate; A metal layer is formed on a first surface of the substrate, the metal layer comprising a first portion covering the pixel region and a second portion covering the logic region, the second portion being electrically connected to the interconnect structure; The first portion is etched to form a plurality of through-hole first grooves; A passivation layer is formed conformally on the metal layer, and the passivation layer of the logic region is etched to thin the passivation layer of the logic region; The passivation layer is subjected to a planarization process; A lens structure is formed on the passivation layer.

2. The method for fabricating an image sensor as described in claim 1, characterized in that, Before forming a metal layer on the first surface of the substrate, the following steps are also included: The substrate is etched to form several deep trenches; A reflective layer is formed on the substrate, the reflective layer at least filling the deep trench.

3. The method for fabricating an image sensor as described in claim 2, characterized in that, A photodiode is formed in the substrate between two adjacent deep trenches.

4. The method for fabricating an image sensor as described in claim 1, characterized in that, The lateral width of the first groove is greater than 5 μm.

5. The method for fabricating an image sensor as described in claim 1, characterized in that, The passivation layer of the pixel region has a second groove that corresponds one-to-one with the first groove, and the depth of the second groove is 1500Å~2500Å.

6. The method for fabricating an image sensor as described in claim 1, characterized in that, The passivation layer has a thickness greater than 10 μm.

7. The method for fabricating an image sensor as described in claim 1, characterized in that, The passivation layer of the pixel area has a second groove that corresponds one-to-one with the first groove. After etching the passivation layer of the logic area to thin the passivation layer of the logic area, the top surface height of the portion of the passivation layer located in the logic area is higher than the bottom surface height of the second groove.

8. The method for fabricating an image sensor as described in claim 7, characterized in that, After etching the passivation layer of the logic region to thin the passivation layer of the logic region, the height difference between the top surface height of the portion of the passivation layer located in the logic region and the bottom surface height of the second groove is greater than 1000 Å.

9. The method for fabricating an image sensor as described in claim 7, characterized in that, After etching the passivation layer of the logic region to thin the passivation layer of the logic region, the thickness of the passivation layer in the portion of the logic region is greater than 1500 Å.

10. The method for fabricating an image sensor as described in claim 1, characterized in that, Before forming the metal layer on the first surface of the substrate, the method further includes: A metal interconnect layer is formed on the second surface of the substrate, and the metal interconnect layer is electrically connected to the interconnect structure.

Images