Fan-out package structure and method of forming the same

Abstract

Embodiments of the present application provide a fan-out package structure, comprising: a substrate; a first circuit layer on the substrate, the first circuit layer having a first opening exposing the substrate; and a first lead electrically connecting the first circuit layer to the portion of the substrate exposed by the first opening through the first lead. The purpose of the present application is to provide a fan-out package structure and a forming method thereof to improve the yield of the fan-out package structure.

Description

Technical Field

[0001] Embodiments of this application relate to fan-out packaging structures and methods for forming the same. Background Technology

[0002] In fan-out packaging structures, especially fan-out substrate (FOSUB) structures, after the fan-out layer is bonded to the substrate, vias are formed to electrically connect the fan-out layer and the substrate. However, this may have the following problems: the vias may not be aligned with the connectors on the substrate due to errors (e.g., machine errors causing via misalignment); the aspect ratio (AR ratio, width relative to depth) of the trench restricts the bottom of the via to be narrow, resulting in poor electrical performance; the vias need to avoid the traces, which reduces the trace routing area and therefore cannot effectively reduce the size of the fan-out layer. Summary of the Invention

[0003] In view of the problems existing in the related technologies, the purpose of this invention is to provide a fan-out packaging structure and a method for forming the same, so as to improve the yield of the fan-out packaging structure.

[0004] To achieve the above objectives, embodiments of the present invention provide a fan-out package structure, comprising: a substrate; a first circuit layer located on the substrate, the first circuit layer having a first opening exposing the substrate; and a first lead electrically connecting the first circuit layer to a portion of the substrate exposed by the first opening.

[0005] In some embodiments, the first lead is connected to a first pad on the upper surface of the first circuit layer.

[0006] In some embodiments, the first lead is connected to a second pad on the upper surface of the substrate.

[0007] In some embodiments, the system further includes an adhesive layer located between the substrate and the first circuit layer, wherein the third lateral dimension of the adhesive layer is greater than the first lateral dimension of the first circuit layer and smaller than the second lateral dimension of the substrate.

[0008] In some embodiments, the adhesive layer has a second opening located below the first opening, the size of the second opening being smaller than the size of the first opening.

[0009] In some embodiments, the second pad is located on the portion of the upper surface of the substrate exposed by the second opening.

[0010] In some embodiments, the first lead includes a lead terminal that contacts the second pad.

[0011] In some embodiments, the system further includes: a second circuit layer located on the first circuit layer, the second circuit layer having a third opening located on the first opening, the size of the third opening being larger than the size of the first opening.

[0012] In some embodiments, the system further includes a second lead that electrically connects a fourth pad of the second circuit layer to a third pad on the upper surface of the substrate.

[0013] In some embodiments, the second and third pads have different heights.

[0014] In some embodiments, the height of the third pad is greater than the height of the second pad.

[0015] In some embodiments, it further includes: a third lead electrically connected to a fourth pad located on both sides of the third opening of the second circuit layer.

[0016] In some embodiments, it further includes: electronic components located on the second circuit layer.

[0017] Embodiments of this application also provide a method for forming a fan-out package structure, comprising: forming a first circuit layer having a first opening; placing the first circuit layer on a substrate; and electrically connecting the first circuit layer to the substrate using a first lead passing through the first opening.

[0018] In some embodiments, forming a first circuit layer includes: forming a first internal circuit on a first carrier; forming a first dielectric layer covering the first internal circuit; forming a first opening exposing the first carrier and a first aperture exposing the first internal circuit; forming a first through-hole in the first opening and forming a first pad on the first dielectric layer.

[0019] In some embodiments, after forming the first opening and the first aperture, a first seed layer is formed in the first opening, the first aperture and on the first dielectric layer; and a first mask is formed on the first seed layer.

[0020] Patterning a first mask to expose a first seed layer in a first opening; forming a first metal layer on the exposed portion of the first seed layer; removing the first mask and patterning the first seed layer using the first metal layer as a mask.

[0021] In some embodiments, the method further includes: forming a second circuit layer on the first circuit layer, the second circuit layer having a third opening on the first opening, the third opening having a size larger than the first opening.

[0022] In some embodiments, the method further includes: inverting the first carrier, the first circuit layer, and the second circuit layer onto the second carrier; removing the first carrier; and inverting the second carrier, the second circuit layer, and the first circuit layer onto the substrate.

[0023] In some embodiments, an adhesive layer is formed on the substrate before the second carrier, the second circuit layer and the first circuit layer are inverted on the substrate, and the first circuit layer is bonded to the adhesive layer after the second carrier, the second circuit layer and the first circuit layer are inverted on the substrate.

[0024] In some embodiments, the adhesive layer has a second opening located below the first and third openings, and the size of the second opening is smaller than the size of the first opening. Attached Figure Description

[0025] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0026] Figure 1 and Figure 2 A schematic diagram of an existing fan-out package structure is shown.

[0027] Figures 3 to 16 The process of forming a fan-out package structure according to some embodiments of this application is illustrated.

[0028] Figures 17 to 25 The process of forming a fan-out package structure according to other embodiments of this application is illustrated.

[0029] Figures 26 to 31 Schematic diagrams of fan-out package structures according to different embodiments of this application are shown. Detailed Implementation

[0030] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0031] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0032] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0033] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0034] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0035] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0036] Figure 1 A schematic diagram of an existing fan-out package structure is shown, wherein the position indicated by the dashed box 10 (same as above) Figure 2Vias cannot be placed at the location of the cross mark to avoid damaging the internal circuitry, thus failing to meet the requirements for internal via connections. Multilayer circuitry is interconnected, therefore input / output (I / O) takes precedence, and only the outermost layer can have fine lines (e.g., linewidth to line spacing (L / S) < 2μm / 2μm). The substrate pads 14 have different heights, making it difficult to control the depth of the vias. Furthermore, cracks or delamination 12 may occur in the structure, leading to corrosion and affecting the yield of the finished product.

[0037] Figure 2 It shows the formation Figure 1 The intermediate steps of the fan-out package structure are shown. In this process, the aperture size of the via 20 is often larger than the design value. When forming the metal layer 22 of the via 20, the size of the mask layer 24 is generally the same as the design value. This makes it easy for over-etching to occur during the subsequent removal of the mask layer 24 and seed layer 26, resulting in defects in the finished product. Figure 1 The cracks or delamination shown 12 may corrode the structure and affect the yield of finished products.

[0038] The fan-out packaging structure and its formation method of this application will be described in detail below with reference to the accompanying drawings.

[0039] See Figure 3 A first internal circuit 32 is formed on a first carrier 30, the first internal circuit including a second seed layer 34 and a second metal layer 36. The first carrier 30 may be a glass carrier substrate, a ceramic carrier substrate, etc. The first carrier 30 may be a wafer, thereby enabling multiple package structures to be formed simultaneously on the first carrier 30. In some embodiments, the materials of the second seed layer 34 and the second metal layer 36 include Cu, Au, Ag, Al, Pd, Pt, Ti, Ni, alloys thereof, or combinations thereof. In some embodiments, the second seed layer 34 and the second metal layer 36 are formed using physical vapor deposition (PVD), sputtering, electroplating, electroless plating, and / or printing and / or potting processes.

[0040] See Figure 4 A first dielectric layer 40 is formed covering the first internal circuitry 32. In some embodiments, the first dielectric layer 40 may include a polyamide (PA) material, and an exposure process 41 is performed on the first dielectric layer 40 to cure it.

[0041] See Figure 5A first opening 50 exposing the first carrier 30 and a first aperture 52 exposing the first internal wiring 32 are formed in the first dielectric layer 40. A first seed layer 54 is formed in the first opening 50, the first aperture 52, and on the first dielectric layer 40. In some embodiments, the material of the first seed layer 54 includes Cu, Au, Ag, Al, Pd, Pt, Ti, Ni, alloys thereof, or combinations thereof. In some embodiments, the first seed layer 54 is formed using physical vapor deposition (PVD), sputtering, electroplating, electroless plating, and / or printing and / or potting processes.

[0042] See Figure 6 A first mask 60 is formed on the first seed layer 54. In some embodiments, the first mask 60 includes a photoresist (PR) material, and an exposure process 61 is performed to cure the first mask layer 60.

[0043] See Figure 7 A first mask 60 is patterned to expose a first seed layer 54 in a first opening 52; a first metal layer 70 is formed on the exposed portion of the first seed layer 54. In some embodiments, the material of the first metal layer 70 includes Cu, Au, Ag, Al, Pd, Pt, Ti, Ni, alloys thereof, or combinations thereof. In some embodiments, the first metal layer 70 is formed using physical vapor deposition (PVD), sputtering, electroplating, electroless plating, and / or printing and / or potting processes.

[0044] See Figure 8 The first mask 60 is removed, and the first seed layer 54 is patterned using the first metal layer 70 as a mask. This forms the first circuit layer 80, and the combination of the first seed layer 54 and the first metal layer 70 constitutes the first pad 82 of the first circuit layer 80 and the first via 84 located in the first opening 52. In some embodiments, the diameter of the first via 84 is 5 μm to 30 μm. In some embodiments, the thickness of the first circuit layer 80 is 3 μm to 20 μm.

[0045] See Figure 9A second circuit layer 90 is formed on the first circuit layer 80. The second circuit layer 90 has a third opening 92 located on the first opening 50, and the size of the third opening 92 is larger than the size of the first opening 50. That is, the lateral dimension of the second circuit layer 90 is smaller than the lateral dimension of the first circuit layer 80. In some embodiments, the second circuit layer 90 has a fourth pad 91 and a second via 94. In some embodiments, the linewidth / spacing (L / S) of the lines in the first circuit layer 80 and the second circuit layer 90 is < 2 μm / 2 μm. In some embodiments, the diameter of the third opening 92 is 2 μm to 40 μm larger than the diameter of the first opening 50. In some embodiments, the diameter of the third opening 92 is greater than 30 μm.

[0046] See Figure 10 The first carrier 30, the first circuit layer 80, and the second circuit layer 90 are inverted onto the second carrier 100, and the first carrier 30 is removed. The second carrier 100 may be identical to the first carrier 30. A release layer 104 is also disposed on the second carrier 100. The release layer 104 may be formed of a polymer-based material, which may be removed from the above structure along with the second carrier 100, to be formed in subsequent steps. In some embodiments, the release layer 104 is a thermally release material based on epoxy resin, which loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the release layer 104 may be a UV adhesive, which loses its adhesiveness upon exposure to UV light. The release layer 104 may be dispensed and cured in liquid form, may be a laminated film laminated onto the carrier substrate 102, or may be similar. The top surface of the release layer 104 may be horizontal and may have a high degree of flatness.

[0047] See Figure 11A second carrier 100, a second circuit layer 90, and a first circuit layer 80 are inverted on a substrate 110, and an adhesive layer 112 is disposed on the substrate 110. In some embodiments, the substrate 110 includes a dielectric layer and circuits located in the dielectric layer. In some embodiments, the materials of the dielectric layer and the adhesive layer 112 of the substrate 110 include organic materials, such as polyimide (PI), epoxy resin, polybenzoxazole (PBO), flame retardant grade 4 material (FR4), prepreg resin (PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT); and / or inorganic materials, such as silicon, glass, ceramics, oxides (e.g., SiOx, TaOx), nitrides (e.g., SiNx). In some embodiments, the dielectric layer and the adhesive layer 112 of the substrate 110 are formed using processes such as deposition, lamination, printing, potting, and impregnation. In some embodiments, the material of the lines in the substrate 110 includes Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. In some embodiments, the lines in the substrate 110 can be formed using processes such as physical vapor deposition (PVD), sputtering, electroplating, electroless plating (E'less), and / or printing, lamination, and / or potting. In some embodiments, the lines in the substrate 110 form a second pad 114 and a third pad 116 on the surface of the substrate 110. In some embodiments, a second opening 118 is provided in the adhesive layer 112. The size of the second opening 118 is smaller than the size of the first opening 50. In some embodiments, the different sizes of the second opening 118, the first opening 50, and the third opening 92 in the adhesive layer 112 form a cavity with a stepped structure, which can reduce structural warpage. In some embodiments, the linewidth / spacing (L / S) of the lines in the substrate 110 is >10 μm / 10 μm. In some embodiments, the thickness of the substrate 110 is 50 μm to 300 μm.

[0048] See Figure 12A Remove the second carrier 100 and the release layer 104. Figure 12B and Figure 12C Top view and cross-sectional view after the second carrier 100 and release layer 104 have been removed are shown, respectively. Figure 12B High-density region 120 and low-density region 122 are shown.

[0049] See Figure 13This forms a first lead 130 electrically connecting the first pad 82 to the second pad 114, a second lead 132 electrically connecting the fourth pad 91 of the second circuit layer 90 to the third pad 116 of the substrate 110, and a fourth lead 134 electrically connecting the second via 94 of the second circuit layer 90 to the fifth pad 115 of the substrate 110. In some embodiments, the materials of the first lead 130, the second lead 132, and the fourth lead 134 include Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. In some embodiments, the first lead 130, the second lead 132, and the fourth lead 134 can be formed using processes such as physical vapor deposition (PVD), sputtering, electroplating, electroless plating (E'less), and / or printing, lamination, and / or potting. In some embodiments, the adhesive layer 112, the first wiring layer 80, and the second wiring layer 90 include additional openings (e.g., the opening on the right and openings not shown in this cross-section), and additional leads pass through the openings to electrically connect the first wiring layer 80 and the second wiring layer 90 to the substrate 110. In some embodiments, the first lead 130, the second lead 132, and the fourth lead 134 each include lead terminals 1301, 1321, and 1341 that respectively contact the second pad 114, the third pad 116, and the fifth pad 115. In some embodiments, the lead terminals 1301, 1321, and 1341 may be made of solder. In some embodiments, the second pad 114 and the third pad 116 have different heights. In some embodiments, the height of the third pad 116 is greater than the height of the second pad 114. In some embodiments, the thickness difference between the pads on the substrate 110 is less than 30% of their thickness. In some embodiments, the diameters of the first lead 130, the second lead 132, and the fourth lead 134 are 12 μm to 50 μm, and the diameters of the first lead 130, the second lead 132, and the fourth lead 134 are uniform and constant (except for the portion of the lead terminal).

[0050] See Figure 14 In some embodiments, electronic component 140 is disposed on second circuit layer 90. In some embodiments, a clamping member 141 is used to hold electronic component 140 on second circuit layer 90. In some embodiments, a vacuum cavity 142 is provided between clamping member 141 and electronic component 140. In some embodiments, a first connector 144 of electronic component 140 is electrically connected to a fourth pad 91 of second circuit layer 90. In some embodiments, the first connector 144 includes microbumps, and the material of the first connector 144 may be solder, such as Cu. In some embodiments, electronic component 140 is a chip. In some embodiments, the thickness of electronic component 140 is 20 μm to 200 μm.

[0051] See Figure 15 In some embodiments, an underfill material 152 is formed between the electronic component 140 and the second circuit layer 90. In some embodiments, the underfill material 152 also covers portions of the sidewalls of the electronic component 140. In some embodiments, a molding compound (CPD) 150 is used to encapsulate the electronic component 140, the substrate 110, and the circuit layers and leads on the substrate 110.

[0052] See Figure 16 ,Will Figure 15 The structure shown is flipped, and a second connector 160 is formed on the back side of the substrate 110. In some embodiments, the material of the second connector 160 may be solder, and the second connector 160 may be a solder ball. In the manufacturing process, multiple Figure 16 The structures shown are formed together and then a monolithic process (e.g., cutting) is performed to form the structure shown. Figure 16 The illustration shows a single fan-out package structure 1600. In some embodiments, the thickness of the fan-out package structure 1600 is less than 0.15 mm. In some embodiments, the thickness of the fan-out package structure 1600 is less than 0.1 mm. In some embodiments, the lateral dimension of the fan-out package structure 1600 is 50 mm to 80 mm.

[0053] Figures 17 to 25 It shows Figures 9 to 16 Alternative embodiments. See also Figure 17 Among them, the first line layer 80' and the second line layer 90' on the third carrier 170 and Figures 8 to 16 The first line layer 80 and the second line layer 90 shown are similar.

[0054] See Figure 18 , directly Figure 17 The structure shown is placed upside down on substrate 110', with substrate 110' and Figure 11 The substrate 110 shown is similar. An adhesive layer 112 is disposed between the substrate 110' and the first circuit layer 80' and the second circuit layer 90'.

[0055] See Figure 19 Then, remove the third substrate 170. See [link / reference] Figure 20 The first seed layer 54' of the first circuit layer 80' is removed using etching process 201 to expose the first metal layer 70' (e.g., ...). Figure 21 (As shown). In some embodiments, etching process 201 is wet etching.

[0056] See Figure 22 The first metal layer 70' and the sixth pad 224 are electrically connected via the fifth lead 220. In some embodiments, the sixth pad 224 is connected to... Figure 13The second pad 114, the third pad 116, and the fifth pad 115 shown are similar, and the fifth lead 220 is... Figure 13 The first lead 130, the second lead 132, and the fourth lead 134 shown are similar. The substrate 110' has a plurality of sixth pads 224, and the plurality of sixth pads 224 have different thicknesses.

[0057] See Figure 23 ,and Figure 14 Similarly, electronic component 140' is disposed on the first circuit layer 80'. In some embodiments, a clamping member 141' is used to hold the electronic component 140' on the first circuit layer 80'. In some embodiments, a vacuum cavity 142' is provided between the clamping member 141' and the electronic component 140'. In some embodiments, a first connector 144' of the electronic component 140' is electrically connected to a first metal layer 70' of the first circuit layer 80'. In some embodiments, the first connector 144' includes microbumps, and the material of the first connector 144' may be solder, such as Cu. In some embodiments, the electronic component 140' is a chip.

[0058] See Figure 24 ,and Figure 15 Similarly, in some embodiments, an underfill material 152' is formed between the electronic component 140' and the first circuit layer 80'. In some embodiments, the underfill material 152' also covers portions of the sidewalls of the electronic component 140'. In some embodiments, a molding compound (CPD) 150' is used to encapsulate the electronic component 140', the substrate 110', and the circuit layers and leads on the substrate 110'. In some embodiments, no underfill material 152' is formed; instead, a molding compound (CPD) 150' is directly formed to encapsulate the electronic component 140', the substrate 110', and the circuit layers and leads on the substrate 110'.

[0059] See Figure 25 ,and Figure 16 Similarly, Figure 24 The structure shown is flipped, and a second connector 160' is formed on the back side of the substrate 110'. In some embodiments, the material of the second connector 160' may be solder, and the second connector 160' may be a solder ball. In the manufacturing process, multiple Figure 16 The structures shown are formed together and then a monolithic process (e.g., cutting) is performed to form the structure shown. Figure 16 The single fan-out package structure shown is 1600'.

[0060] Figure 26 It shows the relationship with Figure 25In different embodiments, a functional wafer 260, including a processor, memory, etc., is electrically connected to a first line layer 80' to form a SIP (System In a Package) structure 2600.

[0061] Figure 27 It shows the relationship with Figure 16 In different embodiments, the third lead 270 is electrically connected to the fourth pad 91 located on both sides of the third opening 92 of the second circuit layer 90.

[0062] Figure 28 It shows the relationship with Figure 27 In different embodiments, electronic component 140 is attached to second circuit layer 90 by adhesive 280, and sixth lead 282 electrically connects electronic component 140 to second circuit layer 90.

[0063] Figure 29 It shows the relationship with Figure 25 In different embodiments, the underfill material 152' further encapsulates the fifth lead 220.

[0064] Figure 30 It shows the relationship with Figure 25 In different embodiments, electronic component 140' spans an opening across a first circuit layer 80' and a second circuit layer 90'.

[0065] Figure 31 It shows the relationship with Figure 25 In different embodiments, electronic component 140' spans two openings across the first circuit layer 80' and the second circuit layer 90'.

[0066] The embodiments of this application use leads instead of traditional through-holes through a stepped design. The leads extend from the top surface of the circuit layer and bond to the substrate, reducing the size of the package structure and shortening the signal transmission path. Compared with the complex process of traditional through-holes, using lead interconnects can reduce manufacturing costs, such as saving the drilling, seed layer formation, mask coating, exposure, development, electroplating, and etching processes required for traditional through-hole fabrication. It also avoids the cracking that can occur with traditional through-holes, improving the yield of the package structure. The path between pads (conducted through leads in space) is shorter than that of traditional through-hole layouts [a 2D structure with loops (vertically extending) while considering cross-wire effects].

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fan-out type packaging structure, characterized in that, include: Substrate; A first circuit layer is located on the substrate, and the first circuit layer has a first opening that exposes the substrate; An adhesive layer is located between the substrate and the first circuit layer, the adhesive layer having a second opening located below the first opening; A second circuit layer is located on the first circuit layer, and the second circuit layer has a third opening located on the first opening; The chip is disposed on the second circuit layer and electrically connected to the second circuit layer; A first lead connects the first circuit layer to the portion of the substrate exposed by the first opening via the first lead; The second lead electrically connects the second circuit layer to the exposed portion of the substrate via the second lead spanning the second circuit layer, the first circuit layer, and the adhesive layer; The chip is horizontally spaced from the third opening, and the first opening, the second opening, and the third opening are continuous with each other. When viewed from above, the second opening is located within the area surrounded by the first opening, and the first opening is located within the area surrounded by the third opening.

2. The fan-out packaging structure according to claim 1, characterized in that, The first lead is connected to the first pad on the upper surface of the first circuit layer.

3. The fan-out packaging structure according to claim 2, characterized in that, The first lead is connected to a second pad on the upper surface of the substrate.

4. The fan-out packaging structure according to claim 3, characterized in that, The third lateral dimension of the adhesive layer is greater than the first lateral dimension of the first circuit layer and smaller than the second lateral dimension of the substrate.

5. The fan-out packaging structure according to claim 4, characterized in that, The second pad is located on the portion of the upper surface of the substrate exposed by the second opening.

6. The fan-out packaging structure according to claim 3, characterized in that, The first lead includes a lead terminal that contacts the second pad.

7. The fan-out packaging structure according to claim 3, characterized in that, The second lead electrically connects the fourth pad of the second circuit layer to the third pad on the upper surface of the substrate.

8. The fan-out packaging structure according to claim 7, characterized in that, The second and third pads have different heights.

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