MBIST circuit, driver chip, electronic equipment and test method

Abstract

The present application relates to an MBIST circuit, a driver chip, an electronic device, and a test method, and belongs to the field of integrated circuit technology. When the MBIST circuit receives a test instruction signal, it inputs an ADR address signal, test data, and a timing signal required for the MBIST test into a memory, compares the test data written to the address to be tested with the result data read by the memory from the address to be tested, and outputs a signal indicating whether the test of the address to be tested is successful; the ADR address signal includes two modes: gradually increasing and gradually decreasing, and each mode corresponds to multiple groups of different test data. The ADR address signal in the present application includes two modes: gradually increasing and gradually decreasing, and each mode corresponds to multiple groups of different test data, and multiple test modes can be combined to obtain multiple test modes. By using at least two test modes to perform MBIST testing on the memory, the accuracy and reliability of the memory test can be improved.

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