Semiconductor package structure and method of forming the same

Abstract

The present application relates to a semiconductor package structure and a method of forming the same. The semiconductor package structure includes a lower wiring layer including a high-density wiring region and a low-density wiring region, the I / O density of the high-density wiring region being greater than the I / O density of the low-density wiring region, and the I / O interface of the high-density wiring region being lower than the I / O interface of the low-density wiring region; and an upper wiring layer located above the lower wiring layer, the upper wiring layer including first through-holes electrically connected to the I / O of the low-density wiring region, and the upper wiring layer further including second through-holes electrically connected to the I / O of the high-density wiring region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and a method for forming the same. Background Technology

[0002] In semiconductor packaging structures, bridge redistribution lines (BRLs) are typically placed inside the substrate to reduce the overall thickness of the package structure. However, this arrangement has the following drawbacks when applied to flip chips.

[0003] like Figure 1a As shown, the bridging chip 15 is located within the substrate. Due to the significant thickness difference of the pads 12 on the substrate 10, the height difference of the top surfaces of each pad 12 is also large. This causes a situation where, during flip-chip bonding of the chip 20, as shown in region S1, the pads 22 of the chip 20 are not connected to the pads 12 on the substrate 10.

[0004] like Figure 1b As shown, when placing the bridge chip 15, the bridge chip 15 located on the DAF (die attachment film) 16 will be tilted due to the tilt of the DAF 16. As shown in region S2, this will result in the phenomenon that the pad 22 of the flip chip 20 is not connected to the pad 12 on the substrate 10.

[0005] Furthermore, the through-hole concept of fan-out substrates (FOSUB) can solve the problems in flip chips. However, traditional fan-out substrates cannot simultaneously satisfy both coarse pitch and fine pitch circuit areas, so the fine circuit area is generally sacrificed, resulting in a decrease in the electrical performance of the device. Summary of the Invention

[0006] To address the aforementioned problems in related technologies, this invention proposes a semiconductor packaging structure and a method for forming the same.

[0007] According to one aspect of the present invention, a semiconductor package structure is provided, comprising: a lower circuit layer including a high-density circuit region and a low-density circuit region, wherein the I / O density of the high-density circuit region is greater than the I / O density of the low-density circuit region, and the I / O interface of the high-density circuit region is lower than the I / O interface of the low-density circuit region; and an upper circuit layer located above the lower circuit layer, wherein the upper circuit layer includes a first through-hole electrically connected to the I / O of the low-density circuit region, and the upper circuit layer further includes a second through-hole electrically connected to the I / O of the high-density circuit region.

[0008] In some embodiments, the upper surface of the first through hole is coplanar with the upper surface of the second through hole.

[0009] In some embodiments, the lower circuit layer also includes a bridging chip located below the high-density circuit area.

[0010] In some embodiments, the semiconductor package structure further includes a substrate having a cavity, wherein a high-density circuit region of the lower circuit layer is located in the cavity of the substrate.

[0011] In some embodiments, the low-density circuit region has a dielectric layer that extends into a cavity in the substrate, and the high-density circuit region is located between the dielectric layers in the cavity.

[0012] In some embodiments, the semiconductor package structure further includes an intermediate layer located between and bonding the upper and lower circuit layers, wherein a first via and a second via pass through the intermediate layer and are electrically connected to the low-density circuit region and the high-density circuit region, respectively.

[0013] In some embodiments, the height of the second through hole is greater than the height of the first through hole.

[0014] In some embodiments, the contact surface between the second through-hole and the I / O of the high-density circuit area is smaller than the contact surface between the first through-hole and the I / O of the low-density circuit area.

[0015] In some embodiments, the semiconductor package structure further includes a first chip and a second chip, the first chip and the second chip being located above the upper circuit layer, and a high-density circuit area being located below the gap between the first chip and the second chip.

[0016] In some embodiments, the first chip is electrically connected to a portion of the first through-hole and a portion of the second through-hole, and the second chip is electrically connected to another portion of the first through-hole and another portion of the second through-hole.

[0017] According to another aspect of the present invention, a method for forming a semiconductor package structure is provided, comprising: providing a substrate having a cavity; placing a high-density circuit region within the cavity and forming a low-density circuit region on a substrate outside the cavity; attaching a circuit layer above the substrate; and forming a through-hole that passes through the upper circuit layer and is electrically connected to the high-density circuit region and the low-density circuit region, wherein the I / O density of the high-density circuit region is greater than the I / O density of the low-density circuit region.

[0018] In some embodiments, before placing the high-density line area within the cavity, the method further includes: forming the high-density line area on the bridging chip.

[0019] In some embodiments, forming a high-density circuit region on a bridging chip includes: forming a dielectric layer covering the substrate and conductive lines located in the dielectric layer on a substrate to form a high-density circuit region; and cutting the high-density circuit region and the substrate to form a single high-density circuit region on the bridging chip.

[0020] In some embodiments, after the high-density line area is placed inside the cavity, there is a gap between the high-density line area and the sidewall of the cavity.

[0021] In some embodiments, forming a low-density circuit region includes: forming a dielectric layer of the low-density circuit region on a substrate outside the cavity and within a gap; and forming conductive lines in the dielectric layer to form the low-density circuit region.

[0022] In some embodiments, attaching a circuit layer over a substrate includes: covering a low-density circuit region and a high-density circuit region with an intermediate layer; and attaching an upper circuit layer over the low-density circuit region and the high-density circuit region through the intermediate layer.

[0023] In some embodiments, forming a through-hole includes: forming a first through-hole electrically connected to a low-density circuit area, and forming a second through-hole electrically connected to a high-density circuit area, wherein the height of the second through-hole is greater than the height of the first through-hole.

[0024] In some embodiments, the contact surface between the second through hole and the high-density circuit area is smaller than the contact surface between the first through hole and the low-density circuit area.

[0025] In some embodiments, forming a through-hole includes forming a through-hole by laser drilling, plasma drilling, or etching back.

[0026] In some embodiments, the method further includes: bonding a first chip and a second chip electrically connected to a via above an upper circuit layer, wherein a high-density circuit region is located below the gap between the first chip and the second chip. Attached Figure Description

[0027] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0028] Figure 1a and Figure 1b This is a schematic diagram of a current semiconductor packaging structure.

[0029] Figure 2a This is a side view of the semiconductor packaging structure according to an embodiment of the present invention.

[0030] Figure 2b yes Figure 2a A magnified view of region A1 of the semiconductor package structure shown.

[0031] Figure 2c and Figure 2d They are shown respectively Figure 2aThe diagram shows a top view of the semiconductor package structure at sections A-A' and B-B'.

[0032] Figures 3a to 7 This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention.

[0033] Figures 8a to 8m This is a schematic diagram of the various stages of a method for forming a high-density circuit region in a semiconductor package structure according to an embodiment of the present invention.

[0034] Figures 9a to 9i This is a schematic diagram of the various stages of a method for forming an upper circuit layer 220 in a semiconductor package structure according to an embodiment of the present invention.

[0035] Figures 10a to 10p This is a schematic diagram of various stages of a method for forming a semiconductor package structure using a pre-formed high-density circuit region and an upper circuit layer according to an embodiment of the present invention. Specific Implementation

[0036] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0037] An embodiment of the present invention provides a semiconductor packaging structure. Figure 2a This is a side view schematic diagram of a semiconductor package structure according to an embodiment of the present invention. Figure 2a As shown, the semiconductor package structure may include a lower circuit layer 210 and an upper circuit layer 220 located above the lower circuit layer 210. I / O connections (hereinafter referred to as I / O) such as pads are disposed on the upper surface of the lower circuit layer 210. The I / O density of the lower circuit layer 210 varies in different regions, thereby the lower circuit layer 210 may include a high-density circuit region 240 and a low-density circuit region 230, wherein the I / O density of the high-density circuit region 240 is greater than that of the low-density circuit region 230. In some embodiments, the high-density circuit region 240 is a circuit layer with fine lines, such as a fan-out layer or a redistribution layer (RDL), thereby the high-density circuit region 240 has a larger I / O density. In some embodiments, the line width and line spacing L / S in the high-density circuit region 240 are 2 μm / 2 μm.

[0038] Since the high-density circuit region 240 and the low-density circuit region 230 are bonded to other connectors via pads on their surfaces, the surfaces of the pads on the surfaces of the high-density circuit region 240 and the low-density circuit region 230 can be referred to as I / O interfaces. According to an embodiment of the present invention, the I / O interface of the high-density circuit region 240 is lower than the I / O interface of the low-density circuit region 230. A bridging chip 215 located below the high-density circuit region 240 is also provided in the lower circuit layer 210. A first through-hole 222 and a second through-hole 224 are provided in the upper circuit layer 220. The first through-hole 222 is electrically connected to the I / O (such as pads) on the surface of the low-density circuit region 230, and the second through-hole 224 is electrically connected to the I / O (such as pads) on the surface of the high-density circuit region 240.

[0039] The semiconductor packaging structure provided by this invention, by providing a high-density line region 240 with a low surface height on the bridging chip 215, allows for a smaller aperture on the lower surface of the high-density line region 244 when forming the first via 222 and the second via 224 due to the aspect ratio (AR) of the vias 222 and 224. This allows for direct fine pitch design on the bridging chip 215 without sacrificing fine pitch and designing large pads due to aperture limitations, thus avoiding impacting the circuit layout space. Furthermore, by providing bridging links through the high-density line region 240, a higher planar levelness (e.g., height deviation less than 5%) is provided, solving the high deviation problem caused by pad thickness in conventional substrates (e.g., height deviation can reach 20%).

[0040] Since the upper ends of both the first through-hole 222 and the second through-hole 224 extend to the upper surface of the upper circuit layer 220, meaning that the holes are both formed starting from the upper surface of the upper circuit layer 220, the upper surfaces of the first through-hole 222 and the second through-hole 224 are coplanar. Therefore, even if the bridging chip 215 is tilted, it will not affect the electrical connection between the first through-hole 222 and the second through-hole 224, solving the problem of poor bonding of bridging chips with tilted angles.

[0041] Figure 2b yes Figure 2a A partially enlarged view of region A1 of the semiconductor package structure shown. Combined with... Figure 2a and Figure 2bAs shown, in some embodiments, the size of the first through-hole 222 (the width of the upper opening) may be larger than the size of the second through-hole 224. In some embodiments, the size of the first through-hole 222 is in the range of 25 μm to 50 μm. The size of the second through-hole 224 is in the range of 10 μm to 30 μm. The height of the second through-hole 224 may be greater than the height of the first through-hole 222. In some embodiments, the ratio of the depth to the width (e.g., diameter) of the first through-hole 222 and / or the second through-hole 224 is in the range of 10 to 0.5. In some embodiments, the height of the second through-hole 224 is greater than the height of the first through-hole 222. In some embodiments, because the height of the second through-hole 224 is greater than the height of the first through-hole 222 and the size of the first through-hole 222 is greater than the size of the second through-hole, in such embodiments, the contact surface between the second through-hole 224 and the I / O of the high-density circuit area 240 is smaller than the contact surface between the first through-hole 222 and the I / O of the low-density circuit area 230. The smaller-sized second through-hole 224 and the high-density line area 240 with fine lines (e.g., fine RDL) on the bridging chip 215 can provide more I / O capabilities.

[0042] Continue to refer to Figure 2a As shown, the high-density circuit region 240 is disposed in the first cavity 217 of the substrate 218. In some embodiments, the thickness of the substrate 218 is in the range of 50 μm to 200 μm. In some embodiments, the substrate 218 has a filler, such as glass fiber. The filler can provide higher strength for the substrate and the package structure.

[0043] The low-density circuit region 230 is located on the substrate 218 outside the first cavity 217, so that the I / O interface of the high-density circuit region 240 can be lower than the I / O interface of the low-density circuit region 230. The embedded arrangement in the high-density circuit region 240 can provide protection for the high-density circuit region 240.

[0044] A DAF (Device Array of Abutments) can be disposed below the bridging chip 215, and the bridging chip 215 is connected within the first cavity 217 via the DAF. In some embodiments, the thickness of the bridging chip 215 is in the range of 20 μm to 100 μm. The first cavity 217 of the substrate 218 has a width W1 in the lateral direction. The bridging chip 215 has a width W2 in the lateral direction. In some embodiments, W2 can be in the range of 0.1 mm to 10 mm. In some embodiments, the value of W1 / W2 is in the range of 0.5-0.8. By embedding the bridging chip 215 into the substrate 218, it is beneficial to reduce the overall thickness of the package structure. Furthermore, since the top surface of the bridging chip 215 is lower than the upper surface of the substrate 218, the bridging chip 215 can be protected.

[0045] The low-density circuit region 230 includes a dielectric layer 232 and conductive lines located within the dielectric layer 232. The dielectric layer 232 in the low-density circuit region 230 covers the upper surface outside the first cavity 217 of the substrate 218 and extends to the sidewalls of the first cavity 217. In some embodiments, the dielectric layer 232 may be formed of an organic material, such as polyimide (PI), epoxy resin, or laminated film (ABF). In some embodiments, the dielectric layer 232 may be formed of an inorganic material, such as oxides (e.g., SiOx, SiNx, TaOx), glass, silicon, or ceramics. In some embodiments, the dielectric layer 232 may be an organic photosensitive liquid material, an organic non-photosensitive liquid material, an organic photosensitive dry film material, or an organic non-photosensitive dry film material. In some embodiments, the thickness of the dielectric layer 232 may be in the range of 1 μm to 10 μm.

[0046] A portion of dielectric layer 232 extending into the first cavity 217 is formed between the substrate 218 and the high-density circuit region 240 and the bridging chip 215. The high-density circuit region 240 and the bridging chip 215 are located between and surrounded by dielectric layer 232 in the first cavity 217. The upper surface of the high-density circuit region 240 is lower than the upper surface of dielectric layer 232, thereby defining a second cavity 219 above the high-density circuit region 240 by dielectric layer 232. Since the gap between the edges of the high-density circuit region 240 and the bridging chip 215 and the substrate 218 is filled with dielectric layer 232, dielectric layer 232 can be considered as a buffer structure to avoid large coefficient of thermal expansion (CTE) mismatch.

[0047] Intermediate layer 235 is located between and attached to upper circuit layer 220 and lower circuit layer 210. The second cavity 219 above high-density circuit region 240 is filled by intermediate layer 235. In some embodiments, intermediate layer 235 may be formed, for example, of an adhesive dielectric material, and its thickness may be, for example, in the range of 20 μm to 80 μm. In some embodiments, intermediate layer 235 may be formed of organic materials, such as polyimide (PI), epoxy resin, laminated film (ABF), etc. In some embodiments, intermediate layer 235 may be formed of inorganic materials, such as oxides (e.g., SiOx, SiNx, TaOx), glass, silicon, ceramics, etc. In some embodiments, intermediate layer 235 may be an organic photosensitive liquid material, an organic non-photosensitive liquid material, an organic photosensitive dry film material, or an organic non-photosensitive dry film material.

[0048] like Figure 2aAs shown, a first chip 252 and a second chip 254 are disposed above the upper circuit layer 220. A high-density circuit region 240 is located below the gap between the first chip 252 and the second chip 254. The first chip 252 and the second chip 254 are electrically connected to the low-density circuit region 230 and the high-density circuit region 240 respectively through a first through-hole 222 and a second through-hole 224. The high-density circuit region 240 may have a bridging line 244 disposed on the surface of the high-density circuit region 240. The first chip 252 can be electrically connected to the bridging line 244 through a corresponding second through-hole 224, and the second chip 254 can be electrically connected to the bridging line 244 through a corresponding second through-hole 224.

[0049] The upper surfaces of the first chip 252 and the second chip 254 may not be flush. Furthermore, an underfill 260 may be disposed on the upper circuit layer 220, filling the space between the first chip 252 and the second chip 254 and the upper circuit layer 220, and surrounding the lower portions of the first chip 252 and the second chip 254. In some embodiments, the underfill 260 may be formed of an organic material, such as polyimide (PI), epoxy resin, or laminated film (ABF). In some embodiments, the underfill 260 may be formed of an inorganic material, such as oxides (e.g., SiOx, SiNx, TaOx), glass, silicon, or ceramics. In some embodiments, the underfill 260 may be an organic photosensitive liquid material, an organic non-photosensitive liquid material, an organic photosensitive dry film material, or an organic non-photosensitive dry film material.

[0050] Both the first chip 252 and the second chip 254 have bump connectors 255 on their lower surfaces, and these bump connectors 255 are electrically connected to the first through-hole 222 and the second through-hole 224 via solder 258. Since the first through-hole 222 and the second through-hole 224 are both formed by opening from the upper surface of the upper circuit layer 220, the top opening dimensions of the first through-hole 222 and the second through-hole 224 are the same, and the pad dimensions on the first through-hole 222 and the second through-hole 224 are also the same. Therefore, the bump connectors 255 of the first chip 252 and the second chip 254, which are electrically connected to the pads on the first through-hole 222 and the second through-hole 224, also have the same dimensions. Thus, with… Figure 1a and Figure 1b Compared to existing chips with mixed-size bump connectors, this design facilitates the bonding of chips to circuit layers, thereby increasing production yield.

[0051] Figure 2c and Figure 2d They are shown respectively Figure 2a The diagram shows a top view of the semiconductor package structure at sections A-A' and B-B'. Figure 2c As shown, bridging lines 244 are installed in the high-density line area 240. For example... Figure 2d As shown, the second through-hole 224 is located above the bridging chip 215. The first chip 252 and the second chip 254 can be interconnected through the second through-hole 224 formed on the bridging chip 215 and the bridging line 244 in the high-density line area 240. The high-density line area 240 and the low-density line area 230 provide interconnection between the bridging chip 215, the substrate 218, and the first chip 252 and the second chip 254.

[0052] Figure 3a and Figure 3b This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention. For example... Figure 3a and Figure 3b As shown, a molding compound 270 encapsulating the first chip 252, the second chip 254, and the underfill 260 can be formed on the upper circuit layer 220. Figure 3a In the illustrated embodiment, the molding compound 270 may have vertical sidewalls, and the sidewalls of the molding compound 270 are vertically aligned with the sidewalls of the lower circuit layer 210 and the substrate 218. Figure 3b In the illustrated embodiment, the molding compound 270 may be formed, for example, by a dispensing process, and has an upwardly convex curved surface profile.

[0053] Figure 4 This is a schematic diagram of a semiconductor package structure according to another embodiment of the present invention. In this embodiment, one of the first chip 252 and the second chip 254, such as the first chip 252, may not use a flip-chip bonding method. Instead, the active surface of the first chip 252 can be facing upwards, and the first chip 252 can be electrically connected to the pads on the upper circuit layer 220 and / or the pads on the second through-hole 224 through bonding wires 272.

[0054] Figure 5 This is a schematic diagram of a semiconductor package structure according to other embodiments of the present invention. Figure 2a The embodiments shown are different, such as Figure 5 As shown, conductive posts 259 can be provided on the first through-hole 222 and the second through-hole 224 below the first chip 252 to connect with the first chip 252. In other embodiments, conductive posts can also be provided on the first through-hole 222 and the second through-hole 224 below the second chip 254 to connect with the second chip 254.

[0055] Figure 6 This is a schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. In this embodiment, the number of chips above the upper circuit layer 220 may be more than two. Figure 6The diagram shows a first chip 252, a second chip 254, and a third chip 256 disposed above the upper circuit layer 220. High-density circuit regions 240 are respectively disposed below the gaps between the first chip 252 and the second chip 254, and between the second chip 254 and the third chip 256. Low-density circuit regions 230 are also respectively disposed below the first chip 252, the second chip 254, and the third chip 256. Each of the first chip 252, the second chip 254, and the third chip 256 is connected to the corresponding lower low-density circuit region 230 through a corresponding first through-hole 222 and to the corresponding lower high-density circuit region 240 through a corresponding second through-hole 224. In other embodiments, the number of chips may also be different.

[0056] Figure 7 This is a schematic diagram of a semiconductor package structure according to another embodiment of the present invention. In this embodiment, the dimensions of the bump connectors 255 beneath the first chip 252 and the second chip 254 may be different. For example, as... Figure 7 As shown, the size of the bump connector 255 below the first chip 252 is larger than the size of the bump connector 255 below the second chip 254. Accordingly, the sizes of the pads on the first through-hole 222 below the first chip 252 and the second chip 254 can be different, and the sizes of the pads on the second through-hole 224 below the first chip 252 and the second chip 254 can also be different.

[0057] Figures 8a to 8m This is a schematic diagram of the various stages of a method for forming a high-density circuit region in a semiconductor package structure according to an embodiment of the present invention.

[0058] like Figure 8a As shown, a carrier board 802 is provided. The carrier board 802 can be a bridge chip with pads 806. For example... Figure 8b A first dielectric layer 811 is formed above the pads of the substrate 802. The first dielectric layer 811 is then patterned. Patterning can be performed using acceptable processes, such as exposing the first dielectric layer 811 to light. After exposure, the first dielectric layer 811 is developed, and openings 821 are formed in the first dielectric layer 811, such as... Figure 8c As shown.

[0059] like Figure 8c As shown, a seed layer 831 is formed on the patterned first dielectric layer 811 and within the opening 821. In some embodiments, the seed layer 831 may be formed using a deposition process such as physical vapor deposition (PVD).

[0060] like Figure 8d As shown, a mask layer 841 is formed on the seed layer 831. In some embodiments, the mask layer 841 may be a photomask layer. Figure 8eAs shown, a patterned mask layer 841 is formed to create an opening 822 in the mask layer 841 that exposes the seed layer 831. In some embodiments, the mask layer 841 may be a photomask and patterned using a photolithography process. Furthermore, a conductive material 850 is formed on the seed layer 831 in the opening 821 of the first dielectric layer 811 and at the bottom of the opening 822 of the mask layer 841. The conductive material 850 may be formed by processes such as electroplating.

[0061] like Figure 8f As shown, the patterned mask layer 841 and the seed layer 831 covered by the patterned mask layer 841 are removed. The remaining seed layer 831 and the conductive material 850 thereon form traces 241 and vias 242 of interconnecting traces 241.

[0062] Then, it can be repeated like this. Figures 8b to 8f The steps involve forming more dielectric layers and traces and vias within those layers. For example... Figure 8g A second dielectric layer 812, a trace 241 located on the second dielectric layer 812, and a via 242 located within the interconnect trace 241 of the second dielectric layer 811 are formed on the first dielectric layer 811.

[0063] like Figure 8h A third dielectric layer 813 is formed on the second dielectric layer 812, and the third dielectric layer 813 is patterned to form an opening 823 located in the third dielectric layer 813. A seed layer 832 is deposited on the third dielectric layer 813 and within the opening 823. Then, as... Figure 8i As shown, a mask layer 842 is formed on the seed layer 832. (As indicated...) Figure 8j A patterned mask layer 842 is formed to create an opening 824 in the mask layer 842 that exposes the seed layer 832. The opening 824 in the mask layer 842 may be formed above the opening 823 of the third dielectric layer 813. A conductive material 850 is formed on the seed layer 832 in the opening 823 of the third dielectric layer 813 and at the bottom of the opening 824 of the mask layer 842. In some embodiments, the conductive material 850 may be a metal (e.g., Cu, Ag, Au, Al, Ni, Ti, Pd, Pt, solder) and / or a non-metal (e.g., graphene). In some embodiments, the seed layers 831 and 832 may be, for example, Ti, W, Ni, etc.

[0064] like Figure 8kThe mask layer 842 and the seed layer 832 covered by the mask layer 842 are removed. The remaining seed layer 832 and the conductive material 850 thereon form a higher layer of traces 21 and vias 242 that interconnect the two layers of traces 241. At this time, the seed layer 832 and the conductive material 850 thereon, which are retained on the third dielectric layer 813, also form a bridging line 244. In this way, a high-density circuit region 240 with fine lines is formed on the carrier board 802.

[0065] Subsequently, as Figure 8l As shown, Figure 8k The resulting structure is inverted, and DAF 808 is applied to the surface of carrier plate 802. Then... Figure 8l The resulting structure is inverted and then cut. For example... Figure 8m As shown, after the cutting process, the carrier board 802 is cut into multiple individual bridge cores 215, and a high-density circuit area 240 is formed above each individual bridge core 215. Subsequently, the bridge core 215 and the high-density circuit area 240 thereon can be picked up using the connector 892 for subsequent processes.

[0066] Figures 9a to 9i This is a schematic diagram of the various stages of a method for forming an upper circuit layer 220 in a semiconductor package structure according to an embodiment of the present invention.

[0067] like Figure 9a As shown, a first dielectric layer 911, on which the circuit layer is formed, is formed on the carrier 902, for example, by a lamination process. The first dielectric layer 911 is then patterned.

[0068] like Figure 9b The patterned first dielectric layer 911 has an opening 921 exposing the carrier 902. A seed layer 931 is formed over the first dielectric layer 911 and in the opening 921. In some embodiments, the seed layer 931 can be formed using, for example, physical vapor deposition (PVD).

[0069] like Figure 9c A mask layer 941 is formed on the seed layer 931. The mask layer 941 is then patterned to form openings 922 within the mask layer 941 that expose the seed layer 931, such as... Figure 9d As shown. The opening 922 of the mask layer 941 may be located above the opening 921 of the first dielectric layer 911 and is larger than the opening 921 of the first dielectric layer 911. A conductive material 950 is formed on the seed layer 931 within the opening 921 of the first dielectric layer 911 and at the bottom of the opening 922 of the mask layer 941.

[0070] like Figure 9eAs shown, the mask layer 941 and the seed layer 931 beneath it are removed. The remaining seed layer 931 and the conductive material 950 thereon form vias 222 and traces 221. Figure 9f As shown, a second dielectric layer 912 is overlaid on a first dielectric layer 911. The second dielectric layer 912 is then patterned, forming an opening 923 within it. The opening 923 in the second dielectric layer 912 exposes the underlying trace 221. A seed layer 932 is overlaid on the second dielectric layer 912 and within the opening 923. Then, as... Figure 9g As shown, a mask layer 942 is formed on the seed layer 932.

[0071] like Figure 9h As shown, a mask layer 942 is patterned, and an opening 924 is formed in the mask layer 942. The opening 924 of the mask layer 942 may be located above the opening 923 of the second dielectric layer 912. A conductive material 950 is formed on the seed layer 932 within the opening 923 of the second dielectric layer 912 and at the bottom of the opening 924 of the mask layer 942. In some embodiments, the conductive material 950 may be a metal (e.g., Cu, Ag, Au, Al, Ni, Ti, Pd, Pt, solder) and / or a non-metal (e.g., graphene). In some embodiments, the seed layers 931 and 932 may be, for example, Ti, W, Ni, etc.

[0072] like Figure 9i As shown, mask layer 942 and seed layer 932 below mask layer 942 are removed. The remaining seed layer 932 and the conductive material 950 thereon form a higher layer of traces 221 and vias 222 for interconnecting the traces 221. Thus, an upper circuit layer 220 is formed on the carrier 902. In other embodiments, the above steps can be repeated to form more dielectric layers, traces, and vias of the upper circuit layer 220.

[0073] Figures 10a to 10p This is a schematic diagram of various stages of a method for forming a semiconductor package structure using a pre-formed high-density circuit region and an upper circuit layer according to an embodiment of the present invention.

[0074] like Figure 10a As shown, a substrate 218 is provided, wherein the substrate 218 has a recessed first cavity 217. Then as... Figure 10b As shown, using the connector 892 to, for example Figure 8mA high-density circuit region 240, formed above the bridging core 215, is placed within the first cavity 217 of the substrate 218. The bridging core 215 and the high-density circuit region 240 can be attached to the first cavity 217 via the DAF 808 below the bridging core 215. The width of the high-density circuit region 240 is smaller than the width of the first cavity 217, so after placing the high-density circuit region 240 within the first cavity 217, there will be a gap between the high-density circuit region 240 and the sidewall of the first cavity 217.

[0075] like Figure 10c As shown, a dielectric layer 232 forms a low-density circuit region. The dielectric layer 232 covers the upper surface of the substrate 218 outside the first cavity 217, and the dielectric layer 232 also extends into the first cavity 217 to fill the gap between the bridge core 215 and the high-density circuit region 240 and the sidewall of the first cavity 217.

[0076] like Figure 10d As shown, the dielectric layer 232 is patterned, forming an opening 1021 within it. Furthermore, the patterned dielectric layer 232 also forms a second cavity 219 exposing the high-density circuit region 240. A seed layer 1031 is deposited on the dielectric layer 232, within the opening 1021 and the second cavity 219. The seed layer 1031 covers the high-density circuit region 240.

[0077] like Figure 10e As shown, a mask layer 1041 is formed on the seed layer 1031. The mask layer 1041 is patterned, and openings 1022 are formed in the mask layer 1041, as shown. Figure 10f As shown. The opening 1022 of the mask layer 1041 can be located above the opening 1021 of the dielectric layer 232. A conductive material 1050 is formed on the seed layer 1031 in the opening 1021 of the dielectric layer 232 and at the bottom of the opening 1022 of the mask layer 1041.

[0078] like Figure 10g As shown, the mask layer 1041 and the seed layer 1031 below the mask layer 1041 are removed to form traces 231 on the dielectric layer 232 and vias 233 in the dielectric layer 232 to interconnect the traces 231. Thus, a low-density circuit region 230 is formed on the substrate 218 outside the first cavity 217, and a lower circuit layer 210 is formed.

[0079] like Figure 10h As shown, an intermediate layer 235 is applied over the low-density circuit area 230 and the high-density circuit area 240. The upper circuit layer 220 is then attached to the low-density circuit area 230 and the high-density circuit area 240 through the intermediate layer 235. The carrier 902 is then removed.

[0080] like Figure 10i As shown, openings are made on the upper surface of the upper circuit layer 220. For example, a laser drilling process can be used to form a first opening 1052 above the low-density circuit region 230 and a second opening 1054 above the high-density circuit region 240. The depths of the first opening 1052 and the second opening 1054 can be the same. The first opening 1052 above the low-density circuit region 230 reaches the surface of the low-density circuit region 230. Since the surface of the high-density circuit region 240 is lower than the surface of the low-density circuit region 230, the second opening 1054 above the high-density circuit region 240 does not reach the high-density circuit region 240.

[0081] like Figure 10j As shown, the depth of the second aperture 1054 above the high-density circuit region 240 is further increased, so that the second aperture 1054 above the high-density circuit region 240 reaches the surface of the high-density circuit region 240. In some embodiments, the depth of the second aperture 1054 can be increased by an etching operation. In some embodiments, the first aperture 1052 and the second aperture 1054 can be formed by laser aperture, plasma aperture, or etch-back method, etc. Then, a seed layer 1032 is deposited on the upper circuit layer 220, within the first aperture 1052 and the second aperture 1054.

[0082] like Figure 10k As shown, a mask layer 1042 is formed on the seed layer 1032. The mask layer 1042 fills each of the first opening 1052 and the second opening 1054. The mask layer 1042 is then patterned, and openings 1023 are formed in the mask layer 1042, as shown. Figure 10l As shown. Patterning of the mask layer 1042 removes the mask layer 1042 in the first opening 1052 and the second opening 1054, such that openings 1023 are formed in the mask layer 1042 to expose the first opening 1052 and the second opening 1054. Then, a conductive material 1050 is formed on the seed layer 1032 in the first opening 1052 and the second opening 1054 and at the bottom of the opening 1023. In some embodiments, the conductive material 1050 may be a metal (e.g., Cu, Ag, Au, Al, Ni, Ti, Pd, Pt, solder) and / or a non-metal (e.g., graphene). In some embodiments, the seed layers 1031, 1032 may be made of, for example, Ti, W, Ni, etc.

[0083] Then remove mask layer 1042, as follows Figure 10mAs shown. The seed layer 1032 and conductive material 1050 within the first aperture 1052 and the second aperture 1054 form the first through-hole 222 and the second through-hole 224. The seed layer 1032 and conductive material 1050 above the first aperture 1052 and the second aperture 1054 form pads 229 that connect to the first through-hole 222 and the second through-hole 224. The contact surface between the second through-hole 224 and the high-density circuit region 240 is smaller than the contact surface between the first through-hole 222 and the low-density circuit region 230. As described above, a bridging line 244 is formed in the high-density circuit region 240. The second through-hole 224 can be electrically connected to the bridging line 244.

[0084] like Figure 10n As shown, a first chip 252 and a second chip 254 are placed on the upper circuit layer 220. A high-density circuit region 240 is located below the gap between the first chip 252 and the second chip 254. Each of the first chip 252 and the second chip 254 is respectively engaged with a first through-hole 222 and a second through-hole 224 to connect to the low-density circuit region 230 and the high-density circuit region 240. In this embodiment, the first through-hole 222 and the second through-hole 224 are bonded to bump connectors 255 on the lower surfaces of the first chip 252 and the second chip 254 by solder 258. The first chip 252 can be electrically connected to a bridging line 244 through a corresponding second through-hole 224, and the second chip 254 can be electrically connected to the bridging line 244 through a corresponding second through-hole 224.

[0085] like Figure 10o As shown, a bottom filler 260 is formed between the first chip 252 and the second chip 254 and the upper circuit layer 220. The bottom filler 260 surrounds the lower portion of the first chip 252 and the lower portion of the second chip 254. Then as... Figure 10p As shown, solder balls 216 are formed on the lower surface of substrate 218, and a dicing process is performed along the dashed line L to form the final package structure, for example, as shown. Figure 2a The packaging structure shown.

[0086] In the method for forming the package structure described above according to the present invention, firstly, a bridging chip 215 and a high-density circuit region 240 are placed in a first cavity 217 of a substrate 218. The high-density circuit region 240 may be pre-formed on the bridging chip 215, and bridging lines 244 are present in the high-density circuit region 240. Then, a dielectric layer 232 of a low-density circuit region 230 is filled between the sidewalls of the bridging chip 215 and the high-density circuit region 240 and the sidewalls of the first cavity 217, and the dielectric layer 232 defines a second cavity 219 on the high-density circuit region 240. Next, an intermediate layer 235 is coated on the surfaces of the high-density circuit region 240 and the substrate 218, and then an upper circuit layer 220 is bonded to the intermediate layer 235 using a carrier 902. After removing the carrier 902, a drilling process is performed from the surface of the upper circuit layer 220 to form a first through-hole 222 and a second through-hole 224. Finally, the chip is bonded to the first through-hole 222 and the second through-hole 224. After the solder ball placement and dicing processes are completed, the final package structure is formed.

[0087] Because the aspect ratio (AR) of vias 222 and 224 allows the second via 224 on the lower surface of the high-density circuit region 240 to have a smaller aperture, fine pitch design can be performed directly on the bridging chip 215 without sacrificing fine pitch and designing large pads due to aperture limitations, thus avoiding impacting circuit layout space. Furthermore, providing bridging links through the high-density circuit region 240 provides a higher plane levelness (e.g., height deviation less than 5%).

[0088] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: The lower circuit layer includes a high-density circuit area and a low-density circuit area. The I / O density of the high-density circuit area is greater than that of the low-density circuit area, and the I / O interface of the high-density circuit area is lower than that of the low-density circuit area. An upper circuit layer, located above the lower circuit layer, includes a first through-hole electrically connected to the I / O of the low-density circuit area, and a second through-hole electrically connected to the I / O of the high-density circuit area. An intermediate layer is located between the upper circuit layer and the lower circuit layer and joins the upper circuit layer and the lower circuit layer; Wherein, the first through hole is a continuous through hole that penetrates the upper surface of the upper circuit layer and the intermediate layer to reach the surface of the low-density circuit area, and the second through hole is a continuous through hole that penetrates the upper surface of the upper circuit layer and the intermediate layer to reach the surface of the high-density circuit area. The height of the second through hole is greater than the height of the first through hole, and the aperture of the second through hole on the surface of the high-density circuit area is smaller than the aperture of the first through hole on the surface of the low-density circuit area.

2. The semiconductor packaging structure according to claim 1, characterized in that, The upper surface of the first through hole is coplanar with the upper surface of the second through hole.

3. The semiconductor packaging structure according to claim 1, characterized in that, The lower circuit layer also includes a bridging chip located below the high-density circuit area.

4. The semiconductor packaging structure according to claim 1, characterized in that, It also includes a substrate having a cavity, wherein the high-density circuit region of the lower circuit layer is located in the cavity of the substrate.

5. The semiconductor packaging structure according to claim 4, characterized in that, The low-density circuit region has a dielectric layer that extends into the cavity of the substrate, and the high-density circuit region is located between the dielectric layers in the cavity.

6. The semiconductor packaging structure according to claim 1, characterized in that, The contact surface between the second through hole and the I / O of the high-density circuit area is smaller than the contact surface between the first through hole and the I / O of the low-density circuit area.

7. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: The first chip and the second chip are located above the upper circuit layer, and the high-density circuit area is located below the gap between the first chip and the second chip.

8. A method for forming a semiconductor package structure, characterized in that, include: Provide a substrate with a cavity; A high-density circuit area is placed inside the cavity, and a low-density circuit area is formed on the substrate outside the cavity. A circuit layer is attached above the substrate, including: An intermediate layer is applied over the low-density line area and the high-density line area; The upper circuit layer is attached to the low-density circuit area and the high-density circuit area through the intermediate layer; A second through-hole is formed that passes through the upper circuit layer and is electrically connected to the high-density circuit area, and a first through-hole is formed that passes through the upper circuit layer and is electrically connected to the low-density circuit area, wherein the I / O density of the high-density circuit area is greater than the I / O density of the low-density circuit area; The formation of the first through hole and the second through hole includes: A first opening is formed on the upper surface of the upper circuit layer, located above the low-density circuit area and a second opening is formed on the upper surface of the high-density circuit area. The first opening and the second opening have the same depth and continuously penetrate the upper circuit layer and the intermediate layer. The end of the first opening reaches the surface of the low-density circuit area, and the end of the second opening does not reach the surface of the high-density circuit area. The depth of the second opening above the high-density circuit area is further increased, so that the end of the second opening continues to reach the surface of the high-density circuit area, and the depth of the second opening is greater than the depth of the first opening. A first through hole is formed in the first opening and a second through hole is formed in the second opening, wherein the diameter of the second through hole on the surface of the high-density circuit area is smaller than the diameter of the first through hole on the surface of the low-density circuit area.

9. The method for forming a semiconductor package structure according to claim 8, characterized in that, Before placing the high-density circuitry area within the cavity, the method further includes: The high-density circuit area is formed on the bridging chip.

10. The method for forming a semiconductor package structure according to claim 9, characterized in that, Forming the high-density circuit region on the bridge chip includes: A dielectric layer covering the carrier and conductive lines located in the dielectric layer are formed on the carrier to form a high-density circuit area; The high-density circuit area and the carrier board are cut to form a single high-density circuit area located on the bridging chip.

11. The method for forming a semiconductor package structure according to claim 8, characterized in that, After the high-density circuit area is placed inside the cavity, there is a gap between the high-density circuit area and the sidewall of the cavity.

12. The method for forming a semiconductor package structure according to claim 11, characterized in that, The formation of the low-density line area includes: A dielectric layer for the low-density circuit region is formed on the substrate outside the cavity and within the interval; Conductive lines are formed in the dielectric layer to form the low-density circuit region.

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