Display substrate and its manufacturing method, display panel

Abstract

A display substrate, its fabrication method, and a display panel are disclosed, relating to the field of display technology. The display substrate includes: a substrate comprising multiple pixel regions and edge regions between adjacent pixel regions; a thin-film transistor array layer disposed on the substrate; and a cover layer covering the thin-film transistor array layer, the cover layer including a first cover portion located in the pixel regions and a second cover portion located in the edge regions; the distance between the surface of the first cover portion and the substrate, and the distance between the surface of the second cover portion and the substrate are unequal; both the surfaces of the first and second cover portions belong to the side of the cover layer away from the substrate. The display substrate, its fabrication method, and the display panel provided by this disclosure can improve the light extraction efficiency of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and its manufacturing method, and a display panel. Background Technology

[0002] With the development of display technology, the light emission efficiency of display panels is receiving increasing attention. However, in related technologies, there is a problem of relatively low light emission efficiency in display panels. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display substrate, a method for manufacturing the same, and a display panel.

[0004] To achieve the above objectives, some embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a display substrate is provided. The display substrate includes: a substrate, a thin-film transistor array layer, and a cover layer. The substrate includes a plurality of pixel regions and edge regions between adjacent pixel regions; the thin-film transistor array layer is disposed on the substrate. The cover layer covers the thin-film transistor array layer, and the cover layer includes a first cover portion located in the pixel region and a second cover portion located in the edge region. The distance between the surface of the first cover portion and the substrate and the distance between the surface of the second cover portion and the substrate are not equal; the surfaces of the first cover portion and the second cover portion both belong to the surface of the cover layer away from the substrate.

[0006] In some embodiments, the display substrate is applied to a top-emitting display panel; the distance between the surface of the first cover portion and the substrate is smaller than the average distance between the surface of the second cover portion and the substrate.

[0007] In some embodiments, the display substrate is applied to a bottom-emitting display panel; the distance between the surface of the first cover portion and the substrate is greater than the average distance between the surface of the second cover portion and the substrate.

[0008] In some embodiments, the display substrate further includes a color filter layer located between the thin-film transistor array layer and the cover layer, the color filter layer including a first filter portion, a second filter portion, a third filter portion and a white filter portion; the material of the cover layer is reused as the white filter portion.

[0009] In some embodiments, the thin-film transistor array layer includes a source / drain metal layer and a passivation layer covering the source / drain metal layer; the passivation layer has a first via through the passivation layer, the first via exposing the source / drain metal layer; the cover layer has a second via through the cover layer, the first via communicating with the second via.

[0010] In some embodiments, the portion of the surface of the second cover that contacts the surface of the first cover is a slope with a first slope angle; the opening of the second via at the end away from the substrate is larger than the opening of the second via at the end near the substrate, and the second via has a second slope angle; the second slope angle is larger than the first slope angle.

[0011] In some embodiments, the second slope angle is 50° to 70°, and the first slope angle is 15° to 30°.

[0012] In some embodiments, the surface of the second cover is an arched surface.

[0013] In some embodiments, the display substrate is applied to a top-emitting display panel, and the thickness of the first covering portion is less than the thickness of the second covering portion; or, the display substrate is applied to a bottom-emitting display panel, and the thickness of the first covering portion is greater than the thickness of the second covering portion.

[0014] In some embodiments, the second covering portion surrounds the first covering portion. Alternatively, the first covering portion is rectangular in shape; the second covering portion is disposed between the long sides of two adjacent first covering portions; and / or, the second covering portion is disposed between the short sides of two adjacent first covering portions.

[0015] In another aspect, a display panel is provided. The display panel includes a display substrate as described above and a light-emitting device. The light-emitting device is disposed on the display substrate, and the light-emitting device includes a reflective electrode and a light-emitting layer. The reflective electrode includes a main body portion located in a pixel region and a reflective portion located in an edge region; the reflective portion protrudes towards the light-emitting layer, reflecting light propagating to the edge region back to the pixel region.

[0016] In some embodiments, the display panel further includes a pixel delimiting layer having multiple openings, each opening defining a pixel region; the pixel delimiting layer is located within the edge region.

[0017] In some embodiments, the display panel is a top-emitting display panel, the reflective electrode is located on the side of the light-emitting layer closer to the substrate, and the edge of the reflective portion extends toward the substrate; or, the display panel is a bottom-emitting display panel, the reflective electrode is located on the side of the light-emitting layer away from the substrate, and the edge of the reflective portion extends toward the substrate.

[0018] In another aspect, a method for manufacturing a display panel is provided. The method includes: providing a substrate, the substrate including a plurality of pixel regions and edge regions between adjacent pixel regions; forming a thin-film transistor array layer on the substrate; and forming a cover layer covering the thin-film transistor array layer, the cover layer including a first cover portion located in the pixel regions and a second cover portion located in the edge regions. The distance between the surface of the first cover portion and the substrate and the distance between the surface of the second cover portion and the substrate are unequal; the surfaces of both the first and second cover portions belong to the side of the cover layer away from the substrate.

[0019] In some embodiments, forming a capping layer covering the thin-film transistor array layer includes: depositing a planarization material layer covering the thin-film transistor array layer; exposing, developing, and etching the planarization material layer using a halftone mask process to retain the planarization material in the edge regions and remove a portion of the planarization material in the pixel regions to form a capping layer; or, depositing a planarization material layer covering the thin-film transistor array layer; exposing, developing, and etching the planarization material layer using a halftone mask process to retain the planarization material in the pixel regions and remove a portion of the planarization material in the edge regions to form a capping layer.

[0020] The display substrate provided in this embodiment has different spacing between the surface of the first cover portion in the pixel area and the substrate and between the surface of the second cover portion in the edge area and the substrate. This makes the surface of the cover layer provide an uneven surface. The shape of each film layer of the light-emitting device subsequently formed on the cover layer is the same as the shape of the cover layer surface. This allows the reflective electrode in the subsequently formed light-emitting device to reflect the light propagating to the edge area to the pixel area, thereby improving the light extraction efficiency of the display panel. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 A top view of a display device;

[0023] Figure 2 For along Figure 1 A cross-sectional view formed by line A-A' in the middle;

[0024] Figure 3A A cross-sectional view of a display panel according to some embodiments of the present disclosure;

[0025] Figure 3B for Figure 3A Enlarged view of the K region;

[0026] Figure 4A This is another cross-sectional view of a display panel according to some embodiments of the present disclosure;

[0027] Figure 4B for Figure 4A Enlarged view of region F in the middle;

[0028] Figure 5 A cross-sectional view of a display device according to some embodiments of the present disclosure;

[0029] Figure 6 This is another cross-sectional view of a display device according to some embodiments of the present disclosure;

[0030] Figures 7A to 7G This is a diagram showing the positional relationship between the first covering portion and the second covering portion according to some embodiments of the present disclosure;

[0031] Figure 8A This is a structural diagram of the color filter layer and the cover layer according to some embodiments of the present disclosure in a single stage;

[0032] Figure 8B This is a structural diagram of the color filter layer and the cover layer according to some embodiments of the present disclosure at another stage;

[0033] Figure 9 This is a flowchart of a method for manufacturing a display substrate according to some embodiments of the present disclosure;

[0034] Figure 10 This is another flowchart of a method for manufacturing a display substrate according to some embodiments of the present disclosure;

[0035] Figure 11A This is a diagram showing the positional relationship between the overlay layer and the half-exposure mask during the exposure process according to some embodiments of the present disclosure;

[0036] Figure 11B This is a structural diagram of the cover layer after etching according to some embodiments of the present disclosure;

[0037] Figure 12A This is a diagram showing the positional relationship between the overlay layer and the half-exposure mask during the exposure process according to some embodiments of the present disclosure;

[0038] Figure 12B This is a structural diagram of the cover layer after etching according to some embodiments of the present disclosure. Detailed Implementation

[0039] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0040] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0041] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0042] The term "electrical connection" is used in describing some embodiments. For example, the term "electrical connection" is used in describing some embodiments to indicate that two or more components are in electrical contact with each other.

[0043] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0044] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0045] As used herein, “approximately” includes the values ​​stated and the average value within an acceptable range of deviation from the given values, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0046] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0047] With the rapid development of OLED (Organic Light-Emitting Diode) display devices, full-screen, narrow bezel, high resolution, and large size have become important development directions for OLED in the future.

[0048] Figure 1 A top view of a display device 00; Figure 2 For along Figure 1 A partial cross-sectional view formed by line A-A'. In some embodiments, such as Figure 2 As shown, the display substrate 10 of the display device 00 includes a substrate 01, and a thin-film transistor array layer 02, a planarization layer 03, a light-emitting device 04, and an encapsulation layer 05 sequentially disposed on the substrate 01. The planarization layer 03 covers the thin-film transistor array layer 02 and provides a flat fabrication surface for the light-emitting device 04, so that multiple light-emitting devices 04 subsequently formed are on the same plane.

[0049] However, the inventors of this disclosure have discovered through research that the light emitted by each light-emitting device 04 in the above-mentioned display device 00 is easily propagated to the edge area between adjacent light-emitting devices 04, and is thus absorbed by light-absorbing materials such as black matrix located in the edge area, resulting in less light emitted by the light-emitting device 04 and a problem of low light emission efficiency of the display device 00.

[0050] Based on this, such as Figure 3A and Figure 4A As shown, some embodiments of this disclosure provide a display panel 100, applied to a display device 1000, such as... Figure 5 and Figure 6As shown. The display device 1000 can be an electroluminescent display device or a photoluminescent display device. When the display device 1000 is an electroluminescent display device, it can be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a liquid crystal display (LCD), or an electrophoretic display (EPD). When the display device is a photoluminescent display device, it can be a quantum dot photoluminescent display device.

[0051] Exemplary embodiments of this disclosure are described using OLED display devices, but should be considered as not being limited to OLED display devices. In some embodiments, such as Figure 5 and Figure 6 As shown, the main structure of the display device 1000 includes a display panel 100, a touch structure 500, an anti-reflective structure such as a polarizer 600, a first optically clear adhesive (OCA) layer 710, and a cover plate 800 arranged sequentially. In some embodiments, the anti-reflective structure may include a color filter and a black matrix.

[0052] The display panel 100 includes a display substrate 200 and an encapsulation layer 300 for encapsulating the display substrate 200. Here, the encapsulation layer 300 can be an encapsulation film or an encapsulation substrate.

[0053] In some embodiments, such as Figure 5 As shown, the touch structure 500 is directly disposed on the encapsulation layer 300, so the display substrate 200 can be regarded as the substrate of the touch structure 500. This structure is conducive to achieving a thinner and lighter display device.

[0054] In some embodiments, the encapsulation layer 300 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer, or it may be a stacked structure of at least one organic layer and at least one inorganic layer. In some embodiments, an anti-reflective structure may be formed in the encapsulation layer 300 to provide anti-reflection protection, while also further reducing the thickness of the display device.

[0055] In other embodiments, such as Figure 6As shown, the touch structure 500 of the display panel 100 is disposed on the substrate 400, and the substrate 400 is attached to the encapsulation layer 300 through the second optical adhesive layer 720. The material of the substrate 400 may be, for example, polyethylene terephthalate (PET), polyimide (PI), cycloolefin polymer (COP), etc.

[0056] like Figures 3A to 6 As shown, each sub-pixel of the display substrate 200 includes a light-emitting device 230 and a driving circuit disposed on the substrate 210. The driving circuit includes a plurality of thin-film transistors 221. The light-emitting device 231 includes an anode 231, a light-emitting layer 232, and a cathode 233. The anode 231 and the drain of the thin-film transistor 221 serving as the driving transistor in the plurality of thin-film transistors 221 of the driving circuit are electrically connected.

[0057] In some embodiments, when the anode 231 and the drain of the thin-film transistor 221 serving as the driving transistor among the plurality of thin-film transistors 221 of the driving circuit are electrically connected, they are also electrically connected through a transfer electrode located between the film layer where the drain is located and the film layer where the anode is located.

[0058] The display substrate 200 also includes a pixel defining layer 240, which includes a plurality of openings 240A, with one light-emitting device 230 corresponding to one opening 240A.

[0059] In some embodiments, the light-emitting device 230 includes a light-emitting layer 232. In other embodiments, in addition to the light-emitting layer 232, the light-emitting device 230 also includes one or more of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0060] like Figures 3A to 6 As shown, the display substrate 200 also includes at least one cover layer 250 disposed between the thin-film transistor 221 and the anode 231. In some embodiments, the cover layer 250 further includes at least one passivation layer.

[0061] When the display device is an electroluminescent display device, it can be a top-emitting display device, in which case the anode 231 near the substrate 210 is opaque and the cathode 233 away from the substrate 210 is transparent or semi-transparent; the display device can also be a bottom-emitting display device, in which case the anode 231 near the substrate 210 is transparent or semi-transparent and the cathode 233 away from the substrate 210 is opaque; the display device can also be a double-sided emitting display device, in which case both the anode 231 near the substrate 210 and the cathode 233 away from the substrate 210 are transparent or semi-transparent.

[0062] like Figure 3A and Figure 4A As shown, some embodiments of this disclosure provide a display substrate 200, including: a substrate 210, a thin film transistor array layer 220, and a cover layer 250.

[0063] Substrate 210 includes multiple pixel regions I and edge regions II between adjacent pixel regions I;

[0064] Thin-film transistor array layer 220 is disposed on substrate 210;

[0065] The capping layer 250 covers the thin film transistor array layer 220. The capping layer 250 includes a first capping portion 251 located in pixel region I and a second capping portion 251 located in edge region II. The distance between the surface of the first capping portion 251 and the substrate 210 is different from the distance between the surface of the second capping portion 252 and the substrate 210. The surfaces of the first capping portion 251 and the second capping portion 252 are both surfaces of the capping layer 250 away from the substrate 210.

[0066] The substrate 210 can be an organic substrate or an inorganic substrate. The material of the substrate 210 can be polyethylene terephthalate (PET), polyimide (PI), cycloolefin polymer (COP), glass substrate, etc., and is not limited here.

[0067] The aforementioned thin-film transistor array layer 220 includes a plurality of thin-film transistors 221, wherein the thin-film transistors 221 can be either top-gate thin-film transistors or bottom-gate thin-film transistors. When the display device 1000 on which the display substrate 200 is applied is a top-emitting display device, the thin-film transistors 221 can be top-gate thin-film transistors; when the display device 1000 is a bottom-emitting display device, the thin-film transistors 221 can be bottom-gate thin-film transistors.

[0068] like Figures 7A to 7EAs shown, both pixel region I and edge region II are located within the display area AA (also known as the effective display area) of the display substrate 200. Pixel region I may be the area where the light-emitting port 240A of the pixel defining layer 240 in the display panel 100 is located. Multiple pixel regions I are arrayed and distributed within the display area, and edge region II is located between adjacent pixel regions I.

[0069] The aforementioned overlay layer 250 includes a first overlay portion 251 located in pixel region I and a second overlay portion 252 located in edge region II. In some embodiments, the second overlay layer 252 may be disposed surrounding the first overlay portion 251, such as... Figure 7A As shown. The second covering layer 252 can also be disposed on at least one side of the first covering portion 251. Taking the shape of the first covering portion 251 as an example, the second covering layer 252 can be disposed on opposite sides of the first covering portion 251, such as... Figure 7B As shown; or, the second covering layer 252 can be disposed on both sides near one corner of the first covering portion 251, such as... Figure 7C As shown; or, the second covering layer 252 can be disposed on three sides of the first covering portion 251, such as... Figure 7D As shown; or, the second covering layer 252 can be disposed on the four sides of the first covering portion 251, as shown. Figure 7E As shown, Figure 7E and Figure 7A The difference is Figure 7E The second cover layers 252 are not interconnected. Of course, the second cover layer 252 can also be provided only on one side of the first cover portion 251, such as... Figure 7F and Figure 7G As shown, no specific limitations are imposed here. Among them, Figure 7F The second covering portion 252 is disposed between the long sides of two adjacent first covering portions 251. Figure 7G The second covering portion 252 is disposed between the short sides of two adjacent first covering portions 251.

[0070] In addition, the cover layer 250 may also include a cover portion located outside the display area. The surface of the cover portion located outside the display area away from the substrate 210 may be a plane or a surface with an unequal distance from the substrate 210, which is not limited here.

[0071] The capping layer 250 can be made of organic materials such as resin. Due to the fluidity of organic materials, the surface of the capping layer 250 on the side away from the substrate 210 is roughly flat after the initial molding. After the initial molding, the capping layer 250 can be exposed again using a half-exposure mask, and after development, etched to remove some of the flat material in pixel area I or edge area II, resulting in a structure where the distance between the surface of the first capping portion 251 and the substrate 210 is unequal to the distance between the surface of the second capping portion 252 and the substrate 210. Figure 3A and Figure 4A As shown, Figure 3A and Figure 4A The distance between the surface of the first covering portion 251 and the substrate 210 is d1, and the distance between the surface of the second covering portion 252 and the substrate 210 is d2, where d1 ≠ d2.

[0072] It should be noted that since the surface of the thin-film transistor array layer 220 away from the substrate 210 is not planar, the surface of the first cover portion 251 near the substrate 210 and the surface of the second cover portion 252 near the substrate 210 may not be on the same surface.

[0073] like Figure 3A and Figure 4A As shown, the light-emitting device 230 is formed on the cover layer 250 in the display panel 100. Since each functional layer in the light-emitting device 230 is a uniformly thick functional layer formed using a deposition process, the thickness of the functional layer is equal at all locations. For example, the anode 231, the light-emitting layer 232, and the cathode 233 are all uniformly thick functional layers. Therefore, the shape of each functional layer in the light-emitting device 230 will be the same as the shape of the surface of the cover layer 250 on the side away from the substrate 210 where the functional layer is located.

[0074] For example, if the distance between the surface of the first covering portion 251 and the substrate 210 is less than the distance between the surface of the second covering portion 252 and the substrate 210, then the distance between portion 1 located in pixel region I and the substrate 210 in the same functional layer is less than the distance between portion 2 located in edge region II and the substrate 210. Furthermore, if the surface of the second covering portion 252 is an arched surface, then the portion in edge region II of the functional layer has an arched structure with the same curvature as the arched surface.

[0075] like Figure 5 As shown, when the display device 1000 is a top-emitting type display device, the cathode 233 is the transmission electrode and the anode 231 is the reflection electrode; as Figure 6As shown, when the display device 1000 is a bottom-emitting display device, the anode 231 is a transmission electrode and the cathode 233 is a reflection electrode. The transmission electrode is made of a transparent material or a semi-transparent semi-reflective material, such as transparent ITO; the reflection electrode is made of a metallic material, such as silver (Ag) or aluminum (Al).

[0076] In summary, the display substrate provided in some embodiments of this disclosure, by designing the spacing d1 between the surface of the first covering portion 251 and the substrate 210 and the spacing d2 between the surface of the second covering portion 252 and the substrate 210 to be unequal, enables the reflective electrode in the light-emitting device 230 subsequently formed on the covering layer 250 to undergo corresponding morphological changes, so that the portion of the reflective electrode located in the edge region II can reflect the light propagating to the edge region II back to the pixel region I, thereby improving the light extraction efficiency of the light-emitting device 230 and thus improving the luminous efficiency of the display device 1000.

[0077] In some embodiments, such as Figure 3A and Figure 3B As shown, the display substrate 200 is applied to the top-emitting display panel 100;

[0078] The distance between the surface of the first cover portion 251 and the substrate 210 is smaller than the average distance between the surface of the second cover portion 251 and the substrate 210.

[0079] The aforementioned top-emitting display panel 100 refers to the light emitted by the light-emitting device 230 propagating away from the substrate 210 to achieve the display of the display panel 100. Since the propagation path of the light does not pass through the thin-film transistor array layer 220, it is not blocked by the reflective material in the thin-film transistor array layer 220, and has a high aperture ratio.

[0080] By designing the distance between the surface of the first cover portion 251 and the substrate 210 to be smaller than the average distance between the surface of the second cover portion 251 and the substrate 210, the anode 231 (reflective electrode) subsequently formed on the cover layer 250 can protrude in the reflective portion 231A of the edge region II relative to the light-emitting portion 231B of the pixel region I in a direction away from the substrate 210. Figure 3B As can be seen, the raised reflective portion 231A can reflect the light propagating to the edge region II (the thick black line with arrows in the attached figure represents the light, and the arrows indicate the direction of light propagation) back to the pixel region I, thereby improving the light emission efficiency of the light-emitting device 230 and thus improving the light emission efficiency of the display device 1000.

[0081] In some embodiments, such as Figure 4A As shown, the display substrate 200 is applied to the bottom-emitting display panel 100;

[0082] The distance between the surface of the first cover portion 251 and the substrate 210 is greater than the average distance between the surface of the second cover portion 252 and the substrate 210.

[0083] The aforementioned bottom-emitting display panel 100 refers to the light emitted from the light-emitting device 230 propagating towards the substrate 210 to achieve the display of the display panel 100. The propagation path of the light in the bottom-emitting display panel 100 partially passes through the thin-film transistor array layer 220.

[0084] By designing the distance between the surface of the first cover portion 251 and the substrate 210 to be greater than the average distance between the surface of the second cover portion 252 and the substrate 210, the cathode 233 (reflective electrode) subsequently formed on the cover layer 250 can protrude from the reflective portion 233A in the edge region II relative to the light-emitting portion 233B in the pixel region I towards the substrate 210. Figure 4B As can be seen, the raised reflective portion 233A can reflect the light propagating to the edge region II back to the pixel region I, thereby improving the light emission efficiency of the light-emitting device 230 and thus improving the light emission efficiency of the display device 1000.

[0085] In some embodiments, such as Figure 8A and Figure 8B As shown, the display substrate 200 also includes a color filter layer 260 located between the thin film transistor array layer 220 and the cover layer 250. The color filter layer 260 includes a first filter portion 261, a second filter portion 262, a third filter portion 263 and a white filter portion 264; the material of the cover layer 250 is reused as the white filter portion 264.

[0086] In the bottom-emitting display panel 100, the light emitted by the light-emitting device 230 can be white light. The white light is converted into colored light by multiple color filters in the color filter layer 260, thereby realizing full-color display of the display panel 100.

[0087] In some embodiments, such as Figure 8A As shown, a first filter portion 261, a second filter portion 262, and a third filter portion 263 are formed on the thin-film transistor array layer 220. The first filter portion 261 is located in the first filter region R, the second filter portion 262 is located in the second filter region G, and the third filter portion 263 is located in the third filter region B. Then, a planarization material is used to cover the first filter portion 261, the second filter portion 262, and the third filter portion 263, and a white filter portion 264 is formed in the white filter region W. Due to the fluidity of the planarization material, a flat surface can be formed in each filter region; that is, the thickness of the filter portion and the planarization material in the first filter region R, the second filter region G, and the third filter region B is equal to the thickness of the planarization material in the white filter region W.

[0088] However, since the evaporation loss of organic solvent is proportional to the thickness of the organic solvent, that is, the evaporation amount of planarizing material in the white filter area W is greater than that in other filter areas (R, G, B), the height of the capping layer 250 in the white filter area W after evaporation is lower than the height of the capping layer 250 in other filter areas. This results in a depression 70A forming at the edge where the white filter area W meets other filter areas. Figure 8B As shown. Figure 8B The recess 70A in the middle will cause the light at the edge of pixel area I to diverge, thereby reducing the light output efficiency of the light-emitting device 230.

[0089] In some of the above embodiments, by improving the morphology of the cover layer 250, the distance between the surface of the first cover portion 251 and the substrate 210 is greater than the average distance between the surface of the second cover portion 252 and the substrate 210, such as... Figure 4A As shown, the recess formed at the edge where the white filter area meets other filter areas can be overcome, thereby eliminating the problems caused by the recess. This allows the cathode 233 (reflective electrode) formed on the cover layer 250 to protrude in the reflective portion 233A of the edge region II relative to the light-emitting portion 233B of the pixel region I, towards the substrate 210. The protruding reflective portion 233A can reflect light propagating to the edge region II back to the pixel region I, thereby improving the light extraction efficiency of the light-emitting device 230 and thus improving the luminous efficiency of the display device 1000.

[0090] In some embodiments, such as Figure 3A and Figure 4A As shown, the thin-film transistor array layer 220 includes a source / drain metal layer 2215 and a passivation layer 2216 covering the source / drain metal layer 2215; the passivation layer 2216 has a first via H1 that penetrates the passivation layer 2216, and the first via H1 exposes the source / drain metal layer 2215.

[0091] The cover layer 250 has a second through hole H2 that penetrates the cover layer 250, and the first through hole H1 is connected to the second through hole H2.

[0092] The thin-film transistor 221 includes an active layer 2211, a gate insulating layer 2212, a gate 2213, an interlayer insulating layer 2214, a source / drain metal layer 2215 that passes through the interlayer insulating layer 2214 and is connected to the active layer 2211, and a passivation layer 2216 that covers the source / drain metal layer 2215, which are sequentially disposed on the substrate 210.

[0093] The first via H1 and the second via H2 are connected, so that the anode 231 subsequently fabricated on the cover layer 250 can pass through the first via H1 and the second via H2 and be connected to the source and drain metal layer 2215 of the thin film transistor 221, thereby realizing the electrical connection between the drain of the thin film transistor 221, which serves as the driving transistor, and the anode 231 among the multiple thin film transistors 221 in the driving circuit.

[0094] In some embodiments, such as Figure 3A and Figure 4A As shown, the active layer 2211 of the thin-film transistor 221 in the thin-film transistor array layer 220 is made of indium gallium zinc oxide (IGZO) material. Since the work function of IGZO material is about 3.4 eV, it is easily affected by light, which can cause the threshold voltage Vth of the thin-film transistor 221 to become negatively biased.

[0095] In some of the above embodiments, by designing that the spacing between the surface of the first covering portion 251 and the substrate 210 is unequal and the spacing between the surface of the second covering portion 252 and the substrate 210 is unequal, the reflective electrode reflects the light propagating to the edge region II back to the pixel region I. This can reduce or avoid the light propagating from the edge region II to the active layer 2211, alleviate or eliminate the negative bias phenomenon of the threshold voltage Vth of the thin film transistor 221 caused by the active layer 2211 being illuminated, thereby improving the stability of the thin film transistor 221.

[0096] In some embodiments, such as Figure 3B and Figure 4B As shown, the portion of the surface of the second cover 252 that contacts the surface of the first cover 251 is a slope with a first slope angle α;

[0097] The opening of the second via H2 at the end away from the substrate 210 is larger than the opening of the second via H2 at the end close to the substrate 210, and the second via H2 has a second slope angle β.

[0098] The second slope angle β is greater than the first slope angle α.

[0099] The distance between the surface of the first cover portion 251 and the substrate 210 is not equal to that between the surface of the second cover portion 252, so that the portion where the surface of the first cover portion 251 and the surface of the second cover portion 252 meet has an uneven slope with a first slope angle α.

[0100] The second via H2 penetrating the capping layer 250 can be etched after exposure and development. The opening of the second via H2 at the end away from the substrate 210 is larger than the opening of the second via H2 at the end close to the substrate 210. The sidewall of the second via H2 forms a second slope angle β with the plane direction of the capping layer 250.

[0101] The second slope angle β is greater than the first slope angle α.

[0102] In some embodiments, the second slope angle β is 50° to 70°, and the first slope angle α is 15° to 30°. Exemplarily, the second slope angle β can be 50°, 54°, 59°, 62°, 66.6°, or 70°. The first slope angle α can be 15°, 18°, 20.6°, 24°, 26.8°, 29.3°, or 30°.

[0103] In some embodiments, the surface of the second cover 252 is an arched surface. This makes the shape of the reflective electrode subsequently formed in the edge region II also an arched structure.

[0104] The reflective electrode is divided into two cases. The first case involves a single-layer structure, where the reflective portion within edge region II is a complete arched structure. Figure 4A and Figure 4B As shown; in the second case, the reflective electrode has a patterned structure. In this case, the reflective portion of the reflective electrode within edge region II is incomplete, and the reflective portion extends along an arched direction within edge region II, as shown. Figure 3A and Figure 3B As shown.

[0105] The arched reflective part has multiple reflection positions in multiple reflection directions, which can increase the angle of light reflection and improve the light output efficiency of the light-emitting device 230.

[0106] In some embodiments, the display substrate is applied to a top-emitting display panel, and the thickness of the first cover portion 251 is less than the thickness of the second cover portion 252; or,

[0107] The display substrate is used in a bottom-emitting display panel, and the thickness of the first cover portion 251 is greater than the thickness of the second cover portion 252.

[0108] like Figure 3A and Figure 4A As shown, the display panel 100 includes multiple inorganic and organic layers. The inorganic layers can be prepared using deposition processes, and their thickness is approximately 150 nm to 2000 nm. For example, the gate 2213 and source / drain metal layers 2215 in the thin-film transistor array layer 220, and the anode 231 in the light-emitting device 230 have a thickness of 200 nm to 1000 nm; the inorganic layer in the encapsulation layer 250 has a thickness of 150 nm to 500 nm. The organic layers can be prepared using processes such as coating and inkjet printing, and their thickness is approximately 1.5 μm to 5 μm. For example, the pixel defining layer 240 has a thickness of 1.8 μm to 2.0 μm; the color filter layer 260 and the cover layer 250 have a thickness of 2.0 μm to 3.5 μm.

[0109] It can be seen that the thickness of an organic layer in the display panel 100 is much greater than the thickness of an inorganic layer. Therefore, even if the surface of the cover layer 250 near the substrate 210 is not flat due to the different pattern of the underlying inorganic layer, the thickness of the inorganic layer in the display panel 100 has a small impact on the thickness of the cover layer 250 because the inorganic layer is relatively thin.

[0110] When the display substrate 200 is applied to the top-emitting display panel 100, the thickness of the first cover portion 251 located in the pixel region I is designed to be less than the thickness of the second cover portion 252 located in the edge region II. As explained above, the unevenness of the surface of the cover layer 250 near the substrate 210 has little effect on the thickness. This is equivalent to the height of the surface of the second cover portion 252 being higher than the height of the surface of the first cover portion 251, that is, the distance between the surface of the second cover portion 252 and the substrate 210 is greater than the distance between the surface of the first cover portion 251 and the substrate 210.

[0111] When the display substrate 200 is applied to the bottom-emitting display panel 100, the thickness of the first cover portion 251 located in the pixel region I is designed to be greater than the thickness of the second cover portion 252 located in the edge region II. As explained above, the unevenness of the surface of the cover layer 250 near the substrate 210 has little effect on the thickness. This is equivalent to the height of the surface of the second cover portion 252 being lower than the height of the surface of the first cover portion 251, that is, the distance between the surface of the second cover portion 252 and the substrate 210 is less than the distance between the surface of the first cover portion 251 and the substrate 210.

[0112] Please see Figure 3A and Figure 4A As shown, some embodiments of this disclosure provide a display panel 100, including: a display substrate 200 and a light-emitting device 230 as described above.

[0113] The light-emitting device 230 is disposed on the display substrate 200, and the light-emitting device 230 includes a reflective electrode 234 and a light-emitting layer 232;

[0114] The reflective electrode 234 includes a main body 2341 located in pixel region I and a reflective part 2342 located in edge region II. The reflective part 2341 protrudes towards the light-emitting layer 232 and reflects the light propagating to edge region II back to pixel region I.

[0115] like Figure 3A and Figure 4AAs shown, the light-emitting device 230 in the display panel 100 is formed on the cover layer 250. Since each functional layer in the light-emitting device 230 is a uniformly thick functional layer formed using a deposition process, the thickness of the functional layer is equal at all locations. For example, the anode 231, the light-emitting layer 232, and the cathode 233 are all uniformly thick functional layers. Therefore, the morphology of each functional layer in the light-emitting device 230 will be the same as the morphology of the surface of the cover layer 250 on the side away from the substrate 210 where the functional layer is located.

[0116] For example, if the distance between the surface of the first covering portion 251 and the substrate 210 is smaller than the distance between the surface of the second covering portion 252 and the substrate 210, then the distance between the portion of the functional layer located in pixel region I and the substrate 210 is smaller than the distance between the portion of the functional layer located in edge region II and the substrate 210. Furthermore, if the surface of the second covering portion 252 is an arched surface, then the portion of the functional layer located in edge region II has an arched structure with the same curvature as the arched surface. The arched reflective portion has multiple reflection positions in multiple reflection directions, which can increase the angle of light reflection and improve the light extraction efficiency of the light-emitting device 230.

[0117] like Figure 5 As shown, when the display device 1000 is a top-emitting type display device, the cathode 233 is the transmission electrode, and the anode 231 is the reflection electrode 234. Figure 6 As shown, when the display device 1000 is a bottom-emitting type display device, the anode 231 is a transmission electrode and the cathode 233 is a reflection electrode 234.

[0118] The aforementioned transmission electrode is located in the direction of light propagation, so it is made of transparent or semi-transparent semi-reflective materials, such as transparent ITO, so that light can pass through the transmission electrode to propagate.

[0119] The aforementioned reflective electrode is located at the light propagation boundary and is made of a metallic material, such as silver (Ag) or aluminum (Al). The reflective electrode 234 is used to reflect the light emitted by the light-emitting layer 232, thereby ensuring that the light in the top-emitting display panel 100 propagates away from the substrate 210, or ensuring that the light in the bottom-emitting display panel 100 propagates towards the substrate 210.

[0120] like Figure 3A and Figure 4A As shown, the main body 2341 of the reflective electrode 234 is located in the pixel area I and is used to generate an electric field in conjunction with the transmission electrode to drive the holes in the anode 231 and the electrons in the cathode 233 to recombine in the light-emitting layer 232, thereby causing the light-emitting layer 232 to emit light.

[0121] The reflective part 2342 of the reflective electrode 234 is located in the edge region II and is used to reflect the light propagating from the edge region II back to the pixel region I, thereby increasing the light output of the pixel region I and improving the light output efficiency of the light-emitting device 230.

[0122] In some embodiments, the display panel 100 further includes a pixel defining layer 240, which has a plurality of openings 240A, each opening 240A defining a pixel region I; the pixel defining layer 240 is located within an edge region II.

[0123] The pixel defining layer 240 has a grid-like structure, with multiple openings 240A formed by barriers. Each opening 240A is configured to define a pixel region I, and the pixel defining layer 240 is located within the edge region II between the multiple pixel regions I.

[0124] The portion of the reflective electrode 234 located within the opening 240A constitutes the main body 2341. Light emitted from the light-emitting layer 232 passes through the opening 240A to obtain the light-emitting area of ​​the light-emitting device 230. Multiple openings 240A in the pixel defining layer 240 that are configured with the same color for pixel areas I can have the same shape, while openings 240A in pixel areas I that are configured with different colors can have different shapes.

[0125] In some embodiments, such as Figure 3A and Figure 3B As shown, the display panel 100 is a top-emitting display panel, and the reflective electrode 234 is located on the side of the light-emitting layer 232 near the substrate 210. The edge of the reflective electrode 234 extends towards the substrate 210.

[0126] like Figure 3B As shown, when the display panel 100 is a top-emitting display panel, the cathode 233 is a transmission electrode and the anode 231 is a reflection electrode 234. The reflective portion 2342 located in the edge region II extends from the center of the edge region II toward the edge of the edge region II in a direction close to the substrate 210.

[0127] In some embodiments, such as Figure 4A and Figure 4B As shown, the display panel 100 is a bottom-emitting display panel, and the reflective electrode 234 is located on the side of the light-emitting layer 232 away from the substrate 210. The edge of the reflective electrode 234 extends in a direction away from the substrate 210.

[0128] like Figure 4B As shown, when the display device 1000 is a bottom-emitting type display device, the anode 231 is a transmission electrode and the cathode 233 is a reflection electrode 234. The reflective portion 2342 located in the edge region II extends from the center of the edge region II toward the edge of the edge region II in a direction away from the substrate 210.

[0129] Please see Figure 9 Some embodiments of this disclosure provide a method for manufacturing a display panel, including:

[0130] Step 91: Provide a substrate, the substrate comprising a plurality of pixel regions and edge regions between adjacent pixel regions;

[0131] Step 92: Form a thin-film transistor array layer on the substrate;

[0132] Step 93: Form a cover layer covering the thin film transistor array layer, the cover layer including a first cover portion located in the pixel region and a second cover portion located in the edge region; the distance between the surface of the first cover portion and the substrate and the distance between the surface of the second cover portion and the substrate are not equal; the surfaces of the first cover portion and the second cover portion both belong to the surface of the cover layer away from the substrate.

[0133] like Figure 3A and Figure 4A As shown, the substrate 210 can be a transparent glass or quartz glass with a thickness of 50μm to 1000μm. When the display panel 100 is a flexible display panel, the substrate 210 can also be a flexible substrate made of organic materials such as polyimide (PI), which is not limited here. The substrate 210 can be 50μm, 90μm, 230μm, 368.8μm, 500μm, 666μm, 773μm, 888.8μm, 920μm or 1000μm.

[0134] In some embodiments, a light-shielding layer 270 can be fabricated between the substrate 210 and the thin-film transistor array layer 220 by sputtering a metal material to block external light, thereby reducing or preventing light from shining on the active layer 2211, mitigating or eliminating the negative bias phenomenon of the threshold voltage Vth of the thin-film transistor 221 caused by light exposure of the active layer 2211, and thus improving the stability of the thin-film transistor 221.

[0135] In some embodiments, a buffer material can be deposited using a plasma-enhanced chemical vapor deposition (PECVD) process to form a buffer layer covering the light-shielding layer 270. The buffer material can be at least one of silicon nitride, silicon oxide, or silicon oxynitride, and the buffer layer can be a single-layer structure or a multi-layer structure. In the case of a multi-layer buffer layer, the buffer materials of different layers can be the same or different.

[0136] The thickness of the buffer layer can be 150nm to 500nm, for example: 150nm, 155nm, 190nm, 260.7nm, 300nm, 468.8nm or 500nm.

[0137] The aforementioned thin-film transistor array layer 220 includes an active layer 2211, a gate insulating layer 2212, a gate 2213, an interlayer insulating layer 2214, a source / drain metal layer 2215 that passes through the interlayer insulating layer 2214 and is connected to the active layer 2211, and a passivation layer 2216 that covers the source / drain metal layer 2215, which are sequentially formed on the substrate 210.

[0138] The active layer 2211 is fabricated by depositing an active material layer on the substrate 210 using a sputtering device, followed by exposure, development, and etching. The active material layer can be an oxide, such as indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), or indium tin zinc oxide (ITZO), or other amorphous oxides. When the display panel 100 includes a light-shielding layer 270, the orthogonal projection of the light-shielding layer 270 onto the substrate 210 covers the orthogonal projection of the active layer 2211 onto the substrate 210.

[0139] Gate insulating layer 2212 and gate 2213: Gate insulating material layers can be deposited using chemical vapor deposition (CVD). Then, a gate material layer covering the gate insulating layer 2212 can be deposited using a sputtering device. After exposing and developing the gate material layer to define the gate 2213, the photoresist is retained, and etching continues using the photoresist on the gate 2213 as a mask to obtain the gate insulating layer 2212.

[0140] The thickness of the gate 2213 can be 200nm to 1000nm, and the gate material can be metals such as aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), and titanium (Ti).

[0141] In some embodiments, after forming the gate insulating layer 2212 and the gate 2213, the exposed portion of the active layer 2211 may be conductively treated with a conductive gas to reduce the ohmic contact resistance between the subsequent source / drain metal layer 2215 and the active layer 2211. The conductive gas may be at least one of ammonia (NH3), nitrogen (N2), and hydrogen (H2).

[0142] Interlayer insulating layer 2214: This layer can be deposited using a PECVD process to cover the active layer 2211, the gate insulating layer 2212, and the gate 2213, and then exposed, developed, and etched. The interlayer insulating layer 2214 has a first via exposed to the active layer 2211 during etching. Additionally, if the display panel 100 includes a light-shielding layer 270, the interlayer insulating layer 2214 and the buffer layer can also jointly include a second via exposed to the light-shielding layer 270.

[0143] The interlayer insulation layer 2214 can be a single layer or a multilayer structure, and the interlayer insulation material can be silicon nitride or silicon oxide. When the interlayer insulation layer 2214 is a multilayer structure, the interlayer insulation materials of different layers can be the same or different.

[0144] Source / drain metal layer 2215: This layer can be deposited using a sputter process to cover the interlayer insulating layer 2214, and then exposed, developed, and etched. The source / drain metal layer 2215 can be connected to the active layer 2211 through a first via, and can also be connected to the light-shielding layer 270 through a second via.

[0145] The thickness of the source / drain metal layer 2215 can be 200nm to 1000nm, and the source / drain metal material can be aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), or other metals.

[0146] Passivation layer 2216: This passivation material layer can be deposited using a CVD process, covering the source / drain metal layer 2215 and the interlayer insulating layer 2214, and then exposed, developed, and etched. The passivation layer 2216 has a first via H1 exposed to the source / drain metal layer 2215 during etching. The passivation material can be silicon dioxide (SiO2).

[0147] In some embodiments, the display panel 100 is a bottom-emitting display panel. After forming the passivation layer 2216, the bottom-emitting display panel can form multiple color filters on the passivation layer 2216, that is, forming a filter of a corresponding color in a pixel area of ​​one color each time, repeating this process multiple times to obtain multiple color filters, such as... Figure 8A and Figure 8B As shown.

[0148] Taking the formation of a color filter as an example: a color filter material of one color is prepared using a slit coating method. After pre-baking, exposure, and development, the cured color filter pattern is exposed. After post-baking at 230°C to remove water and organic solvents, a color filter is obtained. This filter can be any one of a first filter 261, a second filter 262, and a third filter 263, and the thickness of the filter can be 2.0 μm to 3.5 μm.

[0149] After forming the thin-film transistor array layer 220, a capping layer 250 is fabricated on the thin-film transistor array layer 220. The capping layer 250 includes a first capping portion 251 located in pixel region I and a second capping portion 252 located in edge region II; the distance between the surface of the first capping portion 251 and the substrate 210 is not equal to the distance between the surface of the second capping portion 252 and the substrate 210; the surfaces of the first capping portion 251 and the second capping portion 252 are both surfaces of the capping layer 250 away from the substrate 210.

[0150] In addition, the capping layer 250 also includes a second through hole H2 that penetrates the capping layer 250. The second through hole H2 communicates with the first through hole H1 of the passivation layer 2216, thereby exposing the source / drain metal layer 2215 so that the anode 231, which is subsequently fabricated, can pass through the second through hole H2 and the first through hole H1 and connect with the source / drain metal layer 2215.

[0151] After forming the capping layer 250, an anode material layer can be deposited using a sputter process, and the anode material layer can be exposed, developed, and etched to obtain the anode 231. The thickness of the anode 231 can be 200 nm to 1000 nm. In some embodiments, where the display panel 100 is a bottom-emitting display panel and the anode 231 is a transmission electrode, the anode material can be indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0152] After forming the anode 231, a pixel defining material layer can be fabricated using a slit coating method. After pre-baking, exposure, and development, the cured pixel area pattern is exposed. A post-baking process at 230°C removes water and organic solvents, resulting in the pixel defining layer 240. The pixel defining layer 240 includes multiple openings 240A, each opening 240 defining one pixel area. The thickness of the pixel defining layer 240 can range from 1.8 μm to 2.0 μm.

[0153] After the pixel defining layer 240 is formed, a light-emitting layer 232 located in the opening 240A and a cathode 233 covering the light-emitting layer 232 and the pixel defining layer 240 can be formed sequentially using a vapor deposition process.

[0154] After the cathode 233 is formed, a CVD process can be used to deposit an encapsulation layer 300 to form a display panel 100. The encapsulation layer 300 can be a single-layer inorganic structure covering multiple light-emitting devices 230; or it can be a multi-layer structure. When the encapsulation layer 300 is a multi-layer structure, it can include two inorganic films and an organic film disposed between the two inorganic films.

[0155] The inorganic membrane is made of inorganic materials, such as nitrogen oxides. It is a thin film with uniform thickness, used to block external water and oxygen to prevent them from corroding the light-emitting layer 232. The organic membrane is made of organic materials and has fluidity. It is a thin film with a flat surface and uneven thickness.

[0156] In some embodiments, such as Figure 10 As shown, step 93: forming a capping layer covering the thin-film transistor array layer, including:

[0157] Step 931: Deposit a planar material layer covering the thin-film transistor array layer;

[0158] Step 932: Expose, develop, and etch the planarization material layer using a halftone mask process to retain the planar material in the edge area and remove part of the planar material in the pixel area to form a cover layer; or, Step 933: Expose, develop, and etch the planarization material layer using a halftone mask process to retain the planar material in the pixel area and remove part of the planar material in the edge area to form a cover layer.

[0159] A planarization material layer covering the passivation layer 2216 can be prepared using a slit method. The planarization material can be an organic material such as resin.

[0160] In some embodiments, before using the half-exposure mask process, the planarization material layer can be pre-baked, exposed, and developed to expose the cured pixel area pattern, and then post-baked at 230°C to remove water and organic solvents from the planarization material layer, resulting in a planarization transition layer. The subsequent half-exposure mask process is then used to fabricate the planarization transition layer, resulting in a cover layer 250.

[0161] For example, the display panel 100 is a top-emitting display panel. After forming the planarization material layer 250', a positive photoresist 891 is coated on the planarization material layer 250'. Then, the edge region II, the half-exposed pixel region I, and the exposed second via region III are masked using a half-exposure mask 88, as shown below. Figure 11A As shown. After exposure, development and etching are performed to retain the flat material of edge region II, remove part of the flat material of pixel region I, and remove all the flat material of the second via region III, forming a cover layer 250. Figure 11BAs shown, the height of the first covering portion 251 of the cover layer 250 in pixel region I is lower than the height of the second covering portion 252 in edge region II, and a second via H2 connecting the first via is also provided.

[0162] For example, the display panel 100 is a bottom-emitting display panel. After forming the planarization material layer 250', a negative photoresist 892 is coated on the planarization material layer 250'. Then, a half-exposure mask 88 is used to expose the half-exposure edge area II, the exposed pixel area I, and the masked second via area III, as shown in the example. Figure 12A As shown. After exposure, development and etching are performed to retain the planar material of pixel area I, remove part of the planar material of edge area II, and remove all the planar material of the second via area III, forming a capping layer 250. Figure 12B As shown, the height of the first covering portion 251 of the cover layer 250 in pixel region I is higher than the height of the second covering portion 252 in edge region II, and a second via H2 connecting the first via is also provided.

[0163] It should be noted that the two methods described above use positive and negative photoresists respectively, but these are merely illustrative examples. In the top-emitting display panel solution, negative photoresist can also be used by changing the exposure position of the half-exposure mask; similarly, in the bottom-emitting display panel solution, positive photoresist can also be used by changing the exposure position of the half-exposure mask. Regardless of the type of photoresist and half-exposure mask used, the resulting overlay layer 250 remains unchanged.

[0164] In summary, the display substrate and its manufacturing method and display device provided by some embodiments of this disclosure, by designing the spacing d1 between the surface of the first covering portion 251 and the substrate 210 and the spacing d2 between the surface of the second covering portion 252 and the substrate 210 to be unequal, can cause the reflective electrode in the light-emitting device 230 subsequently formed on the covering layer 250 to undergo corresponding morphological changes, so that the portion of the reflective electrode located in the edge region II can reflect the light propagating to the edge region II back to the pixel region I, thereby improving the light extraction efficiency of the light-emitting device 230 and thus improving the luminous efficiency of the display device 1000.

[0165] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate comprising a plurality of pixel regions and an edge region between adjacent pixel regions; a thin film transistor array layer disposed on the substrate; a cover layer covering the thin film transistor array layer, the cover layer comprising a first cover portion located in the pixel region and a second cover portion located in the edge region; a distance between a surface of the first cover portion and the substrate is different from a distance between a surface of the second cover portion and the substrate; the surfaces of the first cover portion and the second cover portion are surfaces of the cover layer away from the substrate; wherein the display substrate is applied to a bottom emission display panel; the distance between the surface of the first cover portion and the substrate is greater than an average distance between the surface of the second cover portion and the substrate.

2. The display substrate of claim 1, wherein, The display substrate further comprises a color filter layer between the thin film transistor array layer and the cover layer, the color filter layer comprising a first filter portion, a second filter portion, a third filter portion and a white filter portion; a material of the cover layer is reused as the white filter portion.

3. The display substrate of claim 1, wherein, The thin film transistor array layer comprises a source-drain metal layer and a passivation layer covering the source-drain metal layer; the passivation layer is provided with a first via hole penetrating through the passivation layer, and the first via hole exposes the source-drain metal layer; The cover layer is provided with a second via hole penetrating through the cover layer, and the first via hole and the second via hole are in communication.

4. The display substrate of claim 3, wherein, A portion where the surface of the second cover portion meets the surface of the first cover portion is a slope surface with a first slope angle; an opening of the second via hole away from the substrate is greater than an opening of the second via hole close to the substrate, and the second via hole has a second slope angle; the second slope angle is greater than the first slope angle.

5. The display substrate of claim 4, wherein, The second slope angle is 50°-70°, and the first slope angle is 15°-30°. 6.The display substrate according to any one of claims 1-5, wherein, The surface of the second cover portion is an arched surface.

7. The display substrate of claim 1, wherein, The thickness of the first cover portion is greater than the thickness of the second cover portion. 8.The display substrate according to any one of claims 1-5, characterized in that, The second cover portion surrounds the first cover portion; alternatively, the first cover portion is in a rectangular shape; the second cover portion is disposed between long sides of two adjacent first cover portions; and / or, the second cover portion is disposed between short sides of two adjacent first cover portions.

9. A display panel, characterized by, The display substrate comprises: The display substrate according to any one of claims 1-8; a light-emitting device disposed on the display substrate, the light-emitting device comprising a reflective electrode and a light-emitting layer; wherein the reflective electrode comprises a main body portion located in a pixel region and a reflective portion located in an edge region; the reflective portion is protruded in a direction close to the light-emitting layer, and reflects light propagating to the edge region to the pixel region.

10. The display panel of claim 9, wherein, The display panel further comprises a pixel definition layer, the pixel definition layer is provided with a plurality of openings, each opening is used to determine a pixel region; the pixel definition layer is located in the edge region.

11. The display panel of claim 9, wherein, The reflective electrode is located on a side of the light-emitting layer away from the substrate, and an edge of the reflective portion extends away from the substrate.

12. A manufacturing method of a display panel, comprising: The display substrate comprises: a substrate comprising a plurality of pixel regions and an edge region between adjacent pixel regions; forming a thin film transistor array layer on the substrate; Forming a cover layer covering the thin film transistor array layer, the cover layer including a first cover portion located at the pixel region and a second cover portion located at the edge region; a distance between a surface of the first cover portion and the substrate is different from a distance between a surface of the second cover portion and the substrate; the surface of the first cover portion and the surface of the second cover portion are both surfaces of the cover layer away from the substrate; The display substrate is applied to a bottom emission display panel. The distance between the surface of the first cover portion and the substrate is greater than an average distance between the surface of the second cover portion and the substrate.

13. The method of claim 12, wherein, Forming a cover layer covering the thin film transistor array layer, including: Depositing a flat material layer covering the thin film transistor array layer; using a half-tone mask process to expose, develop and etch the flat material layer, so as to retain the flat material layer of the pixel region, remove part of the flat material layer of the edge region, and form a cover layer.

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