A method and a circuit for verifying a circuit including a clock device
By employing a multi-level separate verification method for clock devices, the problem of difficulty in building and inheriting verification platforms in situations with numerous clock sources is solved, resulting in a simple and efficient verification platform with a low error rate.
CN114048702BActive Publication Date: 2025-08-01AXERA TECH (BEIJING) CO LTD
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Patent Information
- Application Number
- CN202111323719.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-09
- Publication Date
- 2025-08-01
- Estimated Expiration
- 2041-11-09
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Figure CN114048702B_ABST
Abstract
The present application provides a verification method and circuit for a circuit including a clock device. The circuit structure of the circuit including the clock device is clear at different levels and is applicable to the situation where there are many clock sources. For the verification method of this circuit, a multi-level separate verification method is adopted, that is: a separate verification test is carried out at the phase-locked loop module level, a separate verification test is carried out at the clock generation module level, a separate verification test is carried out at the multi-way selection module level, and a separate verification test is carried out at the level of the multi-way selection module and the gate module as a whole. The verification method of this embodiment can achieve separate verification tests at each level by respectively reserving verification test interfaces in the modules, separating the monitor and test cases, making the verification platform simple and easy to produce, and the produced verification platform can be inherited between projects.
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Citation Information
Patent Citations
Circuit design method, program and semiconductor integrated circuit
JP2012128819A