Semiconductor packaging device and manufacturing method thereof

Abstract

This disclosure relates to a semiconductor packaging apparatus and a method for manufacturing the same. The semiconductor packaging apparatus includes: a first electronic component; and a second electronic component disposed on the first electronic component, the width of the second electronic component being smaller than the width of the first electronic component. A conductive pad is disposed on an area of ​​the first electronic component not covered by the second electronic component, and a first circuit layer is disposed on the conductive pad. An bonding region exists between the conductive pad and the first circuit layer. This semiconductor packaging apparatus can utilize the first circuit layer to export electrical signals within the first electronic component, eliminating the need to directly fabricate conductive pillars on the first electronic component, thus improving product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] In hybrid bonding of chips (dies) and wafers, high-conductivity pillars are typically used to conduct electrical signals from the structure to the outside. The fabrication methods for these pillars can be divided into two types: pillar first and pillar last.

[0003] Pillar-first fabrication refers to fabricating the conductive pillars before hybrid bonding of the chip and wafer. The specific fabrication process includes: first, chemical mechanical polishing (CMP) of the wafer surface; second, coating with photoresist; third, exposure to form openings; and finally, electroplating to form the conductive pillars. In this method, steps such as applying the photoresist and removing the seed layer for electroplating increase the roughness of the bonding area, which can, in severe cases, prevent hybrid bonding.

[0004] Pillar last fabrication refers to fabricating the conductive pillars after the chip and wafer have been co-bonded. This method avoids increasing the roughness of the bonding area; however, it requires coating the wafer surface with photoresist. The presence of the chip prevents the wafer surface from achieving the required flatness for photoresist coating, resulting in uneven photoresist coverage and hindering the fabrication of the conductive pillars.

[0005] Therefore, it is necessary to propose a new technical solution to solve at least one of the above-mentioned technical problems. Summary of the Invention

[0006] This disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0007] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0008] First electronic component;

[0009] A second electronic component is disposed on the first electronic component. The width of the second electronic component is smaller than the width of the first electronic component. A conductive pad is disposed on an area of ​​the first electronic component not covered by the second electronic component. A first circuit layer is disposed on the conductive pad. There is a bonding area between the conductive pad and the first circuit layer.

[0010] In some alternative embodiments, a connection structure is provided between the conductive pad and the first circuit layer, and the connection structure forms the bonding area with the conductive pad.

[0011] In some alternative embodiments, an intermetallic compound layer exists between the connection structure and the conductive pad.

[0012] In some alternative embodiments, a connection structure is provided between the conductive pad and the first circuit layer, and the connection structure forms the bonding area with the first circuit layer.

[0013] In some alternative implementations, an intermetallic compound layer exists between the connection structure and the first circuit layer.

[0014] In some alternative implementations, the upper surface of the first circuit layer is flush with the upper surface of the second electronic component.

[0015] In some alternative implementations, a second line layer is provided on the first line layer.

[0016] In some alternative implementations, the first circuit layer includes conductive pillars.

[0017] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, including:

[0018] The first electronic component and the second electronic component are directly bonded together, wherein the width of the second electronic component is smaller than the width of the first electronic component;

[0019] A pre-fabricated first circuit layer is provided on the first electronic component in an area not covered by the second electronic component, wherein the thickness of the first circuit layer is greater than or equal to the thickness of the second electronic component;

[0020] A second circuit layer is formed on the first circuit layer to obtain a semiconductor packaging device.

[0021] In some optional embodiments, the step of setting a pre-fabricated first circuit layer on the area of ​​the first electronic component not covered by the second electronic component includes:

[0022] A dummy chip is provided, wherein the dummy chip is provided with conductive pillars;

[0023] The dummy chip is flip-chip soldered onto an area of ​​the first electronic component that is not covered by the second electronic component.

[0024] In some alternative implementations, after flip-chip bonding the dummy chip to an area of ​​the first electronic component not covered by the second electronic component, the method further includes:

[0025] Remove part of the structure of the dummy chip to expose the first circuit.

[0026] In some alternative implementations, removing a portion of the dummy chip's structure to expose the first circuitry includes:

[0027] The dummy chip is ground to expose the first circuit.

[0028] In some optional embodiments, after a pre-fabricated first circuit layer is formed on the first electronic component in an area not covered by the second electronic component, the method further includes:

[0029] A capillary bottom filler and a molding material are disposed above the first electronic component; or

[0030] A molded bottom filler is provided above the first electronic component.

[0031] In some alternative implementations, forming a second circuit layer on the first circuit layer includes:

[0032] A redistribution layer is formed on the first line layer.

[0033] In the semiconductor packaging apparatus and manufacturing method disclosed herein, by setting a first circuit layer on a region of the first electronic component that is not covered by the second electronic component, the electrical signals in the first electronic component can be exported using the first circuit layer. This eliminates the need to directly fabricate conductive pillars on the first electronic component, overcoming the difficulty in fabricating conductive pillars used for external connections in hybrid bonding, and is beneficial to improving product yield. Attached Figure Description

[0034] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0035] Figures 1-3 These are first to third schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present disclosure;

[0036] Figure 4 This is a schematic diagram of a method for manufacturing a semiconductor packaging apparatus according to an embodiment of the present disclosure.

[0037] Symbol explanation:

[0038] 100, First electronic component; 110, First conductive pad; 130, Third conductive pad; 200, Second electronic component; 210, Second conductive pad; 310, First circuit layer; 311, Conductive pillar; 320, Second circuit layer; 410, Capillary bottom filler; 420, Molding material; 500, Conductive ball; 600, Substrate; 700, Electrical connection wire; 800, Dummy chip; 900, Connection structure. Detailed Implementation

[0039] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0040] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0041] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0042] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0043] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0044] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] This disclosure provides a semiconductor packaging apparatus. Figures 1-3 These are first to third schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present disclosure.

[0046] Figure 1 A longitudinal cross-section of a semiconductor packaging apparatus according to an embodiment of the present disclosure is shown. Figure 1 As shown, the semiconductor packaging device includes a first electronic component 100 and a second electronic component 200. The second electronic component 200 is disposed on the first electronic component 100. The width of the second electronic component 200 is smaller than the width of the first electronic component 100.

[0047] like Figure 1 As shown, a first conductive pad 110 is disposed on the surface of the first electronic component 100, and a second conductive pad 210 is disposed on the surface of the second electronic component 200. The first conductive pad 110 and the corresponding second conductive pad 210 are directly bonded to achieve an electrical connection between the first electronic component 100 and the second electronic component 200. Furthermore, the dielectric material on the surface of the first electronic component 100 and the dielectric material on the surface of the corresponding second electronic component 200 are directly bonded. Figure 1 (Not shown in the image).

[0048] like Figure 1 As shown, a third conductive pad 130 is disposed on an area of ​​the first electronic component 100 not covered by the second electronic component 200. A first circuit layer 310 is disposed on the third conductive pad 130. The first circuit layer 310 includes a molding material 420 and a plurality of conductive pillars 311 disposed in the molding material 420. The third conductive pad 130 and the conductive pillars 311 in the first circuit layer 310 are connected by a connecting structure 900, thereby forming a bonding area. The connecting structure 900 can be solder, that is, the third conductive pad 130 and the conductive pillars 311 can be connected by welding. Furthermore, an intermetallic compound layer formed by welding can exist between the third conductive pad 130 and the connecting structure 900. Figure 1(Not shown in the image).

[0049] like Figure 1 As shown, the upper surface of the first circuit layer 310 is flush with the upper surface of the second electronic component 200. A second circuit layer 320 is also disposed on the first circuit layer 310 and the first electronic component 100. The second circuit layer 320 is, for example, a redistribution layer (RDL). Conductive balls 500 are further disposed on the surface of the second circuit layer 320. Figure 1 In the semiconductor packaging device shown, electrical signals in the first electronic component 100 and the second electronic component 200 are conducted through the first circuit layer 310 to the second circuit layer 320, and then through the conductive balls 500 on the surface of the second circuit layer 320 to the external components.

[0050] like Figure 1 As shown, a capillary bottom filler 410 is also provided between the first electronic component 100 and the second electronic component 200, and between the first electronic component 100 and the first circuit layer 310, to fill the gaps in the above-mentioned areas and improve the structural strength.

[0051] Figure 1 The semiconductor packaging devices in the substrate can be further electrically connected to the substrate to achieve more complete and diverse functions. For example, 2 and... Figure 3 Different methods of connecting the semiconductor packaging device to the substrate according to embodiments of the present disclosure are shown.

[0052] exist Figure 2 In the above-described semiconductor packaging device, the conductive ball 500 can be electrically connected to the substrate 600, which can be fabricated using a flip-chip process. The substrate 600 can be made of polymer materials, ceramics, or glass, etc., and this disclosure does not limit it.

[0053] exist Figure 3 In the above-described semiconductor packaging device, an electrical connection can be made to a substrate 600 via an electrical connection wire 700, which can be fabricated using a wire bonding process. The substrate 600 can be made of polymer materials, ceramics, or glass, etc., and this disclosure does not limit it.

[0054] In the semiconductor packaging apparatus provided in this disclosure, by setting a first circuit layer 310 on a region of the first electronic component 100 that is not covered by the second electronic component 200, the electrical signals in the first electronic component 100 can be exported using the first circuit layer 310. There is no need to directly fabricate conductive pillars 311 on the first electronic component 100, which overcomes the problem of difficult fabrication of conductive pillars 311 used for external connection in hybrid bonding and is conducive to improving product yield.

[0055] This disclosure also provides a method for manufacturing a semiconductor packaging device. Figure 4 This is a schematic diagram of a method for manufacturing a semiconductor packaging apparatus according to an embodiment of the present disclosure.

[0056] like Figure 4 As shown, the method includes the following steps:

[0057] First, such as Figure 4 As shown in the first step, the first electronic component 100 and the second electronic component 200 are directly bonded together, wherein the width of the second electronic component 200 is smaller than the width of the first electronic component 100.

[0058] Secondly, such as Figure 4 As shown in the second and third steps, a pre-fabricated first circuit layer 310 is provided on the area of ​​the first electronic component 100 not covered by the second electronic component 200, wherein the thickness of the first circuit layer 310 is greater than or equal to the thickness of the second electronic component 200.

[0059] Finally, as Figure 4 As shown in the fourth step, a second circuit layer 320 is formed on the first circuit layer 310 to obtain a semiconductor packaging device.

[0060] In some embodiments, the step of setting the first line layer 310 described above may further include: firstly, as... Figure 4 As shown in the second step, the dummy chip 800 is flip-chip soldered to an area of ​​the first electronic component 100 not covered by the second electronic component 200, wherein the dummy chip 800 is provided with conductive posts 311. Next, as... Figure 4 As shown in the third step, the dummy chip 800 together with the second electronic component 200 is ground to remove part of the structure of the dummy chip 800 to expose the first circuit.

[0061] In some embodiments, after the first circuit layer 310 is set, a capillary bottom filler 410 and a molding material 420 may be set above the first electronic component 100, or a molding bottom filler may be set above the first electronic component 100.

[0062] In some implementations, a second wiring layer 320 can be formed using a rewiring process, in which case the second wiring layer 320 is a rewiring layer.

[0063] The manufacturing method of the semiconductor packaging device provided in this disclosure can achieve similar technical effects to the semiconductor packaging device described above, and will not be repeated here.

[0064] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A method for manufacturing a semiconductor packaging device, comprising: The first electronic component and the second electronic component are directly bonded together, wherein the width of the second electronic component is smaller than the width of the first electronic component; A dummy chip is provided, wherein the dummy chip is provided with conductive pillars; the dummy chip is flip-chip soldered to an area of ​​the first electronic component that is not covered by the second electronic component; A pre-fabricated first circuit layer is provided on the first electronic component in an area not covered by the second electronic component, wherein the dummy chip together with the second electronic component is ground to remove the dummy chip to expose the first circuit, and the thickness of the first circuit layer is greater than or equal to the thickness of the second electronic component. A second circuit layer is formed on the first circuit layer to obtain a semiconductor packaging device.

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