Non-volatile memory devices and storage devices including non-volatile memory devices

Abstract

Non-volatile memory devices and storage devices including non-volatile memory devices are provided. The non-volatile memory device includes a first memory chip and a second memory chip connected to a controller through a same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal based on a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first signal and the second signal.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0099248, filed on August 7, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention provides a memory device, and more specifically, relates to a non-volatile memory device comprising a plurality of memory chips and a storage device comprising a non-volatile memory device. Background Technology

[0004] Storage devices may include non-volatile memory and a controller that controls the non-volatile memory. In related technologies, communication between the non-volatile memory and the controller is performed at a low operating frequency compared to memory systems that include high-speed memory (such as dynamic random access memory (DRAM) or static random access memory (SRAM)). However, there is a recent demand for communication between the non-volatile memory and the controller to be performed at a high operating frequency. Summary of the Invention

[0005] According to an aspect of the present invention, a non-volatile memory device is provided, the non-volatile memory device comprising: a first memory chip configured to generate a first signal from a first internal clock signal based on a clock signal received from a controller; and a second memory chip configured to generate a second signal from the second internal clock signal based on the clock signal, and to perform a phase calibration operation on the second signal relative to the phase of the first signal by delaying the second internal clock signal based on a phase difference between the first signal and the second signal, wherein the first memory chip and the second memory chip are connected to the controller via the same channel.

[0006] According to another aspect of the present invention, a storage device is provided, comprising: a first memory chip configured to generate a first signal from a first internal clock signal based on a received first clock signal; a second memory chip configured to generate a second signal from a second internal clock signal based on a second clock signal; and a controller connected to the first memory chip via a first channel, connected to the second memory chip via a second channel, and delaying the second clock signal based on a phase difference between the first signal and the second signal to perform a phase calibration operation on the second signal based on the phase of the first signal.

[0007] According to another aspect of the present invention, a non-volatile memory device is provided, comprising: a first memory chip configured to generate a first signal from a first internal clock signal based on a clock signal received from a controller; and a second memory chip configured to generate a second signal from a second internal clock signal based on the clock signal, and to perform a phase calibration operation on the second signal based on the phase of the first signal by delaying the second internal clock signal based on a phase difference between the first signal and the second signal, wherein the second memory chip comprises: a memory cell region including a first metal pad; and a peripheral circuit region including a second metal pad and perpendicularly connected to the memory cell region through the first metal pad and the second metal pad, and wherein the peripheral circuit region comprises: a delay circuit configured to delay the clock signal to generate the second internal clock signal; and a phase detector configured to detect the phase difference between the first signal and the second signal and generate a third signal having a duty cycle based on the detected phase difference or a logic high level or a logic low level based on the detected phase difference.

[0008] According to another aspect of the present invention, a non-volatile memory device is provided, comprising: a buffer chip configured to generate a first clock signal and a second clock signal based on a clock signal received from a controller; a first memory chip configured to generate a first signal from a first internal clock signal based on the first clock signal; and a second memory chip configured to generate a second signal from a second internal clock signal based on a second clock signal, wherein the buffer chip is configured to perform a phase calibration operation on the second signal based on the phase of the first signal by delaying the second clock signal based on a phase difference between the first signal and the second signal. Attached Figure Description

[0009] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram schematically illustrating an example embodiment of a storage device according to a concept of the present invention;

[0011] Figure 2 It shows Figure 1 Memory devices;

[0012] Figure 3 Showing more details Figure 1 Storage devices;

[0013] Figure 4 It is shown by Figure 3 Timing diagram of duty cycle correction and phase calibration operations performed by the storage device;

[0014] Figure 5This is a block diagram illustrating the duty cycle correction operation of a first memory chip according to an exemplary embodiment of the present invention;

[0015] Figure 6 This is a block diagram schematically illustrating an example embodiment of a duty cycle correction circuit (DCC) according to the present invention.

[0016] Figure 7 It is shown Figure 6 Circuit diagram of a duty cycle adjustment (DCA) circuit;

[0017] Figure 8 This is a block diagram illustrating the duty cycle correction operation and phase calibration operation of a second memory chip according to an exemplary embodiment of the present invention;

[0018] Figure 9 This illustrates an example embodiment of the concept according to the present invention. Figure 8 Timing diagram of the phase detector operation;

[0019] Figure 10 This section provides a detailed illustration of exemplary embodiments based on the concept of the present invention. Figure 3 A block diagram of a storage device;

[0020] Figure 11 This is a block diagram illustrating in detail an exemplary embodiment of a storage device according to a concept of the present invention;

[0021] Figure 12 This is a block diagram illustrating in detail an exemplary embodiment of a storage device according to a concept of the present invention;

[0022] Figure 13 This is a flowchart illustrating the operation of a controller, a first memory chip, and a second memory chip according to an exemplary embodiment of the present invention.

[0023] Figure 14A and 14B This is a timing diagram illustrating duty cycle correction sequences of some exemplary embodiments of the present invention;

[0024] Figure 15 This is a flowchart illustrating the operation of a controller, a first memory chip, and a second memory chip according to an exemplary embodiment of the present invention.

[0025] Figure 16 This is a block diagram schematically illustrating an example embodiment of a storage device according to a concept of the present invention;

[0026] Figure 17 Showing more details Figure 16Storage devices;

[0027] Figure 18 This is a block diagram schematically illustrating an example embodiment of a storage device according to a concept of the present invention;

[0028] Figure 19 Example embodiments based on the present invention are shown in more detail. Figure 18 Storage devices;

[0029] Figure 20 A storage device according to an exemplary embodiment of the present invention is shown in more detail;

[0030] Figure 21 A storage device according to an exemplary embodiment of the present invention is illustrated schematically;

[0031] Figure 22 A storage device according to an example embodiment of the present invention is shown; and

[0032] Figure 23 This is a block diagram illustrating an example of an SSD system using a memory device according to an exemplary embodiment of the present invention. Detailed Implementation

[0033] Figure 1 This is a block diagram schematically illustrating an example embodiment of a storage device SD1 according to a concept of the present invention.

[0034] refer to Figure 1 The storage device SD1 may include a memory device 10 and a controller 50. The memory device 10 may be a non-volatile memory device including a first memory chip 100 and a second memory chip 100a. The first memory chip 100 and the second memory chip 100a can be connected to the controller 50 through the same channel CH, and therefore, data can be sent to and received from the controller 50 through the same channel CH.

[0035] Memory device 10 may include a plurality of memory chips, including at least a first memory chip 100 and a second memory chip 100a, and therefore may be referred to as a "multi-chip memory". For example, each of the first memory chip 100 and the second memory chip 100a may be a dual die package (DDP) or a quadrupledie package (QDP). However, the inventive concept is not limited thereto. In some example embodiments, memory device 10 may be implemented as a multi-die package including a plurality of memory dies, said plurality of memory dies including at least a first memory die and a second memory die. The description of the first memory chip 100 and the second memory chip 100a provided below can be applied equally to the first memory die and the second memory die.

[0036] When the memory device 10 is implemented as a multi-chip memory, the first memory chip 100 and the second memory chip 100a can operate simultaneously. For example, the controller 50 can simultaneously control read operations on the first memory chip 100 and the second memory chip 100a. As the data input / output speed between the controller 50 and the memory device 10 increases, the requirement for phase alignment between the first memory chip 100 and the second memory chip 100a may increase.

[0037] According to an example embodiment, the second memory chip 100a can align the phases of a first signal and a second signal generated by the first memory chip 100 and the second memory chip 100a respectively connected to the same channel CH by performing a phase calibration operation relative to or based on the first memory chip 100, thereby improving the performance and reliability of the memory device 10. Furthermore, the memory device 10 can reduce the time required for phase calibration operations by performing duty cycle correction operations and phase calibration operations together during a training period (e.g., a duty cycle correction circuit (DCC) training period).

[0038] In some example embodiments, the first memory chip 100 and the second memory chip 100a may be non-volatile memory chips. For example, the first memory chip 100 and the second memory chip 100a may be NAND flash memory chips. For example, at least one of the first memory chip 100 and the second memory chip 100a may be a vertical NAND (VNAND) flash memory chip. A vertical NAND flash memory chip may include word lines stacked on a substrate in a vertical direction and cell strings each including a plurality of memory cells respectively connected to the word lines. However, the inventive concept is not limited thereto, and at least one of the first memory chip 100 and the second memory chip 100a may be a resistive memory chip, such as resistive random access memory (ReRAM), phase change random access memory (PRAM), and magnetic random access memory (MRAM).

[0039] In some example embodiments, the storage device SD1 may be internal memory embedded in an electronic device. For example, the storage device SD1 may be an SSD, an embedded universal flash storage (UFS) memory device, or an embedded multi-media card (eMMC). In some example embodiments, the storage device SD1 may be external memory removable from the electronic device. For example, the storage device SD1 may be a UFS memory card, a compact flash (CF) memory card, a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, or a memory stick.

[0040] Figure 2 It shows Figure 1 10. Memory device.

[0041] refer to Figure 2The memory device 10 may include a substrate SUB and a plurality of memory chips 100 to 100n. The plurality of memory chips 100 to 100n may be vertically stacked on the substrate SUB. Input / output pins Pn may be disposed on the substrate SUB, and input / output nodes ND of the plurality of memory chips 100 to 100n may be connected to the input / output pins Pn. For example, the input / output pins Pn and the input / output nodes ND may be connected to each other via wire bonding. In this respect, for wire bonding, the plurality of memory chips 100 to 100n may be stacked with an skew in the horizontal direction.

[0042] Figure 3 Show in more detail Figure 1 The storage device SD1.

[0043] refer to Figure 3 The memory device 10 may include a first memory chip 100 and a second memory chip 100a, as well as first pins P1 to third pins P3. The first memory chip 100 and the second memory chip 100a may be commonly connected to each of the first pins P1 to third pins P3. The controller 50 may include first pins P1' to third pins P3'. The first pins P1' to third pins P3' may be respectively connected to the first pins P1 to third pins P3.

[0044] The memory device 10 can receive the clock signal CLK from the controller 50 via the first pin P1, and send and receive the data strobe signal DQS from the controller 50 via the second pin P2. Furthermore, the memory device 10 can receive commands and addresses from the controller 50 via the third pin P3, and send and receive data DQ from the controller 50 via the third pin P3. For example, the third pin P3 may include eight input / output pins, but the inventive concept is not limited thereto. In this respect, the signal lines through which the clock signal CLK, the data strobe signal DQS, and the data DQ are sent / received can be configured... Figure 1 The channel CH.

[0045] During a read operation on memory device 10, memory device 10 can receive a clock signal CLK, such as a read enable signal nRE, and output a data strobe signal DQS and data DQ. In double data rate (DDR) mode, data DQ can be output sequentially in sync with the rising and falling edges of the data strobe signal DQS. Therefore, the data windows of the first and second data output sequentially can correspond to the logic high and logic low periods of the data strobe signal DQS, respectively. Since the data strobe signal DQS is generated based on the clock signal CLK, the data windows of the first and second data can be determined based on the ratio of the logic high and logic low periods of the clock signal CLK.

[0046] When a "duty mismatch" occurs in the clock signal CLK, the logic high period of the clock signal CLK may differ from the logic low period; that is, the ratio between the logic high and logic low periods may not be 1:1. In this case, the first data and the second data may have different data windows, and the effective data windows for the first and second data may be reduced. Consequently, the performance of the memory device 10 may deteriorate. Therefore, a method is needed to perform duty cycle correction based on the clock signal CLK to eliminate the duty cycle mismatch and ensure the effective data window.

[0047] The first memory chip 100 can generate the first signal SIG1 from a first internal clock signal CLKi based on the clock signal CLK. For example, the first memory chip 100 may include a delay circuit 110 and a duty cycle correction circuit (DCC) 120. The delay circuit 110 can generate the first internal clock signal CLKi from the clock signal CLK received through the first pin P1. The DCC 120 can generate the first signal SIG1 by performing a first duty cycle correction operation on the first internal clock signal CLKi.

[0048] The second memory chip 100a can generate the second signal SIG2 from the second internal clock signal CLKi' based on the clock signal CLK. For example, the second memory chip 100a may include a delay circuit 110a and a DCC 120a. The delay circuit 110a can generate the second internal clock signal CLKi' from the clock signal CLK received through the first pin P1. The DCC 120a can generate the second signal SIG2 by performing a second duty cycle correction operation on the second internal clock signal CLKi'.

[0049] In some example embodiments, the second memory chip 100a may further include a delay-locked loop (DLL) circuit, and the second memory chip 100a may use the DLL of the DLL circuit to perform a phase calibration operation. For example, the DLL circuit of the second memory chip 100a may receive a first signal SIG1 and a second signal SIG2, and may control the delay circuit 110a based on the phase difference between the first signal SIG1 and the second signal SIG2. Therefore, the second memory chip 100a may delay the second internal clock signal CLKi', and the phases of the first signal SIG1 and the second signal SIG2 may be aligned. At this time, the second memory chip 100a may perform a phase calibration operation together with the DLL training operation during a training period (e.g., a DLL training period).

[0050] Figure 4 It is shown by Figure 3 Timing diagram of duty cycle correction and phase calibration operations performed by the storage device SD1.

[0051] Also refer to Figure 3 and Figure 4 Because memory device 10 is an asynchronous system and does not always have a toggling signal, DCCs 120 and 120a can perform duty cycle correction only during the period when the clock signal CLK is applied. In some example embodiments, memory device 10 can perform duty cycle correction by using the read enable signal nRE as the clock signal CLK. When duty cycle correction is performed during the read period of output read data within the read period of a read operation on memory device 10, the clock duty cycle can be changed by the duty cycle correction operation for each clock cycle, resulting in a reduction in the effective data window for the read data.

[0052] Therefore, in some example embodiments, DCC 120 and 120a can perform duty cycle correction operations in a dedicated period other than the readout period. Hereinafter, the dedicated period for duty cycle correction operations will be referred to as the "DCC training period DCC_PD," and the operations of DCC 120 and 120a performed during the DCC training period DCC_PD will be referred to as "DCC training." In one embodiment, the "DCC training period DCC_PD" may include a previously determined number of clock cycles. During the DCC training period DCC_PD, the clock signal CLK, such as the read enable signal nRE, can be switched at a predetermined frequency regardless of the output buffer (e.g., ...). Figure 19 How to operate 143 and 243 in the code?

[0053] In some example embodiments, during the DCC training period DCC_PD, the first memory chip 100 can provide a first signal SIG1 to the Nth input / output pad DQ_N as a result of performing a first duty cycle correction operation. The Nth input / output pad DQ_N can be connected to one of the third input / output pins P3. Furthermore, during the DCC training period DCC_PD, the second memory chip 100a can provide a second signal SIG2 to either the (N+1)th input / output pad DQ_N+1 or the (N-1)th input / output pad DQ_N-1 as a result of performing a second duty cycle correction operation. The (N+1)th input / output pad DQ_N+1 or the (N-1)th input / output pad DQ_N1 can be connected to the other of the third input / output pins P3. At this time, a phase difference PD may occur between the first signal SIG1 and the second signal SIG2. To improve the reliability of the memory device 10 when the first memory chip 100 and the second memory chip 100a operate simultaneously, it is necessary to eliminate the phase difference PD.

[0054] Therefore, the second memory chip 100a may further include a phase detector 130a. The phase detector 130a can detect the phase difference PD between a first signal SIG1 provided from the first memory chip 100 to the Nth input-output pad DQ_N and a second signal SIG2 provided from the second memory chip 100a to the (N+1)th input-output pad DQ_N+1, thereby generating a third signal SIG3 and providing the generated third signal SIG3 to the DCC 120a. The DCC 120a can generate a control signal by performing a duty cycle correction operation on the third signal SIG3 and provide the generated control signal to the delay circuit 110a. Therefore, the delay circuit 110a can generate a second internal clock signal CLKi' by delaying the clock signal CLK according to the control signal.

[0055] In this specification, the first memory chip 100 may be referred to as a "reference chip," and the second memory chip 100a may be referred to as a "target chip." The second memory chip 100a may perform a phase calibration operation relative to or based on the phase of a first signal SIG1 (i.e., a reference signal) generated from the first memory chip 100, which serves as the reference chip. The configurations of the first memory chip 100 and the second memory chip 100a may be identical or substantially identical, and although not shown, the first memory chip 100 may also include a phase detector. Therefore, in some example embodiments, the first memory chip 100 may be used as the target chip, and the second memory chip 100a may be used as the reference chip. In some example embodiments, the first memory chip 100 may perform a phase calibration operation relative to or based on the phase of a second signal SIG2 generated in the second memory chip 100a.

[0056] Figure 5 This is a block diagram illustrating the duty cycle correction operation of a first memory chip 100 according to an exemplary embodiment of the present invention.

[0057] refer to Figure 5 The first memory chip 100 may include a delay circuit 110, a DCC 120, and a multiplexer 151. The delay circuit 110 can receive a read enable signal nRE through the first pad 101 and generate a first internal read enable signal nRei based on the received read enable signal nRE. For example, the delay circuit 110 may include multiple inverters. When a duty cycle mismatch occurs in the read enable signal nRE, a duty cycle mismatch may also occur in the first internal read enable signal nREi. Even if no duty cycle mismatch occurs in the read enable signal nRE, a duty cycle mismatch may still occur in the first internal read enable signal nREi when passing through the delay circuit 110.

[0058] DCC 120 generates a first corrected read enable signal nREc by performing a first duty cycle correction operation on a first internal read enable signal nREi. DCC 120 can eliminate duty cycle mismatches in the first internal read enable signal nREi; therefore, the duty cycle of the first corrected read enable signal nREc can be 1:1. According to some example embodiments, DCC 120 can have various configurations for performing the first duty cycle correction operation. The configurations and operations of DCC 120 described herein are exemplary, and the inventive concept is not limited thereto.

[0059] Multiplexer 151 can receive first internal data D1 and second internal data D2, and generate a first signal SIG1 from the first internal data D1 and the second internal data D2 according to a first calibrated read enable signal nREc. The generated first signal SIG1 can be output to the Nth input / output pad 103. Multiplexer 151 can generate the first signal SIG1 by outputting the first internal data D1 during the logic high period of the first calibrated read enable signal nREc and outputting the second internal data D2 during the logic low period of the first calibrated read enable signal nREc.

[0060] In some example embodiments, the first memory chip 100 may further include a random data generator, and the first internal data D1 and the second internal data D2 may be generated by the random data generator. In some example embodiments, the first memory chip 100 may further include a register, and the first internal data D1 and the second internal data D2 may be data previously stored in the register. For example, the first internal data D1 may be logic '1', and the second internal data D2 may be logic '0'. In some example embodiments, during the training period, i.e., during phase calibration operations, the first internal data D1 may be fixed to logic '1' (e.g., power supply voltage VDD), and the second internal data D2 may be fixed to logic '0' (e.g., ground voltage GND).

[0061] Figure 6 This is a block diagram schematically illustrating an example embodiment of the DCC 120' according to the concept of the present invention.

[0062] refer to Figure 6 DCC 120' can correspond to Figure 5 An example of DCC 120. DCC 120' may include a duty cycle adjustment (DCA) circuit 121, a first repeater RPT 122 and a second repeater RPT 123, a charge pump PUMP 124, a comparator COMP 125, and an up / down counter UP / DN 126. The DCA circuit 121 can generate an adjusted read enable signal nREa by adjusting the duty cycle of the internal read enable signal nREi.

[0063] The first repeater RPT 122 can receive the regulated read enable signal nREa. The second repeater RPT 123 can output a first clock signal CLKP and a second clock signal CLKN based on the output of the first repeater RPT 122. Each of the first clock signal CLKP and the second clock signal CLKN can have a duty cycle based on the regulated read enable signal nREa. The second clock signal CLKN can be inverted relative to the first clock signal CLKP. However, the inventive concept is not limited thereto. In some exemplary embodiments, the second repeater RPT 123 can output a clock signal and a reference signal based on the regulated read enable signal nREa.

[0064] Charge pump 124 can generate a first charge pump signal CPUMPP and a second charge pump signal CPUMPN from a first clock signal CLKP and a second clock signal CLKN, respectively, through charge pumping. For example, the first charge pump signal CPUMPP can increase during the logic high period of the first clock signal CLKP and decrease during the logic low period of the first clock signal CLKP. Similarly, the second charge pump signal CPUMPN can increase during the logic high period of the second clock signal CLKN and decrease during the logic low period of the second clock signal CLKN. Therefore, when a duty cycle mismatch occurs in the first clock signal CLKP and the second clock signal CLKN, the logic high period in the first clock signal CLKP is relatively long, and the logic high period in the second clock signal CLKN is relatively short. After several clock cycles of the first clock signal CLKP and the second clock signal CLKN, the first charge pump signal CPUMPP can increase, and the second charge pump signal CPUMPN can decrease.

[0065] Comparator 125 compares the first charge pump signal CPUMPP and the second charge pump signal CPUMPN, and generates a comparison result signal CR. For example, when the first charge pump signal CPUMPP is greater than the second charge pump signal CPUMPN, comparator 125 generates the comparison result signal CR as logic high, and when the first charge pump signal CPUMPP is not greater than the second charge pump signal CPUMPN, comparator 125 generates the comparison result signal CR as logic low. Up / down counter 126 generates a control signal CS from the comparison result signal CR. For example, the control signal CS can be generated as a 4-bit digital code. When the comparison result signal CR is logic high, up / down counter 126 increments the code of the control signal CS by 1, and when the comparison result signal CR is logic low, up / down counter 126 decrements the code of the control signal CS by 1.

[0066] Figure 7 It is shown Figure 6 The circuit diagram of DCA circuit 121.

[0067] refer to Figure 7The DCA circuit 121 may include first PMOS transistors PM11 to PM14, second PMOS transistors PM21 to PM25, first NMOS transistors NM11 to NM14, and second NMOS transistors NM21 to NM25. The first PMOS transistors PM11 to PM14 may be commonly connected to the power supply voltage terminal VDD. The first NMOS transistors NM11 to NM14 may be commonly connected to the ground voltage terminal VSS. The first PMOS transistors PM11 to PM14 and the first NMOS transistors NM11 to NM14 may be driven by a control signal CS. The second PMOS transistors PM21 to PM25 and the second NMOS transistors NM21 to NM25 may be driven by an internal read enable signal nREi.

[0068] For example, the control signal CS can be a 4-bit digital code. For instance, when the code of the control signal CS increases by 1, some of the first PMOS transistors PM11 to PM14 can be turned off, and some of the first NMOS transistors NM11 to NM14 can be turned on. Therefore, the logic high period of the regulated internal read signal nREa can be reduced compared to the internal read signal nREi. Alternatively, when the code of the control signal CS decreases by 1, some of the first PMOS transistors PM11 to PM14 can be turned on, and some of the first NMOS transistors NM11 to NM14 can be turned off. Therefore, the logic high period of the regulated internal read signal nREa can be increased compared to the internal read signal nREi.

[0069] Figure 8 This is a block diagram illustrating the duty cycle correction operation and phase calibration operation of a second memory chip 100a according to an exemplary embodiment of the present invention.

[0070] refer to Figure 8 The second memory chip 100a may include a delay circuit 110a, a DCC 120a, a phase detector 130a, a multiplexer 161a, and a first input buffer 152a and a second input buffer 162a. The delay circuit 110a may receive a read enable signal nRE via a first pad 101a and generate a second internal read enable signal nREi' based on the received read enable signal nRE. For example, the delay circuit 110a may include multiple inverters. The delay circuit 110a may be implemented substantially similarly to the delay circuit 110 of the first memory chip 100. However, a phase difference may occur between the first internal read enable signal nREi and the second internal read enable signal nREi' due to reasons such as process variations relative to the first memory chip 100 and the second memory chip 100a, or process variations relative to the delay circuit 110 and the delay circuit 110a.

[0071] DCC 120a can generate a second corrected read enable signal nREc' by performing a second duty cycle correction operation on the second internal read enable signal nREi'. Multiplexer 161a can receive first internal data D1 and second internal data D2, and generate a second signal SIG2 from the first internal data D1 and second internal data D2 based on the second corrected read enable signal nREc'. The generated second signal SIG2 can be output to the (N+1)th input / output pad 104a. DCC 120a and multiplexer 161a can be substantially similar to... Figure 5 The DCC 120 and multiplexer 151 are used for implementation, and the above references... Figure 5 The provided description can also be applied to this example embodiment.

[0072] The first input buffer 152a and the second input buffer 162a can be connected to the Nth input / output pad 103a and the (N+1)th input / output pad 104a, respectively. For example, the first input buffer 152a can buffer the first signal SIG1 received from the first memory chip 100 through the Nth input / output pad 103a and output the buffered first signal SIG1 to the phase detector 130a. The second input buffer 162a can buffer the second signal SIG2 provided to the (N+1)th input / output pad 104a and output the buffered second signal SIG2 to the phase detector 130a. The phase detector 130a can generate a third signal SIG3 based on the phase difference between the first signal SIG1 and the second signal SIG2 and provide the generated third signal SIG3 to the DCC 120a.

[0073] Figure 9 This illustrates an example embodiment of the concept according to the present invention. Figure 8 Timing diagram of the operation of phase detector 130a.

[0074] refer to Figure 9The phase difference PD may occur between the first signal SIG1 and the second signal SIG2, therefore, a time difference may occur between the rising edge of the first signal SIG1 and the rising edge of the second signal SIG2. Phase detector 130a can generate a third signal SIG3 with a logic high level during the logic high period of the first signal SIG1 or the logic high period of the second signal SIG2. For example, phase detector 130a may include an OR gate, so as the phase difference PD between the first signal SIG1 and the second signal SIG2 increases, the logic high period of the third signal SIG3 can increase, and the duty cycle of the third signal SIG3 can increase. As described above, phase detector 130a can convert the phase difference PD between the first signal SIG1 and the second signal SIG2 into the duty cycle of the third signal SIG3. The third signal SI3G may have a duty cycle based on the phase difference PD between the first signal SIG1 and the second signal SIG2.

[0075] Figure 10 This section provides a detailed illustration of exemplary embodiments based on the concept of the present invention. Figure 3 Block diagram of the storage device SD1.

[0076] Also refer to Figure 3 and Figure 10 The first pads 101 to 104 of the first memory chip 100 can be respectively connected to the first pads 101a to 104a of the second memory chip 100a. For example, the first pads 101 and 101a can be connected together to the first pin P1 to receive the read enable signal nRE from the controller 50. For example, the second pads 102 and 102a can be connected together to the second pin P2 to send a data strobe signal DQS to the controller 50 and receive a data strobe signal DQS from the controller 50. For example, the third pads 103 and 103a can be connected together to one of the third pins P3 to send data to the controller 50 and receive data from the controller 50, and the fourth pads 104 and 104a can be connected to the other of the third pins P3 to send data to the controller 50 and receive data from the controller 50. According to some example embodiments, the third pads 103 and 103a may be referred to as the Nth input / output pads, while the fourth pads 104 and 104a may be referred to as the N+1th input / output pads.

[0077] The first memory chip 100 may include a delay circuit 110, a DCC 120, multiplexers 141, 151, and 161, and input buffers 142, 152, and 162. Multiplexer 141 and input buffer 142 may be connected to a second pad 102, multiplexer 151 and input buffer 152 may be connected to a third pad 103, and multiplexer 161 and input buffer 162 may be connected to a fourth pad 104. Although not shown, the first memory chip 100 may also include output buffers connected to each of the second through fourth pads 102, 103, and 104.

[0078] Delay circuit 110 can generate a first internal read enable signal nREi from the read enable signal nRE and provide the generated first internal read enable signal nREi to DCC 120. DCC 120 can generate a first corrected read enable signal nREc by performing a first duty cycle correction operation DCC 1 on the first internal read enable signal nREi. For example, DCC 120 may include DCA circuit 121, repeaters 122, 122' and 123, charge pump 124, comparator 125 and up / down counter 126, and referenced above. Figure 6 The provided description can also be applied to this example embodiment.

[0079] Multiplexer 151 can receive first internal data D1 and second internal data D2, and generate a first signal SIG1 from the first internal data D1 and second internal data D2 according to a first calibrated read enable signal nREc. The generated first signal SIG1 can be output to the third pad 103. In some example embodiments, when the first duty cycle calibration operation DCC1 on the first internal read enable signal nREi is completed, the first memory chip 100 can output the first signal SIG1 to the third pad 103.

[0080] The second memory chip 100a may include a delay circuit 110a, a DCC 120a, a phase detector 130a, multiplexers 141a, 151a, and 161a, and input buffers 142a, 152a, and 162a. Multiplexer 141a and input buffer 142a may be connected to a second pad 102a, multiplexer 151a and input buffer 152a may be connected to a third pad 103a, and multiplexer 161a and input buffer 162a may be connected to a fourth pad 104a. Although not shown, the second memory chip 100a may also include output buffers connected to the second through fourth pads 102a, 103a, and 104a, respectively.

[0081] Delay circuit 110a can generate a second internal read enable signal nREi' from the read enable signal nRE and provide the generated second internal read enable signal nREi' to DCC 120a. DCC 120a can generate a second corrected read enable signal NReC' by performing a second duty cycle correction operation DCC2 on the second internal read enable signal nREi'. For example, DCC 120a may include DCA circuit 121a, repeaters 122a, 122a' and 123a, charge pump 124a, comparator 125a and up / down counter 126a, and referenced above. Figure 6 The provided description can also be applied to this example embodiment.

[0082] Multiplexer 161a can receive first internal data D1 and second internal data D2, and generate a second signal SIG2 from the first internal data D1 and the second internal data D2 according to a second corrected read enable signal nREc'. The generated second signal SIG2 can be output to the fourth pad 104a. In some example embodiments, when the second duty cycle correction operation DCC2 on the second internal read enable signal nREc' is completed, the second memory chip 100a can output the second signal SIG2 to the fourth pad 104a.

[0083] Phase detector 130a can be connected to the output terminals of input buffers 152a and 162a, and can receive a first signal SIG1 and a second signal SIG2 from input buffers 152a and 162a. Phase detector 130a can generate a third signal SIG3 with a duty ratio (or duty cycle) based on the phase difference PD between the first signal SIG1 and the second signal SIG2. In some example embodiments, phase detector 130a can be enabled after the first duty cycle correction operation DCC1 of the first memory chip 100 and the second duty cycle correction operation DCC2 of the second memory chip 100a are completed.

[0084] DCC 120a may also include first switches SW1 to fourth switches SW4. First switch SW1 may be located between repeater 123a and charge pump 124a. Second switch SW2 may be located between up / down counter 126a and DCA circuit 121a. Third switch SW3 may be located between phase detector 130a and charge pump 124a. Fourth switch SW4 may be located between up / down counter 126a and delay circuit 110a. The second duty cycle correction operation DCC2 and the phase calibration operation of the second memory chip 100a, based on the on / off operation of the first switches SW1 to fourth switches SW4, will be described in detail below.

[0085] During the first period of the second duty cycle correction operation DCC2 of the second memory chip 100a, the first switch SW1 and the second switch SW2 can be turned on, and the third switch SW3 and the fourth switch SW4 can be turned off. Therefore, during the first period, a DCC loop of the second internal read enable signal nREi' can be formed in DCC 120a, and DCC 120a can generate the second corrected read enable signal nREc' by performing the second duty cycle correction operation DCC2' on the second internal read enable signal nREi'.

[0086] During the second time period in which the phase calibration operation of the second memory chip 100a is performed, the first switch SW1 and the second switch SW2 can be turned off, and the third switch SW3 and the fourth switch SW4 can be turned on. Therefore, a DCC loop for the third signal SIG3 can be formed during the second time period. In some example embodiments, the charge pump 124a can generate a charge pump signal from the third signal SIG3 by charge pump excitation, and the comparator 125a can compare the charge pump signal with a reference signal and generate a comparison result signal CRa. In some example embodiments, the charge pump 124a can generate a first charge pump signal and a second charge pump signal by receiving the third signal SIG3 and an inverted third signal, and the comparator 125a can generate the comparison result signal CRa by comparing the first charge pump signal and the second charge pump signal. The up / down counter 126a can generate a control signal CSa based on the comparison result signal CSa and provide the generated control signal CSa to the delay circuit 110a.

[0087] The delay circuit 110a can generate a second internal read enable signal nREi' by adjusting the delay time relative to the read enable signal nRE according to the control signal CSa received from the up / down counter 126a. Therefore, the phase of the second signal SIG2 generated from the second internal read enable signal nREi' can be the same as the phase of the first signal SIG1, and the phases of the first signal SIG1 and the second signal SIG2 can be aligned.

[0088] Figure 11 This is a block diagram illustrating in detail an example embodiment of a storage device SD1a according to the concept of the present invention.

[0089] refer to Figure 11 The storage device SD1a can correspond to Figure 10 The above is a modification example of the SD1 storage device, and refers to... Figure 10The provided description can also be applied to this example embodiment. The second memory chip 100a' may include a DCC 120a' and a phase detector 130a'. The phase detector 130a' can generate a third signal SIG 3' with a logic high or low level based on the phase difference between the first signal SIG1 and the second signal SIG2, and provides the generated third signal SIG 3' to the up / down counter 126a'. During a second time period in which the phase calibration operation of the second memory chip 100a' is performed, the first switch SW1 and the second switch SW2 can be turned off, and the fourth switch SW4 and the fifth switch SW5 can be turned on. The up / down counter 126a' can generate a control signal CSa based on the third signal SIG3', and provide the generated control signal CSa to the delay circuit 110a.

[0090] Figure 12 This is a block diagram illustrating in detail an example embodiment of a storage device SD1b according to the present invention.

[0091] Also refer to Figure 3 and Figure 12 The storage device SD1b may include a first memory chip 100', a second memory chip 100a", and a controller 50. The storage device SD1b may correspond to Figure 10 The above is a modification example of the SD1 storage device, and refers to... Figure 10 The provided description can also be applied to this example embodiment.

[0092] The first memory chip 100' may include a delay circuit 110, a delay unit 127, repeaters 122, 122' and 123, a phase detector 128, a control circuit CTRL 129, multiplexers 141, 151 and 161, input buffers 142, 152 and 162, and first pads 101 to fourth pads 104. For example, the delay unit 127, repeaters 122, 122' and 123, phase detector 128 and control circuit 129 may form a DLL, thus enabling the execution of a first DLL operation DLL1.

[0093] Phase detector 128 can generate a phase detection signal PDS with a logic high or logic low level based on the phase difference between the output signal of repeater 123 and the read enable signal nRE. Control circuit 129 can generate a control signal CS' for controlling delay unit 127 based on phase detection signal PDS. Delay unit 127 can adjust the delay time relative to the first internal read enable signal nREi based on control signal CS'.

[0094] The second memory chip 100a” may include a delay circuit 110a, a delay unit 127a, repeaters 122a, 122a' and 123a, a phase detector 130a”, a control circuit 129a, multiplexers 141a, 151a and 161a, input buffers 142a, 152a and 162a, a first switch SW1 and a sixth switch SW6, and first pads 101a to fourth pads 104a. For example, the delay unit 127a, repeaters 122a, 122a' and 123a, phase detector 130a” and control circuit 129a can form a DLL, thus enabling the execution of the second DLL operation DLL2.

[0095] Phase detector 130a” can be connected to the output terminals of input buffers 152a and 162a, and can receive a first signal SIG1 and a second signal SIG2 from input buffers 152a and 162a. Phase detector 130a” can generate a third signal SI3G” with a logic high level or a logic low level based on the phase difference between the first signal SIG1 and the second signal SIG2. In some example embodiments, phase detector 130a” can be enabled after the first DLL operation DLL1 of the first memory chip 100' and the second DLL operation DLL2 of the second memory chip 100a” are completed.

[0096] During the first period of the second DLL operation of the second memory chip 100a", the first switch SW1 and the sixth switch SW6 can be turned on. The phase detector 130a can generate a third signal SIG3" with a logic high level or a logic low level based on the phase difference between the output signal of the repeater 123a and the read enable signal nRE. The control circuit 129a can generate a control signal CSa' for controlling the delay unit 127a based on the third signal SIG3". The delay unit 127a can adjust the delay time relative to the second internal read enable signal nREi' based on the control signal CSa'.

[0097] During the second period in which the phase calibration operation of the second memory chip 100a” is performed, the first switch SW1 and the sixth switch SW6 can be turned off. The phase detector 130a” can generate a third signal SIG3” with a logic high level or a logic low level based on the phase difference between the first signal SIG1 and the second signal SIG2 received from the input buffers 152a and 162a. In some example embodiments, the control circuit 129a can generate a control signal CSa' from the third signal SIG3”, and the delay unit 127a can adjust the delay time relative to the second internal read enable signal nREi' based on the control signal CSa'. Therefore, the phase of the second signal SIG2 generated from the output of the delay unit 127a can be the same as the phase of the first signal SIG1, and the phases of the first signal SIG1 and the second signal SIG2 can be aligned.

[0098] Figure 13 This is a flowchart illustrating the operation of a controller 50, a first memory chip 100, and a second memory chip 100a according to an exemplary embodiment of the present invention.

[0099] refer to Figure 13 In operation S110, the controller 50 issues a DCC start command (CMD) instructing the initiation of DCC training and activates the clock signal CLK. For example, the DCC start command can be implemented as a set feature command. For example, the DCC start command can correspond to a duty cycle correction start command. For example, the clock signal CLK can be a read enable signal nRE. In operation S120, the controller 50 sends the DCC start command and the activated clock signal CLK to the first memory chip 100 and the second memory chip 100a. For example, the DCC start command can be sent from the controller 50 to the first memory chip 100 and the second memory chip 100a via the third pin P3', and the clock signal CLK can be sent from the controller 50 to the first memory chip 100 and the second memory chip 100a via the first pin P1'.

[0100] In operation S130, the first memory chip 100 performs a duty cycle correction operation on the clock signal CLK. The first memory chip 100 can generate a first signal SIG1 from the clock signal CLK as a result of performing the duty cycle correction operation. In operation S135, the second memory chip 100a performs a duty cycle correction operation on the clock signal CLK. The second memory chip 100a can generate a second signal SIG2 from the clock signal CLK as a result of performing the duty cycle correction operation. In some example embodiments, operations S130 and S135 can be executed sequentially. In some example embodiments, operations S130 and S135 can be executed in parallel.

[0101] In operation S140, the first memory chip 100 sends the first signal SIG1 to the second memory chip 100a via the Nth input / output pad. For example, the Nth input / output pad may correspond to an input / output pad through which the Nth data DQ_N is sent / received. In some example embodiments, the first signal SIG1 may correspond to a correction clock signal generated as a result of performing a duty cycle correction operation based on the clock signal CLK.

[0102] In operation S150, the second memory chip 100a detects the phase difference between the first signal SIG1 and the second signal SIG2, and generates a third signal SIG3 with a duty ratio (or duty cycle) based on this phase difference. In operation S160, the second memory chip 100a performs a phase calibration operation based on the third signal SIG3. In operation S170, the second memory chip 100a controls the delay circuit 110a. (Refer to above) Figures 10 to 12 The provided description can be applied to operations S150 to S170.

[0103] In operation S180, controller 50 issues a DCC end command indicating the end of DCC training and deactivates the clock signal CLK. For example, controller 50 may determine the timing of issuing the DCC end command based on a previously determined number of clock cycles relative to the DCC training period. For example, the DCC end command may be implemented as a setting feature command. For example, the DCC end command may correspond to a duty cycle correction end command. In operation S190, controller 50 sends the DCC end command and the deactivation clock signal CLK to the first memory chip 100 and the second memory chip 100a.

[0104] Figure 14A and 14B This is a timing diagram illustrating duty cycle correction sequences of some example embodiments of the present invention.

[0105] refer to Figure 14A The duty cycle correction sequence can be defined as a setting feature type. The controller can issue a setting feature command before normal operation of the non-volatile memory device. For example, a setting feature command is a command used to set a feature or operating condition of the non-volatile memory device. In some example embodiments, the duty cycle correction enable sequence is initiated by receiving a setting feature command. For example, the duty cycle correction sequence may include a first time period PR1 through a third time period PR3.

[0106] In the first time period PR1, via data cable (e.g., connected to) Figure 3The first setup feature command SF1 and address ADDR are sequentially applied to the signal line of the third pin P3. Then, write data WD indicating the start of duty cycle correction operation can be sent. By applying write data WD in the first time period PR1, the operating characteristics of the non-volatile memory device can be modified to the duty cycle correction sequence in normal operation. After the write data WD is sent, the ready / busy state is entered. The signal can be changed to a busy state.

[0107] In the second time period PR2, a random read command RR and address ADDR are sequentially applied via the data lines, and then random read data RD can be sent. In some example embodiments, the non-volatile memory device may include a random data generator, and may output random data generated by the random data generator as random read data RD. In some example embodiments, the non-volatile memory device may include registers, and may output data previously stored in the registers as random read data RD.

[0108] In the third time slot PR3, the second setup feature command SF2 and address ADDR are sequentially applied via the data lines. Then, write data WD, indicating the end of the duty cycle correction operation, can be applied. By applying the write data WD in the third time slot PR3, the operating characteristics of the non-volatile memory device can be modified to normal operation within the duty cycle correction sequence. After the write data WD is sent, the ready / busy state is entered. The signal can be changed to a busy state.

[0109] refer to Figure 14B Duty cycle correction sequence can be defined as a command type. First, the duty cycle correction start command DCS and address ADDR are applied sequentially via the data lines. Therefore, the duty cycle correction operation can be initiated in a non-volatile memory device, and the DCC training period can be started. At this point, the duty cycle correction start command can be referred to as the duty cycle correction enable command.

[0110] Subsequently, random read data RD can be sent via the data line during DCC training. Then, the duty cycle correction end command DCE and address ADDR are sequentially applied via the data line; therefore, the duty cycle correction operation can be terminated in the non-volatile memory device, and the DCC training period can end. In some example embodiments, the duty cycle correction end command DCE may be referred to as the duty cycle correction disable command.

[0111] exist Figure 14ADuring the duty cycle correction sequence shown in 14B, the clock signal CLK, such as the read enable signal nRE, can be activated and switched to a certain frequency. After the duty cycle correction sequence is initiated, the read enable signal nRE switches for tens or hundreds of cycles depending on the operating environment of the non-volatile memory device or the DCC capability. By switching the read enable signal nRE, the DCC included in each memory chip can correct duty cycle mismatches that may occur in the internal read enable signal nRE. Furthermore, the phase detector included in the target chip can perform a phase calibration operation relative to a reference signal generated by the reference chip. After the duty cycle correction sequence ends, the non-volatile memory device can initiate normal read or program operations. When the duty cycle correction sequence ends, the DCC included in each memory chip can continue to provide a duty cycle-corrected clock signal when a clock signal is input during normal read or program operations relative to the non-volatile memory device.

[0112] In some example embodiments, the duty cycle correction sequence may be performed after a power-up sequence that applies power to the non-volatile memory device. In some example embodiments, the duty cycle correction sequence may be performed periodically during the idle state of the non-volatile memory device. In some example embodiments, the duty cycle correction sequence may be performed during a portion of the read latency period preceding the read phase included in the read phase of the non-volatile memory device.

[0113] Figure 15 This is a flowchart illustrating the operation of a controller 50, a first memory chip 100, and a second memory chip 100a according to an exemplary embodiment of the present invention.

[0114] refer to Figure 15 In operation S110, the controller 50 issues a DCC start command indicating the start of DCC training and activates the clock signal CLK. For example, the DCC start command can be implemented as a setting feature command. For example, the DCC start command can correspond to a duty cycle correction start command. For example, the clock signal CLK can be a read enable signal nRE. In operation S120, the controller 50 sends the DCC start command and the activated clock signal CLK to the first memory chip 100 and the second memory chip 100a. For example, the DCC start command can be sent from the controller 50 to the first memory chip 100 and the second memory chip 100a via the third pin P3', and the clock signal CLK can be sent from the controller 50 to the first memory chip 100 and the second memory chip 100a via the first pin P1'.

[0115] In operation S130, the first memory chip 100 performs a duty cycle correction operation on the clock signal CLK. The first memory chip 100 can generate a first signal SIG1 from the clock signal CLK as a result of performing the duty cycle correction operation. In operation S135, the second memory chip 100a performs a duty cycle correction operation on the clock signal CLK. The second memory chip 100a can generate a second signal SIG2 from the clock signal CLK as a result of performing the duty cycle correction operation. In some example embodiments, operations S130 and S135 can be executed sequentially. In some example embodiments, operations S130 and S135 can be executed in parallel.

[0116] In operation S180, the controller 50 issues a DCC end command indicating the end of DCC training and deactivates the clock signal CLK. For example, the DCC end command can be implemented as a setting feature command. For example, the DCC end command can correspond to a duty cycle correction end command. In operation S190, the controller 50 sends the DCC end command and the deactivation clock signal CLK to the first memory chip 100 and the second memory chip 100a.

[0117] In operation S210, controller 50 issues a phase calibration PC start command indicating the start of the phase calibration operation. In operation S220, controller 50 sends the phase calibration PC start command to the first memory chip 100 and the second memory chip 100a. In operation S230, the first memory chip 100 sends a first signal SIG1 to the second memory chip 100a. In operation S240, the second memory chip 100a performs the phase calibration operation. For example, operation S240 may include... Figure 13 Operations S150 to S170 are performed. In operation S250, the controller 50 issues a phase calibration PC end command indicating the end of the phase calibration operation. In operation S260, the controller 50 sends the phase calibration end PC command to the first memory chip 100 and the second memory chip 100a.

[0118] Figure 16 This is a block diagram schematically illustrating an example embodiment of a storage device SD2 according to a concept of the present invention.

[0119] refer to Figure 16The storage device SD2 may include a first memory device 10a, a second memory device 20, and a controller 50a. The first memory device 10a can be connected to the controller 50a via a first channel CH1, and the second storage device 20 can be connected to the controller 50a via a second channel CH2. The first memory device 10a may include a plurality of memory chips, including at least a first memory chip 100 and a second memory chip 100a. Therefore, the plurality of memory chips including the first memory chip 100 and the second memory chip 100a can send data to and receive data from the controller 50a via the first channel CH1. The second storage device 20 may include a plurality of memory chips, including at least a first memory chip 200 and a second memory chip 200a. Therefore, the plurality of memory chips including the first memory chip 200 and the second memory chip 200a can send data to and receive data from the controller 50a via the second channel CH2.

[0120] The multiple memory chips included in the first memory device 10a can be as follows: Figures 1 to 14B The phase calibration operation is performed relative to or based on a first signal generated by a first memory chip 100, which is one of a plurality of memory chips, and therefore the phases of the signals generated by the plurality of memory chips of the first memory device 10a can be aligned. Similarly, the plurality of memory chips included in the second memory device 20 can be aligned as follows. Figures 1 to 14B The phase calibration operation is performed relative to or based on the second signal generated by the first memory chip 200, which is one of a plurality of memory chips, and thus the phases of the signals generated by the plurality of memory chips of the second memory device 20 can be aligned.

[0121] Furthermore, controller 50a can perform a phase calibration operation based on the phase difference between a first signal received from a first memory chip 100, which is one of a plurality of memory chips connected to the first channel CH1, and a second signal received from a first memory chip 200, which is one of a plurality of memory chips connected to the second channel CH2. For example, controller 50a can calibrate the phase of the second signal based on the phase of the first signal.

[0122] As described above, according to this example embodiment, controller 50a can perform phase calibration operations between memory chips connected to the same channel. Furthermore, according to this example embodiment, controller 50a can perform phase calibration operations between memory chips connected to different channels. Hereinafter, reference will be made to… Figure 17 Describes the phase calibration operation between memory chips connected to different channels.

[0123] Figure 17 Showing more details Figure 16 The storage device SD2.

[0124] refer to Figure 17 The first memory device 10a may include a first pin P1 and a second pin P2. Multiple memory chips including the first memory chip 100 may be commonly connected to each of the first pin P1 and the second pin P2. The second memory device 20 may include a first pin P1a and a second pin P2a. Multiple memory chips including the first memory chip 200 may be commonly connected to each of the first pin P1a and the second pin P2a. The controller 50a may include multiple pins P1', P2', P1a', and P2a'. Pins P1' and P2' may be connected to the first pin P1 and the second pin P2 of the first memory device 10a, respectively. Pins P1a' and P2a' may be connected to the first pin P1a and the second pin P2a of the second memory device 20, respectively.

[0125] The first memory device 10a can receive a first clock signal CLK1 from the controller 50a via the first pin P1, and send and receive a first data strobe signal DQS1 from the controller 50a via the second pin P2. During the DCC training period, the first memory chip 100 included in the first memory device 10a can perform a duty cycle correction operation based on the first clock signal CLK1. For example, the delay circuit 110 can generate a first internal clock signal CLK1i from the first clock signal CLK1, and the DCC 120 can perform a duty cycle correction operation on the first internal clock signal CLK1i. The result of performing the duty cycle correction operation can be output as the first data strobe signal DQS1. The first memory device 10a can provide the first data strobe signal DQS1 to the controller 50a via the second pin P2.

[0126] The second memory device 20 can receive the second clock signal CLK2 from the controller 50a via the first pin P1a, and send and receive the second data strobe signal DQS2 from the controller 50a via the second pin P2a. During the DCC training period, the first memory chip 200 included in the second memory device 20 can perform a duty cycle correction operation based on the second clock signal CLK2. For example, the delay circuit 210 can generate a second internal clock signal CLK2i from the second clock signal CLK2, and the DCC 220 can perform a duty cycle correction operation on the second internal clock signal CLK2i. The result of performing the duty cycle correction operation can be output as the second data strobe signal DQS2, and the second memory device 20 can provide the second data strobe signal DQS2 to the controller 50a via the second pin P2a.

[0127] The controller 50a may further include a phase detector 510, a DCC 520, and a delay circuit 530. The phase detector 510 receives a first data strobe signal DQS1 from the first memory device 10 via pin P2' and a second data strobe signal DQS2 from the second memory device 20 via pin P2a'. The phase detector 510 can detect the phase difference between the first data strobe signal DQS1 and the second data strobe signal DQS2, and generate a phase detection signal PDS1 with a duty cycle based on the detected phase difference.

[0128] The DCC 520 may include a charge pump 521, a comparator 522, and an up / down counter 523. The DCC 520 can be substantially similar to... Figure 6 Implemented using DCC 120', and refer to the above. Figure 6 The provided description can also be applied to this example embodiment. In some example embodiments, charge pump 521 can generate a charge pump signal from phase detection signal PDS1 via charge pump excitation, and comparator 522 can compare the charge pump signal with a reference signal and generate a comparison result signal CRb. In some example embodiments, charge pump 521 can generate a first charge pump signal and a second charge pump signal by receiving phase detection signal PDS1 and an inverted phase detection signal, and comparator 522 can generate a comparison result signal CRb by comparing the first charge pump signal and the second charge pump signal. Up / down counter 523 can generate a control signal CSb based on the comparison result signal CRb and provide the generated control signal CSb to delay circuit 530. In some example embodiments, phase detector 510 can detect the phase difference between first data strobe signal DQS1 and second data strobe signal DQS2 and generate an output signal with a logic high level or logic low level according to the detected phase difference. Phase detector 510 can provide the generated output signal to up / down counter 523.

[0129] The delay circuit 530 can generate a second clock signal CLK2 by adjusting the delay time relative to the clock signal CLK according to the control signal CSb received from the up / down counter 523. Therefore, the phase of the second clock signal CLK2 can be synchronized with, for example, the phase of the first clock signal CLK1, and consequently, the phase of the second data strobe signal DQS2 can be aligned with the phase of the first data strobe signal DQS1. Thus, the storage device SD2 can perform a phase calibration operation on the first memory device 10a and the second memory device 20, which are respectively connected to different first channels CH1 and second channels CH2.

[0130] In some example embodiments, controller 50a may further include a DLL circuit, and use the DLL of the DLL circuit to perform a phase calibration operation. For example, the DLL circuit of controller 50a may receive a first data strobe signal DQS1 and a second data strobe signal DQS2, and the DLL circuit may control the delay circuit 53 based on the phase difference between the first data strobe signal DQS1 and the second data strobe signal DQS2. Therefore, the delay circuit 530 may delay the second clock signal CLK2, and the phases of the first data strobe signal DQS1 and the second data strobe signal DQS2 may be aligned. In this case, controller 50a may perform the phase calibration operation along with the DLL training operation during the DLL training period.

[0131] Figure 18 This is a block diagram schematically illustrating an example embodiment of a storage device SD3 according to a concept of the present invention.

[0132] refer to Figure 18 The storage device SD3 may include a first memory device 10a and a second memory device 20, a buffer chip 30, and a controller 50b. Figure 16 Compared to storage device SD2, storage device SD3 according to this example embodiment may further include a buffer chip 30. The buffer chip 30 may be connected between controller 50b and the first memory device 10a and the second memory device 20, and may be referred to as a frequency boosting interface (FBI) circuit. In some example embodiments, the first memory device 10a, the second memory device 20, and the buffer chip 30 may be implemented in a single package, and may be referred to as a non-volatile memory device.

[0133] A first memory device 10a can be connected to a buffer chip 30 via a first channel CH1. A second memory device 20 can be connected to the buffer chip 30 via a second channel CH2. The buffer chip 30 can be connected to a controller 50b via a third channel CH3. The first memory device 10a may include a plurality of memory chips, including at least a first memory chip 100 and a second memory chip 100a. Therefore, the plurality of memory chips including the first memory chip 100 and the second memory chip 100a can send data to and receive data from the buffer chip 30 via the first channel CH1. The second memory device 20 may include a plurality of memory chips, including at least a first memory chip 200 and a second memory chip 200a. Therefore, the plurality of memory chips including the first memory chip 200 and the second memory chip 200a can send data to and receive data from the buffer chip 30 via the second channel CH2.

[0134] The multiple memory chips included in the first memory device 10a can be as follows: Figures 1 to 14B As shown, a phase calibration operation is performed relative to a first signal generated by a first memory chip 100, which is one of a plurality of memory chips. Therefore, the phases of the signals generated by the plurality of memory chips in the first memory device 10a can be aligned. Similarly, the plurality of memory chips included in the second memory device 20 can be aligned as follows. Figures 1 to 14B As shown, a phase calibration operation is performed relative to the second signal generated by the first memory chip 200, which is one of a plurality of memory chips. Therefore, the phases of the signals generated by the plurality of memory chips of the second memory device 20 can be aligned.

[0135] Furthermore, the buffer chip 30 can perform a phase calibration operation on the first signal and the second signal based on the phase difference between a first signal received from a first memory chip 100, which is one of a plurality of memory chips connected to the first channel CH1, and a second signal received from a first memory chip 200, which is one of a plurality of memory chips connected to the second channel CH2. For example, the buffer chip 30 can calibrate the phase of the second signal based on the phase of the first signal.

[0136] As described above, according to this example embodiment, the buffer chip 30 can perform phase calibration operations between memory chips connected to the same channel. Furthermore, according to this example embodiment, the buffer chip 30 can perform phase calibration operations between memory chips connected to different channels. Hereinafter, reference will be made to… Figure 19 Describes the phase calibration operation between memory chips connected to different channels.

[0137] Figure 19 Example embodiments of the present invention are shown in more detail. Figure 18 The storage device SD3.

[0138] refer to Figure 18 and Figure 19 The first memory chip 100 may include internal circuitry 110', an input buffer 142, an output buffer 143, and a first pad 101 and a second pad 102. The input buffer 142 and the output buffer 143 may be connected to the second pad 102. The internal circuitry 110' can receive a first read enable signal nRE1 from the buffer chip 30 or the controller 50b via the first pad 101, and generate a first data strobe signal DQS1 from the first read enable signal nRE1. According to an example embodiment, the first memory chip 100 may be substantially similar to... Figure 10 , 11 The first memory chip 100 shown in 12 or 17 is used for implementation, and the above reference is made to Figures 10 to 12 as well as Figure 17 The provided description can also be applied to this example embodiment.

[0139] The first memory chip 200 may include internal circuitry 210', an input buffer 242, an output buffer 243, a first pad 201, and a second pad 202. The input buffer 242 and the output buffer 243 may be connected to the second pad 202. The internal circuitry 210' can receive a second read enable signal nRE2 from the buffer chip 30 or the controller 50b via the first pad 201, and generate a second data strobe signal DQS2 from the second read enable signal nRE2. The first memory chip 200 may be substantially similar to... Figure 10 , 11 The first memory chip 100 shown in 12 or 17 is used to implement this, and the above reference is made to... Figures 10 to 12 as well as Figure 17 The provided description can also be applied to this example embodiment.

[0140] The buffer chip 30 or controller 50b may include a phase detector 310a, a DCC 320, a delay circuit 330, and pads 301a to 304. The buffer chip 30 or controller 50b can provide a first read enable signal nRE1 to the first memory chip 100 via pad 301a, and a second read enable signal nRE2 to the first memory chip 200 via pad 303. Furthermore, the buffer chip 30 or controller 50b can send and receive a first data strobe signal DQS1 to and from the first memory chip 100 via pad 302, and send and receive a second data strobe signal DQS2 to and from the first memory chip 200 via pad 304.

[0141] Phase detector 310a can detect the phase difference between a first data gating signal DQS1 and a second data gating signal DQS2, and generate a phase detection signal PDS2 with a duty ratio (or duty cycle) based on the detected phase difference. DCC 320 may include a charge pump 321, a comparator 322, and an up / down counter 323. DCC 320 can be substantially similar to... Figure 6 Implemented using DCC 120', and refer to the above. Figure 6The provided description can also be applied to this example embodiment. In some example embodiments, charge pump 321 can generate a charge pump signal from phase detection signal PDS2 via charge pump excitation, and comparator 332 can compare the charge pump signal with a reference signal to generate a comparison result signal CRc. In some example embodiments, charge pump 331 can generate a first charge pump signal and a second charge pump signal by receiving phase detection signal PDS2 and an inverted phase detection signal, and comparator 322 can generate the comparison result signal CRc by comparing the first charge pump signal and the second charge pump signal. Up / down counter 323 can generate a control signal CSc based on the comparison result signal CRc and provide the generated control signal CSc to delay circuit 330.

[0142] In some example embodiments, phase detector 310a can detect the phase difference between the first data strobe signal DQS1 and the second data strobe signal DQS2, and generate an output signal having a logic high level or a logic low level according to the detected phase difference. Phase detector 310a can provide the generated output signal to up / down counter 323.

[0143] The delay circuit 330 can generate a second read enable signal nRE2 by adjusting the delay time relative to the read enable signal nRE according to the control signal CSc received from the up / down counter 323. Therefore, the phase of the second read enable signal nRE2 can be aligned with, for example, the phase of the first read enable signal nRE1, and consequently, the phase of the second data strobe signal DQS2 can be aligned with the phase of the first data strobe signal DQS1. Thus, the storage device SD3 can perform a phase calibration operation on the first memory device 10a and the second memory device 20, which are respectively connected to different first channels CH1 and second channels CH2.

[0144] In some example embodiments, the buffer chip 30 or controller 50b may further include a DLL circuit, and the DLL of the DLL circuit is used to perform a phase calibration operation. For example, the DLL circuit of the buffer chip 30 or controller 50b may receive a first data strobe signal DQS1 and a second data strobe signal DQS2, and the DLL circuit may control the delay circuit 330 based on the phase difference between the first data strobe signal DQS1 and the second data strobe signal DQS2. Therefore, the delay circuit 330 may delay the second read enable signal nRE2, and the phases of the first data strobe signal DQS1 and the second data strobe signal DQS2 may be aligned. In some example embodiments, the buffer chip 30 or controller 50b may perform the phase calibration operation along with the DLL training operation during the DLL training period.

[0145] Figure 20A storage device SD3a is schematically shown according to an example embodiment of the present invention.

[0146] Also refer to Figure 18 and Figure 20 The storage device SD3a corresponds to Figure 19 The above is a modification example of the SD3 storage device, and refers to... Figure 19 The provided description can also be applied to this example embodiment. The storage device SD3a differs in the configuration of the buffer chip 30a or the controller 50b. Figure 19 The storage device SD3. The buffer chip 30a or controller 50b may include a phase detector 310b, a controller 324, a delay unit 325, a delay circuit 330, and pads 301a to 304.

[0147] Phase detector 310b can detect the phase difference between the first data strobe signal DQS1 and the second data strobe signal DQS2, and generate a phase detection signal PDS2' with a logic high level or logic low level according to the detected phase difference. Control circuit 324 can control delay unit 325 based on phase detection signal PDS2', and delay unit 325 can provide control signal CSd to delay circuit 330.

[0148] The delay circuit 330 can generate a second read enable signal nRE2 by adjusting the delay time relative to the read enable signal nRE according to the control signal CSd received from the delay unit 325. Therefore, the phase of the second read enable signal nRE2 can be aligned with, for example, the phase of the first read enable signal nRE1, and consequently, the phase of the second data strobe signal DQS2 can be aligned with the phase of the first data strobe signal DQS1. Thus, the storage device SD3a can perform a phase calibration operation on the first memory device 10a and the second memory device 20, which are respectively connected to different first channels CH1 and second channels CH2.

[0149] Figure 21 The storage device SD4 is schematically illustrated according to an exemplary embodiment of the present invention.

[0150] refer to Figure 21 The storage device SD4 may include a first path (WAY1) to a fourth path (WAY4), a buffer chip 30, and a controller 50b. The storage device SD4 corresponds to... Figure 18 The above is a modification example of the SD3 storage device, and refers to... Figures 18 to 20 The provided description can also be applied to this example embodiment.

[0151] The buffer chip 30 may include first to third pins Pa, Pb, and Pc. The buffer chip 30 can communicate with the controller 50b via the first pin Pa. For example, the buffer chip 30 can communicate with the controller 50b at 4.8 Gbps. The buffer chip 30 can communicate with the first path WAY1 and the second path WAY2 via the second pin Pb, and with the third path WAY3 and the fourth path WAY4 via the third pin Pc. For example, the buffer chip 30 can communicate with the first path WAY1 and the second path WAY2 at a speed of 2.4 Gbps, and with the third path WAY3 and the fourth path WAY4 at a speed of 2.4 Gbps.

[0152] Furthermore, the buffer chip 30 may also include a serializer / deserializer SERDES 31 and first to third input / output buffers 32, 33, and 34. The first input / output buffer 32 may be disposed between the first pin Pa and the serializer / deserializer SERDES 31. The second input / output buffer 33 may be disposed between the serializer / deserializer SERDES 31 and the second pin Pb. The third input / output buffer 34 may be disposed between the serializer / deserializer SERDES 31 and the third pin Pc. For example, the serializer / deserializer SERDES 31 can convert serial data received from the controller 50b via the first input / output buffer 32 into parallel data. In some example embodiments, the parallel data may include first data and second data. The serializer / deserializer SERDES 31 can send the first data to the first path WAY1 and the second path WAY2 via the second input / output buffer 33, and send the second data to the third path WAY3 and the fourth path WAY4 via the third input / output buffer 34.

[0153] In some example embodiments, each of the first path WAY1 to the fourth path WAY4 can be a non-volatile memory die. In some example embodiments, each of the first path WAY1 to the fourth path WAY4 can be a non-volatile memory chip. In some example embodiments, each of the first path WAY1 to the fourth path WAY4 can be a non-volatile memory package. The first path WAY1 and the second path WAY2 can communicate with the buffer chip 30 through the same channel, and the third path WAY3 and the fourth path WAY4 can communicate with the buffer chip 30 through the same channel.

[0154] In some example embodiments, such as Figure 19As shown, the buffer chip 30 may include a phase detector 310a, a DCC 320, and a delay circuit 330, and performs phase calibration operations on the data gating signals between the first path WAY1 and the second path WAY2, as well as the third path WAY3 and the fourth path WAY4. In some example embodiments, the controller 50b may be as follows: Figure 17 The device includes a phase detector 510, a DCC 520, and a delay circuit 530, and performs phase calibration operations on the data gating signals between the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4.

[0155] Figure 22 A memory device 500 according to an example embodiment of the present invention is shown.

[0156] refer to Figure 22 The memory device 500 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then bonding the upper and lower chips together. For example, the bonding method may include a method of electrically connecting bonding metals formed on the topmost metal layer of the upper chip and bonding metals formed on the topmost metal layer of the lower chip. For example, when the bonding metal can be formed of copper (Cu), the bonding method may be Cu-Cu bonding, and the bonding metal may also be formed of aluminum or tungsten.

[0157] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device 500 may include an external pad bonding region (PA), a word line bonding region (WLBA), and a bit line bonding region (BLBA). The PERI may include a first substrate 310, an interlayer insulating layer 315, a plurality of circuit elements 320a, 320b, and 320c formed on the first substrate 310, first metal layers 330a, 330b, and 330c respectively connected to the plurality of circuit elements 320a, 320b, and 320c, and second metal layers 340a, 340b, and 340c formed on the first metal layers 330a, 330b, and 330c. In some example embodiments, the first metal layers 330a, 330b, and 330c may be formed of tungsten, which has relatively high resistance, and the second metal layers 340a, 340b, and 340c may be formed of copper, which has relatively low resistance.

[0158] Although first metal layers 330a, 330b, and 330c and second metal layers 340a, 340b, and 340c are shown and described in this specification, they are not limited thereto, and one or more metal layers may also be formed on the second metal layers 340a, 340b, and 340c. At least a portion of one or more metal layers formed on the second metal layers 340a, 340b, and 340c may be formed of aluminum or the like, having a lower resistance than the copper used to form the second metal layers 340a, 340b, and 340c.

[0159] An interlayer insulating layer 315 may be disposed on a first substrate 310 and cover a plurality of circuit elements 320a, 320b and 320c, first metal layers 330a, 330b and 330c, and second metal layers 340a, 340b and 340c. The interlayer insulating layer 315 may include an insulating material, such as silicon oxide, silicon nitride, etc.

[0160] Lower bonding metals 371b and 372b can be formed on the second metal layer 340b in the word line bonding region (WLBA). In the WLBA, the lower bonding metals 371b and 372b in the peripheral circuit region (PERI) can be electrically connected to the upper bonding metals 471b and 472b by bonding, and the lower bonding metals 371b and 372b, as well as the upper bonding metals 471b and 472b, can be formed of aluminum, copper, tungsten, etc. Furthermore, the upper bonding metals 471b and 472b in the cell region (CELL) can be referred to as first metal pads, and the lower bonding metals 371b and 372b in the peripheral circuit region (PERI) can be referred to as second metal pads.

[0161] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 410 and a common source line 420. On the second substrate 410, multiple word lines 431 to 438 (e.g., 430) may be stacked in a direction perpendicular to the upper surface of the second substrate 410 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 430, respectively, and the multiple word lines 430 may be disposed between the at least one string select line and the at least one ground select line.

[0162] In the bit line bonding region BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 410 and pass through multiple word lines 430, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 450c and the second metal layer 460c. For example, the first metal layer 450c may be a bit line contact point, and the second metal layer 460c may be a bit line. In an example embodiment, the bit line 460c may extend in a first horizontal direction HD1 parallel to the upper surface of the second substrate 410.

[0163] exist Figure 22 In the example embodiment shown, the region where the channel structure CH, bit line 460c, etc., are provided can be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 460c can be electrically connected to circuit element 320c in the peripheral circuit region PERI that provides the page buffer 493. For example, bit line 460c can be connected to upper bonding metals 471c and 472c in the cell region CELL, and upper bonding metals 471c and 472c can be connected to lower bonding metals 371c and 372c of the circuit element 320c connected to the page buffer 493.

[0164] In the word line bonding area (WLBA), multiple word lines 430 may extend in a second horizontal direction HD2 parallel to the upper surface of the second substrate 410 and may be connected to multiple cell contact plugs 441 to 447 (e.g., 440). The multiple word lines 430 and the multiple cell contact plugs 440 may be connected to each other in a pad provided by at least a portion of the multiple word lines 430 extending at different lengths in the second horizontal direction HD2. A first metal layer 450b and a second metal layer 460b may be sequentially connected to the upper portion of the multiple cell contact plugs 440 connected to the multiple word lines 430. The multiple cell contact plugs 440 may be connected to the circuit region PERI via upper bonding metals 471b and 472b of the cell region CELL in the word line bonding area (WLBA) and lower bonding metals 371b and 372b of the peripheral circuit region PERI.

[0165] Multiple unit contact plugs 440 may be electrically connected to circuit element 320b providing line decoder 494 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 320b providing line decoder 494 may differ from the operating voltage of circuit element 320c providing page buffer 493. For example, the operating voltage of circuit element 320c providing page buffer 493 may be greater than the operating voltage of circuit element 320b providing line decoder 494.

[0166] A common source line contact plug 480 can be disposed in the external pad bonding region PA. The common source line contact plug 480 can be formed of a conductive material (such as a metal, metal compound, polysilicon, etc.) and can be electrically connected to the common source line 420. A first metal layer 450a and a second metal layer 460a can be sequentially stacked on top of the common source line contact plug 480. For example, the region where the common source line contact plug 480, the first metal layer 450a, and the second metal layer 460a are disposed can be defined as the external pad bonding region PA.

[0167] Input / output pads 305 and 405 can be set in the external pad bonding area PA. (See reference) Figure 22 A lower insulating film 301 covering the lower surface of the first substrate 310 may be formed below the first substrate 310, and a first input / output pad 305 may be formed on the lower insulating film 301. The first input / output pad 305 can be connected to at least one of a plurality of circuit elements 320a, 320b, and 320c disposed in the peripheral circuit region PERI via a first input / output contact plug 303, and can be separated from the first substrate 310 via the lower insulating film 301. Furthermore, a side insulating film may be disposed between the first input / output contact plug 303 and the first substrate 310 to electrically separate the first input / output contact plug 303 and the first substrate 310.

[0168] refer to Figure 22 An upper insulating film 401 covering the upper surface of the second substrate 410 may be formed on the second substrate 410, and a second input / output pad 405 may be disposed on the upper insulating layer 401. The second input / output pad 405 may be connected to at least one of a plurality of circuit elements 320a, 320b and 320c disposed in the peripheral circuit region PERI via a second input / output contact plug 403.

[0169] According to some example embodiments, the second substrate 410 and the common source line 420 may not be located in the region where the second input-output contact plug 403 is provided. Furthermore, the second input-output pad 405 may not overlap with the word line 430 in the third direction (Z-axis direction). Reference Figure 22 The second input-output contact plug 403 can be separated from the second substrate 410 in a direction parallel to the upper surface of the second substrate 410, and can pass through the interlayer insulating layer 415 of the cell region to connect to the second input-output pad 405.

[0170] According to some example embodiments, the first input / output pad 305 and the second input / output pad 405 may be selectively formed. For example, the memory device 500 may include only the first input / output pad 305 disposed on the first substrate 310 or the second input / output pad 405 disposed on the second substrate 410. Alternatively, the memory device 500 may include both the first input / output pad 305 and the second input / output pad 405.

[0171] In each of the outer pad bonding region PA and bit line bonding region BLBA, which are respectively included in the cell region CELL and the peripheral circuit region PERI, the metal pattern in the uppermost metal layer can be provided as a virtual pattern, or the uppermost metal layer may not exist.

[0172] In the external pad bonding region PA, the memory device 500 may include a lower metal pattern 373a corresponding to an upper metal pattern 472a formed in the uppermost metal layer of the cell region CELL, and having the same shape as the upper metal pattern 472a of the cell region CELL in the uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 373a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact point. Similarly, in the external pad bonding region PA, an upper metal pattern may be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same shape as the lower metal pattern of the peripheral circuit region PERI.

[0173] Lower bonding metals 371b and 372b can be formed on the second metal layer 340b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 371b and 372b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 471b and 472b of the cell region CELL via Cu-Cu bonding.

[0174] Furthermore, the bit line bonding region BLBA, corresponding to the lower metal pattern 352 formed in the uppermost metal layer of the peripheral circuit region PERI and having an upper metal pattern 492 with the same shape as the lower metal pattern 352 of the peripheral circuit region PERI, can be formed in the uppermost metal layer of the cell region CELL. Contact points may not be formed on the upper metal pattern 492 formed in the uppermost metal layer of the cell region CELL.

[0175] According to the reference Figures 1 to 21 At least one of the memory chips in the described example embodiments can be used as Figure 22The C2C structure implementation shown. For example, Figure 3 The first memory chip 100 and the second memory chip 100a can be implemented in a C2C structure. In some example embodiments, the second memory chip 100a may include a memory cell region (CELL) and a peripheral circuit region (PERI). The memory cell region (CELL) includes a first metal pad 471b or 472b, and the peripheral circuit region (PERI) includes a second metal pad 371b or 372b and is vertically connected to the memory cell region (CELL) through the first metal pad 471b or 472b and the second metal pad 371b or 372b.

[0176] The Peripheral Circuit Region (PERI) may include a delay circuit that generates a second internal clock signal by delaying a clock signal, and a phase detector that detects the phase difference between a first signal and a second signal and generates a third signal having a duty cycle based on the detected phase difference. In some example embodiments, the PERI may also include a DCC that performs a duty cycle correction operation on the second internal clock signal based on the third signal and controls the delay circuit. In some example embodiments, the PERI may also include a control circuit that generates a control signal based on the third signal, and a delay unit that adjusts the delay time relative to the second internal clock signal based on the control signal.

[0177] Figure 23 This is a block diagram illustrating an example of an SSD system 1000 that utilizes a memory device according to an exemplary embodiment of the present invention.

[0178] refer to Figure 23 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 exchanges signals with the host 1100 via a signal connector and receives power via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices MEM 1230, 1240, and 1250. Memory devices 1230, 1240, and 1250 may be vertically stacked NAND flash memory devices. In some example embodiments, the SSD 1200 may use the references above. Figures 1 to 22 The example embodiments described are used for implementation.

[0179] One or more elements disclosed above may include or be implemented in processing circuitry (such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof). More specifically, processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0180] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A non-volatile memory device, comprising: A first memory chip is configured to generate a first signal from a first internal clock signal based on a clock signal received from a controller; and A second memory chip is configured to generate a second signal from a second internal clock signal based on the clock signal, and to perform a phase calibration operation on the second signal based on the phase of the first signal by delaying the second internal clock signal based on the phase difference between the first signal and the second signal. The first memory chip and the second memory chip are connected to the controller via the same channel. The second memory chip further includes: A delay circuit is configured to delay the clock signal to generate the second internal clock signal; A phase detector is configured to detect the phase difference between the first signal and the second signal and generate a third signal having a duty cycle based on the detected phase difference or a logic high level or a logic low level based on the detected phase difference; and The duty cycle correction DCC circuit is configured to perform a second duty cycle correction operation on the second internal clock signal and control the delay circuit based on the third signal.

2. The non-volatile memory device according to claim 1, wherein the second memory chip includes a first input / output pad and a second input / output pad. The first signal is received from the first memory chip to the second memory chip via the first input / output pad, and The second signal is provided to the second input / output pad.

3. The non-volatile memory device according to claim 1 or 2, wherein the second memory chip is a dual-die package or a quad-die package.

4. The non-volatile memory device according to claim 2, wherein the second memory chip further comprises: A first input buffer is connected to the first input / output pad and configured to buffer the first signal; and A second input buffer, connected to the second input / output pad and configured to buffer the second signal, is provided. The phase detector is connected to the output terminals of the first input buffer and the second input buffer.

5. The non-volatile memory device of claim 4, wherein the phase detector is configured to generate the third signal having a logic high level during a logic high period of the first signal or a logic high period of the second signal.

6. The non-volatile memory device according to claim 2, wherein the second memory chip further comprises: The control circuit is configured to generate a control signal based on the third signal; and The delay unit is configured to adjust the delay time relative to the second internal clock signal according to the control signal.

7. The non-volatile memory device according to claim 2, wherein the first memory chip comprises: A delay circuit is configured to delay the clock signal to generate the first internal clock signal; and DCC is configured to perform a first duty cycle correction operation on the first internal clock signal. The first memory chip is configured to output the first signal to the first input / output pad when the first duty cycle correction operation is completed.

8. The non-volatile memory device of claim 1, wherein the clock signal is a read enable signal that is switched at a predetermined frequency during a training period.

9. The non-volatile memory device of claim 1, wherein the clock signal is a data strobe signal that is switched at a predetermined frequency during a training period.

10. The non-volatile memory device of claim 1, wherein the first memory chip is configured to generate the first signal by performing a first duty cycle correction operation on the first internal clock signal, and The second memory chip is configured to generate the second signal by performing a second duty cycle correction operation on the second internal clock signal.

11. The non-volatile memory device of claim 10, wherein the second memory chip is configured to sequentially perform the second duty cycle correction operation and the phase calibration operation in response to a duty cycle correction circuit DCC start command received from the controller.

12. The non-volatile memory device of claim 10, wherein the second memory chip is configured to perform the second duty cycle correction operation in response to a DCC start command received from the controller, and The phase calibration operation is performed in response to a phase calibration command received from the controller.

13. A storage device, comprising: A first memory chip is configured to generate a first signal from a first internal clock signal based on a received first clock signal; The second memory chip is configured to generate a second signal from a second internal clock signal based on a second clock signal; and The controller, connected to the first memory chip via a first channel and to the second memory chip via a second channel, is configured to delay the second clock signal based on the phase difference between the first and second signals to perform a phase calibration operation on the second signal based on the phase of the first signal. The controller includes: A delay circuit is configured to delay a clock signal to generate the second clock signal; A phase detector is configured to generate a phase detection signal based on the phase difference between a first signal received via a first pin and a second signal received via a second pin, the phase detection signal having a duty cycle based on the phase difference or a logic high level or a logic low level based on the phase difference; A duty cycle correction DCC circuit is configured to generate a control signal for controlling the delay circuit by performing a duty cycle correction operation on the phase detection signal.

14. The storage device of claim 13, wherein the first memory chip is configured to generate the first signal by performing a first duty cycle correction operation on the first internal clock signal, and The second memory chip is configured to generate the second signal by performing a second duty cycle correction operation on the second internal clock signal.

15. The storage device of claim 13, wherein the first signal corresponds to a first data strobe signal generated by the first memory chip, and the second signal corresponds to a second data strobe signal generated by the second memory chip, and The controller is configured to delay the second clock signal based on the phase difference between the first data strobe signal and the second data strobe signal.

16. The storage device of claim 13, wherein the second memory chip is a dual-die package or a quad-die package.

17. The storage device of claim 13, wherein the controller comprises: The control circuit is configured to generate a control signal based on the phase detection signal; and The delay unit is configured to adjust the delay time relative to the clock signal according to the control signal.

18. The storage device of claim 13, wherein the first clock signal corresponds to a first read enable signal, and the second clock signal corresponds to a second read enable signal.

19. The storage device of claim 13, further comprising a buffer chip connected between the controller and the first memory chip and the second memory chip, and including a serializer / deserializer.

20. A non-volatile memory device, comprising: A first memory chip is configured to generate a first signal from a first internal clock signal based on a clock signal received from a controller; and A second memory chip is configured to generate a second signal from a second internal clock signal based on the clock signal, and to perform a phase calibration operation on the second signal based on the phase of the first signal by delaying the second internal clock signal based on the phase difference between the first signal and the second signal. The second memory chip includes: The memory cell region includes a first metal pad; and The peripheral circuitry region includes a second metal pad and is vertically connected to the memory cell region via the first and second metal pads. The peripheral circuit region includes: A delay circuit is configured to delay the clock signal to generate the second internal clock signal; A phase detector is configured to detect the phase difference between the first signal and the second signal and generate a third signal having a duty cycle based on the detected phase difference or a logic high level or a logic low level based on the detected phase difference; and The duty cycle correction DCC circuit is configured to perform a duty cycle correction operation on the second internal clock signal and control the delay circuit based on the third signal.

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