Memory and memory read circuit

Abstract

This invention provides a memory and a memory read circuit. The memory includes a memory cell and a reference resistor. The memory cell includes a magnetic storage tunnel junction, which comprises a first free layer, a first tunneling layer, and a first reference layer sequentially stacked along a direction perpendicular to a first plane. The magnetization directions of the first free layer and the first reference layer are both perpendicular to the first plane. The reference resistor includes a reference magnetic tunnel junction, which comprises a second free layer, a second tunneling layer, and a second reference layer sequentially stacked along a direction perpendicular to the first plane. The magnetization direction of the second free layer is parallel to the first plane, and the magnetization direction of the second reference layer is perpendicular to the first plane. In the above-mentioned reference resistor, the easy magnetization direction of the free layer is always within the first plane, and the magnetization direction of the reference layer is always perpendicular to the first plane. The stable state of the reference magnetic tunnel junction corresponds to the same resistance state, thus preventing the reference magnetic tunnel junction from being changed during the read process.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically, to a memory and a memory read circuit. Background Technology

[0002] MTJ devices based on the magnetic tunneling magnetoresistance (TMR) effect consist of two magnetic layers and a dielectric layer between them. The first magnetic layer has a fixed magnetization orientation (reference layer), while the second magnetic layer's magnetization orientation can be changed by a magnetic field or current (free layer), allowing the two magnetic layers to be in parallel or antiparallel states, corresponding to high-resistance and low-resistance states, which can be used to store information.

[0003] Magnetic random access memory (STT-MRAM) utilizes electric current to change the state of the MTJ (Medium-Touch Layer), a promising new type of memory. Besides its advantages of simple circuit design, fast read / write speeds, and unlimited erase / write cycles, its biggest advantage over traditional memories like DRAM is its non-volatility (data is not lost when power is off). The magnetic direction of the free layer (magnetic recording layer) can be controlled by an external field (H) or a write current (I). When the magnetization direction of the free layer is parallel or antiparallel to the reference layer, it corresponds to data 0 or 1, respectively.

[0004] In existing magnetic random access memory (MRAM) technology, MTJ storage bits and fixed resistors are typically electrically connected to the read amplifier respectively. However, under different operating conditions, the high resistance state (R) of the MTJ storage cell... AP ), low resistance state (R) P Furthermore, the resistance value of the fixed resistor changes with temperature, which can easily lead to a smaller read window for the MRAM at high temperatures, thereby increasing the data read error rate. Summary of the Invention

[0005] The main objective of this invention is to provide a memory and a memory read circuit to solve the problem that the data read error rate of the memory tends to increase with increasing temperature in the prior art.

[0006] To achieve the above objectives, according to one aspect of the present invention, a memory is provided, comprising a memory cell and a reference resistor, wherein the memory cell includes a magnetic storage tunnel junction, the magnetic storage tunnel junction comprising a first free layer, a first tunneling layer and a first reference layer sequentially stacked along a direction perpendicular to a first plane, the magnetization directions of the first free layer and the first reference layer being perpendicular to the first plane; the reference resistor includes a reference magnetic tunnel junction, the reference magnetic tunnel junction comprising a second free layer, a second tunneling layer and a second reference layer sequentially stacked along a direction perpendicular to the first plane, the magnetization direction of the second free layer being parallel to the first plane, and the magnetization direction of the second reference layer being perpendicular to the first plane.

[0007] Furthermore, the diameter of the magnetic storage tunnel junction is smaller than the diameter of the reference magnetic tunnel junction.

[0008] Furthermore, the diameter of the magnetic storage tunnel junction is less than 1.2 times the thickness of the first free layer, and the diameter of the reference magnetic tunnel junction is greater than 1.2 times the thickness of the second free layer.

[0009] Furthermore, the reference resistor includes N reference magnetic tunnel junctions, where N≥2. Each reference magnetic tunnel junction is connected in series or in parallel, and the equivalent resistance of the reference resistor is located between the high-resistivity resistance value and the low-resistivity resistance value of the magnetic storage tunnel junction.

[0010] Furthermore, each reference magnetic tunnel junction has the same diameter.

[0011] Furthermore, the diameters of each reference magnetic tunnel junction are different.

[0012] Furthermore, the reference resistor also includes a decoder and switching devices. The switching devices are connected one-to-one with the reference magnetic tunnel junction. The decoder is used to control the switching of each switching device to adjust the resistance value of the reference resistor.

[0013] Furthermore, the reference resistor includes a base resistor and multiple unit resistors, both of which contain a reference magnetic tunnel junction.

[0014] Furthermore, let K be the diameter ratio of the reference magnetic tunnel junction to the magnetic storage tunnel junction, and let N = K be the number of reference resistors. 2 / [(1-P 2 (1+P) 2 )], where P is the effective spin polarization.

[0015] According to another aspect of the present invention, a memory read circuit is provided, comprising a memory and a read amplifier, characterized in that the memory is the aforementioned memory, and the input terminal of the read amplifier is electrically connected to a memory cell in the memory and a reference resistor in the memory, respectively.

[0016] The present invention provides a memory comprising parallel storage cells and a reference resistor. Each storage cell includes a magnetic storage tunnel junction (MDTJ). A first free layer and a first reference layer in the MDTJ have parallel or antiparallel perpendicular magnetization directions. The reference resistor includes a reference magnetic tunnel junction (MTTJ). The magnetization direction of a second free layer in the MTTJ is parallel, and the magnetization direction of the second reference layer remains perpendicular. Because the easy magnetization direction of the free layer in the reference resistor is always within a first plane, and the magnetization direction of the reference layer is always perpendicular to the first plane, the stable state of the reference magnetic tunnel junction corresponds to the same resistance state. Therefore, the situation where the reference magnetic tunnel junction's state is changed during reading, as is common in the prior art, is avoided. Furthermore, since the direction of temperature change of the reference resistance of the reference magnetic tunnel junction is consistent with the direction of temperature change of the resistance of the magnetic storage tunnel junction, the reference resistor exhibits a temperature-adaptive effect, thereby preventing an increase in data read error rate due to a smaller read window at high temperatures. Attached Figure Description

[0017] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0018] Figure 1 A schematic diagram of the structure of a memory provided according to an embodiment of the present invention is shown;

[0019] Figure 2 It shows Figure 1 The diagram shows the structure of a magnetic storage tunnel junction in a memory.

[0020] Figure 3 It shows Figure 1 The diagram shows a schematic representation of the reference magnetic tunnel junction in the memory.

[0021] Figure 4 It shows Figure 1 The diagram shows a partial circuit diagram of the reference resistor in the memory.

[0022] The above figures include the following reference numerals:

[0023] 10. Read amplifier; 20. Magnetic storage tunnel junction; 210. First free layer; 220. First tunneling layer; 230. First reference layer; 30. Reference magnetic tunnel junction; 310. Second free layer; 320. Second tunneling layer; 330. Second reference layer; 301. Base resistor; 302. Unit resistor; 40. Switching device. Detailed Implementation

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] As described in the background section, under different usage environments, the high resistance state (R) of MTJ memory cells... AP ), low resistance state (R) P Furthermore, the resistance value of the fixed resistor changes with temperature, which can easily lead to a smaller read window for the MRAM at high temperatures, thereby increasing the data read error rate.

[0028] In order to solve the above-mentioned technical problems, the applicant of this invention provides a memory, such as... Figure 1 As shown in region A, the device includes a memory cell and a reference resistor. The memory cell includes a magnetic storage tunnel junction 20, which comprises a first free layer 210, a first tunneling layer 220, and a first reference layer 230 stacked sequentially along a direction perpendicular to the first plane. The magnetization directions of the first free layer 210 and the first reference layer 230 are both perpendicular to the first plane. The reference resistor includes a reference magnetic tunnel junction 30, which comprises a second free layer 310, a second tunneling layer 320, and a second reference layer 330 stacked sequentially along a direction perpendicular to the first plane. The magnetization direction of the second free layer 310 is parallel to the first plane, and the magnetization direction of the second reference layer 330 is perpendicular to the first plane.

[0029] Since the easy magnetization direction of the free layer in the aforementioned reference resistor is always within the first plane, and the magnetization direction of the reference layer is always perpendicular to the first plane, the stable state of the reference magnetic tunnel junction corresponds to the same resistance state. Therefore, the situation where the reference magnetic tunnel junction is changed during the reading process, as is the case in the prior art, does not exist. Furthermore, since the direction of the change of the reference resistance of the aforementioned reference magnetic tunnel junction with temperature is consistent with the direction of the change of the resistance of the magnetic storage tunnel junction with temperature, the reference resistor has a temperature adaptive effect, thereby avoiding the increase in data read error rate caused by the smaller read window at high temperatures.

[0030] Furthermore, the memory and its reference resistor of the present invention can be formed in the same thin film growth process as the magnetic storage tunnel junction simply by replacing the fixed resistor in the prior art with the reference resistor. Therefore, no additional process cost is required, nor is it necessary to change the existing magnetic tunnel junction fabrication process (i.e., thin film deposition, photolithography, etching, chemical mechanical polishing, etc.).

[0031] The memory of the present invention may further include a first control transistor and a second control transistor. The first control transistor is electrically connected to a magnetic storage tunnel junction 20, and the second control transistor is electrically connected to a reference magnetic tunnel junction 30. The first control transistor and the second control transistor are electrically connected to the word line (WL) and the source line (SL), respectively.

[0032] In the memory of the present invention, the diameter of the magnetic storage tunnel junction 20 is smaller than the diameter of the reference magnetic tunnel junction 30. Utilizing shape anisotropy, when the height and diameter of the first free layer are comparable, the demagnetizing field of the magnetic storage tunnel junction in the memory cell is very weak or along the direction perpendicular to the thin film. Combined with the interface-perpendicular magnetic anisotropy, the magnetization direction of the first free layer is perpendicular to the thin film plane. Based on the same magnetic material structure, the dimensions of the reference magnetic tunnel junction are designed such that the corresponding second free layer demagnetizing field is along the in-plane direction of the thin film and is greater than the interface-perpendicular anisotropy. Finally, the magnetization direction of the reference magnetic tunnel junction is along the in-plane direction of the thin film.

[0033] In the memory of the present invention, the storage cell is based on an ultra-small diameter magnetic storage cell, and the size of the magnetic storage tunnel junction 20 can be miniaturized to about 10 nm. A perpendicularly magnetized magnetic tunnel junction can be obtained using shape anisotropy. Preferably, the diameter CD1 of the magnetic storage tunnel junction 20 is less than 1.2 times the thickness t1 of the first free layer 210. Figure 2 As shown.

[0034] In the memory described above in this invention, shape anisotropy can also be used to give the second free layer 310 in the magnetic reference tunnel junction a magnetization direction in the horizontal plane, while the reference layer is magnetized vertically. Preferably, the diameter CD2 of the reference magnetic tunnel junction 30 is greater than 1.2 times the thickness t2 of the second free layer 310, such as... Figure 3 As shown.

[0035] In the aforementioned magnetic reference tunnel junction, the magnetization directions of the second free layer 310 and the second reference layer 330 are orthogonal. Assuming TMR = 150%, then P ≈ 0.654, where P is the effective spin polarization. The high and low resistance states of the magnetic reference tunnel junction satisfy: R ap =1.75R0, R p =0.7R0; The resistance of a single reference tunnel junction satisfies: R ap and R p These represent the high-resistivity resistance value and the low-resistivity resistance value corresponding to the magnetic reference tunnel junction, respectively.

[0036] In a preferred embodiment, the reference resistor comprises N reference magnetic tunnel junctions 30, where N ≥ 2, and the reference magnetic tunnel junctions 30 are connected in series or in parallel. By using a reference resistor with multiple reference magnetic tunnel junctions 30 connected in series or in parallel, the equivalent resistance of the reference resistor can be positioned between the high-resistance state resistance value and the low-resistance state resistance value of the magnetic storage tunnel junction by reasonably designing the diameters of the magnetic storage tunnel junction 20 and the reference magnetic tunnel junction 30, and by reasonably selecting the number of reference magnetic tunnel junctions 30, so that the total resistance R of the reference resistor is between these values. ref Approaching (R) ap +R p This ensures that during read operations, the read windows corresponding to the AP and P states of the magnetic tunnel junction are large enough, preventing an increase in the read error rate of one state when the read window for another state is sufficient due to insufficient read windows.

[0037] In the preferred embodiment described above, to facilitate adjustment of the total resistance R of the reference resistor ref This allows it to get closer to (R) ap +R p More preferably, each reference magnetic tunnel junction 30 has the same diameter. However, it is not limited to the above-mentioned preferred embodiment; for example, the diameters of each reference magnetic tunnel junction 30 may also be different.

[0038] To achieve the total resistance R of the reference resistor ref For adjustment, the aforementioned reference resistor may also include a decoder and switching devices 40. Each switching device 40 is connected to a corresponding reference magnetic tunnel junction 30. The decoder controls the switching of each switching device 40 to adjust the resistance value of the reference resistor. By turning on different switching devices 40 (such as MOSFETs), different R values ​​can be achieved for the reference resistor.ref value.

[0039] When the aforementioned magnetic storage tunnel junction 20 achieves perpendicular magnetization through shape anisotropy, and the aforementioned reference magnetic tunnel junction 30 achieves in-plane magnetization of the second free layer 310 through shape anisotropy, the magnetic storage tunnel junction 20 and the reference magnetic tunnel junction 30 can be formed in the same thin film growth process, thus achieving the same thickness. At this time, to ensure the total resistance R of the reference resistor... ref Able to approach (R) ap +R p ) / 2, which can make the diameter of the magnetic storage tunnel junction 20 smaller than the diameter of the reference magnetic tunnel junction 30.

[0040] The design concept of the memory with N reference magnetic tunnel junctions 30 will be illustrated below with an example.

[0041] Assuming that the magnetic storage tunnel junction 20 and the reference magnetic tunnel junction 30 have the same thickness, the diameter of the magnetic storage tunnel junction 20 is 10 nm, the diameter of the reference magnetic tunnel junction 30 is 40 nm, the TMR does not change with size, and the TMR = 150%.

[0042] The low-resistivity resistance value R of the magnetic storage tunnel junction 20 p1 and high resistance value R ap1 They respectively satisfy:

[0043] R p1 =RA / (π×10nm×10nm / 4);

[0044] R ap1 = (TMR+1)×R p1 .

[0045] The resistance R0 of a single reference magnetic tunnel junction 30 and its corresponding low-resistance state resistance R p2 High resistance value R ap2 They respectively satisfy:

[0046] R p2 =RA / (π×40nm×40nm / 4)=R p1 / 16;

[0047] R ap2 ==(TMR+1)×R p2 =R ap1 / 16;

[0048]

[0049] To make the total resistance R of the reference resistor ref The low-resistivity R value of the magnetic storage tunnel junction 20p1 and high resistance value R ap1 Near the midpoint of (R) ap1 +R p1 For a magnetic storage tunnel junction 20 with a diameter of 10 nm, the total resistance R of its reference resistor is 2 / 2. ref satisfy:

[0050] R ref =(R p1 +R ap1 ) / 2≈20×R0.

[0051] Based on the above derivation, it can be seen that connecting 20 reference magnetic tunnel junctions with a diameter of 40 nm in series will make the total resistance R of the reference resistor... ref Located in magnetic storage tunnel junction 20 (R ap1 +R p1 ) / 2 around.

[0052] Following the above design concept, the diameter ratio of the reference magnetic tunnel junction 30 to the magnetic storage tunnel junction 20 can be defined as K. In this case, the number of reference resistors and reference magnetic tunnel junctions 30 satisfies: N = K. 2 / [(1-P 2 (1+P) 2 )], where P is the effective spin polarization.

[0053] More preferably, the reference resistor includes a base resistor 301 and multiple unit resistors 302, and both the base resistor and the unit resistors contain the reference magnetic tunnel junction; preferably, both the base resistor 301 and the unit resistors 302 are reference magnetic tunnel junctions 30, and the resistance value of the base resistor 301 is greater than the resistance value of the unit resistors 302. By using the aforementioned unit resistors 302 with smaller resistance values, the total resistance R of the reference resistor can be achieved. ref Fine-tuning.

[0054] In one embodiment, the unit resistors 302 are connected in series, and the base resistor 301 is connected to the aforementioned unit resistors 302 connected in series, such as... Figure 4 As shown. In another embodiment, the unit resistors 302 are connected in parallel, and the base resistor 301 is connected to the aforementioned unit resistors 302 connected in parallel.

[0055] According to another aspect of the present invention, a memory read circuit is also provided, such as Figure 1 As shown, it includes the aforementioned memory and read amplifier 10, and the input terminal of the read amplifier 10 is electrically connected to the memory cell and the reference resistor in the memory, respectively.

[0056] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0057] 1. Because the magnetization directions of the free layers in the above-mentioned storage cells and reference resistors are different, the increase in data read error rate caused by the read voltage and write voltage being in the same direction is avoided;

[0058] 2. Since the reference resistance of the aforementioned magnetic tunnel junction changes in the same direction as the resistance of the magnetic storage tunnel junction changes in the same direction as the temperature, the reference resistance has a temperature adaptive effect, thereby avoiding the increase in data read error rate caused by the smaller read window at high temperatures.

[0059] 3. The memory and its reference resistor described above in this invention do not require additional process costs, nor do they require changes to the existing magnetic tunnel junction fabrication process.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memory, characterized in that, Includes memory cells and a reference resistor, wherein, The storage unit includes a magnetic storage tunnel junction, which comprises a first free layer, a first tunneling layer, and a first reference layer sequentially stacked along a direction perpendicular to the first plane. The magnetization directions of the first free layer and the first reference layer are both perpendicular to the first plane. The reference resistor includes a reference magnetic tunnel junction, which includes a second free layer, a second tunneling layer, and a second reference layer sequentially stacked along a direction perpendicular to the first plane. The magnetization direction of the second free layer is parallel to the first plane, and the magnetization direction of the second reference layer is perpendicular to the first plane. The reference resistor includes N reference magnetic tunnel junctions, where N≥2. Each reference magnetic tunnel junction is connected in series or in parallel. The equivalent resistance of the reference resistor is located between the high-resistivity resistance value and the low-resistivity resistance value of the magnetic storage tunnel junction. The reference resistor includes a base resistor and multiple unit resistors, and both the base resistor and the unit resistors contain the reference magnetic tunnel junction. The diameter ratio of the reference magnetic tunnel junction to the magnetic storage tunnel junction is defined as K, and the number of reference resistors satisfies: N=K 2 / [(1-P 2 (1+P) 2 )], where P is the effective spin polarization.

2. The memory according to claim 1, characterized in that, The diameter of the magnetic storage tunnel junction is smaller than the diameter of the reference magnetic tunnel junction.

3. The memory according to claim 1, characterized in that, The diameter of the magnetic storage tunnel junction is less than 1.2 times the thickness of the first free layer, and the diameter of the reference magnetic tunnel junction is greater than 1.2 times the thickness of the second free layer.

4. The memory according to claim 1, characterized in that, Each of the aforementioned reference magnetic tunnel junctions has the same diameter.

5. The memory according to claim 1, characterized in that, The diameters of the various reference magnetic tunnel junctions are all different.

6. The memory according to claim 1, characterized in that, The reference resistor also includes a decoder and a switching device. The switching device is connected to the reference magnetic tunnel junction in a one-to-one correspondence. The decoder is used to control the switching of each of the switching devices to adjust the resistance value of the reference resistor.

7. A memory read circuit, comprising a memory and a read amplifier, characterized in that, The memory is the memory according to any one of claims 1 to 6, and the input terminal of the read amplifier is electrically connected to the memory cell and the reference resistor in the memory, respectively.

Images