Semiconductor device

Abstract

The present disclosure relates to semiconductor devices. A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy a desired characteristic is provided. The semiconductor device includes a memory cell, a bit line pair coupled to the memory cell, and a designation circuit for designating a bit line from the bit line pair, and a voltage is changed to a power supply voltage and a ground voltage according to data of the memory cell in a read mode. In the semiconductor device, a wiring capacitance is coupled to the bit line designated by the designation circuit, and a voltage of the designated bit line is set to a voltage between the power supply voltage and the ground voltage in a test mode.

Description

[0001] Cross-reference to related applications

[0002] The disclosure of Japanese Patent Application No. 2020-128971, filed on July 30, 2020, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Background Technology

[0003] This invention relates to a semiconductor device, and more particularly to a semiconductor device including a static random access memory.

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. H3-154289.

[0006] As a semiconductor device, Patent Document 1 discloses a semiconductor memory device. Patent Document 1 discloses a semiconductor memory device capable of testing the operating margin of memory cells. More precisely, Patent Document 1 discloses a technique for detecting memory cells with small operating margins, etc., by coupling a fixed capacitor or by testing, wherein in test mode, charge is pre-accumulated during reading to enable the device to detect potential differences appearing between bit lines based on charge redistribution. Summary of the Invention

[0007] In SRAM, to read data from a memory cell, for example, in an initial state, a precharge is performed on the bit line pair (the paired bit lines) coupled to the memory cell. When a memory cell is selected, a read current flows through the memory cell according to the data stored in the memory cell, and then the potential of one bit line in the bit line pair can be lowered. At this time, the other bit line is regarded as a reference bit line, and the potential difference between the one bit line and the reference bit line is amplified to read the data from the selected memory cell.

[0008] To detect memory cells with small operating margins (in other words, memory cells that do not meet desired characteristics), according to the technique disclosed in Patent Document 1, a fixed capacitor for testing is coupled to a reference bit line. In this way, charge redistribution occurs between the fixed capacitor for testing and the capacitance of the reference bit line, allowing the potential of the reference bit line to be lowered. As a result, the potential difference between the bit lines of the bit line pair is reduced when one of the bit lines' potentials decreases, potentially reducing the ability to read data from the selected memory cell. In memory cells that do not meet desired characteristics, because the read current during selection is smaller, the time period during which the potential difference between the bit lines of the bit line pair reaches a predetermined value is longer, making it possible to detect memory cells with small operating margins.

[0009] In this way, according to the inventors' research based on the present invention, when the technology disclosed in Patent Document 1 is applied to SRAM, it is also possible to detect memory cells with small operating margins.

[0010] However, according to the inventors’ research according to the present invention, there are problems in the technology disclosed in Patent Document 1, for example, in SRAM (compiled SRAM) configured by using, for example, compiled SRAM technology.

[0011] In other words, in the technology according to Patent Document 1, since a fixed capacitor is coupled to the bit line, it is effective in DRAM and the like because the potential of the bit line, which is reduced by charge redistribution, can be made approximately constant, as long as the length of the bit line is always constant.

[0012] Conversely, in compiled SRAM technology, for example, the lengths of bit lines and / or word lines are variable. Therefore, when the same fixed capacitor is coupled between multiple SRAMs with different bit line lengths, for example, excessive charge may accumulate in the fixed capacitor in some SRAMs, while conversely, the desired amount of charge may not accumulate. As a result, it is conceivable that, according to charge redistribution, the potential of the bit line decreases significantly and conversely, does not decrease by the desired amount. In this way, for example, even if a memory cell meets the desired characteristics, it may be detected as a memory cell with a small operating margin.

[0013] The following describes a semiconductor device according to an embodiment.

[0014] The semiconductor device includes memory cells, bit line pairs, and designated circuitry for specifying bit lines from the bit line pairs. In read mode, the bit line pairs change voltage to a first voltage and a second voltage different from the first voltage based on data from the memory cells. Here, in test mode, a capacitive element is coupled to the bit line specified by the designated circuitry to set the voltage of the specified bit line to a potential between the first voltage and the second voltage.

[0015] Other issues and novel features will become clear from the description in this specification and the accompanying drawings.

[0016] According to an embodiment, a semiconductor device including SRAM can be provided, which is capable of detecting defective memory cells that do not have the desired characteristics. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating the configuration of the semiconductor device according to the first embodiment;

[0018] Figure 2 This is a diagram illustrating an example of the specifications of an SRAM according to the first embodiment;

[0019] Figure 3 This is a block diagram illustrating the configuration of the SRAM according to the first embodiment;

[0020] Figure 4 This is a circuit diagram showing the configuration of the cell memory array, cell column selection circuit, and cell I / O control circuit according to the first embodiment;

[0021] Figure 5 This is a diagram illustrating the operation of the intermediate potential generation circuit of the first embodiment;

[0022] Figure 6 This is a diagram showing the configuration of the control circuit according to the first embodiment;

[0023] Figure 7 This is a diagram showing the configuration of the control circuit according to the first embodiment;

[0024] Figure 8 This is a diagram illustrating the configuration of the column selection circuit according to the first embodiment;

[0025] Figure 9 This is a waveform diagram illustrating the operation of the SRAM according to the first embodiment;

[0026] Figure 10 This is a waveform diagram illustrating the operation of the SRAM according to the first embodiment;

[0027] Figure 11 This is a waveform diagram illustrating the operation of the SRAM according to the first embodiment;

[0028] Figure 12 This is a circuit diagram showing the configuration of the memory cells according to the first embodiment;

[0029] Figure 13 This is a waveform diagram showing the operation of the memory cell in test mode;

[0030] Figure 14 This is a waveform diagram illustrating the operation of the DFT control block according to the first embodiment;

[0031] Figure 15 This is a circuit diagram illustrating the configuration of the cell memory array, cell column selection circuit, and cell I / O control circuit according to the second embodiment; and

[0032] Figure 16 This is a diagram illustrating the operation of the intermediate potential generation circuit of the second embodiment. Detailed Implementation

[0033] Hereinafter, various embodiments of the invention will be described with reference to the accompanying drawings. Note that this disclosure is merely illustrative and may, of course, include any modifications as desired while maintaining the scope of the invention readily apparent to those skilled in the art. Furthermore, for clarity of description, although widths, numbers, shapes, etc., may be described schematically with respect to actual embodiments in the drawings, this is merely an example and does not limit the interpretation of the invention.

[0034] Furthermore, in this specification and the corresponding drawings, the same components as described in the above drawings are indicated by the same reference numerals, and their detailed descriptions may be appropriately omitted.

[0035] The following describes an embodiment of a semiconductor device having multiple SRAMs. Here, the multiple SRAMs are configured according to compiled SRAM technology.

[0036] First Embodiment

[0037] Configuration of semiconductor devices

[0038] Figure 1 This is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment. Figure 1 In this context, the number "1" represents a semiconductor device. Although there are no specific restrictions, according to known semiconductor device manufacturing techniques, multiple circuit blocks are formed within a semiconductor chip to constitute a semiconductor device 1. While in Figure 1 Multiple circuit blocks are formed in the semiconductor device 1, but in order not to complicate the drawings, only some of the circuit blocks required for description are shown.

[0039] exist Figure 1 In the diagram, as circuit blocks included in the semiconductor device 1, processor (CPU) block 2, image processing block 3, external interface (I / F) block 4, system control block 5, and test (DFT: design for test) control block (DFT control circuit) 6 are shown.

[0040] CPU Block 2 includes CPU Core 2C and SRAMs 2S1 and 2S2. When CPU Core 2C executes, for example, a program, it uses SRAM2S1 as the main (L1) cache and SRAM 2S2 as the secondary (L2) cache. SRAM2S1, used as the main cache, is a high-speed SRAM, although its storage capacity is small. Conversely, SRAM 2S2, used as the secondary cache, is a medium-speed SRAM with a medium storage capacity. That is, compared to SRAM 2S1, SRAM 2S2 has a larger storage capacity and a slower speed.

[0041] Image processing block 3 is a functional block for performing image processing and includes SRAM 3S1 used during processing. In the same manner as image processing block 3, system control block 5 for controlling the system also includes SRAM 4S1 and SRAM 5S1 used during processing. The system consists of an external interface (I / O) block that provides an interface between the semiconductor device 1 and its external and internal components, as well as the semiconductor device 1.

[0042] DFT control block 6 is a test control block configured using test facilitation technology. DFT control block 6 outputs signals and data for testing SRAMs 2S1 to 5S1, which will be described below with reference to the accompanying drawings.

[0043] SRAMs 2S1 to 5S1 are compiled SRAMs. That is, SRAMs 2S1 to 5S1 are configured to be best suited for the processing performed by the corresponding circuit blocks (CPU block 2, image processing block 3, external I / F block 4, and system control block 5) according to compiled SRAM technology. Although there are no limitations, Figure 2 An example of the specifications for SRAM 2S1 to 5S1 is shown. When describing the configuration of compile memory, conventionally, "word" represents the number of memory cells coupled to one I / O, "bit" represents the number of I / Os, and cpb represents the number of bit line pairs coupled to one I / O. The number of word lines is determined by dividing "word" by cpb, and the number of bit line pairs is determined by multiplying "bit" by cpb. Figure 2 As shown, for example, SRAM 2S1 is configured as 512 words × 64 bits with an operating speed of 1 GHz, and SRAM 2S2 is configured as 4096 words × 32 bits with an operating speed of 500 MHz.

[0044] Each of SRAMs 2S1 to 5S1 comprises a memory array consisting of multiple word lines arranged in each row and multiple bit line pairs arranged in each column. For the purposes of the following description with reference to the accompanying drawings, SRAMs 2S1 and 2S2 are illustrated to summarize examples of memory arrays. SRAM 2S1 consists of 64 I / O circuits with 512 memory cells, the memory array having 128 word lines and 256 bit line pairs, with each bit line pair coupled to 128 memory cells. In contrast, SRAM 2S2 consists of 32 I / O circuits, comprising 4096 memory cells, the memory array including 512 word lines and 256 bit line pairs, with each bit line pair coupled to 512 memory cells. Due to the different number of coupled memory cells, the lengths of the bit line pairs and word lines differ in SRAM 2S1 and SRAM 2S2. In this way, by using compiled SRAM technology, SRAM is installed to meet the needs of the portion to be used.

[0045] SRAM configuration

[0046] The configurations of SRAMs 2S1 to 5S1 will now be described with reference to the accompanying drawings. As can be understood from the above description, although the lengths of the bit line pairs and word lines differ in SRAMs 2S1 to 5S1, their basic configurations are the same. Therefore, one SRAM (e.g., SRAM 2S1) will be described below as an example.

[0047] Figure 3 This is a block diagram illustrating the configuration of the SRAM according to the first embodiment.

[0048] The SRAM includes a memory array 10, a row selection circuit 11, a control circuit 12, a column selection circuit 13, and an input / output (IO) control circuit 14. Figure 3 This illustrates that multiple input data items or multiple output data items are input to semiconductor device 1 substantially simultaneously. Figure 1 Other circuit blocks in ) and output from them.

[0049] From the semiconductor device 1 ( Figure 1 Other circuit blocks in the SRAM provide the SRAM with a clock signal CLK, address signals AD[3:0], enable signal CEN, write enable signal WEN, and test enable signal TE. The clock signal CLK is a synchronous clock, and the SRAM operates synchronously with the clock signal CLK. In addition, the SRAM is set to the enabled state by the enable signal CEN, and when the SRAM is set to write mode by the write enable signal WEN, input data D[0] to D[2] are provided from other circuit blocks to perform the write operation. On the other hand, when the SRAM is set to read mode by the write enable signal WEN, data is read from the SRAM and provided to other circuit blocks as output data Q[0] to Q[2].

[0050] The control circuit 12 is provided with a clock signal CLK, address signals AD[3:0], enable signal CEN, write enable signal WEN, and test enable signal TE, and the control circuit 12 generates multiple signals based on these signals. Note that the symbol [3:0] in the address signal AD indicates that the address signal AD consists of four bits (address signals AD[0] to AD[3]).

[0051] In the signals generated by control circuit 12, column address signals RA[0] to RA[3] and control signals RGA[0] and RGA[1] are provided to column selection circuit 11. Furthermore, column address signals CA[0] to CA[1] generated by control signal 12 are provided to column selection circuit 13. Additionally, write control signal WTE, read control signal RDE, sense amplifier control circuit signal SAE, boost control signal BOOST, and bias mode control signal BIASMODE are generated by control circuit 12 and provided to IO control circuit 14. An example of the configuration of control circuit 12 will be described in detail later with reference to the accompanying drawings, and therefore the detailed description is omitted here.

[0052] Column select circuit 11 is coupled to word lines WL[0] to WL[7] arranged in memory array 10. Although an example of column select circuit 11 will be described with reference to the accompanying drawings, column select circuit 11 selects the word line specified by address signals RA[0] to RA[3] from word lines WL[0] to WL[7] arranged in memory array 10 based on column address signals RA[0] to RA[3] and control signals RGA[0] to RGA[1].

[0053] The column selection circuit 13 is coupled to a plurality of bit lines arranged in the memory array 10 and selects the bit line pairs specified by the column address signals CA[0] to CA[1].

[0054] The bit line pairs selected by column select circuit 13 are coupled to IO control circuit 14. IO control circuit 14 is provided with write control signal WTE, read control signal RDE, sense amplifier control circuit signal SAE, boost control signal BOOST, and bias mode control signal BIASMODE, and IO control circuit 14 inputs input data D[0] to D[2] and outputs output data Q[0] to Q[2].

[0055] The memory array 10 includes a plurality of memory cells MC arranged in a matrix, a plurality of word lines WL[0] to WL[7] arranged in each row of the matrix, and a plurality of bit line pairs BL[0], / BL[0] to BL[1], / BL[1] arranged in each column of the matrix.

[0056] The memory cell MC includes two inverters cross-coupled to form a latch circuit, and transfer transistors NTT1 and NTT2, which are coupled between the input / output cell and the data input / output terminals / ni and ni of the latch circuit. In the first embodiment, a field-effect transistor (MOSFET) is used as the transistor. The gate electrodes of the transfer transistors NTT1 and NTT2 are coupled to word lines arranged in the row where the memory cell is disposed, and the data input / output terminals / ni and ni of the memory cell are coupled to bit line pairs arranged in the column where the memory cell is disposed.

[0057] In a first embodiment, wiring pairs TL and / or TL are arranged in the memory array 10. The wiring pairs TL and / TL are arranged parallel to the bit line pairs BL and / BL and extend in the same direction as the bit line pairs BL and / BL in the memory array 10. Furthermore, the length of the wiring pairs TL and / TL is substantially the same as the length of the bit line pairs BL and / BL. Additionally, a terminal portion of the wiring pairs TL and / TL is coupled to the I / O control circuitry 14. In the first embodiment, the wiring pairs TL and / TL are formed on the semiconductor chip via an insulator, and the insulator is also provided via the wiring TL and / TL, such that the wiring (the other wiring) TL and the wiring (one of the wirings) are electrically isolated. Although not particularly limited, the wiring pairs TL and / TL are composed of metal wiring formed on the semiconductor chip via an insulator.

[0058] In the first embodiment, the memory array 10, the column selection circuit 13, and the I / O control circuit 14 are composed of a plurality of cell memory arrays, a plurality of cell column selection circuits, and a plurality of cell I / O control circuits corresponding to the input data and output data. Figure 3 In the example shown, the memory array 10 consists of three cell memory arrays 10[0] to 10[2], the column selection circuit 13 consists of three cell selection circuits 13[0] to 13[2], and the IO control circuit 14 consists of three cell IO control circuits 14[0] to 14[2]. Furthermore, the aforementioned wiring pairs TL and / TL are arranged in each cell memory array and coupled to the corresponding cell IO control circuit.

[0059] Since the configurations of each of the cell memory array, cell column selection circuit and cell I / O control circuit are identical, the cell memory array 10[0], cell column selection circuit 13[0] and cell I / O control circuit 14[0] corresponding to the input data D[0] and output data Q[0] will be described below as representative elements.

[0060] Circuit configuration

[0061] Next, the configuration of the cell memory array 10[0], the cell column selection circuit 13[0], and the cell I / O control circuit 14[0] will be described with reference to the accompanying drawings. Figure 4 This is a circuit diagram showing the configuration of the cell memory array, cell column selection circuit, and cell I / O control circuit according to the first embodiment.

[0062] Cell memory array and cell column selection circuit

[0063] exist Figure 3 In the diagram, WL[0] to WL[7] are shown as word lines. Conversely, a word line WL[n] is shown in... Figure 4 The image is shown as an example. Additionally, although the latching circuit inside the memory cell MC... Figure 3 The example uses a cross-connected inverter, but... Figure 4 The diagram shows P-channel MOSFETs (hereinafter referred to as P-type FETs) MP1 and MP2, and N-channel MOSFETs (hereinafter referred to as N-type FETs) MN1 and MN2, which constitute an inverter. In other words, an inverter is constructed by connecting the P-type FET MP1 (MP2) and the N-type FET MN1 (MN2) in series between the power supply voltage (first voltage) Vdd and the ground voltage (second voltage) Vss.

[0064] To select a memory cell MC, the word line WL[n] is high (power supply voltage Vdd), and to deselect a memory cell MC, the word line WL[n] is low (ground voltage Vss). Similarly, to select a bit line pair, the column address signal CA[0] or CA[1] is high, and to deselect a bit line pair, the column address signal CA[0] or / and CA[1] are low.

[0065] The precharge circuit PCH1 couples to the complementary bit lines in bit pairs BL[0] and / BL[0]. Figure 4 In the SRAM according to the first embodiment, the precharge circuit PCH1 includes P-type FETs MP3 and MP4 coupled between bit line pairs BL[0] and / BL[0], and P-type FET MP5 coupled between the bit lines of bit line pairs BL[0] and / BL[0]. The bit line pairs are precharged when they are deselected.

[0066] When bit line pairs BL[0] and / BL[0] are deselected, the column address signal CA[0] is low. Therefore, P-type FETs MP3 and MP4 are on, causing bit line pairs BL[0] and / BL[0] to be pre-charged to the supply voltage Vdd. Additionally, at this time, bit line BL[0] and bit line / BL[0] are short-circuited by P-type FET MP5, reducing the potential difference between the bit lines of bit line pairs BL[0] and / BL[0]. Note that in Figure 4 In the diagram, although the precharge circuit PCH1 is shown as being arranged in the cell memory array 10[0], it is not limited to this arrangement and the precharge circuit PCH1 may be arranged in the cell selection circuit[0].

[0067] The cell column selection circuit 13[0] includes a common bit line pair CBL and / CBL shared among multiple bit line pairs, N-type FETs MN3 and MN4 coupled between bit line pairs BL[0] and / BL[0] and bit line pairs BL[1] and / BL[1], and P-type FETs MP6 and MP7, and an inverter IV1. To illustrate bit line pairs BL[0] and / BL[0], the source-drain paths of N-type FET MN3 and P-type FET MP6 are coupled in series between bit line / BL[0] and the common bit line CBL. Similarly, the source-drain paths of N-type FET MN4 and P-type FET MP7 are coupled in series between bit line BL[0] and the common bit line CBL. To select bit line pairs BL[0] and / BL[0], the N-type FETs MN3 and MN4 and the P-type FETs MP6 and MP7 are turned on by setting the column address signal CA[0] high, so that bit line pairs BL[0] and / BL[0] are electrically coupled to the common bit line pairs CBL[0] and / CBL[0]. Note that when bit line pairs BL[0] and / BL[0] are deselected, the N-type FETs MN3 and MN4 and the P-type FETs MP6 and MP7 are turned off, so that bit line pairs BL[0] and / BL[0] are electrically decoupled from the common bit line pairs CBL[0] and / CBL[0].

[0068] Unit I / O control circuit

[0069] The unit IO control circuit 13[0] includes a precharge circuit PCH2, a sensing amplifier SA, a write circuit WCK, and an intermediate potential generation circuit IVG1.

[0070] A precharge circuit PCH2, consisting of P-type FETs MP12 to MP14, is coupled between the common bit line pair CBL and / CBL and the power supply voltage Vdd. Here, P-type FETs MP12 and MP13 are coupled between the power supply voltage Vdd and the common bit line pair / CBL and CBL, and P-type FET MP14 is coupled between the bit lines of the common bit line pair / CBL and CBL. P-type FETs MP12 to MP14 are controlled by the output of OR circuit LG3. OR circuit LG3 is provided with a write control signal WTE, a sense amplifier control signal SAE, and a read control signal RDE. In this way, P-type FETs MP12 to MP14 are in the off state in the following modes: a read mode for reading data from a selected memory cell, a write mode for writing data to a selected memory cell, and a test mode for performing tests on the memory cell. In other cases, P-type FETs MP12 to MP14 are in the ON state, where the common bit line pair / CBL and CBL are precharged to the supply voltage Vdd and the potential difference between the bit lines of the bit line pair decreases simultaneously.

[0071] The sense amplifier SA includes P-type FETs MP15 and MP16, N-type FETs MN9 to MN11, a latch circuit LTH, and an inverter SIV8. Inverter SIV1 is composed of P-type FET MP15 and N-type FET MN9, and inverter SIV2 is composed of P-type FET MP16 and N-type FET MN10. Inverters SIV1 and SIV2 are cross-coupled. In other words, the input of inverter SIV1 is coupled to the output of inverter SIV2, and the input of inverter SIV2 is coupled to the output of inverter SIV1.

[0072] Furthermore, the input of inverter SIV1 is coupled to the common bit line CBL, and the input of SIV2 is coupled to the common bit line / CBL. Additionally, the sources of P-type FETs MP15 and MP16 are coupled to the power supply voltage Vdd, and the sources of N-type FETs MN9 and MN10 are coupled to ground voltage Vss via N-type FET MN11, which is controlled by the sense amplifier control signal SAE. The latch circuit LTH is coupled to the common bit line CBL and is controlled by the sense amplifier control signal SAE. Furthermore, the output of the latch circuit LTH is output as output data Q[0] via inverter IV8.

[0073] By setting the sense amplifier control signal SAE to a high level, the cross-connected inverters SIV1 and SIV2 operate to amplify the potential difference between the bit lines of the common bit line pair CBL and / CBL. The latch circuit LTH latches the amplified voltage of the common bit line CBL as a logic value. In this way, the logic value latched by the latch circuit LTH is logically inverted by the inverter IV8 and output as the output data Q[0].

[0074] The write circuit WCK includes an AND circuit LG2 that is provided with input data D[0] and write control signal WTE, an AND circuit LG1 that is provided with input data D[0] inverted by inverter IV3 and write control signal WTE, inverter IV2, N-type FETs MN5 to MN8, and P-type FETs MP8 to MP11 and P-type FET MP17.

[0075] N-type FET MN7 and P-type FET MP10 are series coupled between the bias node BIAS_Node and the supply voltage Vdd via P-type FET MP17. The connection node n7_10 between N-type FET MN7 and P-type FET MP10 is coupled to the common bit line / CBL via N-type FET MN5 and P-type FET MP8. Similarly, N-type FET MN8 and P-type FET MP11 are also series coupled between the bias node BIAS_Node and the supply voltage Vdd via P-type FET MP17. The connection node n8_11 between N-type FET MN8 and P-type FET MP11 is coupled to the common bit line CBL via N-type FET MN6 and P-type FET MP9.

[0076] The write control signal WTE is provided to the gates of N-type FETs MN5 and MN6. The write control signal WTE is logically inverted by inverter IV2. The inverted write control signal WTE is then provided to the gates of P-type FETs MP8 and MP9. N-type FETs MN5 (MN6) and P-type FET MP10 (MP11) are coupled such that their source-drain paths are in parallel. Therefore, N-type FETs MN5 (MN6) and P-type FET MP10 (MP11) act as transmission gates that selectively couple the common bit line pair CBL and / CBL to connection nodes n7_10 and n8_11 according to the write control signal WTE. In other words, when the write control signal WTE is set high, the transmission gates electrically couple the common bit line pair CBL and / CBL to connection nodes n7_10 and n8_11.

[0077] The gates of N-type FET MN7 and P-type FET MP10 are provided with the output signal CBW from AND circuit LG1. The gates of N-type FET MN8 and P-type FET MP11 are provided with the output signal CTW from AND circuit LG2. In this way, when the write control signal WTE is high, N-type FET MN7 or P-type FET MP10 becomes on according to the logic value of input data D[0], so that the common bit line / CBL is electrically coupled to the power supply voltage Vdd via the bias node BIAS_Node or P-type FET MP17. In the same way, N-type FET MN8 or P-type FET MP11 becomes on according to the logic value of input data D[0], so that the common bit line CBL is also electrically coupled to the power supply voltage Vdd via the bias node BIAS_Node or P-type FET MP17.

[0078] In write mode and test mode, the output signal CTW has the same logic value as the input data D[0], and the output signal CBW has the opposite logic value to the input data D[0]. Furthermore, the P-type FET MP17 is controlled to be either on or off depending on the potential of the bias node BIAS_Node. As described later, in write mode, the potential of the bias node BIAS_Node is ground voltage Vss or a negative potential below ground voltage Vss. Conversely, in test mode, the potential of the bias node BIAS_Node becomes close to the supply voltage Vdd. In this way, in write mode, the P-type FET MP17 becomes on, allowing the supply voltage Vdd to be supplied to P-type FETs MP10 and MP11 via the P-type FET MP17. Conversely, in test mode, when the P-type FET MP17 becomes off, the node connecting P-type FETs MP10, MP11, and MP17 is in a high-impedance state.

[0079] Therefore, in write mode, depending on the logic value of the input data D[0], for example, when the common bit line CBL is coupled to the power supply voltage Vdd, the common bit line / CBL is coupled to the bias node BIAS_ node. In this way, for example in write mode, the write circuit WCK becomes capable of providing different potentials to the bit lines in the selected bit line pair (e.g., BL[0] and / BL[0]) according to the logic value of the input data D[0], so that the input data D[0] can be written to the memory cell.

[0080] The intermediate potential generation circuit IVG1 includes N-type FETs MN13 and MN14, the aforementioned wiring pair TL and / TL, inverters IV4 to IV7, and inverters CIV1 and CIV2 capable of high-impedance output. Inverters CIV1 and CIV2 include control nodes nc and / nc. They are input-independent inverters: by providing a low level (high level) to the control node nc ( / nc), the output is set to a high-impedance state; and by providing a high level (low level) to the control node nc ( / nc), the input is inverted and its output is generated. Clock inverters can be used, for example, as such inverters CIV1 and CIV2.

[0081] exist Figure 4 In this embodiment, the symbol MTC represents the capacitance formed between wiring TL and wiring / TL (wiring capacitance). Additionally, in the N-type FET MN12, its source and drain are coupled to wiring / TL and its gate is coupled to wiring TL. In this way, the MOS capacitor is constructed from the N-type FET MN12, and the MOS capacitor is coupled between wiring TL and wiring / TL. In other words, in the first embodiment, two capacitive elements are equivalently coupled between wiring TL and wiring / TL. Although the capacitive element has a pair of terminals, the terminal coupled to wiring / TL can be considered as one terminal of the capacitive element, and the terminal coupled to wiring TL can be considered as the other terminal of the capacitive element.

[0082] Furthermore, the wiring / TL is coupled to the drain of the N-type FET MN13, and the source of the N-type FET MN13 is coupled to ground voltage Vss. The aforementioned bias node BIAS_Node is coupled to the connection node between the wiring / TL and the N-type FET MN13.

[0083] Inverters IV4 through IV7, along with inverters CIV1 and CIV2, constitute a switching circuit used to switch between transmitting the boost control signal BOOST to wiring TL without inverting its logic value, and transmitting the boost control signal BOOST to wiring TL and inverting its logic value. This switch is controlled by the bias mode control signal BIASMODE. In other words, the boost control signal BOOST is inverted by inverter IV7, and the inverted boost control signal BOOST is provided to the input of inverter CIV2 and also to the input of inverter CIV1 via inverter IV6. In this way, the inverted boost control signal is provided to the input of inverter CIV2, and a control signal synchronized with the boost control signal BOOST is provided to the input of inverter CIV1.

[0084] The bias mode control signal BIASMODE is provided to the control node nc of inverter CIV1, and the bias mode control signal BIASMODE, inverted by inverter IV5, is provided to the control node nc of inverter CIV2. In this way, depending on the level (logic value) of the bias mode control signal BIASMODE, the output of one of inverters CIV1 and CIV2 becomes high impedance, and the other inverter inverts the input and output.

[0085] The outputs of inverters CIV1 and CIV2 are provided to wiring TL via inverter IV4. In the following description, a portion of wiring TL coupled to the gate of N-type FET MN12 will be described as the boost node BOOST_Node. Furthermore, the gate of N-type FET MN13 is provided with a boost control signal BOOST, inverted by inverter IV7.

[0086] As will be described below, in test mode, the N-type FET MN13 is turned off. Here, by setting the bias mode control signal BIASMODE to a high level, the boost node BOOST_Node also increases towards the supply voltage Vdd as the boost control signal BOOST increases. Since the wiring TL and wiring / TL are coupled through capacitors (wiring capacitor MTC and MOS capacitor), the wiring / TL and the bias node BIAS_Node coupled to the wiring / TL also increase to slightly below the supply voltage Vdd. Here, according to the input data D[0], the bias node BIAS_Node is coupled to the bit line CBL or / CBL via the N-type FET MN8 or MN7 and the transmission gate in the cell column select circuit.

[0087] Therefore, through charge redistribution, the potential of the bit line connected to the bias node BIAS_Node drops to a level below the pre-charge supply voltage Vdd. That is, the potential of the bit line becomes an intermediate potential between the supply voltage Vdd and the ground voltage Vss. In test mode, the memory cell is determined by comparing the intermediate potential with the potential of the bit line shifted according to the read current flowing through the selected memory cell by the sense amplifier SA.

[0088] In the first embodiment, the lengths of the wiring pairs TL and / or TL depend on the length of the bit line pair. In this way, when the bit line length changes according to the SRAM compilation technique, the capacitance value of the wiring capacitance MTC, which contributes to charge redistribution according to this change, can be altered. In other words, the capacitance value of the wiring capacitance MTC changes according to the bit line wiring length. As a result, in test mode, the error in determining the characteristics of memory cells can be reduced.

[0089] Furthermore, in write mode, the intermediate potential generation circuit IVG1 is used as part of the write circuit WCK. In write mode, the bias mode control signal BIASMODE is set to low. When the boost control signal BOOST changes from ground voltage Vss to power supply voltage Vdd, the potential of the boost node BOOST_Node changes from power supply voltage to ground voltage Vss. Due to the capacitance between the wiring TL and wiring / TL, the potential of the bias node BIAS_Node changes to a negative potential (third voltage) below ground potential Vss according to the potential change of the boost node BOOST_Node. In this way, in write mode, a power supply voltage Vdd, which is positive relative to ground voltage Vss, and a negative voltage relative to ground voltage Vss can be provided to the bit line pair selected from the write circuit WCK, thereby ensuring that input data is written to the selected memory cell. That is, according to the first embodiment, a write circuit with write assistance function can be provided while suppressing the increase in occupied area.

[0090] Figure 5 This is a diagram illustrating the operation of the intermediate potential generation circuit IVG1 according to the first embodiment. Figure 5 The diagram illustrates the relationship between the bias mode control signal BIASMODE, the boost control signal BOOST, the boost node BOOST_Node, and the bias node BIAS_Node.

[0091] When the bias mode control signal BIASMODE has a logic value of "1" and the boost control signal BOOST has a logic value of "1", as described above, the potential of the boost node BOOST_Node becomes ground voltage Vss and the potential of the bias node BIAS_Node becomes an intermediate potential. Furthermore, when the bias mode control signal BIASMODE has a logic value of "0" and the boost control signal BOOST has a logic value of "1", as described above, the potential of the boost node BOOST_Node becomes ground voltage Vss and the potential of the bias node BIAS_Node becomes a negative potential.

[0092] Conversely, when both the bias mode control signal BIASMODE and the boost control signal BOOST have a logic value of "0", the potential of the boost node BOOST_Node becomes the supply voltage Vdd and the potential of the bias node BIAS_Node becomes the ground voltage Vss, depending on the conduction state of the N-type FET MN13. Furthermore, when the bias mode control signal BIASMODE has a logic value of "1" and the boost control signal BOOST has a logic value of "0", the potentials of both the boost node BOOST_Node and the bias node BIAS_Node become the ground voltage Vss.

[0093] Configuration of control circuit and column selection circuit

[0094] Next, the description Figure 1 The configuration example of column selection circuit 11 and control circuit 12 is shown. Figure 6 and 7 This is a block diagram illustrating the configuration of the control circuit according to the first embodiment. Furthermore, Figure 8 This is a block diagram illustrating the configuration of the column selection circuit according to the first embodiment.

[0095] like Figure 6 As shown, the control circuit 12 includes flip-flops 12F1 to 12F3, buffer groups (multiple buffers coupled in series) 12BFG1 to 12BFG3, logic gates 12LG1 to 12LG10, buffer 12BF1, and pre-decoder P_DEC.

[0096] Flip-flops 12F1 through 12F3 retrieve and maintain inputs and outputs synchronously with the clock signal CLK. Specifically, flip-flop 12F1 retrieves the address signals AD[3:0] and outputs the internal address signals ADL[3:0], while flip-flop 12F2 retrieves the write enable signal WEN and outputs the internal write enable signal WENL. Furthermore, flip-flop 12F3 retrieves the test enable signal TE and outputs the internal test signal TEL.

[0097] Logic gate (AND) 12LG1 is provided with an enable signal CEN and a clock signal CLK, and logic gate 12LG1 outputs an internal enable signal CK1 synchronized with the clock signal CLK. The internal enable signal CK1 is provided to logic gate (AND) 12LG2, and the internal control signal TDEC is output from logic gate 12LG2. The internal control signal TDEC and the internal test signal TEL are provided to the combinational logic circuit composed of buffer groups 12BFG1 and 12BFG2 and logic gates 12LG3 and 12LG4, and the output signal of this combinational logic circuit is provided to logic gate 12LG2 as the internal control signal BACK. The aforementioned sense amplifier control signal SAE is formed by the combinational logic circuit configured with logic gates 12LG7 and 12LG8, based on the internal control signal BAK, the internal test signal TEL, and the internal write enable signal WENL.

[0098] The read control signal RDE is formed by logic gate 12LG5 based on the internal control signal TDEC and the internal write enable signal WENL, and the write control signal WTE is formed by logic gate 12LG6 based on the internal control signal TDEC and the internal write enable signal WENL.

[0099] The aforementioned bias mode control signal BIASMODE is formed by buffer 12BF1 based on the internal test signal TEL. Furthermore, the aforementioned boost control signal BOOST is formed by combinational logic circuits configured with buffer group 12BFG3 and logic gates 12LG9 to 12LG11, based on the internal test signal TEL, the internal control signal TDEC, and the internal write enable signal WENL.

[0100] The internal address signals ADL[3:0] and the internal control signal TDEC are provided to the pre-decoder P_DEC. For example... Figure 7 As shown, the predecoder P_DEC has logic gates D_LG1 to D_LG8, and the row address signal RA[3:0], column address signal CA[1:0] and control signal RGA[1:0] (RGA[0] and RGA[1]) are formed by logic gates D_LG1 to D_LG8 based on the internal address signal ADL[3:0] and the internal control signal TDEC.

[0101] Furthermore, the row selection circuit 11 is composed of logic gates 11LG1 to 11LG8, and the outputs of logic gates 11LG1 to 11LG8 are coupled to word lines WL[0] to WL[7], such as Figure 8 As shown, and based on the row address signals RA[0] to RA[3] and the control signals RGA[0] and RGA[1], a high level is provided to the word lines specified by the row address signals RA[3:0].

[0102] Note that in Figure 6 and 7 In this context, the circle placed on the input side of the logic gate indicates logical inversion.

[0103] SRAM operation example

[0104] Next, the operation of the SRAM according to the first embodiment will be described with reference to the accompanying drawings. Figures 9 to 11 This is a waveform diagram illustrating the operation of the SRAM according to the first embodiment. Note that in the following description, reference will be made to the diagram showing the configuration of the SRAM. Figures 3 to 6 .

[0105] Read operation

[0106] refer to Figure 9 This section describes the read operation in read mode. A read operation is indicated when the enable signal CEN is low (indicating an enabled state), the write enable signal WEN is high (indicating a read state), and the test enable signal TE is low (indicating it is not in a test state). Here, the word line WL[n] and the bit line pairs BL[0] and / BL[0] are selected by the address signals AD[3:0].

[0107] from Figure 6 and Figure 5 The structure of the control circuit 12 shown can be understood as follows: when the enable signal CEN and the test enable signal TE are set to low level and the write enable signal WEN is set to high level, the boost control signal BOOST and the bias mode control signal BIASMODE are set to low level, as shown. Figure 9 As shown. Additionally, because the test enable signal TE is at a low level and Figure 6 The internal test signal TEL shown is at a low level, so after the clock signal CLK changes, the sense amplifier control signal SAE changes from low to high level, and the delay is mainly determined by the buffer group 12BFG1.

[0108] When the write enable signal WEN is set high, the write control signal WTE goes low. As a result, the N-type FETs MN5 and MN6, which constitute the transmission gate, and the P-type FETs MP8 and MP9 become off, and the write circuit WCK is electrically disconnected from the common bit line pairs CBL and / CBL.

[0109] To select bit line pairs BL[0] and / BL[0], the column address signal CA[0] goes high, causing the N-type FETs MN3 and MN4 and the P-type FETs MP6 and MP7, which form the transmission gates between bit line pairs BL[0] and / BL[0] and the common bit line pairs CBL and / CBL, to turn on. Here, the P-type FETs MP3 to MP5 of the precharge circuit PCH1, which is configured in the same manner to couple to bit line pairs BL[0] and / BL[0], turn off. As a result, precharging of the selected bit line pairs is terminated, and the selected bit line pairs are coupled to the common bit line pairs. Furthermore, during read operations, since the read control signal RDE is set high, precharging of the common bit line pairs CBL and / CBL by the precharge circuit CH2 is also terminated.

[0110] Based on the read current in the memory cell (the selected memory cell) coupled to the selected word line WL[n], the selected bit line pair BL[0], and / BL[0], the potential of bit line BL[0] or / BL[0] gradually decreases from the precharge potential. As the potential decreases, the common bit line of either the common bit line pair CBL and / CBL, coupled to the bit line pair BL[0] and / BL[0] via the transmission gate, gradually decreases from the precharge potential. Figure 9 In this context, the symbol CBL represents the potential of the common bit line CBL, and the symbol / CBL represents the potential of the common bit line / CBL.

[0111] When the sense amplifier control signal SAE is set to high, the N-type FET MN11 becomes on, and the sense amplifier SA amplifies the voltage, increasing the potential difference between the common bit line and the common bit line of CBL and / CBL. The latch circuit LTH retains the potential of the common bit line amplified by the sense amplifier as a logic value. The logic value retained in the latch circuit is read from the inverter IV8 as the output data Q[0].

[0112] Write operation

[0113] refer to Figure 10 This describes the write operation in write mode. A write operation is indicated when the enable signal CEN is set low, the write enable signal WEN is set low to indicate a write operation, and the test enable signal TE is set low. In the same manner as the read operation, the word line WL[n] and the bit line pairs BL[0] and / BL[0] are selected by the address signals AD[3:0].

[0114] Because the write enable signal WEN and the test enable signal TE are at a low level, therefore, as from Figure 6 As understood from the configuration of the control circuit 12 shown, the sense amplifier control signal SAE is set to a low level, such as Figure 10 As shown. Additionally, since the internal write enable signal WENL is set low in response to the low level of the write enable signal WEN, the read control signal RDE is set high, causing the precharge circuit PCH2 to terminate the precharge of the common bit line pairs CBL and / CBL. Here, the precharge circuit PCH1 also terminates the precharge of the selected bit line pairs BL[0] and / BL[0] in the same manner as the read operation. Furthermore, the selected bit line pairs BL[0] and / BL[0] are electrically coupled to the common bit line pairs CBL and / CBL via the transmission gate in the same manner as the read operation.

[0115] During a write operation, in the same manner as a read operation, the internal write enable signal WENL is set low, while the internal control signal TDEC is set high, and the write control signal WTE is set high. Figure 6 The configuration shown is understandable. In this way, the transmission gate, consisting of N-type FETs MN5 and MN6 and P-type FETs MP8 and MP9, becomes on, so that the common bit line pair CBL and / CBL is electrically coupled to the write circuit via the transmission gate.

[0116] In the write circuit WCK, based on the logic value of the input data D[0], either the output signal CBW of the AND circuit LG1 or the output signal CTW of the AND circuit LG2 is set to a high level, and the other is set to a low level. For example, when the input data D[0] has a logic value "1" (high level), the output signal CTW is set to a high level, causing the N-type FET MN9 to be turned on and the P-type FET MP11 to be turned off. Here, since the output signal CBW is set to a low level, the N-type FET MN7 is turned off and the P-type FET MP10 is turned on.

[0117] Conversely, when the input data D[0] is logic value "0" (low level), the output signal CTW is set to low level, the P-type FET MP11 is set to the on state, and the N-type FET MN is set to the off state. Here, since the output signal CBW is set to high level, the N-type FET MN7 is set to the on state and the P-type FET MP10 is set to the off state.

[0118] In this way, the common bit line CBL corresponding to the output signal CTW and the selected bit line BL[0] are coupled to the bias node BIAS_Node via N-type FET MN8 when the input data D[0] has a logic value of "1", and are coupled to the power supply voltage Vdd via P-type FET MP11 when the input data D[0] has a low logic value of "0".

[0119] Similarly, when the input data D[0] has a logic value of "0", the N-type FET MN7 is set to the ON state, and the common bit line / CBL and the selected bit line / BL are coupled to the bias node BIAS_Node. When the input data D[0] has a logic value of "1", the common bit line / CBL and the selected bit line / BL are coupled to the power supply voltage Vdd.

[0120] Because the test enable signal TE is low, the bias mode control signal BIASMODE is set low, and after the internal control signal TDEC goes high according to the clock signal CLK, primarily after the time period determined by buffer group 12BFG, the boost control signal BOOST changes from low to high. Figure 5 As shown, when the bias mode control signal BIASMODE is set to low level (logic value "0") and the boost control signal BOOST becomes high level (logic level "1"), the potential of the bias node BIAS_Node rises to a negative voltage.

[0121] Therefore, based on the logic value of the input data D[0], a power supply voltage Vdd and a negative voltage are provided to the bit line pairs BL[0] and / BL[0]. For example, when the input data D[0] has a logic value "1", a negative potential is provided to the bit line BL[0] and the power supply voltage Vdd is provided to the bit line / BL[0]. In this way, for example, a large potential difference based on the input data D[0] is provided to the selected memory cell, so that the input data D[0] can be reliably written to the memory cell.

[0122] Test operation

[0123] refer to Figure 11 This describes the test operation in the test mode. The test operation is indicated when the enable signal CEN is set to low, the write enable signal WEN is low, and the test enable signal TE is high.

[0124] Similarly, in the same manner as read and write operations, the word line WL[n] and bit line pairs BL[0] and / BL[0] are selected by the address signals AD[3:0]. That is, the following case will be described as an example: performing a test on the selected memory cell coupled to the word line WL[n] and bit line pairs BL[0] and / BL[0].

[0125] When the test enable signal TE changes from low to high, the bias mode control signal BIASMODE also changes from low to high. In this way, Figure 6 In the control circuit 12 shown, the output of logic gate 12LG10 changes from low to high, and the boost control signal BOOST also changes from low to high. In this way, an intermediate potential appears at the bias node BIAS_Node, as shown... Figure 5 As shown.

[0126] The transmission gate between the selected bit line pairs BL[0] and / BL[0] and the common bit line pairs CBL and / CBL is set to the ON state. Therefore, the bit line pairs BL[0] and / BL[0] are electrically connected to the common bit line pairs CBL and / CBL.

[0127] exist Figure 11In the example shown, the input data D[0] is set to high (logic value "1"). Additionally, since the write control signal WTE is high, the output signal CTW of the AND circuit LG2 is set to high, causing the N-type FET MN8 to be turned on. As a result, the bias node BIAS_Node is electrically coupled to the common bit line CBL via the N-type FET MN8, and charge redistribution is performed between the wiring / TL, the bias node BIAS_Node, the common bit line CBL, and the bit line BL[0]. The potentials of the bit line BL[0] and the common bit line CBL are slightly reduced from the precharge potential (Vdd). Figure 11 In the diagram, the potential change of the common potential line CBL is shown by the dashed line.

[0128] exist Figure 10 In the write operation described, when the logic value "0" is provided as input data D[0], bit line BL[0] is set to high level, so that the data with the logic value "0" that sets bit line / BL[0] to low level is written to the selected memory cell. With the input data D[0] already written with a logic value of "0", as long as the selected memory cell is normal, word line WL[n] is selected in the test operation, so that the potential of bit line / BL[0] gradually decreases from the precharge potential (Vdd). When the sense amplifier control signal SAE goes high, the potential of bit line / BL[0] becomes lower than the potential of bit line BL[0], and the potential of common bit line / CBL also becomes lower than the potential of common bit line CBL. As a result, as output data Q[0], the low-level logic value "0" is output, and it can be determined that the selected memory is normal and the test has passed.

[0129] Conversely, when the read current of the memory cell being tested (i.e., the selected memory cell) is small, for example due to problems in the manufacturing process of semiconductor device 1, the timing of the decrease in the potential of bit line / BL[0] from the precharge potential is delayed. At the moment the sense amplifier control signal SAE goes high, the potential of bit line / BL[0] does not decrease sufficiently and is not lower than the potential of bit line BL[0]. As a result, the potential of common bit line / CBL is not lower than the potential of common bit line CBL, causing a high level of logic value "1" to be output as output data Q[0]. In this way, an error of the desired value appears in the selected memory cell, and a problem with the target cell can be detected.

[0130] Here, the case where the logic value "0" is written as the desired value to the target memory cell has been described. However, the same applies to the case where the logic value "1" is written to the target memory cell. In other words, in the case of logic value "1", data with logic value "1" (such as data where bit line BL[0] is set low and bit line / BL[0] is set high) is written to the selected memory cell. In this case, during the test operation, a low level (logic value "0") is provided as input data D[0]. In this way, the output signal CBW of logic gate LG1 is set high, and pre-charging is performed between the wiring / TL, bias node BIAS_Node, common bit line / CBL, and bit line / BL[0], such that the potentials of bit line / BL[0] and common bit line / CBL gradually decrease from the pre-charging potential Vdd. When the target cell is normal, the output data Q[0] has the same logic value as the previously written desired value "1", and when a problem occurs in the memory cell, the output data Q[0] has a different logic value "0" than the desired value "1".

[0131] As described above, in the first embodiment, a logic value that is out of phase (inverted) with the logic value written into the target memory cell (the logic value as the expected value) is provided as input data in the test operation.

[0132] Furthermore, in the SRAM according to the first embodiment, during a test operation, the timing of the sense amplifier control signal SAE changing from low to high is set to a delay compared to a read operation. In the first embodiment, the delay setting of the sense amplifier control circuit SAE is mainly achieved through... Figure 6 The control circuit 12 in the diagram is implemented using logic gate 12LG3 and buffer group 12BFG2. Specifically, after the internal test signal TEL is set high, the internal control signal TDEC, delayed by buffer group 12BFG2, is provided to the inverted input of logic gate 12LG3, causing the sense amplifier control signal SAE to go high. Therefore, for example, by changing the number of buffers constituting buffer group 12BFG2, the rise timing of the sense amplifier control signal SAE can be changed. Although reference will be made to... Figure 2 and 3 It can be described that by utilizing the sensing amplifier control signal SAE to delay the timing of the activation of the sensing amplifier SA, it is possible to better determine whether the read current flowing into the target memory cell is small.

[0133] Note that by making the sensing amplifier control signal SAE high, the sensing amplifier SA is activated, therefore, as Figure 11 As shown, the potential difference between the common bit lines of the common bit line pair increases as the sensing amplifier SA amplifies, and the potential of the bias node BIAS_Node increases.

[0134] N-type FETs MN7 and MN8, and P-type FETs MP10 and MP11 constitute a circuit that provides a voltage to a selected bit line pair to follow the data to be written to the memory cell MC. Conversely, in test operation, N-type FETs MN7 and MN8, and P-type FETs MP10 and MP11 are used as a designation circuit to specify the bit line coupled to the wiring capacitor MTC, thereby coupling the specified bit line to the wiring capacitor MTC.

[0135] memory unit

[0136] Figure 12 This is a circuit diagram illustrating the configuration of the memory cells according to the first embodiment. Furthermore, Figure 13 It is a waveform diagram showing the operation of the memory cell during the test operation.

[0137] exist Figure 12 The diagram shows the state of memory cell MC, where the logic value "0" has been written. In other words, when word line WL[n] is selected, memory cell MC retains data such that bit line / BL[0] is set high and bit line BL[0] is set low. In this state, N-type FET MN1 and P-type FET MP2 are off, and N-type FET MN2 and P-type FET MP1 are on. Therefore, node MT is set low, so "low" is stored, and node MB is set high, so "high" is stored.

[0138] When the memory cell MC is normal, the word line WL[n] is high, even if the node MT is electrically coupled to the bit line BL[0] via the N-type FET NTT2. Figure 13 As shown by the solid line MT1, the potential of node MT is also changed by the read current flowing through the memory cell MC. In other words, it can prevent the potential of node MT from fluctuating significantly from the ground voltage Vss due to the read current. In this way, the potential of bit line BL[0] changes as shown by the solid line BL[0]_1. Conversely, when the read current flowing through the memory cell MC is small due to process issues, the ability to suppress the potential of node MT is reduced, causing the potential of node MT to fluctuate significantly from the ground voltage Vss, as shown by the dashed line MT2. In this way, the potential of bit line BL[0] changes as shown by the dashed line BL[0]_2.

[0139] exist Figure 13 In this context, the symbol / BL[0]_V represents the potential of the bit line / BL[0]. From... Figure 13It is understandable that after word line WL[n] goes high, after a sufficient period of time, the potential difference between bit line / BL[0]_V and bit line BL[0]_2 can be increased. Therefore, in the first embodiment, in the test operation, the timing of activating the sensing amplifier SA is set to be delayed compared to the read operation.

[0140] DFT control block

[0141] Figure 1 The DFT control block shown outputs signals to the SRAM for testing and data processing. Figure 14 This is a waveform diagram illustrating the operation of the DFT control block according to the first embodiment.

[0142] DFT control block 6 writes the logic value "0" as the expected value to all memory cells in the SRAM or example, and then tests all memory cells by providing the logic value "1", which is the inverted logic value relative to the expected value of the input data D[n]. Then, the logic value "1" is set to the expected value, and a write is performed on all memory cells to test all memory cells by providing the logic value "0" as input data.

[0143] refer to Figure 14 The description is as follows: Between time t0 and t1, by changing the address signal AD[n], the logic value "0" is written as input data D[n] to all memory cells from address 0 (zero) to F. During the following time period t1 to t2, the test enable signal TE is set high to put the SRAM into test mode. In test mode, DFT control block 6 provides the logic value "1" as input data D[n] to the SRAM by changing the address signal AD[n]. In test mode, when the output data Q[n] is a logic value "0", DFT control block 6 determines that the target memory has passed the test. Conversely, when the output data Q[n] has a logic value "1", DFT control block 6 determines that the target memory cell has failed the test.

[0144] Next, during the time interval t2 to t3, the address signal AD[n] is changed to write the logic value "1" as input data D[n] to all memory cells from address 0 (zero) to F. In the next time interval from t3 to t4, the test enable signal TE is set high to put the SRAM into test mode. In test mode, DFT control block 6 provides the SRAM with the logic value "0" as input data D[n]. In test mode, when the output data Q[n] is the logic value "1", DFT control block 6 determines that the target memory cell has passed the test. Conversely, when the output data Q[n] is the logic value "0", DFT control block 6 determines that the target memory cell has failed the test.

[0145] In the first embodiment, SRAM 2S1 to 5S1 ( Figure 1 Each of the SRAMs 2S1 to 5S1 is provided with wiring pairs T1 and / TL. The wiring length of wiring pairs TL and / TL in each of the SRAMs 2S1 to 5S1 is the same as the wiring length of the bit line pairs of the SRAM (corresponding STAM) in which wiring pairs TL and / TL are provided. In this way, in test mode, the value of the wiring capacitance coupled to the bit lines can be appropriately set for each SRAM, and defective memory cells can be reliably detected in test mode. That is, according to the compiled SRAM technology, defective memory cells can be reliably detected even if various types of SRAM are provided in the semiconductor device.

[0146] Second Embodiment

[0147] Figure 15 This is a circuit diagram showing the configuration of the cell memory array, cell column selection circuit, and cell I / O control circuit. Figure 15 Similar to Figure 4 The difference is that the intermediate potential generation circuit is changed to the intermediate potential generation circuit IVG2.

[0148] The intermediate potential generation circuit IVG2 includes inverters IV21 to IV24, N-type FET MN21, P-type FET MP21, NAND circuit LG21, NOR circuit LG22, wiring pair TL and / or TL, and N-type FET MN12 that constitutes a MOS capacitor.

[0149] Figure 16 This is a diagram illustrating the operation of the intermediate potential generation circuit of the second embodiment.

[0150] During a write operation, the bias mode control signal BIASMODE has a logic value of "0" and the boost control signal BOOST changes from a logic value of "0" to a logic value of "1" upon activation. Furthermore, during a test operation, the bias mode control signal BIASMODE has a logic value of "1" and the boost control signal BOOST changes from a logic value of "0" to a logic value of "1" upon activation.

[0151] During a read operation, when the boost control signal BOOST has a logic value of "0", the boost node BOOST_Node is at the power supply voltage Vdd, and the bias node BIAS_Node is at ground voltage Vss. From this state, the boost control signal BOOST changes (activates) from ground voltage Vss to power supply voltage Vdd, the boost node BOOST_Node becomes ground voltage Vss, and the bias node BIAS_Node is set to a negative potential. That is, in the same manner as in the first embodiment, a negative potential can be provided to the bit line during a write operation.

[0152] Furthermore, during testing, when the boost control signal BOOST has a logic value of "0", the boost node BOOST_Node is set to the power supply voltage Vdd, and the bias node BIAS_Node is set to a power supply voltage different from that in the first embodiment. From this state, when the boost control signal BOOST changes (activates) from ground voltage Vss to the power supply voltage Vdd, the boost node BOOST_Node can generate an intermediate potential slightly lower than the power supply voltage Vdd. In this way, in the same manner as in the first embodiment, the potential of the reference bit line can become slightly lower than the pre-charge power supply voltage Vdd in test mode. As a result, defective memory cells can be detected in the same manner as in the first embodiment.

[0153] exist Figure 4 and 15 In this circuit, the intermediate potential generation circuits IVG1 and IVG2 can be considered as intermediate potential control circuits. These control circuits include wiring pairs TL and / or TL, and voltages coupled to and providing voltages corresponding to the mode (write mode, test mode). Therefore, the intermediate potential control circuits specify the mode via the bias mode control signal BIASMODE, such as... Figure 5 and 16 As shown. In addition, the intermediate control circuit changes the voltage of the wiring TL (boost node) corresponding to the specified mode according to the change of the boost control signal BOOST.

[0154] Although the invention made by the inventors has been specifically described based on embodiments, the invention is not limited to these embodiments, and needless to say, various modifications can be made within the scope of the invention. For example, the wiring lengths of wiring pairs TL and / TL can be substantially different from the wiring lengths of bit line pairs BL[0] and / BL[0], and can depend on the length of the bit line pairs.

Claims

1. A semiconductor device having a static random access memory, comprising: Memory unit; In read mode, the voltage on the bit line pair is changed to a first voltage and a second voltage different from the first voltage according to the data of the memory cell, and the bit line pair is coupled to the memory cell. as well as Designated circuitry for designating bit lines from the bit line pairs. The capacitor element is coupled to the bit line specified by the specified circuit, and in test mode the voltage of the specified bit line is set to a voltage between the first voltage and the second voltage.

2. The semiconductor chip according to claim 1, The capacitor element has a wiring capacitance, which is determined based on the length of the bit line pair.

3. The semiconductor device according to claim 2, further comprising: A write circuit is used to provide a potential in write mode according to the data to be written to the bit line pair. The write circuit includes a designated circuit, and in the write mode provides a third voltage to the bit line designated by the designated circuit, the third voltage being different from the first voltage and the second voltage.

4. The semiconductor device according to claim 3, The specified circuitry specifies a bit line from the bit line pair based on the data to be written.

5. The semiconductor device according to claim 4, The first voltage is a positive voltage relative to the second voltage, and the third voltage is a negative voltage relative to the second voltage.

6. The semiconductor device according to claim 4, The capacitor element includes one terminal to be coupled to the bit line specified by the designated circuit, and another terminal supplied with a voltage corresponding to the mode. In the write mode, the voltage at the other terminal of the capacitor element changes from the first voltage to the second voltage, and The voltage at the other terminal of the capacitor element changes from the second voltage to the first voltage.

7. The semiconductor device according to claim 6, further comprising: A sensing amplifier is used to amplify the potential difference between the bit lines of the bit line pair in the readout mode and the test mode. In the test mode, the operation of the sensing amplifier begins with a greater delay compared to the readout mode.

8. The semiconductor device according to claim 5, The capacitor element has a length that depends on the length of the bit line pair. The capacitor element includes the wiring capacitor and a MOS capacitor. The wiring capacitor is formed by a pair of wirings extending in the same direction as the bit line pair. The MOS capacitor is coupled between the wirings of the wiring pair. One of the wirings in the wiring pair is coupled to the bit line specified by the designated circuit. An intermediate potential control circuit for providing voltage according to a pattern is coupled to another wiring in the wiring pair, and In the test mode, the intermediate potential control circuit provides the other wiring with a voltage that changes from the second voltage to the first voltage.

9. The semiconductor device according to claim 8, In the write mode, the intermediate potential control circuit provides the other wiring with a voltage that changes from the first voltage to the second voltage.

10. The semiconductor device according to claim 3, further comprising: The DFT control circuit is used to generate the signal used in the test mode. In the test mode, the DFT control circuit applies data with a logic level opposite to that of the data in the write mode.

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