Semiconductor device including defect detection circuit and method of detecting defects therein

Abstract

A semiconductor device includes a semiconductor chip having a surrounding peripheral region, a defect detection circuit in the peripheral region, the defect detection circuit being arranged in an open conductive loop, the defect detection circuit including a plurality of latch circuits and a plurality of defect detection conductive paths, each of the plurality of defect detection conductive paths connecting two adjacent latch circuits of the plurality of latch circuits, and a test control circuit configured to (a) perform a test write operation by transmitting bits of an input data pattern in a forward direction of the open conductive loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) perform a test read operation by transmitting the bits stored in the plurality of latch circuits in a reverse direction of the open conductive loop.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0094375, filed on July 29, 2020, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some embodiments generally relate to semiconductor integrated circuits, and more specifically, to defect detection circuits, semiconductor devices including the defect detection circuits, and / or methods for detecting defects in the semiconductor devices. Background Technology

[0004] Generally, integrated circuits are produced / manufactured by forming repeating patterns in a substrate / wafer of semiconductor material. The wafer can be diced and / or sawed into multiple semiconductor dies, and each semiconductor die can be packaged into a semiconductor chip. During the dicing and / or packaging processes, cracks may appear in the semiconductor dies. To reduce the impact of defective products on yield, the semiconductors are inspected for cracks. Summary of the Invention

[0005] Some example embodiments may provide defect detection circuits and / or semiconductor devices including such defect detection circuits for improving the detectability of various types of crack penetration.

[0006] Some example embodiments can provide methods for detecting defects in semiconductor devices to improve the detectability of various types of crack penetration.

[0007] According to some example embodiments, a semiconductor device includes: a semiconductor die including a central region and a peripheral region surrounding the central region; a defect detection circuit in the peripheral region, the defect detection circuit being arranged in an open conductive loop, the defect detection circuit including a plurality of latch circuits and a plurality of defect detection conductive paths, each of the plurality of defect detection conductive paths connecting two adjacent latch circuits among the plurality of latch circuits; and a test control circuit configured to (a) perform a test write operation by sequentially transmitting bits of an input data pattern in the positive direction of the open conductive loop to cause the plurality of latch circuits to store bits of the input data pattern in the plurality of latch circuits, and (b) perform a test read operation by transmitting bits stored in the plurality of latch circuits in the negative direction of the open conductive loop to read out an output data pattern.

[0008] According to some example embodiments, a method for detecting defects in a semiconductor device includes: forming an open conductive loop in a peripheral region of a semiconductor die, the peripheral region surrounding a central region of the semiconductor die; forming the open conductive loop using a defect detection circuit disposed in the peripheral region, the defect detection circuit including a plurality of latch circuits and a plurality of defect detection conductive paths, each of the plurality of defect detection conductive paths connecting two adjacent latch circuits among the plurality of latch circuits; performing a test write operation by sequentially transmitting bits of an input data pattern in the positive direction of the open conductive loop and storing the bits of the input data pattern in the plurality of latch circuits; performing a test read operation by transmitting bits stored in the plurality of latch circuits in the negative direction of the open conductive loop and reading out an output data pattern; and determining a defect detection conductive path, including the presence and absence of a defect, among the plurality of defect detection conductive paths by comparing the input data pattern and the output data pattern.

[0009] According to some example embodiments, a defect detection circuit includes: a plurality of latch circuits; and a plurality of defect detection conductive paths, each of the plurality of defect detection conductive paths connecting two adjacent latch circuits among the plurality of latch circuits. The defect detection circuit is located in a peripheral region of a semiconductor die and arranged in an open conductive loop, the peripheral region surrounding a central region of the semiconductor. Each of the plurality of latch circuits is configured to transfer a bit stored in each latch circuit to an adjacent latch circuit in each shift cycle, either in the forward direction or the reverse direction of the open conductive loop.

[0010] Semiconductor devices and / or related methods according to some example embodiments can use defect detection circuits including multiple latch circuits and multiple defect detection conductive paths to thoroughly or more thoroughly detect various types of crack penetration. Semiconductor devices and related methods according to some example embodiments can prevent or reduce the likelihood of yield impact associated with defective products, and / or can improve crack detectability. Attached Figure Description

[0011] Some exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a diagram illustrating a semiconductor device including a defect detection circuit according to some example embodiments.

[0013] Figure 2 This is a cross-sectional view showing the vertical structure of a defect detection circuit according to some example embodiments.

[0014] Figure 3This is a flowchart illustrating a method for detecting defects in a semiconductor device according to some example embodiments.

[0015] Figure 4 This is a diagram illustrating a test write operation of a defect detection circuit according to some example embodiments.

[0016] Figure 5 This is a diagram illustrating a test readout operation of a defect detection circuit according to some example embodiments.

[0017] Figure 6 This is a diagram illustrating an example of a test write operation of a defect detection circuit according to some example embodiments.

[0018] Figure 7 This is a diagram illustrating an example of a test read operation of a defect detection circuit according to some example embodiments.

[0019] Figure 8A and Figure 8B This is a diagram used to describe defect detection in a semiconductor device according to some example embodiments.

[0020] Figure 9 This is a diagram illustrating a defect detection circuit according to some example embodiments.

[0021] Figure 10 It is shown Figure 9 A circuit diagram of an example embodiment of the latch circuit included in the defect detection circuit.

[0022] Figure 11A , Figure 11B and Figure 12 It is shown Figure 9 Timing diagram of the operation of the defect detection circuit.

[0023] Figure 13 It is shown Figure 10 The circuit diagram of the inverter included in the latch circuit.

[0024] Figure 14A and Figure 14B It is used to describe Figure 10 A diagram illustrating the operation of a latch circuit.

[0025] Figure 15 It is shown Figure 9 A circuit diagram of an example embodiment of the latch circuit included in the defect detection circuit.

[0026] Figure 16 It is shown Figure 15 The circuit diagram of the three-state inverter included in the latch circuit.

[0027] Figure 17A and Figure 17BIt is used to describe Figure 15 A diagram illustrating the operation of a latch circuit.

[0028] Figure 18 This is a diagram illustrating a defect detection circuit according to some example embodiments.

[0029] Figure 19 It is shown Figure 18 A circuit diagram of an example embodiment of the latch circuit included in the defect detection circuit.

[0030] Figure 20A and Figure 20B It is shown Figure 18 Timing diagram of the operation of the defect detection circuit.

[0031] Figures 21A to 21D It is used to describe Figure 19 A diagram illustrating the operation of a latch circuit.

[0032] Figure 22 This is a flowchart illustrating a method for detecting defects in a semiconductor device according to some example embodiments.

[0033] Figure 23 This is a diagram illustrating a defect detection circuit according to some example embodiments.

[0034] Figure 24 It is shown Figure 23 A diagram of an example embodiment of a path selector included in a defect detection circuit.

[0035] Figure 25A and Figure 25B It is used to describe Figure 23 The diagram shows the test operation of the defect detection circuit.

[0036] Figure 26 This is a diagram illustrating a defect detection circuit according to some example embodiments.

[0037] Figure 27A and Figure 27B It is used to describe Figure 26 The diagram shows the test operation of the defect detection circuit.

[0038] Figure 28 This is a flowchart illustrating a method for detecting defects in a semiconductor device according to some example embodiments.

[0039] Figure 29 This is a diagram illustrating a defect detection circuit according to some example embodiments.

[0040] Figure 30 It is shown Figure 29 A cross-sectional view of the vertical structure for defect detection.

[0041] Figure 31 It is shown Figure 29 The diagram shows some example embodiments of the path selector included in the defect detection circuit.

[0042] Figure 32A and Figure 32B It is used to describe Figure 29 The diagram shows the test operation of the defect detection circuit.

[0043] Figure 33 This is a perspective view of a non-volatile storage device according to some example embodiments.

[0044] Figure 34 It is a diagram used to describe the manufacturing / production process of a stacked semiconductor device according to some example embodiments.

[0045] Figure 35 This is a cross-sectional view showing a stacked semiconductor device according to some example embodiments.

[0046] Figure 36 This is a block diagram illustrating a system including a semiconductor device according to some example embodiments. Specific Implementation

[0047] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, some of which are illustrated in the drawings. In the drawings, the same reference numerals consistently refer to the same elements. Repeated descriptions may be omitted.

[0048] As disclosed herein, the direction substantially perpendicular to the top surface of the substrate is referred to as the vertical direction Z, and the two directions substantially parallel to the top surface of the substrate and intersecting each other are referred to as the first horizontal direction X and the second horizontal direction Y. For example, the first horizontal direction X and the second horizontal direction Y may be perpendicular to each other.

[0049] Figure 1 This is a diagram illustrating a semiconductor device including a defect detection circuit according to some example embodiments. Figure 2 This is a cross-sectional view showing the vertical structure of a defect detection circuit according to some example embodiments.

[0050] Reference Figure 1 The semiconductor device 100 may include at least one semiconductor die SD. The semiconductor die SD may include a central region CREG and a peripheral region PREG surrounding the central region CREG.

[0051] Depending on the type or variety of semiconductor device 100, various semiconductor integrated circuits can be formed in the central region CREG. For example, semiconductor device 100 may be or include a semiconductor memory device, and memory integrated circuits may be formed in the central region CREG of a semiconductor die SD.

[0052] A defect detection circuit CDC can be arranged within a peripheral region PREG surrounding a central region CREG, and can be configured to detect defects such as cracks (e.g., cracks within or partially within semiconductor device 100). The defect detection circuit CDC can be formed or arranged in an open conductive loop. The defect detection circuit CDC includes multiple latch circuits LC1~LC16 and multiple defect detection conductive paths CDP1~CDP15, such that each of the multiple defect detection conductive paths CDP1~CDP15 connects two adjacent latch circuits among the multiple latch circuits CDC1~CDC16. For example, the i-th defect detection conductive path CDPi (where i is an integer between 1 and 15) can connect the rear node BNi of the i-th latch circuit LCI to the front node FNi+1 of the (i+1)-th latch circuit LCI+1.

[0053] For ease of explanation, Figure 1 Sixteen latch circuits LC1~LC16 and fifteen defect detection conductive paths CDP1~CDP15 are shown; however, the example embodiment is not limited thereto, and the number of latch circuits and / or the number of defect detection conductive paths can be determined in various ways.

[0054] The test control circuit TCC can be located in / within the central region CREG. As will be described below, the test control circuit TCC can perform a test write operation by sequentially transmitting the bits of the input data pattern on the positive direction FDR of the open conductive loop to store the bits of the input data pattern in multiple latch circuits LC1~LC16, and can perform a test read operation by transmitting the bits stored in the multiple latch circuits LC1~LC16 on the negative direction BDR of the open conductive loop to read the output data pattern. Here, the positive direction FDR indicates the direction along the open conductive loop from the first latch circuit LC1 to the last latch circuit LC16, and the negative direction BDR indicates the direction along the open conductive loop from the last latch circuit LC16 to the first latch circuit LC1. Furthermore, although in Figure 1 In the example, the positive direction FDR is shown as clockwise around the central region CREG, and the negative direction BDR is shown as counterclockwise around the central region CREG. However, the example embodiment is not limited to this; the positive direction FDR can be counterclockwise around the central region CREG, and the negative direction BDR can be clockwise around the central region CREG. Furthermore, although... Figure 1 The latch circuits LC1 to LC16 are shown as one loop around the central region CREG, but the example embodiment is not limited to this. The defect detection circuit CDC may include latches that loop multiple times around the central region.

[0055] The test control circuit TCC can apply the input data pattern to the first latch circuit LC1, and can receive the output data pattern from the first latch circuit LC1 through the input-output line IOL.

[0056] In some example embodiments, the test control circuit TCC may include a pattern generator PTT (such as an automatic test pattern generator (ATPG)) that outputs each bit of the input data pattern in each shift cycle corresponding to a bit transfer cycle between two adjacent latch circuits. The bits may be based on a pseudo-random number generator (PRNG); however, the example embodiments are not limited thereto, for example, the bits may be based on an even / odd pattern. Furthermore, the test control circuit TCC may include a clock generator CGEN that generates clock signals for controlling test write and test read operations. According to some example embodiments, the pattern generator PTT and / or the clock generator CGEN may be included in an external tester (not shown), and the input data pattern and / or clock signals may be provided to the test control circuit TCC from the external tester.

[0057] The test control circuit (TCC) can compare the input data pattern and the output data pattern to determine the defect detection conductive path that includes the defect among multiple defect detection conductive paths LC1~LC16. According to some example embodiments, the output data pattern can be provided to an external tester, which can then determine the defect detection conductive path that includes the defect.

[0058] In some example embodiments, such as Figure 2 As shown, the semiconductor device 100 may include at least one semiconductor die. In some example embodiments, as will be discussed in more detail below... Figure 35 As shown, the semiconductor device 100 may include a plurality of semiconductor dies stacked in the vertical direction Z.

[0059] Figure 2 The portion of the defect detection conductive path CDP corresponding to the two adjacent latch circuits LCn~LCn+1 is shown.

[0060] Reference Figure 1 and Figure 2 Each defect detection conductive path may include: a horizontal line disposed in the conductive layer within the semiconductor die SD; a front vertical line connecting the horizontal line to the front latch circuit of two adjacent latch circuits; and a rear vertical line connecting the horizontal line to the rear latch circuit of two adjacent latch circuits.

[0061] For example, such as Figure 2As shown, the nth defect detection conductive path CDPn may include: a horizontal line HLn, disposed in the conductive layer ML2 of the semiconductor die SD; a front vertical line FVLn, connecting the horizontal line HLn to the front latch circuit LCn in two adjacent latch circuits LCn and LCn+1; and a rear vertical line BVLn, connecting the horizontal line HLn to the rear latch circuit LCn+1 in two adjacent latch circuits LCn and LCn+1.

[0062] The defect detection conductive path CDPn can be formed in the conductive layer ML2 of the semiconductor die SD. Figure 2 Examples are shown of a polysilicon layer PL and two metal layers ML1 and ML2 serving as conductive layers in the dielectric layer DLY above the semiconductor substrate SUB of a semiconductor die SD; however, these examples are not limited to specific embodiments. Figure 2 As shown. For example, according to some example embodiments, a semiconductor die SD may include two or more polysilicon layers and / or three or more metal layers. The conductive layer ML2 forming the horizontal line HLn may be / correspond to the uppermost metal layer of the semiconductor die SD, but the example embodiments are not limited thereto.

[0063] The front vertical line FVLn and the rear vertical line BVLn may include a conductive line pattern PC in the intermediate conductive layer and a vertical path, landing pad and / or vertical contact VC connecting the horizontal line HLn to the latch circuit LCn.

[0064] Each latch circuit LCn may include multiple transistors, such as PMOS and / or NMOS transistors, such that the gate of the transistor is formed in at least a portion of the polysilicon layer PL, corresponding to at least a portion of the polysilicon layer PL, or including at least a portion of the polysilicon layer PL, and the source and drain of the transistor are formed in at least a portion of the upper part of the semiconductor substrate SUB, corresponding to at least a portion of the upper part of the semiconductor substrate SUB, or including at least a portion of the upper part of the semiconductor substrate SUB. The front vertical line FVLn and the rear vertical line BVLn may extend in the vertical direction Z to the upper surface of the semiconductor substrate SUB.

[0065] Figure 3 This is a flowchart illustrating a method for detecting defects in a semiconductor device according to some example embodiments.

[0066] Reference Figures 1 to 3An open conductive loop can be formed in the peripheral region PREG of the semiconductor die SD, surrounding the central region CREG of the semiconductor die SD, using a defect detection circuit CDC disposed in / within the peripheral region PREG (S100). The defect detection circuit CDC includes multiple latch circuits LC1~LC16 and multiple defect detection conductive paths CDP1~CDP15. Each of the multiple defect detection conductive paths CDP1~CDP14 connects two adjacent latch circuits among the multiple latch circuits LC1~LC16. In some example embodiments, the open conductive loop can be formed by including all of the multiple latch circuits LC1~LC16 and the multiple defect detection conductive paths CDP1~CDP15; however, the example embodiments are not limited thereto. For example, in some example embodiments, as will be referred to below... Figures 22 to 32B As described above, an open conductive loop can be formed by including a portion of multiple latch circuits LC1~LC16 and multiple defect detection conductive paths CDP1~CDP15.

[0067] Under the control of the test control circuit TCC, a test write operation (S200) can be performed by sequentially transmitting the bits of the input data pattern on the positive direction FDR of the open conductive loop to store the bits of the input data pattern in multiple latch circuits LC1~LC16. The test write operation will be referred to below. Figure 4 It was described further.

[0068] Under the control of the test control circuit TCC, a test read operation (S300) can be performed by transferring bits stored in multiple latch circuits LC1~LC16 in the opposite direction of the open conductive loop (BDR) to read the output data mode. Figure 5 It was described further.

[0069] The test control circuit TCC and / or external tester can determine the defect detection conductive path (including the presence or absence of a defect) among multiple defect detection conductive paths DCP1~DCP15 by comparing the input data pattern and output data. The determination of the defect detection conductive path including the defect (i.e., the determination of the defect location) will be referred to below. Figure 6 This is described in Figure 8.

[0070] Thus, the defect detection circuit, semiconductor device, and related method according to some example embodiments can more thoroughly detect crack penetration of various types and depths using a defect detection circuit that includes multiple latch circuits and multiple defect detection conductive paths. The defect detection circuit, semiconductor device, and related method according to some example embodiments can prevent or reduce the likelihood of yield impact from defective / faulty semiconductor dies or products, and improve crack detectability.

[0071] Figure 4 This is a diagram illustrating a test write operation of a defect detection circuit according to some example embodiments. Figure 5 This is a diagram illustrating a test readout operation of a defect detection circuit according to some example embodiments.

[0072] Figure 4 and Figure 5 The transmission of bits B1 to Bm at time points T0 to Tm during the shift period tSFT is illustrated in the defect detection circuit CDC. The defect detection circuit CDC includes multiple latch circuits LC1 to LCm and multiple defect detection conductive paths CDP1 to CDPm-1 such that each defect detection conductive path connects two adjacent latch circuits. Figure 4 and Figure 5 The diagram illustrates a defect detection circuit (CDC) that does not include defects such as cracks. Figure 4 The upper part shows the composition of Figure 1 The pattern generator PTT generates and provides the input data pattern DPI to the defect detection circuit CDC during the test write operation. The pattern generator PTT outputs each bit of the input data pattern DPI for each shift cycle tSFT corresponding to the bit transfer cycle between two adjacent latch circuits. Figure 5 The upper part shows the output data pattern DPO from the defect detection circuit CDC and provided to the test control circuit TCC during the test read operation.

[0073] Reference Figure 4 At time T0, corresponding to the start time of the test write operation, the mode generator PTT applies the first bit B1 of the input data mode DPI to the front node of the first latch circuit LC1 via the input-output line IOL.

[0074] At time T1, the first latch circuit LC1 latches (stores) the first bit B1 and applies the first bit B1 to the front node of the second latch circuit LC2 through the first defect detection conductive path CDP1, which connects the rear node of the first latch circuit LC2 and the front node of the second latch circuit LC2. The mode generator PTT applies the second bit B2 of the input data mode DPI to the front node of the first latch circuit LC1 through the input-output line IOL.

[0075] At time T2, the first latch circuit LC1 latches (stores) the second bit B2 and applies it to the preceding node of the second latch circuit LC2 via the first defect detection conductive path CDP1. The second latch circuit LC2 latches the first bit B1 and applies it to the preceding node of the third latch circuit LC3 via the second defect detection conductive path CDP2, which connects the following node of the second latch circuit LC2 and the preceding node of the third latch circuit LC3. The mode generator PTT applies the third bit B3 of the input data mode DPI to the preceding node of the first latch circuit LC1 via the input-output line IOL.

[0076] At time T3, the first latch circuit LC1 latches / stores the third bit B3 and applies the third bit B2 to the front node of the second latch circuit LC2 through the first defect detection conductive path CDP1. The second latch circuit LC2 latches / stores the second bit B2 and applies the second bit B2 to the front node of the third latch circuit LC3 through the second defect detection conductive path CDP2. The third latch circuit LC3 latches / stores the first bit B1 and applies the first bit B1 to the front node of the fourth latch circuit LC4 through the third defect detection conductive path CDP3 connecting the rear node of the third latch circuit LC3 and the front node of the fourth latch circuit LC4. The mode generator PTT applies the fourth bit B4 of the input data mode DPI to the front node of the first latch circuit LC1 through the input-output line IOL.

[0077] In this way, a test write operation can be performed by sequentially transmitting the first to m bits B1~Bm of the input data mode DPI in the positive direction FDR of the open conductive loop to store the first to m bits B1~Bm of the input data mode DPI in the first to m latch circuits LC1~LCm.

[0078] At time point Tm corresponding to the completion time of the test write operation, the m-th bit Bm is stored in the first latch circuit LC1, the (m-1)-th bit Bm-1 is stored in the second latch circuit LC2, and in this way, the second bit B2 is stored in the (m-1)-th latch circuit LCm-1, and the first bit B1 is stored in the m-th latch circuit LCm.

[0079] Now refer to Figure 5 The time point T0 indicates the start time of the test read operation.

[0080] At time T1, the first latch circuit LC1 outputs the m-th bit Bm through the input-output line IOL, and the m-th to second bits Bm-B2 stored in the second to m-th latch circuits LC2-LCm are respectively applied to the adjacent latch circuits in the opposite direction BDR.

[0081] In this way, at time point Tm-2, the first latch circuit LC1 outputs the third bit B3 through the input-output line IOL, and the second bit B2 stored in the second latch circuit LC2 and the first bit B1 stored in the third to m-th latch circuits LC3~LCm are respectively applied to the adjacent latch circuits in the opposite direction BDR.

[0082] At time point Tm-1, the first latch circuit LC1 outputs the second bit B2 through the input-output line IOL, and the first bit B1 stored in the second to m-th latch circuits LC2~LCm is applied to the adjacent latch circuits in the opposite direction BDR.

[0083] At time Tm, the first latch circuit LC1 completes the output of the first bit B1 through the input-output line IOL.

[0084] In this way, a test read operation can be performed by transmitting the m to the first bits Bm to B1 stored in the first to m latch circuits LC1 to LCm on the BDR in the opposite direction of the open conductive loop to read the output data mode DPO.

[0085] At time point Tm corresponding to the completion time of the test read operation, all the first bits B1 stored in the first to m-th latch circuits LC1~LCm are propagated sequentially / serially to the adjacent latch circuits in the reverse direction during each shift period tSFT because the first bit B1 stored in the m-th latch LCm at time point T0 is propagated sequentially / serially to the adjacent latch circuits in the reverse direction during each shift period tSFT.

[0086] Figure 6 This is a diagram illustrating an example of a test write operation of a defect detection circuit according to some example embodiments. Figure 7This is a diagram illustrating an example of a test read operation of a defect detection circuit according to some example embodiments. Figure 6 Test write operation and Figure 4 The descriptions are basically the same. Figure 7 Test read operation and Figure 5 The descriptions are basically the same, so for the sake of brevity, repeated descriptions are omitted.

[0087] Figure 4 and Figure 5 This illustrates a scenario where a defect, such as a crack, is present or has already occurred in the defect detection circuit CDC (e.g., in the third defect detection conductive path CDP3 connecting the third latch circuit LC3 and the fourth latch circuit LC4). As an example, the input data mode DPI may include bits with odd-numbered values ​​of 1 and bits with even-numbered values ​​of 0.

[0088] like Figure 6 As shown, due to a defect in the third defect detection conductive path CDP3, bits of the input data mode DPI may not be transmitted to the fourth to m-th latch circuits LC4~LCm during the test write operation. For example, a defect in the third defect detection conductive path CDP3 can stop or prevent the transmission of bits from latch circuit LC3 to latch circuit LC4. As a result, at time point Tm corresponding to the completion time of the test write operation, the first latch circuit LC1 stores the m-th bit 0, the second latch circuit LC2 stores the (m-1)-th bit 1, and the third latch circuit LC3 stores the (m-2)-th bit 0.

[0089] like Figure 7 As shown, according to the test read operation, the first latch circuit LC1 outputs the m-th bit 0 at time point T1, the (m-1)-th bit 1 at time point T2, and the (m-2)-th bit 0 at time point T3. From time points T4 to Tm, the first latch circuit LC1 repeatedly outputs the (m-2)-th bit 0 stored in the third latch circuit LC3, which is located precisely before the third defect detection conductive path CDP3, which includes the defect.

[0090] Therefore, due to the defect / crack in the third defect detection conductive path CDP3, the bits of the output data mode DPO may differ from the bits of the input data mode DPI at time points T4~Tm. Thus, the test control circuit TCC and / or the external tester can determine the location of the defect (e.g., a defect detection conductive path containing the defect among multiple defect detection conductive paths CDP1~CDPm-1) by comparing the input data mode DPI and the output data mode DPO.

[0091] Figure 8A and Figure 8BThis is a diagram used to describe defect detection in a semiconductor device according to some example embodiments.

[0092] Reference Figure 8A The defect detection circuit of semiconductor device 101 may include multiple latch circuits LC1-LC12 and multiple defect detection conductive paths, such that each of the multiple defect detection conductive paths CDP1-CDP11 connects to two adjacent latch circuits among the multiple latch circuits. The multiple latch circuits LC1-LC12 and the multiple defect detection conductive paths can form an open conductive loop. For ease of explanation, Figure 8A The diagram shows twelve latch circuits LC1~LC12 arranged counterclockwise and eleven defect detection conductive paths. The number / direction of the latch circuits and the number / direction of the defect detection conductive paths can be determined in various ways.

[0093] For example, during the process of grinding and / or cutting / or sawing semiconductor wafers, defects such as cracks may exist or may have appeared at various locations. The first crack CR1 indicates a defect near the lower left corner region, the second crack CR2 indicates a defect near the lower right corner region, the third crack CR3 indicates a defect near the upper right corner region, and the fourth crack CR4 indicates a defect near the upper left corner region.

[0094] Reference Figure 8A and Figure 8B The test control circuit TCC can perform test write and test read operations as described above. A test write operation can be performed by sequentially transmitting the first to twelfth bits B1~B12 of the input data mode DPI on the positive direction FDR of the open conductive loop to store the first to twelfth bits B1~B12 of the input data mode DPI in the first to twelfth latch circuits LC1~LC12. A test read operation can be performed by transmitting the bits stored in the first to twelfth latch circuits LC1~LC12 on the negative direction BDR of the open conductive loop to read the output data mode DPO.

[0095] When the first crack CR1 has appeared / existed, the eleventh bit B11 and twelfth bit B12 of the output data mode DPO are equal to the eleventh bit B11 and twelfth bit B12 of the input data mode DPI. However, the first to tenth bits B11 of the output data mode DPO are different from the first to tenth bits B1~B10 of the input data mode DPI. Therefore, it can be determined that a defect has appeared / existed in the defect detection conductive path between the second latch circuit LC2 and the third latch circuit LC3.

[0096] When a second crack CR2 has appeared / existed, bits 8 to 12 of the output data mode DPO (B8~B12) are equal to bits 8 to 12 of the input data mode DPI (B8~B12). However, bits 1 to 7 of the output data mode DPO (B8) are different from bits 1 to 7 of the input data mode DPI (B1~B7). Therefore, it can be determined that a defect has appeared / existed in the defect detection conductive path between the fifth latch circuit LC5 and the sixth latch circuit LC6.

[0097] When the third crack CR3 is present, bits 5 to 12 of the output data mode DPO (B5~B12) are equal to bits 5 to 12 of the input data mode DPI (B5~B12). However, bits 1 to 4 of the output data mode DPO (B5) are different from bits 1 to 4 of the input data mode DPI (B1~B4). Therefore, it can be determined that a defect has appeared / exists in the defect detection conductive path between the eighth latch circuit LC8 and the ninth latch circuit LC9.

[0098] When the fourth crack CR4 is present / has already appeared, the second to twelfth bits B2~B12 of the output data mode DPO are equal to the second to twelfth bits B2~B12 of the input data mode DPI, but the first bit B2 of the output data mode DPO is different from the first bit B1 of the input data mode DPI. Therefore, it can be determined that a defect exists / has already appeared in the defect detection conductive path between the eleventh latch circuit LC11 and the twelfth latch circuit LC12.

[0099] Thus, by using a defect detection circuit that includes multiple latch circuits forming an open conductive loop and a defect detection conductive path, semiconductor devices and related methods that include a defect detection circuit can determine not only the occurrence (presence) of a defect but also its location.

[0100] Figure 9 This is a diagram illustrating a defect detection circuit according to some example embodiments.

[0101] Reference Figure 9 The defect detection circuit CDC1 may include multiple latch circuits LC1~LC6 and multiple defect detection conductive paths CDP1~CDP6, such that each defect detection conductive path connects two adjacent latch circuits. (See above reference.) Figure 1 The defect detection circuit CDC1 can be disposed in the peripheral area PREG of the semiconductor device SD to form an open conductive loop.

[0102] Figure 1The test control circuit TCC can perform a test write operation by sequentially / serially transmitting the bits of the input data mode DPI on the positive direction FDR of the open conductive loop to store the bits of the input data mode DPI in multiple latch circuits LC1~LC6, and perform a test read operation by transmitting the bits stored in the multiple latch circuits LC1~LC6 on the negative direction BDR of the open conductive loop to read the output data mode DPO.

[0103] Figure 1 The clock generator CGEN can generate a first positive clock signal FCK1, a second positive clock signal FCK2, a first negative clock signal BCK1, and a second negative clock signal BCK2. The first positive clock signal FCK1 and the first negative clock signal BCK1 can be applied to odd-numbered latch circuits LC1, LC3, and LC5, while the second positive clock signal FCK2 and the second negative clock signal BCK2 can be applied to even-numbered latch circuits LC2, LC4, and LC6.

[0104] Figure 10 It is shown Figure 9 A circuit diagram of an example embodiment of the latch circuit included in the defect detection circuit.

[0105] Figure 10 The diagram shows the portions of the defect detection circuit CDC1 corresponding to three adjacent latch circuits LCn-1, LCn, and LCn+1, as well as the two defect detection conductive paths CDPn-1 and CDPn connecting these three adjacent latch circuits LCn-1, LCn, and LCn+1. The (n-1)th latch circuit LCn-1 and the (n+1)th latch circuit LCn+1 correspond to the odd-numbered latch circuits that receive the first positive clock signal FCK1 and the first negative clock signal BCK1, while the nth latch circuit LCn corresponds to the even-numbered latch circuit that receives the second positive clock signal FCK2 and the second negative clock signal BCK2.

[0106] Reference Figure 10Each latch circuit LCI (i = n-1, n, or n+1) includes: a forward transmission gate FTG connected to the preceding node FNi; a first inverter INV1 having an input node connected to the forward transmission gate FTG and an output node connected to the first intermediate node IN1i; a second inverter INV2 having an input node connected to the first intermediate node IN1i and an output node connected to the following node BNi; a third inverter INV3 having an input node connected to the following node BNi and an output node connected to the first intermediate node IN1i; an inverting transmission gate BTG connected to the preceding node FNi; a fourth inverter INV4 having an input node connected to the second intermediate node IN2i and an output node connected to the following node BNi; a fifth inverter INV5 having an input node connected to the following node BNi and an output node connected to the second intermediate node IN2i; and a sixth inverter INV6 having an input node connected to the second intermediate node IN2i and an output node connected to the inverting transmission gate BTG.

[0107] The first positive clock signal FCK1 can be applied to the forward transmission gate FTG of the odd-numbered latch circuits LCn-1 and LCn+1, and the second positive clock signal FCK2 can be applied to the forward transmission gate FTG of the even-numbered latch circuit LCn. The first negative clock signal BCK1 can be applied to the negative transmission gate BTG of the odd-numbered latch circuits LCn-1 and LCn+1, and the second negative clock signal BCK2 can be applied to the negative transmission gate BTG of the even-numbered latch circuit LCn. Clock signals FCK1B, FCK2, BCK1, and BCK2 are the inverted clock signals of clock signals FCK1, FCK2, BCK1, and BCK2, respectively (e.g., 180 degrees out of phase). The inverted clock signals FCK1B, FCK2, BCK1, and BCK2 can be generated using the inverter (not shown) in the defect detection circuit CDC1 and / or can be generated by... Figure 1 The clock generator CGEN generates the clock.

[0108] Figure 11A , Figure 11B and Figure 12 It is shown Figure 9 Timing diagram of the operation of the defect detection circuit.

[0109] Figure 11A The test write operation of the defect detection circuit CDC1 is shown. Figure 11B The test read operation of the defect detection circuit CDC1 is shown. Figure 11A and Figure 11BThe diagram shows bits B1 to B6 latched at time points T1 to T9 at the following nodes BNn-1 of the (n-1)th latch circuit LCn-1, BNn of the nth latch circuit LCn, and BNn+1 of the (n+1)th latch circuit LCn+1. Time points T1 to T9 have an interval corresponding to half of the shift period tSFT.

[0110] Reference Figure 11A During the test write operation, Figure 1 The clock generator CGEN in the test control circuit TCC can activate the first positive clock signal FCK1 and the second positive clock signal FCK2 to have opposite phases (180 degrees out of phase), and can deactivate the first reverse clock signal BCK1 and the second reverse clock signal BCK2. As a result, as... Figure 11A As shown, bits B1 to B6 can be transferred sequentially / serially from the last node BNn-1 of the (n-1)th latch circuit LCn-1 to the last node BNn of the nth latch circuit LCn, and then from the last node BNn of the nth latch circuit LCn to the last node BNn+1 of the (n+1)th latch circuit LCn+1. For example, during a test write operation, bits B1 to B6 of the input data mode DPI can be transferred sequentially / serially in the positive direction FDR of the open conductive loop.

[0111] Reference Figure 11B During the test read operation, the clock generator CGEN can activate the first inverted clock signal BCK1 and the second inverted clock signal BCK2 with opposite phases (180 degrees out of phase), and can deactivate the first positive clock signal FCK1 and the second positive clock signal FCK2. As a result, as... Figure 11B As shown, bits B1 to B6 can be transferred sequentially / serially from the last node BNn+1 of the (n+1)th latch circuit LCn+1 to the last node BNn of the nth latch circuit LCn, and then from the last node BNn of the nth latch circuit LCn to the last node BNn-1 of the (n-1)th latch circuit LCn-1. For example, bits B1 to B6 stored in the latch circuit can be transferred sequentially / serially on the reverse direction BDR of the open conductive loop, and can be read out as the output data mode DPO during a test read operation.

[0112] Figure 12A stagnation time interval of 2*tD is shown to be implemented between the edges of the first positive clock signal FCK1 and the first negative clock signal BCK1, and between the edges of the second positive clock signal FCK2 and the second negative clock signal BCK2. By using such a stagnation time interval of 2*tD, the accuracy of defect detection can be improved by preventing / reducing the possibility that the positive transmission gate FTG and the negative transmission gate BTG of two adjacent latch circuits will be turned on simultaneously.

[0113] Figure 13 It is shown Figure 10 The circuit diagram of the inverter included in the latch circuit.

[0114] In some example embodiments, Figure 10 The first to sixth inverters INV1~INV6 in the diagram can be implemented as ordinary inverters INV, for example, Figure 13 The diagram illustrates a typical CMOS inverter. A typical inverter INV may include a p-type metal-oxide-semiconductor (PMOS) transistor PM and an n-type metal-oxide-semiconductor (NMOS) transistor NM that together invert the input signal IN to output the output signal OUT. When the input signal IN is low (e.g., "0"), the PMOS transistor PM is turned on, and the output signal OUT is pulled up by a pull-up current Ip flowing from the supply voltage VDD. When the input signal IN is high (e.g., "1"), the NMOS transistor NM is turned on, and the output signal OUT is pulled down by a pull-down current Id flowing to the ground voltage VSS. The currents Ip and Id may be based on the dimensions and / or width and / or aspect ratio of the transistors PM and NM, for example, proportional to the dimensions and / or width and / or aspect ratio of the transistors PM and NM.

[0115] Figure 14A and Figure 14B It is used to describe Figure 10 A diagram illustrating the operation of a latch circuit.

[0116] Figure 14A The diagram shows the positive transmission gate FTG of the even-numbered latch circuit LCn being turned on during a test write operation. For example, Figure 14A The situation corresponds to Figure 11A The time interval is T2~T3. During the time interval T2~T3, only the forward transmission gate FTG of the even-numbered latch circuit LCn is turned on, and the reverse transmission gate BTG of the even-numbered latch circuit LCn and the forward transmission gate FTG and reverse transmission gate BTG of the odd-numbered latch circuit LCn+1 are turned off.

[0117] As a result, Figure 11ADuring the time interval T2~T3, bits from the preceding node FNn of the latch circuit LCn can be transferred to the following node BNn of the latch circuit LCn. The dimensions, drive current, and electrical characteristics of the second inverter INV2 and the fourth inverter INV4 (represented by dashed circles) can affect bit transfer. The dimensions, drive current, and electrical characteristics of the second inverter INV2 and the fourth inverter INV4 can be set to be greater than those of the third inverter INV3 and the fourth inverter INV5. Therefore, bit transfer in the forward direction FDR can be more advantageous than bit transfer in the reverse direction BDR.

[0118] Figure 14B The diagram shows the inverted transmission gate BTG of the odd-numbered latch circuit LCn+1 being turned on during a test read operation. For example, Figure 14B The situation corresponds to Figure 11B The time interval is T1~T2. During the time interval T1~T2, only the reverse transmission gate FTG of the odd-numbered latch circuit LCn+1 is turned on, and the forward transmission gate FTG of the odd-numbered latch circuit LCn+1 and the forward transmission gate FTG and reverse transmission gate BTG of the even-numbered latch circuit LCn are turned off.

[0119] As a result, Figure 11B During the time interval T1~T2, bits from the subsequent node BNn+1 of latch circuit LCn+1 are transferred to the preceding node FNn+1 of latch circuit LCn+1. The dimensions, drive current, and electrical performance of the second inverter INV2 and the fourth inverter INV4 of latch circuit LCn+1, as indicated by the dashed circles, affect the bit transfer. The dimensions, drive current, and electrical performance of the sixth inverter INV6 can be set to be greater than the sum of the dimensions of the second inverter INV2 and the fourth inverter INV4. Therefore, bit transfer on the reverse BDR can be more advantageous than bit transfer on the forward FDR.

[0120] Figure 15 It is shown Figure 9 A circuit diagram of an example embodiment of the latch circuit included in the defect detection circuit.

[0121] Figure 15The diagram shows the portions of the defect detection circuit CDC1 corresponding to three adjacent latch circuits LCn-1, LCn, and LCn+1, as well as the two defect detection conductive paths CDPn-1 and CDPn connecting these three adjacent latch circuits LCn-1, LCn, and LCn+1. The (n-1)th latch circuit LCn-1 and the (n+1)th latch circuit LCn+1 correspond to the odd-numbered latch circuits that receive the first positive clock signal FCK1 and the first negative clock signal BCK1, while the nth latch circuit LCn corresponds to the even-numbered latch circuit that receives the second positive clock signal FCK2 and the second negative clock signal BCK2.

[0122] Reference Figure 15 Each latch circuit LCI (i = n-1, n, or n+1) includes: a forward transmission gate FTG connected to the preceding node FNi; a first tri-state inverter TSI1 having an input node connected to the forward transmission gate FTG and an output node connected to the first intermediate node IN1i; a second tri-state inverter TSI2 having an input node connected to the first intermediate node IN1i and an output node connected to the following node BNi; a third tri-state inverter TSI3 having an input node connected to the following node BNi and an output node connected to the first intermediate node IN1i; an inverting transmission gate BTG connected to the preceding node FNi; a fourth tri-state inverter TSI4 having an input node connected to the second intermediate node IN2i and an output node connected to the following node BNi; a fifth tri-state inverter TSI5 having an input node connected to the following node BNi and an output node connected to the second intermediate node IN2i; and a sixth tri-state inverter TSI6 having an input node connected to the second intermediate node IN2i and an output node connected to the inverting transmission gate BTG.

[0123] The first positive clock signal FCK1 can be applied to the forward transmission gate FTG of the odd-numbered latch circuits LCn-1 and LCn+1, and the second positive clock signal FCK2 can be applied to the forward transmission gate FTG of the even-numbered latch circuit LCn. The first negative clock signal BCK1 can be applied to the negative transmission gate BTG of the odd-numbered latch circuits LCn-1 and LCn+1, and the second negative clock signal BCK2 can be applied to the negative transmission gate BTG of the even-numbered latch circuit LCn. Clock signals FCK1B, FCK2, BCK1, and BCK2 are the inverted clock signals of FCK1, FCK2, BCK1, and BCK2, respectively. The inverted clock signals FCK1B, FCK2, BCK1, and BCK2 can be generated using the inverter (not shown) in the defect detection circuit CDC1, or can be generated by... Figure 1 The clock generator CGEN generates the clock.

[0124] The first to sixth three-state inverters TSI1~TSI6 can respectively receive, as... Figure 15 The clock signals FCK1, FCK2, BCK1, and BCK2, and the inverting clock signals FCK1B, FCK2, BCK1, and BCK2 are shown. The first to sixth tri-state inverters TSI1 to TSI6 can be enabled in response to the corresponding one of the clock signals FCK1, FCK2, BCK1, and BCK2, and the inverting clock signals FCK1B, FCK2, BCK1, and BCK2.

[0125] Figure 16 It is shown Figure 15 The circuit diagram of the three-state inverter included in the latch circuit.

[0126] Reference Figure 16 A three-state inverter (TSI) may include a first PMOS transistor MP1, a second PMOS transistor PM2, a first NMOS transistor NM1, and a second NMOS transistor NM2 connected in series between the power supply voltage VDD and the ground voltage VSS.

[0127] When the enable signal CTRL is at a logic low level (e.g., logic "0"), the node of the output signal OUT is floated and independent of the input signal IN, and the tri-state inverter TSI is disabled. The clock signal / CTRL is the inverted signal of the enable signal CTRL. When the enable signal CTRL is at a logic high level (e.g., logic "1"), the tri-state inverter TSI is enabled to output the output signal OUT by inverting the input signal IN. The first to sixth tri-state inverters TSI1~TSI6 can receive signals such as... Figure 15 One of the clock signals FCK1, FCK2, BCK1 and BCK2 shown, and the corresponding one of the inverted clock signals FCK1, FCK2, BCK1 and BCK2, is used as the enable signal CTRL.

[0128] Figure 17A and Figure 17B It is used to describe Figure 15 A diagram illustrating the operation of a latch circuit.

[0129] Figure 17A The diagram shows the positive transmission gate FTG of the even-numbered latch circuit LCn being turned on during a test write operation. For example, Figure 17A The situation corresponds to Figure 11AThe time interval is T2~T3. During the time interval T2~T3, only the forward transmission gate FTG of the even-numbered latch circuit LCn is turned on, and the inverting transmission gate BTG of the even-numbered latch circuit LCn, as well as the forward transmission gate FTG and inverting transmission gate BTG of the odd-numbered latch circuit LCn+1, are turned off. Furthermore, during the time interval T2~T3, only the first three-state inverter TSI1 and the second three-state inverter TSI2 of the even-numbered latch circuit LCn are turned on, and the third to sixth three-state inverters TSI3~TSI6 of the even-numbered latch circuit LCn and the first to sixth three-state inverters TSI1~TSI6 of the odd-numbered latch circuit LCn+1 are turned off.

[0130] As a result, Figure 11A During the time interval T2~T3, bits from the preceding node FNn of the latch circuit LCn can be transferred to the following node BNn of the latch circuit LCn. This allows a test write operation to be performed by transmitting data bits on the positive direction FDR.

[0131] Figure 17B The diagram shows the inverted transmission gate BTG of the odd-numbered latch circuit LCn+1 being turned on during a test read operation. In other words, Figure 17B The situation corresponds to Figure 11B The time interval T1~T2 is specified. During the time interval T1~T2, only the inverting transmission gate FTG of the odd-numbered latch circuit LCn+1 is turned on, while the forward transmission gate FTG of the odd-numbered latch circuit LCn+1 and the forward gate FTG and inverting transmission gate BTG of the even-numbered latch circuit LCn are turned off. Furthermore, during the time interval T1~T2, only the fifth tri-state inverter TSI5 and the sixth tri-state inverter TSI6 of the odd-numbered latch circuit LCn+1 are turned on, while the first to fourth tri-state inverters TSI1~TSI4 of the odd-numbered latch circuit LCn+1 and the first to sixth tri-state inverters TSI1~TSI6 of the odd-numbered latch circuit LCn+1 are turned off.

[0132] As a result, Figure 11B During the time interval T1~T2, bits from the subsequent node BNn+1 of latch circuit LCn+1 can be transferred to the preceding node FNn+1 of latch circuit LCn+1. Thus, a test read operation can be performed by transferring data bits on BDR in the opposite direction.

[0133] Figure 18 This is a diagram illustrating a defect detection circuit according to some example embodiments.

[0134] Reference Figure 18The defect detection circuit CDC2 may include multiple latch circuits LC1~LC6 and multiple defect detection conductive paths CDP1~CDP6, such that each defect detection conductive path connects two adjacent latch circuits. (See above reference.) Figure 1 The defect detection circuit CDC1 can be disposed in the peripheral area PREG of the semiconductor device SD to form an open conductive loop.

[0135] Figure 1 The test control circuit TCC can perform a test write operation by sequentially transmitting the bits of the input data mode DPI on the positive direction FDR of the open conductive loop to store the bits of the input data mode DPI in multiple latch circuits LC1~LC6, and perform a test read operation by transmitting the bits stored in the multiple latch circuits LC1~LC6 on the negative direction BDR of the open conductive loop to read the output data mode DPO.

[0136] Figure 1 The clock generator CGEN in the circuit can generate a transmission clock signal TCK and a direction clock signal DCK that are jointly applied to multiple latch circuits LC1~LC6.

[0137] Figure 19 It is shown Figure 18 A circuit diagram of an example embodiment of the latch circuit included in the defect detection circuit.

[0138] Figure 19 The portion of the defect detection circuit CDC1 corresponding to the two adjacent latch circuits LCn and LCn+1 and the three defect detection conductive paths CDP1n-1, CDPn and CDPn+1 is shown.

[0139] Reference Figure 19 Each latch circuit LCI (i=n or n+1) includes: a first transmission gate TG1 connected between the front node FNi and the first intermediate node IN1i; a first tri-state inverter TSI1 having an input node connected to the first intermediate node IN1i and an output node connected to the second intermediate node IN2i; a second tri-state inverter TSI2 having an input node connected to the second intermediate node IN2i and an output node connected to the first intermediate node IN1i; a second transmission gate TG2 connected between the second intermediate node IN2i and the third intermediate gate IN3i; a third tri-state inverter TSI3 having an input node connected to the third intermediate node IN3i and an output node connected to the rear node BNi; and a fourth tri-state inverter TSI4 having an input node connected to the rear node BNi and an output node connected to the third intermediate node IN3i.

[0140] The first transmission gate TG1 can be turned on in response to the transmission clock TCK, and the second transmission gate TG2 can be turned on in response to the inverted transmission clock signal TCKB, which is the inverse of the transmission clock signal TCK. The first tri-state inverter TSI1 and the fourth tri-state inverter TSI4 can be turned on in response to the direction clock signal DCK, and the second tri-state inverter TSI2 and the third tri-state inverter TSI3 can be turned on in response to the inverted direction clock signal DCKB.

[0141] Figure 20A and Figure 20B It is shown Figure 18 Timing diagram of the operation of the defect detection circuit.

[0142] Figure 20A The test write operation of the defect detection circuit CDC2 is shown. Figure 20B The test readout operation of the defect detection circuit CDC2 is shown. Figure 20A and Figure 20B The diagram shows bits B1 to B6 latched at time points T1 to T9 at the following nodes BNn of the nth latch circuit LCn and BNn+1 of the (n+1)th latch circuit LCn+1. Time points T1 to T9 have an interval corresponding to half of the shift period tSFT.

[0143] Reference Figure 20A , Figure 1 The clock generator CGEN in the test control circuit TCC can activate the transfer clock signal TCK and the direction clock signal DCK to have the same phase during the test write operation. As a result, as... Figure 20A As shown, bits B1 to B6 can be transferred sequentially in each shift cycle tSFT, and then transferred from the last node BNn of the nth latch circuit LCn to the last node BNn+1 of the (n+1)th latch circuit LCn+1. In other words, during a test write operation, bits B1 to B6 of the input data mode DPI can be transferred sequentially in the positive direction FDR of the open conductive loop.

[0144] Reference Figure 20B The clock generator CGEN can activate the transmit clock signal TCK and the direction clock signal DCK to have opposite phases during the test read operation. As a result, as... Figure 20B As shown, bits B1 to B6 can be sequentially transferred from the last node BNn+1 of the (n+1)th latch circuit LCn+1 to the last node BNn of the nth latch circuit LCn in each shift cycle tSFT. In other words, during the test read operation, bits B1 to B6 stored in the latch circuit can be sequentially transferred in the opposite direction of the open conductive loop BDR and can be read out as the output data mode DPO.

[0145] Figures 21A to 21D It is used to describe Figure 19 A diagram illustrating the operation of a latch circuit.

[0146] Figure 21A The diagram shows the first transmission gate TG1 of each latch circuit LCI (i=n or n+1) being turned on during a test write operation. In other words, Figure 21A The situation corresponds to Figure 20A The time interval is T1~T2. During the time interval T1~T2, the first transmission gate TG1 is turned on, the first tri-state inverter TSI1 is enabled, and therefore the bits of the previous node FNi are transmitted to the second intermediate node IN2i.

[0147] Figure 21B The diagram shows the second transmission gate TG2 of each latch circuit LCI (i=n or n+1) being turned on during a test write operation. In other words, Figure 21B In the case of corresponding Figure 20A The time interval is T2~T3. During the time interval T2~T3, the second transmission gate TG2 is turned on, and the third tri-state inverter TSI3 is enabled, so the bits of the second intermediate node IN2i are transmitted to the subsequent node BNi.

[0148] In this way, during the test write operation, data bits can be transferred from the previous node FNi to the next node BNi in each shift cycle tSFT, that is, transferred in the positive direction FDR.

[0149] Figure 21C The diagram shows the second transmission gate TG2 of each latch circuit LCI (i=n or n+1) being turned on during a test read operation. In other words, Figure 21C The situation corresponds to Figure 20B The time interval is T2~T3. During the time interval T2~T3, the second transmission gate TG2 is turned on, and the fourth tri-state inverter TSI4 is enabled, so the bits of the subsequent node BNi are transmitted to the second intermediate node IN2i.

[0150] Figure 21D The diagram shows the first transmission gate TG1 of each latch circuit LCI (i=n or n+1) being turned on during a test read operation. In other words, Figure 21D The situation corresponds to Figure 20B The time interval is T3~T4. During the time interval T3~T4, the first transmission gate TG1 is turned on, the second tri-state inverter TSI2 is enabled, so the bits of the second intermediate node IN2i are transmitted to the previous node FNi.

[0151] In this way, during the test read operation, data bits can be transferred from the rear node BNi to the front node FNi in each shift cycle tSFT, that is, transferred in the reverse direction BDR.

[0152] Figure 22 This is a flowchart illustrating a method for detecting defects in a semiconductor device according to some example embodiments.

[0153] Reference Figure 22 This can form a first open conductive loop including a reference latch circuit and multiple defect detection conductive paths (S110). Furthermore, a second open conductive loop including a selection latch, a reference latch circuit, and at least one of the multiple defect detection conductive paths (S120) can be formed. The multiple defect detection conductive paths can be grouped into a selection latch circuit and a reference latch circuit.

[0154] You can use the following reference Figure 23 and Figure 24 The described path selector selectively forms a first open conductive loop and a second open conductive loop.

[0155] The presence / occurrence of a defect and the range of defect detection conductive paths including the defect can be determined by performing test write and test read operations on a first open conductive loop. When it is determined that a defect exists / has occurred on the first open conductive loop, the defect detection conductive path including the defect can be determined among the plurality of defect detection conductive paths by performing test write and test read operations on a second open conductive loop.

[0156] Figure 23 This is a diagram illustrating a defect detection circuit according to some example embodiments. Figure 24 It is shown Figure 23 A diagram of an example embodiment of a path selector included in a defect detection circuit.

[0157] Reference Figure 23 The defect detection circuit CDC3 may include multiple latch circuits LC1~LC13 and multiple defect detection conductive paths CDP1~CDP12, such that each defect detection conductive path connects two adjacent latch circuits. (See above reference.) Figure 1 The defect detection circuit CDC3 can be disposed in the peripheral region PREG of the semiconductor device SD to form an open conductive loop. Figure 23 In the diagram, the dark circuit indicates the preceding node FN of each latch circuit, and the white circuit indicates the following node BN of each latch circuit.

[0158] The defect detection circuit CDC3 may also include multiple path selectors PS, which are configured to selectively include selection latch circuits LC2~LC4, LC6~LC8 and LC10~LC12 in the open conductive loop, in addition to the reference latch circuits LC1, LC5, LC9 and LC13.

[0159] Reference Figure 24 The path selector PS may include a PSW switch, a front FSW switch, and a rear BSW switch. The PSW switch can be turned on in response to the activation of the path selection signal SEL, while the front FSW switch and the rear BSW switch can be turned on in response to the deactivation of the path selection signal SEL. SELB indicates the inverted signal of the path selection signal SEL. It can be viewed from... Figure 1 The test control circuit TCC or an external tester provides the test selection signal SEL.

[0160] When the path selection signal SEL is activated, the switch PSW is turned on and the front switch FSW and the rear switch BSW are turned off. As a result, by electrically disconnecting each of the selection latch circuits LC2~LC4, LC6~LC8 and LC10~LC12 from two adjacent defect detection conductive paths CDPn and CDPn+1 and directly connecting the two defect detection conductive paths CDPn and CDPn, a first open conductive loop can be formed, including multiple defect detection conductive paths CDP1~CDP12 and only including reference latch circuits LC1, LC5, LC9 and LC13 in addition to the selection latch circuits LC2~LC4, LC6~LC8 and LC10~LC12.

[0161] When the path selection signal SEL is deactivated, it is turned off by the switch PSW, and the front switch FSW and the rear switch BSW are turned on. As a result, by electrically connecting the selection latch circuits LC2~LC4, LC6~LC8 and LC10~LC12 to the two defect detection conductive paths CDPn and CDPn+1, a second open conductive loop is formed, including multiple defect detection conductive paths CDP1~CDP12, the selection LC2~LC4, LC6~LC8 and LC10~LC12, and the reference latch circuits LC1, LC5, LC9 and LC13.

[0162] Figure 25A and Figure 25B It is used to describe Figure 23 The diagram shows the test operation of the defect detection circuit.

[0163] Figure 25A This illustrates the first open conductive loop formed when, for example, the path selection signal SEL is activated with a logic high level H. Figure 25BThis illustrates a second open conductive loop formed when, for example, the path selection signal SEL is activated with a logic low level L.

[0164] like Figure 23 As shown, the path selector PS corresponding to the selection latch circuits LC2~LC4, LC6~LC8, and LC10~LC12 can operate in response to the same path selection signal SEL. In this case, regardless of the range of defective paths, all selection latch circuits LC2~LC4, LC6~LC8, and LC10~LC12 can be included as shown in the diagram. Figure 25B In the second open conductive loop shown, where such a loop can be used... Figure 25A The first open conductive loop shown is used to determine the range of the defect path.

[0165] Figure 26 This is a diagram illustrating a defect detection circuit according to some example embodiments. Figure 27A and Figure 27B It is used to describe Figure 26 The diagram shows the test operation of the defect detection circuit. Figure 26 The defect detection circuit CDC4 and Figure 23 The defect detection circuit CDC3 is basically the same, and repeated descriptions have been omitted.

[0166] Reference Figure 26 The selection latch circuits LC2~LC4, LC6~LC8 and LC10~LC12 can be divided into: a first group GRP1, including selection latch circuits LC2~LC4 corresponding to the first path selector PS1 in response to the first path selection signal SEL1; a second group GRP2, including selection latch circuits LC6~LC8 corresponding to the second path selector PS2 in response to the second path selection signal SEL2; and a third group GRP3, including selection latch circuits LC10~LC12 corresponding to the third path selector PS3 in response to the third path selection signal SEL3.

[0167] Figure 27A This illustrates the first open conductive loop formed when, for example, the first to third path selection signals SEL1~SEL3 are activated with a logic high level H. Figure 27B The diagram illustrates a second open conductive loop formed when, for example, the first path selection signal SEL1 and the second path selection signal SEL2 are activated with a logic low level L, and only the third path selection signal SEL3 is deactivated.

[0168] For example, using Figure 27AThe first open conductive loop can define the third group, including the selection latch circuits LC10~LC12, as the defect path range containing the defect. In this case, by maintaining the activation of the first path selection signal SEL1 and the second path selection signal SEL2 and the deactivation of the third path selection signal SEL3, it is possible to achieve the following: Figure 27B This forms a second open conductive loop. As a result, the second open conductive loop may only include the selection latch circuits LC10~LC12 corresponding to the range of the defect path.

[0169] For reference Figures 22 to 27B The method described above combines coarse detection using a first open conductive loop with fine detection using a second open conductive loop, which can efficiently detect the location of defects in addition to their occurrence, and reduce testing time and power consumption.

[0170] Figure 28 This is a flowchart illustrating a method for detecting defects in a semiconductor device according to some example embodiments.

[0171] Reference Figure 28 This can form a higher open conductive loop including multiple latch circuits and multiple higher defect detection conductive paths (S130). Furthermore, a lower open conductive loop including multiple latch circuits and multiple lower defect detection conductive paths can be formed (S140). The multiple defect detection conductive paths described above can include, as will be referred to below... Figure 29 and Figure 30 The description includes multiple higher-order defect detection conductive paths and multiple lower-order defect detection conductive paths.

[0172] You can refer to the following: Figures 23 to 24 The described path selector selectively forms higher open conductive loops and lower open conductive loops.

[0173] The presence / occurrence of defects and the identification of higher defect detection conductive paths, including those containing defects, can be determined by performing test write and test read operations on higher open conductive loops. Conversely, the presence / occurrence of defects and the identification of lower defect detection conductive paths, including those containing defects, can be determined by performing test write and test read operations on lower open conductive loops.

[0174] Figure 29 This is a diagram illustrating a defect detection circuit according to some example embodiments. Figure 30 It is shown Figure 29 A cross-sectional view of the vertical structure for defect detection.

[0175] Reference Figure 29 and Figure 30The defect detection circuit CDC5 may include multiple latch circuits LC1~LCm and multiple defect detection conductive paths CDP1~CDPm-1, such that each defect detection conductive path connects two adjacent latch circuits. The defect detection circuit CDC5 may also include multiple path selectors PS. (See above reference.) Figure 1 The defect detection circuit CDC5 can be disposed in the peripheral area PREG of the semiconductor device SD to form an open conductive loop. Figure 29 In the diagram, the dark circuit indicates the preceding node FN of each latch circuit, and the white circuit indicates the following node BN of each latch circuit.

[0176] The multiple defect detection conductive paths CDP1~CDPm-1 may include multiple higher defect detection conductive paths UCDP1~UCDPm-1 and multiple lower defect detection conductive paths DCDP1~DCDPm-1. Each of the higher defect detection conductive paths UCDP1~UCDPm-1 may include a horizontal line disposed in the higher metal layer ML2, and each of the lower defect detection conductive paths DCDP1~DCDPm-1 may include a horizontal line disposed in the lower metal layer ML1. The lower metal layer ML1 may be closer to the substrate of the semiconductor device than the higher metal layer ML2.

[0177] Figure 30 The portion of the defect detection conductive path CDP5 corresponding to the two adjacent latch circuits LCn~LCn+1 is shown. The portion corresponding to these two circuits can be omitted. Figure 2 Repeated description.

[0178] For example, such as Figure 30 As shown, the higher defect detection conductive path UCDPn of the nth defect detection conductive path CDPn may include: a horizontal line UHLn, disposed in the higher conductive layer ML2; a front vertical line UFVLn, connecting the horizontal line UHLn to the front latch circuit LCn in two adjacent latch circuits LCn and LCn+1; and a rear vertical line UBVLn, connecting the horizontal line UHLn to the rear latch circuit LCn+1 in two adjacent latch circuits LCn and LCn+1. Furthermore, the lower defect detection conductive path DCDPn of the nth defect detection conductive path CDPn may include: a horizontal line DHLn, disposed in the lower conductive layer ML1; a front vertical line DFVLn, connecting the horizontal line DHLn to the front latch circuit LCn in two adjacent latch circuits LCn and LCn+1; and a rear vertical line DBVLn, connecting the horizontal line DHLn to the rear latch circuit LCn+1 in two adjacent latch circuits LCn and LCn+1.

[0179] Figure 31 It is shown Figure 29The diagram shows some example embodiments of the path selector included in the defect detection circuit.

[0180] Reference Figure 31 The path selector PS may include a front switch FSW and a rear switch BSW. The front switch FSW and rear switch BSW can, in response to the activation of the path selection signal SEL, electrically connect two adjacent higher defect detection conductive paths UCDPn and UCDPn+1 to the front node FNn and rear node BNn of the corresponding latch circuit LCn, forming a higher open conductive loop including multiple latch circuits LC1~LCm and multiple higher defect detection conductive paths UCDP1~UCDPm-1. Conversely, the front switch FSW and rear switch BSW can, in response to the deactivation of the path selection signal SEL, electrically connect two adjacent lower defect detection conductive paths DCDPn and DCDPn+1 to the front node FNn and rear node BNn of the corresponding latch circuit LCn, forming a lower open conductive loop including multiple latch circuits LC1~LCm and multiple lower defect detection conductive paths DCDP1~DCDPm-1.

[0181] Figure 32A and Figure 32B It is used to describe Figure 29 The diagram shows the test operation of the defect detection circuit.

[0182] Figure 32A This illustrates a higher open conductive loop formed when, for example, the path selection signal SEL is activated with a logic high level H. Figure 32B This illustrates a lower open conductive loop formed when, for example, the path selection signal SEL is activated with a logic low level L.

[0183] By performing the test write and test read operations as described above for each of the higher and lower open conductive loops, the vertical position of the defect can be detected in addition to its horizontal position.

[0184] Figure 33 This is a perspective view of a non-volatile memory device according to some example embodiments.

[0185] Reference Figure 33 The non-volatile memory device 102 may include a peripheral circuit region PCR in which peripheral circuitry is formed and a memory cell region MCR in which an array of memory cells is formed.

[0186] For example, the non-volatile memory device 102 may have a stacked structure in which a first semiconductor die SD1 and a second semiconductor die SD2 are stacked in the vertical direction Z. A peripheral circuit region PCR may be formed in the first semiconductor die SD1, and a memory cell region MCR may be formed in the second semiconductor die SD2. Thus, the size of the non-volatile memory device 102 can be reduced by employing a cell-on-periphery (COP) structure in which a memory cell array is stacked on the peripheral circuitry.

[0187] Figure 34 This is a diagram used to describe the manufacturing process of a stacked semiconductor device according to some example embodiments.

[0188] Reference Figure 34 Various integrated circuits can be formed in the first wafer WF1 and the second wafer WF2. Identical circuits can be integrated in the first wafer WF1 and the second wafer WF2, or different circuits can be integrated in the first wafer WF1 and the second wafer WF2. After the integrated circuits are formed in the first wafer WF1 and the second wafer WF2, the first wafer WF1 and the second wafer WF2 can be bonded. The bonded wafers WF1 and WF2 are diced and divided into multiple chips, each corresponding to a semiconductor device 1003, which includes a vertically stacked first semiconductor die SD1 and a second semiconductor die SD2 (e.g., the first semiconductor die SD1 is stacked on the second semiconductor die SD2, etc.). Each diced portion of the first wafer WF1 corresponds to the first semiconductor die SD1, and each diced portion of the second wafer WF2 corresponds to the second semiconductor die SD2.

[0189] Figure 35 This is a cross-sectional view showing a stacked semiconductor device according to some example embodiments.

[0190] Reference Figure 35 The first semiconductor die SD1 may include a first semiconductor substrate SUB1 and a first dielectric layer DLY1 in which an upper structure of the first semiconductor substrate SUB1 is formed. The second semiconductor die SD2 may include a second semiconductor substrate SUB2 and a second dielectric layer DLY2 in which an upper structure of the second semiconductor substrate SUB2 is formed. Each of the first dielectric layer DLY1 and the second dielectric layer DLY2 may include multiple conductive layers. For ease of explanation, Figure 35 A polysilicon layer PL in the first dielectric layer DLY1 and a metal layer ML2 in the second dielectric layer DLY2 are shown.

[0191] Reference above Figure 2 The described defect detection circuit can be formed in Figure 35 In the stacked structure. For the sake of simplicity, the elements are omitted. Figure 2Repeated descriptions. For example... Figure 35 As shown, the horizontal line HLn of the defect detection conductive path CDPn can be formed in the metal layer ML2 within the second dielectric layer DLY2, and the latch circuits LCn and LCn+1 can be formed in the first semiconductor substrate SUB1. In this case, the front vertical line FVLn and the rear vertical line BVLn of the defect detection conductive path CDPn can include vertical contacts VC1 and VC2 and a through silicon via TSV penetrating the second semiconductor substrate SUB2.

[0192] Figure 36 This is a block diagram illustrating a system including a semiconductor device according to some example embodiments.

[0193] Reference Figure 36 The system 3000 includes an application processor 3100, a connection unit 3200, a volatile memory device VM 3300, a non-volatile memory device NVM 3400, a user interface 3500, and a power supply 3600, all connected via a bus.

[0194] Application processor 3100 can be configured to run at least one application such as a web browser, game application, video player, etc. Connection unit 3200 can perform wired and / or wireless communication with external devices. Volatile memory device 3300 can store data processed by application processor 3100 and / or can be used as working memory. For example, volatile memory device 3300 can be or include DRAM, such as at least one of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power DDR (LPDDR) SDRAM, Graphics DDR (GDDR) SDRAM, Rambus DRAM (RDRAM), etc. Non-volatile memory device 3400 can store a boot image and other data for booting system 3000. User interface 3500 can include at least one input device (such as a keyboard, touchscreen, etc.) and at least one output device (such as a speaker, display device, etc.). Power supply 3600 can supply power voltage to system 3000. The mobile system 3000 may also include at least one of a camera image processor (CIS) and / or a storage device such as a memory card, a solid-state drive (SSD), a hard disk drive (HDD), a compact disk read-only memory (CD-ROM), etc.

[0195] According to some example embodiments, volatile memory device 3300 and / or non-volatile memory device 3400 can be implemented as described above. Figures 1 to 35 The semiconductor device for detecting the conductive path of defects.

[0196] As described above, semiconductor devices and related methods according to some example embodiments can thoroughly detect various types of crack penetration using a defect detection circuit that includes multiple latch circuits and multiple defect detection conductive paths. Semiconductor devices and related methods according to some example embodiments can prevent or reduce the likelihood of yield impact from defective and / or substandard products, and improve the detectability of crack penetration.

[0197] Some example embodiments can be applied to any electronic device and system formed using semiconductor dies. For example, the defect detection circuit according to some example embodiments can be applied to systems such as at least one of the following: memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0198] Any element disclosed above may include circuitry such as processing circuitry or implemented in circuitry such as processing circuitry, such as hardware including logic circuitry; hardware / software combination, such as a processor running software; or a combination thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0199] The foregoing description is illustrative of some exemplary embodiments and should not be construed as limiting thereto. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the inventive concept.

Claims

1. A semiconductor device, comprising: A semiconductor die, comprising a central region and a peripheral region surrounding the central region; The defect detection circuit in the peripheral area is arranged in an open conductive loop. The defect detection circuit includes multiple latch circuits and multiple defect detection conductive paths. Each of the multiple defect detection conductive paths connects two adjacent latch circuits among the multiple latch circuits. as well as The test control circuit is configured to (a) perform a test write operation by sequentially transmitting bits of an input data pattern in the positive direction of an open conductive loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) perform a test read operation by transmitting bits stored in the plurality of latch circuits in the reverse direction of the open conductive loop to read out the output data pattern. The test control circuit is configured to compare input data modes and output data modes, and determine the presence or absence of a defect detection conductive path, including the defect, among the multiple defect detection conductive paths. Each of the plurality of latch circuits includes: A forward transmission gate connected to the previous node; A first inverter having an input node and an output node, wherein the input node of the first inverter is connected to a forward transmission gate, and the output node of the first inverter is connected to a first intermediate node; A second inverter having an input node and an output node, wherein the input node of the second inverter is connected to a first intermediate node, and the output node of the second inverter is connected to a subsequent node; A third inverter has an input node and an output node, wherein the input node of the third inverter is connected to the next node, and the output node of the third inverter is connected to the first intermediate node; A reverse transmission gate connected to the previous node; A fourth inverter has an input node and an output node, wherein the input node of the fourth inverter is connected to the second intermediate node, and the output node of the fourth inverter is connected to the rear node; A fifth inverter with input and output nodes, wherein the input node of the fifth inverter is connected to the next node, and the output node of the fifth inverter is connected to the second intermediate node; and A sixth inverter has an input node and an output node. The input node of the sixth inverter is connected to the second intermediate node, and the output node of the sixth inverter is connected to the reverse transmission gate.

2. The semiconductor device according to claim 1, wherein the test control circuit comprises: The pattern generation circuit is configured to output each bit of the input data pattern in each shift cycle, the shift cycle corresponding to the bit transfer cycle between two adjacent latch circuits.

3. The semiconductor device of claim 1, wherein each of the plurality of defect detection conductive paths comprises: Horizontal lines, within the conductive layer of a semiconductor die; The front vertical line connects the horizontal line to the front latch circuit in the two adjacent latch circuits; as well as The vertical line connects the horizontal line to the rear latch circuit in the two adjacent latch circuits.

4. The semiconductor device of claim 1, wherein the test control circuit is configured to generate (a) a first positive clock signal to be applied to the positive transmission gates of the odd-numbered latch circuits, (b) a second positive clock signal to be applied to the positive transmission gates of the even-numbered latch circuits, (c) a first negative clock signal to be applied to the negative transmission gates of the odd-numbered latch circuits, and (d) a second negative clock signal to be applied to the negative transmission gates of the even-numbered latch circuits. The test control circuit is configured to activate a first positive clock signal and a second positive clock signal to have opposite phases and deactivate the first negative clock signal and the second negative clock signal during a test write operation. The test control circuit is configured to activate the first inverted clock signal and the second inverted clock signal to have opposite phases and deactivate the first positive clock signal and the second positive clock signal during a test read operation.

5. The semiconductor device of claim 4, wherein the first to sixth inverters comprise tri-state inverters, each of the tri-state inverters being configured to be enabled based on one of a first forward clock signal, a second forward clock signal, a first reverse clock signal, and a second reverse clock signal.

6. The semiconductor device according to claim 1, further comprising: The path selector circuit, each path selector circuit being configured to form a first open conductive loop including a reference latch circuit and the plurality of defect detection conductive paths, the first open conductive loop being formed by electrically disconnecting each selection latch circuit from two adjacent defect detection conductive paths and directly electrically connecting the two adjacent defect detection conductive paths to each other, each path selector circuit being configured to form a second open conductive loop including at least one selection latch circuit, a reference latch circuit and the plurality of defect detection conductive paths, the second open conductive loop being formed by electrically connecting the at least one selection latch circuit to the two defect detection conductive paths, the plurality of defect detection conductive paths being grouped into selection latch circuits and reference latch circuits.

7. The semiconductor device according to claim 1, wherein the plurality of defect detection conductive paths comprise: Multiple higher defect detection conductive paths, each of which includes a horizontal line in a higher conductive layer. as well as Multiple lower defect detection conductive paths, each comprising a horizontal line in a lower conductive layer, which is below the higher conductive layer.

8. The semiconductor device according to claim 7, further comprising: A path selector circuit, each of the path selector circuits being configured to (a) form a higher open conductive loop including the plurality of latch circuits and the plurality of higher defect detection conductive paths by electrically connecting each of the plurality of latch circuits to two adjacent higher defect detection conductive paths, and (b) form a lower open conductive loop including the plurality of latch circuits and the plurality of lower defect detection conductive paths by electrically connecting each of the plurality of latch circuits to two adjacent lower defect detection conductive paths.

9. A semiconductor device, comprising: A semiconductor die, comprising a central region and a peripheral region surrounding the central region; The defect detection circuit in the peripheral area is arranged in an open conductive loop. The defect detection circuit includes multiple latch circuits and multiple defect detection conductive paths. Each of the multiple defect detection conductive paths connects two adjacent latch circuits among the multiple latch circuits. as well as The test control circuit is configured to (a) perform a test write operation by sequentially transmitting bits of an input data pattern in the positive direction of an open conductive loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) perform a test read operation by transmitting bits stored in the plurality of latch circuits in the reverse direction of the open conductive loop to read out the output data pattern. The test control circuit is configured to compare input data modes and output data modes, and determine the presence or absence of a defect detection conductive path, including the defect, among the multiple defect detection conductive paths. Each of the plurality of latch circuits includes: The first transmission gate connects the front node and the first intermediate node; A first tri-state inverter having an input node and an output node, wherein the input node of the first tri-state inverter is connected to a first intermediate node, and the output node of the first tri-state inverter is connected to a second intermediate node; A second tri-state inverter having an input node and an output node, wherein the input node of the second tri-state inverter is connected to a second intermediate node, and the output node of the second tri-state inverter is connected to a first intermediate node; The second transmission gate is connected between the second intermediate node and the third intermediate gate; A third tri-state inverter with input and output nodes, wherein the input node of the third tri-state inverter is connected to a third intermediate node, and the output node of the third tri-state inverter is connected to a subsequent node; and A fourth tri-state inverter with an input node and an output node, wherein the input node of the fourth tri-state inverter is connected to the next node, and the output node of the fourth tri-state inverter is connected to the third intermediate node.

10. The semiconductor device of claim 9, wherein the test control circuit is configured to generate (a) a transmission clock signal to be applied to the first and second transmission gates of the plurality of latch circuits, and (b) a direction clock signal to be applied to the first through fourth tri-state inverters of the plurality of latch circuits. The test control circuit is configured to activate the transfer clock signal and the direction clock signal to have the same phase during a test write operation. The test control circuit is configured to activate the transmission clock signal and the direction clock signal to have opposite phases during the test read operation.

11. A method for detecting defects in a semiconductor device, the method comprising: An open conductive loop is formed in the peripheral region of a semiconductor die, which surrounds the central region of the semiconductor die. The open conductive loop is formed by using a defect detection circuit arranged in the peripheral region. The defect detection circuit includes multiple latch circuits and multiple defect detection conductive paths. Each of the multiple defect detection conductive paths connects two adjacent latch circuits in the multiple latch circuits. The test write operation is performed by sequentially transmitting the bits of the input data pattern in the positive direction of the open conductive loop and storing the bits of the input data pattern in the plurality of latch circuits; The test read operation is performed by transmitting bits stored in the plurality of latch circuits in the opposite direction of the open conductive loop and reading out the output data pattern; as well as By comparing the input data pattern and the output data pattern among the multiple defect detection conductive paths, the defect detection conductive path that includes both the presence and absence of defects is determined. The formation of an open conductive loop includes: A first open conductive loop is formed, comprising a reference latch circuit and the plurality of defect detection conductive paths; as well as A second open conductive loop is formed, comprising at least one of the selection latches, a reference latch circuit, and the plurality of defect detection conductive paths, which are grouped into the selection latch circuit and the reference latch circuit.

12. The method of claim 11, further comprising: By performing test write and test read operations on the first open conductive loop, it is determined whether a defect exists and the defect path range, including the defect detection conductive path, is determined. as well as In response to determining that a defect exists in the first open conductive loop, a defect detection conductive path including the defect is determined among the plurality of defect detection conductive paths by performing a test write operation and a test read operation on the second open conductive loop.

13. The method of claim 12, wherein forming the second open conductive loop comprises: All selection latch circuits are included in the second open conductive loop, regardless of the defect path range.

14. The method of claim 12, wherein forming the second open conductive loop comprises: Only the selection latch circuit corresponding to the defect path range is included in the second open conductive loop.

15. The method of claim 11, wherein the plurality of defect detection conductive paths comprise: Multiple higher defect detection conductive paths, each of which includes a horizontal line in a higher conductive layer; as well as Multiple lower defect detection conductive paths, each lower defect detection conductive path including a horizontal line set in a lower conductive layer than a higher conductive layer, and The formation of an open conductive loop includes: Forming a higher open conductive loop including the plurality of latch circuits and the plurality of higher defect detection conductive paths, and This forms a lower open conductive loop that includes the plurality of latch circuits and the plurality of lower defect detection conductive paths.

16. The method of claim 15, further comprising: By performing test write and test read operations on high-level open conductive loops, the existence of high-level defects is determined, and the range of high-level defect paths, including high-level defect detection conductive paths, is determined; and By performing test write and test read operations on lower open conductive loops, it is determined whether lower defects exist and the range of lower defect paths that include lower defect detection conductive paths is determined.

17. A defect detection circuit, comprising: Multiple latch circuits; as well as Multiple defect detection conductive paths are provided, and each of the multiple defect detection conductive paths connects to two adjacent latch circuits in the multiple latch circuits. The defect detection circuit is located in the peripheral region of the semiconductor die and arranged in an open conductive loop. This peripheral region surrounds the central region of the semiconductor. Each of the plurality of latch circuits is configured to transfer the bits stored in each latch circuit to the adjacent latch circuit in each shift cycle, either in the positive direction or the negative direction of the open conductive loop. The defect detection circuit is configured to compare the input data pattern transmitted in the positive direction of the open conductive loop and the output data pattern transmitted in the opposite direction of the open conductive loop using a test control circuit, in order to determine the presence or absence of a defect detection conductive path including a defect among the plurality of defect detection conductive paths. The defect detection circuit is configured as follows: Forming a first open conductive loop including a reference latch circuit and the plurality of defect detection conductive paths; and A second open conductive loop is formed, comprising at least one of the selection latches, a reference latch circuit, and the plurality of defect detection conductive paths, which are grouped into the selection latch circuit and the reference latch circuit.

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