Low cost three-dimensional stacked semiconductor assembly

Abstract

Disclosed herein is a low-cost three-dimensional stacked semiconductor assembly and associated methods. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having first metallization structures at the front side; (2) a semiconductor device package having a first side, a second side having a recess, and second metallization structures at the first side and contact regions exposed in the recess at the second side; (3) an interconnect structure at least partially located in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.

Description

Technical Field

[0001] This invention relates to semiconductor assemblies having stackable semiconductor packages. More specifically, some embodiments of the invention pertain to semiconductor assemblies manufactured using a three-dimensional stacking (3DS) process. In these embodiments, the semiconductor packages are directly electrically coupled to each other without the use of through-silicon vias (TSVs). Background Technology

[0002] A packaged semiconductor die, containing memory chips, microprocessor chips, logic chips, and imager chips, typically comprises a semiconductor die mounted on a substrate and encased in a protective plastic covering. Individual semiconductor dies may contain functional features such as memory cells, processor circuitry, imager devices, and other circuitry, as well as bonding pads electrically connected to these functional features. Semiconductor manufacturers are continuously reducing the size of die packages to fit within the space constraints of electronic devices. One method to increase the processing power of semiconductor packages is to vertically stack multiple semiconductor dies on top of each other within a single package. Dies in such vertically stacked packages can be electrically interconnected using TSVs, which requires multiple processing steps, such as photolithography. Summary of the Invention

[0003] In one aspect, this disclosure relates to a semiconductor device package assembly comprising: a substrate assembly having a front side and a back side, the substrate assembly having a first metallization structure at the front side; a semiconductor device package having a first side, a second side having a recess, a second metallization structure at the first side, and a contact area exposed in the recess at the second side; and an interconnect structure at least partially located in the recess at the second side of the semiconductor device package, wherein the interconnect structure includes discrete conductive particles electrically coupled to each other, and wherein the interconnect structure is electrically coupled to the second metallization structure at the contact area, and wherein the interconnect structure is electrically coupled to the first metallization structure; and a thermosetting structure between the front side of the substrate assembly and the second side of the semiconductor device package, wherein the discrete conductive particles are in a thermosetting material.

[0004] In another aspect, this disclosure relates to a semiconductor device package assembly comprising: a first semiconductor device package having a front side and a back side, the first semiconductor device package having a first metallization structure at the front side and a first substrate at the back side, the first metallization structure being exposed from the back side via a cavity; a second semiconductor device package having a first side and a second side, the second semiconductor device package having a second metallization structure at the first side and a second substrate at the second side; an interconnect structure at least partially located in the cavity, wherein the interconnect structure comprises discrete conductive particles electrically coupled to each other, and wherein the interconnect structure is electrically coupled to the first metallization structure and the second metallization structure; and a resin structure between the back side of the first semiconductor device package and the first side of the second semiconductor device package, wherein the discrete conductive particles are in a thermosetting material.

[0005] In another aspect, this disclosure relates to a semiconductor device package assembly comprising: a substrate assembly having a front side and a back side, the substrate assembly having a first metallization structure at the front side; a semiconductor device package having a first side having a contact area, a second side having a recess, and a second metallization structure at the first side and a contact area exposed in the recess at the second side; a thermosetting structure between the front side of the substrate assembly and the first side of the semiconductor device package; and an interconnect structure having discrete conductive particles electrically coupled to each other, wherein the interconnect structure is in the thermosetting structure, and wherein the interconnect structure is electrically coupled to the second metallization structure at the contact area, and wherein the interconnect structure is electrically coupled to the first metallization structure. Attached Figure Description

[0006] The following figures provide a better understanding of many aspects of the invention. The components in the figures are not necessarily drawn to scale. The focus is on illustrating the principles of the invention.

[0007] Figure 1 This is a schematic cross-sectional view of a semiconductor device package assembly according to the present invention.

[0008] Figures 2A to 2H A schematic cross-sectional view illustrating the various stages of a method for forming a semiconductor device package according to the present invention.

[0009] Figure 3 A schematic cross-sectional view illustrating a semiconductor device package assembly according to the present invention.

[0010] Figure 4 A schematic cross-sectional view illustrating another semiconductor device package assembly according to the present invention.

[0011] Figure 5 A block diagram illustrating a system incorporating a semiconductor assembly according to the present invention. Detailed Implementation

[0012] The following describes specific details of several embodiments of stacked semiconductor die packages and methods for manufacturing such die packages. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. A semiconductor device may comprise, for example, a semiconductor substrate or wafer, or a die monolithized from a wafer or substrate. Throughout this disclosure, semiconductor die is generally described in the context of a semiconductor device, but is not limited thereto.

[0013] The term "semiconductor device package" can refer to an arrangement in which one or more semiconductor devices are incorporated into a common package. A semiconductor package may include a housing or enclosure that partially or completely encloses at least one semiconductor device. The term "semiconductor device package assembly" can refer to an assembly that includes multiple stacked semiconductor device packages. As used herein, the terms "vertical," "lateral," "upper," and "lower" can refer to the relative orientation or position of features in a semiconductor device or package given the orientation shown in the figures. However, these terms should be understood to include semiconductor devices with other orientations, such as inverted or tilted orientations.

[0014] Figure 1 This is a schematic cross-sectional view of a semiconductor device package assembly 100 according to an embodiment of the present invention. As shown, the semiconductor device package assembly 100 includes a base assembly 101 stacked on a base assembly 101 and a plurality of semiconductor device packages 103. Figure 1 Four semiconductor device packages 103a to 103d are shown as examples. Although the illustrated embodiments show only four individual stacked semiconductor device packages 103, it should be understood that in other embodiments, the semiconductor device package assembly 100 may include any suitable number of stacked semiconductor device packages 103. The semiconductor device package assembly 100 includes an encapsulating material 104 covering the substrate assembly 101 and the semiconductor device packages 103. In some embodiments, the encapsulating material 104 may comprise resin, plastic, silicon, oxide, polymer, or other suitable dielectric material.

[0015] The semiconductor device package assembly 100 has a vertically compact design. For example, a substrate assembly 101 and a plurality of semiconductor device packages 103 are directly stacked together such that the bonding line thickness (BLT) between the plurality of semiconductor device packages 103 can be minimal. In some embodiments, the BLT between the substrate assembly 101 and adjacent semiconductor device packages 103 can be negligible or close to zero.

[0016] The substrate assembly 101 includes a substrate metallization structure 107 electrically coupled to a semiconductor component 102 (e.g., an integrated circuit system) within the substrate assembly 101. The substrate assembly 101 may be a circuit board or other type of substrate typically used for semiconductor device packaging, or it may be a semiconductor device such as a logic device, memory device, or processor. As shown, the substrate assembly 101 has a first side 1011 (e.g., a front / active side) and a second side 1013 (e.g., a back / non-active side) opposite the first side 1011. The substrate assembly 101 may further be coupled to external components via discrete conductive connectors 108 (e.g., solder balls).

[0017] like Figure 1 As shown, the semiconductor device package 103 is connected via interconnect structure 111 ( Figure 1 Four interconnect structures 111a to 111d are shown as examples, electrically coupled to each other and to the substrate assembly 101. Each of the semiconductor device packages 103 has a metallization structure 105 configured to be electrically coupled to the interconnect structures 111. Figure 1 Four metallization structures 105a to 105d are shown as examples. As shown, the (bottommost) interconnect structure 111a is electrically coupled to the substrate metallization structure 107 at the contact region 1071 of the substrate metallization structure 107. With this arrangement, the substrate assembly 101 and the semiconductor device package 103 can be electrically coupled via the interconnect structure 111 without the use of a TSV.

[0018] In some embodiments, the substrate metallization structure 107 may be a metal pad (e.g., an aluminum pad). In other embodiments, the substrate metallization structure 107 may comprise copper or other suitable metals or conductive materials. The substrate metallization structure 107 may include one or more metallization layers defining traces, vias, and / or planes.

[0019] In the illustrated embodiment, the substrate metallization structure 107 extends from the surface of the substrate assembly 101 at the front side 1011. In other embodiments, the substrate metallization structure 107 may (i) be flush with the surface at the front side 1011 of the substrate assembly 101, or (ii) be embedded in the substrate assembly 101, wherein the contact area 1071 is exposed for coupling with the (lowest) interconnect structure 111a.

[0020] Each of the interconnecting structures 111 may contain discrete conductive particles 109 electrically coupled to each other. As shown, the conductive particles 109 are discrete elements in the sense that they are individual components movable to contact each other. The conductive particles 109 are in a thermosetting material 114, which may be a polymer-based fluid material that can become solid or harden upon heating, being placed under pressure, being treated with chemicals, and / or being exposed to radiation. The thermosetting material 114 may comprise resins, plastics, and / or other suitable thermosetting materials. Figure 1 As shown, the substrate component 101 and the semiconductor device package 103 are separated by thermosetting material 114. The interconnect structure 111 and the thermosetting material 114 can be formed using solder anisotropic conductive adhesive (ACP) or solder anisotropic conductive film (ACF). See below for reference. Figures 2E to 2H The related methods are discussed in detail.

[0021] exist Figure 1 In the illustrative embodiment shown, an individual semiconductor device package 103 has a first side 1031 (e.g., front / active / front side) and a second side 1033 (e.g., back / non-active side) opposite the first side 1031. As shown, the individual semiconductor device package 103 may include a passivation layer 1035 at the first side 1031 of the semiconductor device package 103 to protect the semiconductor device package 103. In some embodiments, the passivation layer 1035 may comprise an oxide layer, an inert layer (e.g., a layer unlikely to chemically react or corrode with air), or other suitable protective layer. Alternatively, the passivation layer 1035 may be a pre-formed protective film.

[0022] In the illustrated embodiment, individual metallization structures 105a of the semiconductor device package 103a are within a passivation layer 1035. The semiconductor device package 103a includes a first semiconductor region 1037 and a second semiconductor region 1039. In some embodiments, the first semiconductor region 1037 may include complementary metal-oxide-semiconductor (CMOS), logic circuitry, control circuitry, and / or other suitable components. In some embodiments, the second semiconductor region 1039 may include memory components, such as NAND memory components, dynamic random access memory (DRAM) components (e.g., master DRAM components or slave master DRAM components), low-power (LP) DRAM components, stackable cross-point (SXP) memory components, etc. In some embodiments, the first semiconductor region 1037 and the second semiconductor region 1039 may be implemented as a single semiconductor layer.

[0023] Individual semiconductor device packages 103 may also include a redistribution structure 106 located at a first side 1031 of the semiconductor device package 103. The redistribution structure 106 is electrically coupled to a metallization structure 105 (an element 105a of the semiconductor device package 103a), and thus further electrically coupled to an interconnect structure 111. The redistribution structure 106 may be further electrically coupled to a semiconductor component 1032 (e.g., an integrated circuit system, etc.) in a second semiconductor region 1039 of the semiconductor device package 103a.

[0024] A recess 113 (or cavity, trench, or recess) is formed at a second side 1033 of the semiconductor device package 1033. The recess 113 exposes a metallization structure 105a at the second side 1033 to expose a contact area 1131. At least a portion of an interconnect structure 111a may reside in the recess 113 and be electrically coupled to the metallization structure 105a at the contact area 1131. In some embodiments, the recess 113 may be formed by laser cutting, plasma drilling, etching, photolithography, and / or other suitable processes. In some embodiments, the recess 113 may be formed during a wire-scribing or track-sawing process (e.g., a process for cutting a wafer into multiple dies).

[0025] like Figure 1 As shown, at least a portion of the interconnect structure 111a is located in the recess 113. With this arrangement, the present invention enables the substrate assembly 101 to be electrically coupled to the semiconductor device package 103 without using TSVs in the substrate assembly 101 or the semiconductor device package 103.

[0026] In some embodiments, the metallization structure 105 may comprise layers of aluminum, copper, or other suitable metals or conductive materials. The metallization structure 105 may be formed during a back-to-end (BEOL) manufacturing process and may include multiple traces, vias, or other electrical feature layers.

[0027] In some embodiments, the semiconductor device package assembly 100 may be a memory device in which the semiconductor device package 103 is a memory die (e.g., DRAM, LPDRAM, SRAM, flash memory, etc.). In some embodiments, the substrate assembly 101 may be a logic device, a processor, and / or another memory device.

[0028] Figures 2A to 2H This is a schematic cross-sectional view of each stage of a method for manufacturing a semiconductor device package 103a according to an embodiment of the present invention. (Through) Figures 2A to 2H Similar icons and symbols refer to similar components. (See reference.) Figure 2AAt this stage of the method, the semiconductor device package 103a has a first side 1031 (e.g., front / active side) and a second side 1033 (e.g., back / non-active side) opposite the first side 1031. The semiconductor device package 103a includes a substrate 2037 and a dielectric material 2035 on the substrate 2037. The semiconductor device package 103a includes a metallization structure 105a that may be formed in the dielectric material 2035 during the BEOL manufacturing process. A semiconductor component 1032 may be in and / or on the substrate 2037 and electrically coupled to a vertical via 220. The vertical via 220 extends from the semiconductor component 1032 and through the dielectric material 2035. At this stage, the semiconductor component 1032 is not electrically coupled to the metallization structure 105a.

[0029] Figure 2B The semiconductor device package 103a is shown after a redistribution structure 106 has been formed at the first side 1031 of the package. The redistribution structure 106 is electrically coupled to a metallization structure 105a and a vertical via 220 to electrically couple a semiconductor component 1032 to the metallization structure 105a. The redistribution structure 106 has a front opening 222 formed at the first side 1031 of the package to expose the metallization structure 105a. In some embodiments, the lateral dimension LD of the front opening 222 may be about 40 μm, or in other embodiments, the lateral dimension LD may vary from 10 μm to 50 μm.

[0030] Figure 2C The image shows a semiconductor device package 103a with a recess 113 formed at a second side 1033 in a substrate 2037. The recess 113 extends completely through the substrate 2037, exposing a metallization structure 105a at the second side 1033 to form a contact region 1131. The recess 113 may have a first sidewall 224 and a second sidewall 226, respectively. The first sidewall 224 and the second sidewall 226 facilitate the formation of an interconnect structure 111 in the recess 113 by allowing conductive particles in the thermosetting material to flow toward the contact region 1131. See below for reference. Figures 2E to 2H The process of forming the interconnect structure 111a is described in detail. In some embodiments, the slopes of the first sidewall 224 and the second sidewall 226 may be substantially the same, or the slopes of the first sidewall 224 and the second sidewall 226 may be different.

[0031] Figure 2DThe semiconductor device package 103a is described after the substrate 2037 has been thinned. The substrate 2037 may be thinned such that the semiconductor device package 103a has a thickness T between the thinned surface 219 and the first side 1031 of the semiconductor device package 103a. In some embodiments, the thickness T may vary from 5 to 30 μm, and for example, not exceeding 30 μm, 25 μm, 20 μm, 15 μm, 10 μm, or 5 μm. At this stage of the process, the semiconductor device package 103 may be stacked on a substrate assembly (…). Figure 2E and 2F ) stacked on top of each other or on top of each other ( Figure 2G and 2H ).

[0032] By thinning the substrate 2037 to the aforementioned extent, the metallization structure 105a of the semiconductor device package 103a can be accessed and electrically coupled to other metallization structures or semiconductor components of the stacked semiconductor device package without the use of a TSV. Generally, the minimum thickness of the semiconductor substrate for forming a TSV in the semiconductor structure can be about 50 μm. This is 200% to 1000% thicker than the semiconductor device package 103a of the present invention. Therefore, the improved method provided by the present invention is advantageous, at least because the improved method provides a semiconductor device package with a smaller thickness (or vertical dimension) and achieves stacking without forming a TSV. It is particularly advantageous for manufacturing compact semiconductor devices or packages.

[0033] Figure 2E Demonstrated in semiconductor device package 103a and substrate components (e.g., Figure 1 Interconnection structures are formed between the base components 101 in the middle (e.g., Figure 1 This is a stage in the process of interconnecting the structure 111a). As shown, a thermosetting material 114 is located between the semiconductor device package 103a and the substrate assembly 101. The thermosetting material 114 may be a polymer-based fluid material that becomes solid or hardens when heated, subjected to pressure, treated with chemicals, and / or irradiated. The thermosetting material 114 may comprise resins, plastics, and / or other suitable thermosetting materials. As shown, conductive particles 109, such as metal particles or carbon nanotubes, are disposed in the thermosetting material 114. The conductive particles 109 are (typically) uniformly distributed in the thermosetting material 114 at this stage. The conductive particles 109 may be solder particles. In some embodiments, the conductive particles 109 may be other metal particles or other suitable conductive particles. In some embodiments, the thermosetting material 114 may be solder ACP or ACF manufactured by Sekisui Chemical Co., Ltd. of Tokyo, Japan.

[0034] To form the interconnect structure 111a, pressure can be applied to the semiconductor device package 103a in directions P1 and P2. By doing so, conductive particles 109 flow toward the center of the thermosetting material 114 and are then retained in the groove 113. The conductive particles 109 in the groove 113 then begin to couple with each other to form the interconnect structure 111a. In the illustrated embodiment, directions P1 and P2 may be substantially parallel. In some embodiments, directions P1 and P2 are not parallel, depending on various factors such as the distribution of particles in the thermosetting material 114 and the location of the semiconductor component 1032. In some embodiments, heat or a magnetic field may be applied during this stage to facilitate the flow of the conductive particles 109.

[0035] Figure 2F This illustrates a stage in the process of forming an interconnect structure 111a between the semiconductor device package 103a and the substrate assembly 101. As shown, at least a portion of the conductive particles 109 are in the recess 113. Therefore, the semiconductor device package 103a and the substrate assembly 101 are electrically coupled through the interconnect structure 111a. For example, the semiconductor component 1032 in the semiconductor device package 103a may be electrically coupled to the substrate metallization structure 107 via the interconnect structure 111a, the metallization structure 105a, the redistribution structure 106, and the vertical via 220.

[0036] Figure 2G The semiconductor device package 103a is shown with another semiconductor device package (e.g., Figure 1 Interconnect structures are formed between semiconductor device packages 103b in the package (e.g., Figure 1 The process involves interconnecting the structure 111b in the semiconductor device package 103b. The package has a metallization structure 105b on its front side and a recess 213 on its back side. The metallization structure 105b is electrically coupled to a redistribution structure 206, which is electrically coupled to a semiconductor component 2032 within the package via a vertical via 222. The recess 213 exposes the metallization structure 105b from the back side.

[0037] As shown, thermosetting material 214 is located between semiconductor device packages 103a and 103b. Thermosetting material 214 may be a polymer-based fluid film or adhesive, and conductive particles 209 are distributed (e.g., uniformly distributed) within thermosetting material 214. Conductive particles 209 may be solder particles. In some embodiments, conductive particles 209 may be metal particles or other suitable conductive particles (e.g., carbon nanotubes). To form interconnect structure 111b, pressure, heat, and / or a magnetic field may be applied to semiconductor device packages 103a, 103b, causing the conductive particles 209 to move toward the center of thermosetting material 214 and be positioned (retained) in grooves 213. The conductive particles 209 in grooves 213 are electrically and physically coupled to each other to form interconnect structure 111b.

[0038] Figure 2H This illustrates a stage of the process following the formation of an interconnect structure 111b between semiconductor device packages 103a and 103b. As shown, the interconnect structure 111b is formed in a recess 213 by at least a portion of conductive particles 209 in a thermosetting material 214. Semiconductor device packages 103a and 103b are electrically coupled via the interconnect structure 111b. For example, a semiconductor component 1032 in semiconductor device package 103a may be electrically coupled to a semiconductor component 2032 in semiconductor device package 103b via the interconnect structure 111b, metallization structures 105a and 105b, redistribution structures 106 and 206, and vertical vias 220 and 222.

[0039] Figure 3 A schematic cross-sectional view illustrating the semiconductor device package assembly 300 according to the present invention. Compared to... Figure 1 Semiconductor device package assembly 100 described herein, and semiconductor device package assembly 300 further include an intermediate semiconductor device package 303 between a substrate assembly 101 and stacked semiconductor device packages 103a to 103d. The intermediate semiconductor device package 303 has a structure similar to those of the stacked semiconductor device packages 103a to 103d, except that the intermediate semiconductor device package 303 does not have a recess on its back side. The intermediate semiconductor device package 303 has a metallization layer 305 electrically coupled to metallization structures 105a to 105d in the stacked semiconductor device packages 103a to 103d via interconnect structures 111a to 111d. As shown, the metallization layer 305 may further be electrically coupled to the substrate assembly 101 via one or more bonding lines 319. Semiconductor device package assembly 300 includes an encapsulating material 304 covering the substrate assembly 101, the intermediate semiconductor device package 303, the stacked semiconductor device packages 103a to 103d, and the bonding lines 319.

[0040] Figure 4A schematic cross-sectional view illustrating the semiconductor device package assembly 400 according to the present invention. Compared to Figure 3 The semiconductor device package assembly 300 and semiconductor device package assembly 400 described herein have an "inverted" arrangement. More precisely, the stacked semiconductor device packages 103a to 103d and the intermediate semiconductor device package 303 are "inverted," such that semiconductor device package 103d is the "closest" semiconductor device package relative to the substrate assembly 101 (in Figure 3 In this context, semiconductor device package 103d is the "farthest" semiconductor device package relative to substrate component 101. As shown, the metallization structure 105d of semiconductor device package 103d can be electrically coupled to the substrate metallization structure 107 of substrate component 101 via interconnect structure 411 in resin structure 414 (see, for example...). Figure 1 With this arrangement, the metallization layer 305 of the intermediate semiconductor device package 303 can be electrically coupled to the substrate metallization structure 107 of the substrate assembly 101 without the use of TSVs or bonding wires.

[0041] References above Figures 1 to 4 Any of the semiconductor devices with the described features can be incorporated into any of a large number of larger and / or more complex systems, representative examples of which are... Figure 5 The system 500 is schematically shown in the diagram. System 500 may include a processor 501, a memory 503 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 505, and / or other subsystems or components 507. (See above reference) Figures 1 to 4 The described semiconductor assemblies, devices, and device packages may be included in Figure 5 The resulting system 500 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 500 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, networked appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and microcomputers. Additional representative examples of system 500 include lights, cameras, vehicles, etc. Regarding these and other examples, system 500 can be housed in a single unit or distributed, for example, across multiple interconnected units via a communication network. Therefore, components of system 500 can include local and / or remote memory storage devices and any of a wide variety of suitable computer-readable media.

[0042] This disclosure is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments have been disclosed herein for illustrative purposes, various equivalent modifications are possible without departing from the invention, as will be recognized by those skilled in the art. In some instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the invention. Although the steps of a method may be presented in a specific order herein, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the invention disclosed in the context of a particular embodiment may be combined or removed in other embodiments. Furthermore, while advantages associated with certain embodiments of the invention may have been disclosed in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

[0043] Throughout this disclosure, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” include a plural of indicators. Similarly, unless the word “or” is explicitly limited to meaning only a single item other than those in a list of two or more items, its use in this list should be interpreted as including any single item in (a) the list, all items in (b) the list, or any combination of items in (c) the list. Furthermore, the term “comprising” throughout is used to mean at least one or more of the described features, such that any larger number of identical features and / or other features of additional types are not excluded. References herein to “an embodiment,” “some embodiments,” or similar expressions mean that a particular feature, structure, operation, or characteristic described in connection with an embodiment may be included in at least one embodiment of the inventive technique. Therefore, the appearance of such phrases or expressions herein does not necessarily refer to the same embodiment. Moreover, in one or more embodiments, the various particular features, structures, operations, or characteristics may be combined in any suitable manner.

[0044] As will be understood from the foregoing, although specific embodiments of the invention have been described herein for illustrative purposes, various modifications may be made without departing from the scope of the invention. The invention is not limited to the appended claims.

Claims

1. A semiconductor device package assembly comprising: A base assembly having a front side and a back side, the base assembly having a first metallization structure at the front side; A semiconductor device package having a first side, a second side having a groove, a second metallization structure at the first side, and a contact area exposed in the groove at the second side; and An interconnect structure, at least partially located in the recess at the second side of the semiconductor device package, wherein the interconnect structure comprises discrete conductive particles electrically and physically coupled to each other, and wherein a portion of the discrete conductive particles of the interconnect structure is directly coupled to the second metallization structure at the contact area, and wherein another portion of the discrete conductive particles of the interconnect structure is directly coupled to the first metallization structure. and A thermosetting material between the front side of the substrate assembly and the second side of the semiconductor device package, wherein the discrete conductive particles are present in the thermosetting material.

2. The semiconductor device package assembly of claim 1, wherein the semiconductor device package is electrically coupled to the substrate assembly only via the first metallization structure and the second metallization structure without through-silicon vias.

3. The semiconductor device package assembly of claim 1, wherein the semiconductor device package includes a passivation layer on the first side, and wherein the second metallization structure is in the passivation layer.

4. The semiconductor device package assembly of claim 3, wherein the semiconductor device package includes a redistribution structure on the passivation layer, and wherein the redistribution structure is electrically coupled to the second metallization structure.

5. The semiconductor device package assembly of claim 1, wherein the first metallization structure comprises aluminum bonding pads.

6. The semiconductor device package assembly of claim 1, wherein the semiconductor device package includes a complementary metal-oxide-semiconductor (CMOS) on the first side and a memory component on the second side.

7. The semiconductor device package assembly of claim 6, wherein the memory component comprises one of the following: a NAND memory component, a dynamic random access memory (DRAM) component, a low-power DRAM component, or a stackable cross-point (SXP) memory component.

8. The semiconductor device package assembly of claim 4, wherein the redistribution structure forms a front opening on the first side, and the front opening has a lateral dimension of about 40 µm.

9. The semiconductor device package assembly of claim 4, wherein the redistribution structure forms a front opening on the first side, and the front opening has a lateral dimension in the range of 10 µm to 50 µm.

10. The semiconductor device package assembly of claim 1, wherein the recess is defined by the contact area, the first sidewall, and the second sidewall opposite to the first sidewall.

11. The semiconductor device package assembly of claim 10, wherein the first sidewall has a first slope, and wherein the second sidewall has a second slope different from the first slope.

12. The semiconductor device package assembly of claim 10, wherein the first sidewall has a first slope, and wherein the second sidewall has a second slope having the same slope as the first slope.

13. The semiconductor device package assembly of claim 1, wherein the semiconductor device package has a vertical dimension of less than 30 µm.

14. The semiconductor device package assembly of claim 1, wherein the semiconductor device package has a vertical dimension of less than 10 µm.

15. A semiconductor device package assembly comprising: A first semiconductor device package has a front side and a back side, the first semiconductor device package having a first metallization structure at the front side and a first substrate at the back side, the first metallization structure being exposed from the back side via a cavity; A second semiconductor device package has a first side and a second side, the second semiconductor device package having a second metallization structure at the first side and a second substrate at the second side; An interconnect structure, at least partially located in the cavity, wherein the interconnect structure comprises discrete conductive particles electrically and physically coupled to each other, and wherein a portion of the discrete conductive particles of the interconnect structure is directly coupled to the first metallized structure, and wherein another portion of the discrete conductive particles of the interconnect structure is directly coupled to the second metallized structure. and A resin structure located between the back side of the first semiconductor device package and the first side of the second semiconductor device package, wherein the discrete conductive particles are present in the resin structure.

16. The semiconductor device package assembly of claim 15, wherein the first semiconductor device package and the second semiconductor device package have a vertical dimension of less than 10 µm.

17. The semiconductor device package assembly of claim 15, wherein the interconnect structure has a lateral dimension of less than 20 µm at both its contact with the first metallization structure and its contact with the second metallization structure.

18. The semiconductor device package assembly of claim 15, wherein the first semiconductor device package is electrically coupled to the second semiconductor device package only via the first metallization structure and the second metallization structure without silicon through-hole (STB) connection.

19. A semiconductor device package assembly comprising: A base assembly having a front side and a back side, the base assembly having a first metallization structure at the front side; A semiconductor device package having a first side with a contact area, a second side with a groove, a second metallization structure at the first side, and a contact area exposed in the groove at the second side; and A thermosetting structure between the front side of the substrate assembly and the first side of the semiconductor device package; and An interconnect structure having discrete conductive particles electrically and physically coupled to each other, wherein the interconnect structure is in the thermosetting structure, and wherein a portion of the discrete conductive particles of the interconnect structure is directly coupled to the second metallized structure at the contact region, and wherein another portion of the discrete conductive particles of the interconnect structure is directly coupled to the first metallized structure.

20. The semiconductor device package assembly of claim 19, wherein the interconnect structure is a first interconnect structure, the semiconductor device package is a first semiconductor device package, the thermosetting structure is a first thermosetting structure, the discrete conductive particles are a first group of conductive particles, and the semiconductor device package assembly further comprises: A second interconnect structure is electrically coupled to a second metallized structure at a contact area exposed in the groove, the second interconnect structure having a second set of discrete conductive particles electrically coupled to each other; A second semiconductor device package having a third metallization structure electrically coupled to the second interconnect structure; A second thermosetting structure is located between the first semiconductor device package and the second semiconductor device package, wherein the second set of conductive particles is located within the second thermosetting structure.

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