Channel and body region formation for semiconductor devices

Abstract

This disclosure relates to channel and body region formation for semiconductor devices. Systems, methods, and apparatus are provided for vertically forming layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeated iterations to form a vertical stack, and for forming vertical openings using an etching process to expose vertical sidewalls in the vertical stack. A seed material selective for the semiconductor material is deposited on the vertical stack and the vertical sidewalls in the vertical stack, and the seed material is processed such that it advances within the semiconductor material, thereby transforming the crystal structure of a portion of the semiconductor material.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically to channel and body region formation for semiconductor devices. Background Technology

[0002] Memory is frequently implemented in electronic systems such as computers, mobile phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is applied and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, less semiconductor space can be used to fabricate memories containing DRAM arrays. A corresponding memory cell for DRAM can contain access devices, such as transistors, having a first source / drain region and a second source / drain region separated by a channel and a body region. The gate can be opposite the channel region and separated from it by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. A DRAM cell can contain memory nodes, such as capacitor cells, coupled to digit lines via access devices. Access devices can be activated (e.g., to select a cell) by access lines coupled to access transistors. Capacitors can store charge corresponding to the data value (e.g., logic "1" or "0") of the corresponding cell. Summary of the Invention

[0004] On one hand, this disclosure provides a method comprising: vertically forming layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeated iterations to form a vertical stack; forming vertical openings using an etchant process to expose vertical sidewalls in the vertical stack; depositing seed material on the vertical sidewalls in the vertical stack; and processing the vertical stack under temperature and time parameters such that the seed material on the sidewalls of the semiconductor material advances a first distance toward the semiconductor material to transform a portion of the semiconductor material at the first distance into a crystalline structure.

[0005] On the other hand, this disclosure further provides a method comprising: vertically depositing layers of oxide material, silicon material, and nitride material in repeated iterations to form a vertical stack; forming vertical openings using an etchant process to expose vertical sidewalls in the vertical stack; selectively depositing a metal seed material to form metal silicides on the vertical sidewalls of the silicon material in the vertical openings of the vertical stack; and processing the vertical stack under temperature and time parameters such that the metal silicides advance horizontally through the silicon material defined by the oxide material and the nitride material, and transform a portion of the silicon material from an amorphous silicon structure to a monocrystalline silicon structure along a length of a first distance from the vertical opening.

[0006] In another aspect, this disclosure further provides a method comprising: vertically depositing layers of oxide material, amorphous silicon material, and nitride material in repeated iterations to form a vertical stack; forming a vertical opening using an etchant process to expose vertical sidewalls in the vertical stack; selectively depositing a metal seed material on the vertical sidewalls of the amorphous silicon to form a metal silicide using an atomic layer deposition (ALD) process; and processing the vertical stack under temperature and time parameters such that the metal silicide advances horizontally through the amorphous silicon at a first distance from the vertical opening, recrystallizing the amorphous silicon into a monocrystalline silicon structure to define a first region in the vertical stack.

[0007] In another aspect, this disclosure further provides a memory cell array comprising: a plurality of access transistors stacked on top of each other, each of the access transistors including a first source / drain region, a second source / drain region, and a channel region and a body region arranged horizontally therebetween, wherein the channel region and the body region are each formed of a single-crystal semiconductor material; at least one access line extending vertically and coupled to each channel region of the plurality of access transistors with the intervention of a gate dielectric; a plurality of storage capacitors stacked on top of each other, each of the plurality of storage capacitors being placed horizontally and coupled to a corresponding second source / drain region of the second source / drain region of the plurality of access transistors; a plurality of digit lines, each of the plurality of digit lines being coupled to a corresponding first source / drain region of the first source / drain region of the plurality of access transistors; and a body contact extending vertically and coupled to each body region of the plurality of access transistors. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a vertical three-dimensional (3D) memory according to many embodiments of the present disclosure.

[0009] Figure 2 This is a perspective view showing the channel and body regions of a three-node access device of a semiconductor device according to many embodiments of the present disclosure.

[0010] Figure 3 This is a perspective view showing the channel and body regions of a three-node access device of a semiconductor device according to many embodiments of the present disclosure.

[0011] Figures 4A-4F This is a cross-sectional view of a vertically stacked array of memory cells at various stages of a semiconductor manufacturing process, according to many embodiments of the present disclosure, to form channels and body regions for a semiconductor device.

[0012] Figures 5A-5B An example method is shown for forming a vertically stacked array of memory cells with channels and body regions for semiconductor devices and vertically oriented access lines at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure.

[0013] Figures 6A to 6E An example method is shown for forming a vertically stacked array of memory cells having channels and body regions for semiconductor devices at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure.

[0014] Figures 7A to 7E An example method is shown for forming a vertically stacked array of memory cells having channels and body regions for semiconductor devices at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure.

[0015] Figures 8A to 8E An example method is shown for forming a vertically stacked array of memory cells having channels and body regions for semiconductor devices at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure.

[0016] Figure 9 This is a block diagram of a device in the form of a computing system including a memory device, according to many embodiments of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure describe channel and body region formation for a semiconductor device. The channel and body region are formed using horizontal access devices in a vertically stacked array of memory cells. The horizontal access devices are integrated with vertically oriented access lines and with horizontally oriented digit lines. The channel provides improved electron mobility due to the increased grain size and decreased grain boundary density of the amorphous silicon material in the channel. The reduced grain boundary density also reduces electron-hole pair generation and decreases the value of the cutoff current (Ioff). Furthermore, the metal-induced lateral crystallization (MILC) distance can be such that it covers only the channel region. This reduces annealing process time compared to other processes not disclosed herein.

[0018] The figures in this document follow a numbering convention, where one or more first digits correspond to the figure's figure number, and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. For example, figure numeral 104 can refer to... Figure 1 The element "04" in the text, and similar elements can be referenced as Figure 2 In Figure 204, multiple similar elements can be referenced using a figure number followed by a hyphen and another number or letter. For example, 302-1 can be referenced... Figure 3 Component 302-1 can be referenced as 302-2, while 302-2 can refer to component 302-2, which may be similar to component 302-1. Such similar components can typically be referenced without hyphens and additional numbers or letters. For example, components 302-1 and 302-2, or other similar components, can generally be referenced as 302.

[0019] Figure 1 This is a block diagram of an apparatus according to many embodiments of the present disclosure. Figure 1 A circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure is shown. Figure 1 A cell array with multiple sub-cell arrays 101-1, 101-2, ..., 101-N is shown. The sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each sub-cell array (e.g., sub-cell array 101-2) can contain multiple access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines). Furthermore, each sub-cell array (e.g., sub-cell array 101-2) can contain multiple bit lines 107-1, 107-2, ..., 107-P (which may also be referred to as bit lines, data lines, or read lines). Figure 1The diagram illustrates digital lines 107-1, 107-2, ..., 107-P extending in a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, access lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0020] A memory cell (e.g., 110) may include access means (e.g., access transistors) and storage nodes (e.g., storage capacitors) located at the intersections of each access line 103-1, 103-2, ..., 103-Q and each digital line 107-1, 107-2, ..., 107-P. The memory cell can be written to or read from using the access lines 103-1, 103-2, ..., 103-Q and the digital lines 107-1, 107-2, ..., 107-P. Digital lines 107-1, 107-2, ..., 107-P can electrically interconnect memory cells along parallel columns of each sub-cell array 101-1, 101-2, ..., 101-N, and access lines 103-1, 103-2, ..., 103-Q can electrically interconnect memory cells along vertical columns of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) can be located between an access line (e.g., 103-2) and a digital line (e.g., 107-2). Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-P.

[0021] The digit lines 107-1, 107-2, ..., 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. The digit lines 107-1, 107-2, ..., 107-P may extend in a first direction (D1) 109. The digit lines 107-1, 107-2, ..., 107-P (e.g., 101-2) in a subcell array may be spaced apart from each other in a vertical direction (e.g., a third direction (D3) 111).

[0022] Access lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending relative to the substrate in a vertical direction (e.g., a third direction (D3) 111). Access lines (e.g., 101-2) in a subcell array may be spaced apart from each other in a first direction (D1) 109.

[0023] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 103-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a digit line (e.g., 107-2). Each memory cell in memory cell 110 may be connected to a memory node (e.g., a capacitor). The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a memory node (e.g., a capacitor). While the references to the first source / drain region and the second source / drain region are used herein to refer to two separate and distinct source / drain regions, the source / drain regions referred to as “first” and / or “second” are not intended to have any particular meaning. One source / drain region is only intended to be connected to a digit line (e.g., 107-2), and the other source / drain region may be connected to a memory node.

[0024] Figure 2 This illustrates a three-dimensional (3D) semiconductor memory device (e.g., a vertically oriented stack of memory cells in an array) according to some embodiments of the present disclosure. Figure 1 A perspective view of a portion of the subcell array 101-2 shown. Figure 3 Showing Figure 2 The unit cell of the 3D semiconductor memory device shown (e.g., Figure 1 A perspective view of the memory cell 110 shown.

[0025] like Figure 2 As shown, a bonding can be formed on the substrate 200. Figure 1 One of the multiple sub-cell arrays, such as 101-2. For example, substrate 200 may be or contain a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0026] like Figure 2 As shown in the example embodiment, substrate 200 may be fabricated thereon with a vertically oriented stack of memory cells extending in a vertical direction (e.g., third direction (D3) 111), for example Figure 1The memory cell 110 is shown in some embodiments. According to some embodiments, the vertically oriented stack of memory cells can be manufactured such that each memory cell is formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)), for example... Figure 1 The memory cell 110 in the middle. Repeated vertical horizontals L1, L2 and L3 can be in the vertical direction (e.g., Figure 1 The third-party (D3) 111 shown is arranged, for example, stacked, and separated from the substrate 200 by an insulating material 220. Each of the repeating vertical levels L1, L2, and L3 may contain multiple discrete components (e.g., regions) of laterally oriented access devices 230 (e.g., transistors and memory nodes (e.g., capacitors)), which include access lines 203-1, 203-2, ..., 203-Q connections and digit lines 207-1, 207-2, ..., 207-P connections. The multiple discrete components of the laterally oriented access devices 230 (e.g., transistors) may be formed within each level in multiple vertical repeating layer iterations, such as in combination Figures 4A-4F As described in more detail below, and may be found in conjunction with Figure 1 The second direction (D2) 105 shown extends horizontally in a similar manner to the second direction (D2) 205.

[0027] A plurality of discrete components of a laterally oriented access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223, separated by a channel and a body region 225, laterally extending in a second direction (D2) 205 and formed within the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type dopant region formed within a p-type dopant of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type dopant region formed within an n-type dopant of the access device to form a p-type conductive transistor. By way of example and not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed within a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0028] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2As shown, storage node 227 (e.g., a capacitor) can be connected to the second source / drain region 223 of the access device. A storage node can be or contains a memory element capable of storing data. Each storage node can be a memory element using one of the following: a capacitor, a magnetic tunnel junction pattern, and / or a variable resistive body containing a phase change material, etc. However, the embodiments are not limited to these examples. In some embodiments, with unit cell (e.g., Figure 1 Each memory node associated with an access device in the memory cell 110 can be connected to a memory node in the memory cell 110. Figure 1 The second direction (D2) 105 shown extends similarly to the second direction (D2) 205.

[0029] like Figure 2 As shown, multiple horizontally oriented digit lines 207-1, 207-2, ..., 207-P are in relation to... Figure 1 The first direction (D1) 109 extends similarly to the first direction (D1) 209. The plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P can be similar to... Figure 1 The digital lines 107-1, 107-2, ..., 107-P are shown. These plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P may be arranged along a third direction (D3) 211, for example, "stacked". The plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.) and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0030] In each of the vertical levels (L1) 213-1, (L2) 213-2, and (L3) 213-M, the horizontally oriented memory cells (e.g., Figure 1 The memory cells 110 in the memory can be horizontally spaced apart from each other in the first direction (D1) 209. However, as combined Figures 4A-4EAs described in more detail below, a plurality of discrete components (e.g., a first source / drain region 221 and a second source / drain region 223 separated by a channel and a body region 225) extending laterally in a second direction (D2) 205 and a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally in a first direction (D1) 209 can be formed in different vertical layers within each level. For example, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 can be disposed on and electrically contacted on the top surface of the first source / drain region 221 and orthogonal to the laterally oriented access device 230 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, compared to the layers forming the discrete components of the laterally oriented access device (e.g., the first source / drain region 221 and the second source / drain region 223 separated by channels and body region 225), the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 are formed in a higher vertical layer, more distant from the substrate 200, in the horizontal direction (L1). In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0031] like Figure 2 As shown in the example embodiment, access lines 203-1, 203-2, ..., 203-Q extend vertically relative to substrate 200 (e.g., on third-direction (D3) 211). Further, as... Figure 2 As shown, a sub-cell array (e.g., Figure 1 Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 101-2 can be spaced apart from each other in the first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can be provided in the third direction (D3) 211, extending vertically relative to the substrate 200 between a pair of laterally oriented access devices 230 (e.g., transistors), which extend laterally in the second direction (D2) 205 but are adjacent to each other horizontally (e.g., in the first horizontal level (L1)) in the first direction (D1) 209. Each access line 203-1, 203-2, ..., 203-Q can extend vertically in the third direction (D3) on the sidewall of the corresponding access device of a plurality of vertically stacked laterally oriented access devices 230 (e.g., transistors).

[0032] For example, and as Figure 3 As shown in more detail, the first access line (e.g., 203-1) in the vertically extending access line may be adjacent to the sidewall of the channel and body region 225 of the first access device in the laterally oriented access device 230 (e.g., transistor) in the first level (L1) 213-1, adjacent to the sidewall of the channel and body region 225 of the first access device in the laterally oriented access device 230 (e.g., transistor) in the second level (L2) 213-2, and adjacent to the sidewall of the channel and body region 225 of the first access device in the laterally oriented access device 230 (e.g., transistor) in the third level (L3) 213-M, etc. Similarly, the second access line in the vertically extending access line (e.g., 203-2) may be adjacent, in the first direction (D1) 209, to the sidewall of the channel and body region 225 of the second access device spaced apart from the first access device in the laterally oriented access device 230 (e.g., transistor) in the first horizontal level (L1) 213-1. Furthermore, the second access line in the vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel and body region 225 of the second access device in the laterally oriented access device 230 (e.g., transistor) in the second horizontal level (L2) 213-2, and adjacent to the sidewall of the channel and body region 225 of the second access device in the laterally oriented access device 230 (e.g., transistor) in the third horizontal level (L3) 213-M, etc. The implementation is not limited to a specific number of levels.

[0033] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. Figure 1 The access lines 203-1, 203-2, ..., 203-Q can correspond to word lines (WL).

[0034] like Figure 2 As shown in the example embodiment, the conductive contact 250 may be formed by extending the end face of the laterally oriented access device 230 (e.g., a transistor) in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-M above the substrate 200 in a first direction (D1) 209. The body contact 250 may be connected to each memory cell (e.g., Figure 1The body 226 (e.g., body region) of the laterally oriented access device 230 (e.g., transistor) in the memory cell 110. The body contact 250 may contain a conductive material, such as one of a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal semiconductor compound.

[0035] although Figure 2 Not shown, but insulating material will fill the remaining spaces in the vertically stacked array of memory cells. For example, the insulating material may comprise one or more of the following: silicon oxide, silicon nitride, and / or silicon oxynitride, etc. However, the embodiments are not limited to these examples.

[0036] Figure 3 A vertically stacked array of memory cells according to some embodiments of the present disclosure is shown in more detail (e.g., Figure 1 The unit cell (e.g., within the sub-cell array 101-2) in the sub-cell array Figure 1 (Memory cell 110 in the memory). For example Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of a laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2 The first source / drain region 221 and the second source / drain region 223 are shown. The first source / drain region and the second source / drain region can be separated by a channel and a body region 325 formed in a semiconductor material body (e.g., body region 326) of a laterally oriented access device 230 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be formed by an n-type or p-type dopant doped in the body region 326. Embodiments are not limited thereto.

[0037] For example, in an n-type conductive transistor configuration, the body region 326 of the laterally oriented access device 230 (e.g., a transistor) can be formed of a lightly doped (p)p-type semiconductor material. In one embodiment, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 can comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon material composed of boron (B) atoms as a polysilicon impurity dopant. In this example, the first source / drain region 321 and the second source / drain region 323 can comprise a high dopant concentration, i.e., an n-type conductive impurity (e.g., a high dopant (n+)), doped in the first source / drain region 321 and the second source / drain region 323. In some embodiments, the high dopant n-type conductive impurity in the first drain region 321 and the second drain region 323 can comprise a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the laterally oriented access device 230 (e.g., a transistor) may have a p-type conductivity configuration, in which case the conductivity type of the impurities (e.g., dopants) will be reversed.

[0038] like Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the laterally oriented access device 330, said bottom surface being positioned vertically higher than the bottom surface of the body 326 of the laterally horizontally oriented access device 330 in a third direction (D3) 311. Thus, the laterally horizontally oriented transistor 330 may have a body portion 326 lower than the first source / drain region 321 and connected to a body contact (e.g., Figure 2 The 250° electrical contact shown. Further, as... Figure 3 As shown in the example embodiments, with Figure 2 The digit lines shown are 207-1, 207-2, ..., 207-P and Figure 1 The digital lines shown, such as 107-1, 107-2, ..., 107-P, and similar digital lines (e.g., 307-1), can be placed on the top surface 322 of the first source / drain region 321 and electrically coupled thereto.

[0039] like Figure 3 As shown in the example embodiments, with Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1Access lines 103-1, 103-2, ..., 103-Q, and similar access lines (e.g., 303-1), can extend vertically along a third direction (D3) 311 adjacent to the sidewall of a portion of the channel region 325 of the body 326 of a laterally oriented access device 330 (e.g., a transistor), which is horizontally conductive along a second direction (D2) 305 between a first source / drain region 321 and a second source / drain region 323. A gate dielectric material 304 can be interposed between the access line 303-1 (a portion of which forms the gate of the laterally oriented access device 330 (e.g., a transistor)) and the channel region 325. The gate dielectric material 304 can comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Embodiments are not limited thereto. For example, in the high-k dielectric material example, the gate dielectric material 304 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, tantalum lead scandium oxide, lead zinc niobium ore, etc.

[0040] Figures 4A-4F This is a cross-sectional view of a vertically stacked array of memory cells at various stages of a semiconductor manufacturing process, according to many embodiments of the present disclosure, to form channels and body regions for a semiconductor device.

[0041] Figure 4A This is a cross-sectional view of the channels and body regions used at a stage of a semiconductor manufacturing process to form a vertically stacked array of memory cells to form a horizontally oriented access device, according to many embodiments of the present disclosure.

[0042] exist Figure 4AIn the illustrated example embodiment, the method includes depositing alternating layers of first dielectric material 430-1, 430-2, ..., 430-N (collectively referred to as first dielectric material 430), semiconductor material 432-1, 432-2, ..., 432-N (collectively referred to as dielectric material 432), and second dielectric material 433-1, 433-2, ..., 433-N (collectively referred to as dielectric material 433) in repeated iterations to form a vertical stack 401 on the working surface of the semiconductor substrate 400. In some embodiments, the first dielectric material 430, semiconductor material 432, and second dielectric material 433 may be deposited using a chemical vapor deposition (CVD) process. In one embodiment, the first dielectric material 430 may be deposited to have a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm, for example, a vertical height in a third direction (D3). In one embodiment, semiconductor material 432 may be deposited having a thickness in the range of twenty (20) nm to one hundred (100) nm, for example, in a vertical height. In one embodiment, second dielectric material 433 may be deposited having a thickness in the range of ten (10) nm to thirty (30) nm, for example, in a vertical height. However, the embodiments are not limited to these examples. Figures 4A-4F As shown, vertical direction 411 is displayed as... Figure 1-3 The third direction (D3) shown in the first direction, second direction and third direction is similar to the third direction (D3), for example, the z direction in the xyz coordinate system.

[0043] In some embodiments, the first dielectric materials 430-1, 430-2, ..., 430-N may be interlayer dielectrics (ILDs). By way of example and not limitation, the first dielectric materials 430-1, 430-2, ..., 430-N may include oxide materials, such as SiO2. In another example, the first dielectric materials 430-1, 430-2, ..., 430-N may include silicon nitride (Si3N4) materials (also referred to herein as “SiN”). In yet another example, the first dielectric materials 430-1, 430-2, ..., 430-N may include silicon carbide (SiO2). x C y In another example, the first dielectric material 430-1, 430-2, ..., 430-N may comprise silicon oxynitride (SiO2). x N y Materials (also referred to herein as "SiON") and / or combinations thereof. Examples are not limited to these instances.

[0044] In some embodiments, semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon (Si) material in a polycrystalline and / or amorphous state. Semiconductor materials 432-1, 432-2, ..., 432-N may be lightly doped p-type (p-) silicon materials. Semiconductor materials 432-1, 432-2, ..., 432-N may be formed by vapor-phase doping with boron atoms (B) as a low-concentration impurity dopant to form lightly doped p-type (p-) silicon materials. In some embodiments, semiconductor materials 432-1, 432-2, ..., 432-N may be formed in situ by vapor-phase doping with boron atoms (B). The lightly doped p-type (p-) silicon material may be amorphous silicon material. However, the embodiments are not limited to these examples.

[0045] In some embodiments, the second dielectric materials 433-1, 433-2, ..., 433-N may be interlayer dielectrics (ILDs). By way of example and not limitation, the second dielectric materials 433-1, 433-2, ..., 433-N may include nitride materials. The nitride material may be silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another example, the second dielectric materials 433-1, 433-2, ..., 433-N may include silicon carbide (SiOC) material. In yet another example, the second dielectric materials 433-1, 433-2, ..., 433-N may comprise silicon nitride (SiON) and / or combinations thereof. The embodiments are not limited to these examples. However, according to an embodiment, the second dielectric materials 433-1, 433-2, ..., 433-N are intentionally selected to be different from the first dielectric materials 430-1, 430-2, ..., 430-N in terms of material or composition, such that a selective etching process can be performed on one of the first and second dielectric layers, and the selective etching process can be selected for the other dielectric layer. For example, the second SiN dielectric materials 433-1, 433-2, ..., 433-N can be selectively etched relative to the semiconductor materials 432-1, 432-2, ..., 432-N and the first oxide dielectric materials 430-1, 430-2, ..., 430-N.

[0046] Furthermore, alternating layers of first dielectric material 430-1, 430-2, ..., 430-N, semiconductor material 432-1, 432-2, ..., 432-N, and second dielectric material 433-1, 433-2, ..., 433-N can be deposited in a semiconductor manufacturing apparatus using a semiconductor manufacturing process such as chemical vapor deposition (CVD). However, the embodiment is not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of first dielectric material, semiconductor material, and second dielectric material in repeated iterations to form a vertical stack 401.

[0047] The layers can appear vertically in repeated iterations. Figure 4A In the example, three levels numbered 1, 2, and 3 are shown for repeated iterations. For example, the stack may include: a first dielectric material 430-1, a semiconductor material 432-1, a second dielectric material 433-1, a third node material 430-2, a second semiconductor material 432-2, a fourth dielectric material 433-2, a fifth dielectric material 430-3, a third semiconductor material 432-3, and a sixth dielectric material 433-3. Thus, the stack may include: a first oxide material 430-1, a first semiconductor material 432-1, a first nitride material 433-1, a second oxide material 430-2, a second semiconductor material 432-2, a second nitride material 433-2, a third oxide material 430-3, a third semiconductor material 432-3, and a third nitride material 433-3 in further repeated iterations. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0048] Figure 4B This is a cross-sectional view of the channel and body regions used at another stage of the semiconductor manufacturing process to form a vertically stacked array of memory cells to form a horizontally oriented access device (e.g., a transistor), according to many embodiments of the present disclosure.

[0049] According to an embodiment, Figure 4B-4F The semiconductor manufacturing process described herein can occur in, for example, Figures 5A-6E The elongated pillars extending primarily in the second direction and the access lines shown have been formed after this process. According to an embodiment, Figures 4A-4F The method described herein can transform semiconductor material 432 (e.g., low-doped (p-) polycrystalline silicon material) into a single-crystal structure.

[0050] like Figure 4BAs shown, a vertical opening 471 can be formed through layers within a vertically stacked memory cell to expose vertical sidewalls in the vertical stack 401. A first etching process can be used to form a first region adjacent to the semiconductor material 432 (e.g., polysilicon (poly-Si)) by alternately forming the opening 471 in repeated iterations. Figure 7C The vertical opening 471 (742) is formed by repeated iterations of oxide material 430, semiconductor material 432, and nitride material 433. Thus, the vertical opening 471 can be formed through the first oxide material 430-1, the first semiconductor material 432-1, the first nitride material 433-1, the second oxide material 430-2, the second semiconductor material 432-2, the second nitride material 433-2, the third oxide material 430-3, the third semiconductor material 432-3, and the third nitride material 433-3. However, the embodiment is not limited to this. Figure 4B A single vertical opening 471 is shown. Multiple vertical openings may be formed through the material layers. The vertical opening 471 may be formed to expose the vertical sidewalls in the vertical stack 401. In one example, the working surface of the substrate 400 may be masked and patterned to form a vertical opening 471 with a width ranging from fifty (50) nanometers (nm) to five hundred (500) nm and a depth ranging from five hundred (500) nm to twenty thousand (20,000) nm. However, the embodiments are not limited to this example.

[0051] Figure 4C This is a cross-sectional view of the channels and body regions of a vertically stacked memory cell array with vertically oriented access lines at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure, to form a horizontally oriented access device.

[0052] like Figure 4C As shown, a metal (e.g., seed material) 416 can be deposited over the sidewalls of the vertical stack 401, the vertical opening 471, and the bottom of the vertical opening 471. In some embodiments, the metal material 416 can be deposited using an atomic layer deposition (ALD) process. In one embodiment, the metal material 416 is a nickel (Ni) metal material 416. In this example, the nickel (Ni) metal material 416 can be selectively deposited to form a Ni silicide (NiSi) 416 having a silicon material 432. In one embodiment, the metal material 416 (e.g., seed material) can be deposited to a thickness (t1) ranging from approximately 5 to 50 angstroms (Å). However, the embodiments are not limited to these examples. In some embodiments, the metal material 416 comprises a metal that can form a silicide with the silicon (Si) material (e.g., polycrystalline silicon material 432).

[0053] Figure 4DThis is a cross-sectional view of the channels and body regions of a vertically stacked memory cell array with vertically oriented access lines at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure, to form a horizontally oriented access device.

[0054] exist Figure 4D In an example embodiment, according to metal-induced lateral crystallization (MILC) and solid-state crystallization (SPC) processes, the vertical stack 401 can be processed under temperature, pressure, and time parameters such that the metal material 416 advances horizontally within a portion of the semiconductor material 432 and transforms the crystal structure of that portion of the semiconductor material 432 into a large-grain-size polycrystalline material 417, such as a single-crystal semiconductor material. As a result of a high-temperature annealing process, as the metal material 416 advances through the semiconductor material 432, the metal material 416 can acquire silicon atoms from the semiconductor material 432 and become a metal silicide material 415. In some embodiments, the metal silicide material 415 may be a nickel silicide, a cobalt silicide, or a silver silicide. As a result of a chemical reaction between the metal silicide material 415 and the semiconductor material 432, the metal silicide material 415 can advance through the semiconductor material 432. The speed at which the metal silicide material 415 advances through the semiconductor material 432 can be controlled by adjusting the temperature applied to the vertical stack 401 and the metal silicide material 415. In some embodiments, the vertical stack 401 can be processed at a temperature in the range of 400 to 600 degrees Celsius (°C) so that the metal silicide material 415 advances horizontally through the semiconductor material 432 (e.g., polycrystalline silicon), thereby transforming a portion of the semiconductor material 432 into a single-crystal semiconductor material 417.

[0055] In some embodiments, the distance (DIST1) by which the metal silicide material 415 advances horizontally within a portion of the semiconductor material 432 is determined by many factors, such as the thickness (H1), for example, the vertical height of the semiconductor material 432 layer, the thickness of the metal material (e.g., seed material deposited on the vertical sidewalls of the semiconductor material 432 and on the first region in the vertical opening 471 of the vertical stack 401), and the temperature. In some embodiments, the distance (DIST1) by which the metal silicide material 415 advances horizontally within a portion of the semiconductor material 432 to transform a portion of the semiconductor material 432 into a single-crystal semiconductor material 417 can be controlled by adjusting the temperature applied to the vertical stack 401 and the metal silicide material 415 during the process and adjusting the amount of time for which the temperature is applied.

[0056] In some embodiments, at an applied temperature below 600 degrees Celsius (°C), the thickness (H1) (e.g., vertical height) of the semiconductor material 432 layer in the range of twenty (20) nm to one hundred (100) nm and the thickness, timing, and process parameters of the metal material 416 (e.g., seed material) deposited to a thickness (t1) in the range of approximately 5-50 angstroms (Å) are controlled such that the metal silicide material 415 advances horizontally through the silicon material 432 over a first distance (DIST1) in the range of 100 nanometers (nm) to 300 nm, thereby transforming a portion of the semiconductor material 432 into a single-crystal silicon semiconductor material 417. In one embodiment, the metal silicide material 415 advances horizontally through the silicon material 432 over a first distance (DIST1) of at least 200 nanometers (nm), thereby transforming a portion of the semiconductor material 432 into a large-grain polycrystalline silicon and / or single-crystal silicon structure 417. In some embodiments, the process can be performed at temperatures as low as 400 degrees Celsius (°C) according to the design rules described herein.

[0057] In some embodiments, under the process parameters described above, the metal silicide material 415 advances diagonally-horizontally through the silicon material 432, thereby transforming a portion of the semiconductor material 432 into a large-grain polycrystalline silicon and / or monocrystalline silicon structure 417. However, this diagonal-horizontal advance is defined by a first dielectric material 430 (e.g., as a base plate in the vertical direction (D3)) and by a second dielectric material 433 (e.g., as a top plate in the vertical direction), such that the advance of the metal silicide material 415 continues horizontally in the second direction (D2) within the semiconductor material 432 in a direction away from the vertical opening 471 by a distance (DIST1) and a height (H1), thereby transforming a portion of the semiconductor material 432 into a large-grain polycrystalline silicon and / or monocrystalline silicon structure 417.

[0058] In some embodiments, metal 416 (e.g., seed material) may be deposited in a second region (e.g., through the vertical stack 400) Figure 7C The second vertical opening in 744) is open (e.g., Figure 7C In 751), to ultimately form a storage node. For those described above using similar processes and processing parameter control techniques, the resulting metal silicide material 415 can be placed away from the second vertical opening (e.g., Figure 7CThe semiconductor material 432 moves horizontally through the direction of the first opening 471 (751), which is the side of a vertical stack 401 containing memory nodes formed adjacent to the second vertical opening and the second region (e.g., 744) and in the second vertical opening and the second region. In these embodiments, the metal silicide material 415 may move through the semiconductor material 432 in the direction toward the first opening 471. However, the embodiments are not limited to these examples.

[0059] In one embodiment, the metal silicide material 415 continues along the semiconductor material 432 in the second direction (D2). <100> Crystal plane facing or near <100> The crystal plane advances horizontally by a distance (DIST1) and a height (H1), thereby transforming a portion of the semiconductor material 432 into a large-grain polycrystalline silicon and / or monocrystalline silicon structure 417. However, the embodiments are not limited to this example. In some embodiments, advancing the metal silicide material 415 a greater distance from the initial metal 416 (e.g., seed material at the deposition site) can achieve better monocrystalline uniformity.

[0060] According to some embodiments, a portion of the resulting transformed silicon crystal material 417 is a substantially monocrystalline silicon structure, such that the grain boundaries (GBs) of the crystal structure are mostly sub-GBs, and such that a portion of the transformed silicon crystal material 417 has a crystal orientation difference of approximately less than (<) one degree (1°). In one embodiment, the grain boundary defect concentration of the large-grain polycrystalline silicon and / or substantially monocrystalline silicon crystal material 417 is less than 1 × 10⁻⁶. 18 cubic centimeters (also known as centimeters cubed (cm)) 3 A defect within the structure. For example, according to an embodiment, the vertical stack 401 can be processed under temperature, deposition thickness, and time parameters to allow the metal silicide material 415 to advance horizontally, thereby recrystallizing the polycrystalline silicon and / or amorphous silicon semiconductor material 432 into a substantially monocrystalline silicon structure 417 having sub-grain boundaries (sub-GBs). Furthermore, according to the embodiments described herein, the polycrystalline silicon semiconductor material and / or amorphous silicon semiconductor material 432 is recrystallized into a substantially monocrystalline silicon structure 417 such that the crystal orientation difference of the grain boundaries within the monocrystalline silicon structure 417 is less than one degree (1°). Again, in some embodiments, the defect density of the monocrystalline silicon structure 417 can be less than 1 × 10⁻⁶. 18 cubic centimeters (cm) 3 A defect within the single-crystal silicon structure 417.

[0061] Therefore, due to the large grain size and low grain boundary (GB) density, the improved crystal structure for the channel and bulk regions of the horizontally oriented access device provides better electron mobility. For example, a lower GB trap density can be achieved, and fewer electron-hole pairs may occur, resulting in a lower “off” current (“Ioff”) for the horizontally oriented access device according to the aforementioned design rules and scale. Moreover, better uniformity with an improved tail-side growth profile can be achieved compared to other low-temperature chemical vapor deposition (CVD) processes for forming (e.g., depositing) amorphous silicon:hydrogen (a-Si:H) films of semiconductor material 432.

[0062] As noted, in some embodiments, metal-induced lateral crystallization (MILC) is used, whereby metal material 415 can transform semiconductor material 432 into crystalline material 417. MILC may be a more efficient recrystallization process when applied to amorphous silicon than to polycrystalline silicon. When applied to polycrystalline silicon, MILC may be less efficient because grain boundaries in polycrystalline silicon can hinder the movement of metal silicides (e.g., metal silicide material 415) through the polycrystalline silicon during the recrystallization process. Because grain boundaries in the polycrystalline silicon material hinder the movement of metal silicides through the polycrystalline silicon material, the crystal growth rate in the polycrystalline silicon material during MILC may be slower than the crystal growth rate in the amorphous silicon material during MILC. Furthermore, polycrystalline silicon is more stable than amorphous silicon, therefore the amount of energy required to recrystallize polycrystalline silicon is greater than the amount of energy required to recrystallize amorphous silicon.

[0063] In some embodiments, MILC can occur at temperatures below 450 degrees Celsius. In some embodiments, using solid-state crystallization (SPC), a metal silicide material 415 can transform a semiconductor material 432 into a crystalline material 417. A vertical stack 401 can be fabricated under specific temperature and time parameters such that as the metal silicide material 415 advances within the semiconductor material 432, the metal silicide material increases the transformation of the crystal structure of said portion of the semiconductor material 432 according to the size of individual crystals within that portion.

[0064] After advancing through semiconductor material 432, vertical stack 401 can be processed to form other semiconductor components, such as memory nodes, digit lines, vertical access lines, and / or discrete regions such as source / drain regions. In some embodiments, and by way of example rather than limitation, the remaining metal silicide material 415 has a very low defect concentration and / or impurities. Further, as the metal silicide material 415 advances through silicon material 432 a first distance (e.g., DIST1), a separating interface can be provided between monocrystalline silicon 417 and the remaining untransformed and / or recrystallized semiconductor material 432 (e.g., amorphous silicon), wherein the crystals on the monocrystalline side of the interface are larger than those in the amorphous silicon structure 432, and such that after crystallization, very low levels of metallic impurities from metal material 416 (e.g., seed material) are retained in semiconductor material 432 (e.g., polycrystalline silicon).

[0065] As will be described in more detail below, a recrystallized single-crystal silicon structure 417 can be used in the first region to form a horizontally oriented access device in the vertical stack 401. In some embodiments, the remaining metal silicide material 415 now at a first distance (D1) from the vertical opening 471 can be used as an etch stop while selectively removing semiconductor material 432 from the second region of the vertical stack 401 to form a memory node. For example, a horizontal capacitor cell can be formed in the selectively removed semiconductor material 432 in the second region using an ALD process.

[0066] As noted, the vertical stack 401 is processed such that the metal silicide material 415 advances horizontally through a first distance (DIST1) of silicon material and provides a separating interface between the transformed monocrystalline silicon 417 of the remaining semiconductor material 432 and the crystal structure. The crystal on the monocrystalline side 417 of the interface is larger than the crystal in the structure of the remaining semiconductor material 432. Because the crystal in the transformed material 417 is larger than that used in non-metallic silicide formation processes (e.g., MILC / SPC processes) for the remaining amorphous silicon and / or polycrystalline silicon semiconductor material 432, the transformed crystal material 417 can provide improved channels and bulk regions (e.g., Figure 3 The channel and body region (325) formed using the deposited semiconductor material 432 have better electron mobility and lower "cutoff current" ("Ioff") leakage compared to the channel and body region formed using the deposited semiconductor material 432. Again, in some embodiments, the channel and body region formed by the transformed crystal material 417 ( Figure 3The thickness (H1) of the vertical opening 425 (e.g., vertical height) can range from approximately twenty (20) nm to one hundred (100) nm. In some embodiments, the remaining, untransformed semiconductor material 432 on the interface side in the horizontal direction away from the vertical opening 471 can be sacrificially removed to form a horizontal opening in order to form a horizontally oriented memory node of vertically stacked memory cells with vertically oriented access lines. For example, in some embodiments, any remaining metal silicide material 415 can be used as an etch stop to sacrificially remove the semiconductor material 432 and / or as an ohmic contact for the first electrode of a capacitor formed as a memory node in a second region of the vertical stack 401.

[0067] Figure 4E This is a cross-sectional view of the channel and body regions used at another stage of the semiconductor manufacturing process to form a vertically stacked array of memory cells to form a horizontally oriented access device, according to many embodiments of the present disclosure.

[0068] like Figure 4E As shown in the examples, such as from Figure 4D As can be seen, the metal material 416 that does not advance within the semiconductor material 432 can remain on the vertical sidewalls of the first dielectric material 430 and the second dielectric material 433 of the vertical opening 471, as well as on the bottom surface of the vertical opening 471 of the vertical stack 401. Therefore, in one embodiment, as Figure 4E As shown, isotropic etching cleaning can be performed in vertical openings 471 on the vertical stack 401, for example, on the sidewalls and bottom of the vertical openings 471, to remove residual, unused metal material 416 from those surfaces. Removing metal material 416 from such surfaces (e.g., the sidewalls and bottom of the vertical openings 471) of the vertical stack 401 can preserve the original aspect ratio (A / R) and vertical height-to-width ratio of the vertical openings 471 for subsequent material deposition in subsequent semiconductor fabrication processes described herein. In some embodiments, the A / R can range from ten (10) to forty (40). In some embodiments, the A / R can range from 40 nm to 150 nm.

[0069] Figure 4F This is a cross-sectional view of the channel and body regions used at another stage of the semiconductor manufacturing process to form a vertically stacked array of memory cells to form a horizontally oriented access device, according to many embodiments of the present disclosure.

[0070] like Figure 4FAs shown in the example embodiment, subsequent semiconductor manufacturing processes can be performed to selectively remove the sacrificial portion of the second dielectric material 433, deposit a first source / drain region in the top surface of the transformed crystalline material 417 using vapor phase doping, deposit conductive digital line material electrically contacting the first source / drain region, provide an isolation barrier, and deposit body contact 495 material in the vertical opening to form, as shown in the example embodiment. Figure 3 The device structure shown.

[0071] exist Figure 4F In the example, the digit line 477 can be as follows: Figure 2 As shown, it extends and travels in the first direction (D1) to Figure 4F The drawing plane contains horizontally oriented digit lines 477 and 207 that extend from it. An example of a first source / drain region formed in the top surface of a transformed crystalline material 417, a conductive digit line material electrically in contact with a first source / drain region, an isolation barrier, and a body contact 495 material is described in U.S. Patent Application No. 16 / 943,494, filed July 30, 2020, with at least one co-inventor. Another example is provided in U.S. Patent Application No. 16 / 943,163, filed July 30, 2020, with at least one co-inventor, entitled "Digit Line and Body Contact for Semiconductor Devices". Another example is provided in U.S. Patent Application No. 16 / 943,108, entitled "Digit LineFormation for Horizontally Oriented Access Devices," which has at least one co-inventor and was filed July 30, 2020, and is co-pending. All of these patents are incorporated herein by reference in their entirety.

[0072] Figure 5A An example method is shown for forming a vertically stacked array of memory cells with channels and body regions having semiconductor devices and vertically oriented access lines at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure. Figure 5AA top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 5A In the example embodiment shown in the example, the method includes using an etching process to form a plurality of first vertical openings 500 having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505 through a vertical stack to a substrate. In one example, as Figure 5A As shown, the plurality of first vertical openings 500 extend primarily in the second horizontal direction (D2) 505 and can form an elongated column of vertical columns 513 with sidewalls 514 in a vertical stack. The plurality of first vertical openings 500 can be formed by patterning a photomask 535 using photolithography techniques, for example, to form a hard mask (HM) on the vertical stack before etching the plurality of first vertical openings 500.

[0073] Figure 5B It is along Figure 5A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at a specific time in the semiconductor manufacturing process. Figure 5B The cross-sectional view shown illustrates the repeated iterations of alternating layers of first dielectric material 530-1, 530-2, ..., 530-N, semiconductor material 532-1, 532-2, ..., 532-N, and second dielectric material 533-1, 533-2, ..., 533-N on a semiconductor substrate 500 to form a vertical stack, for example as... Figure 4A 401 shown. Figure 5B The illustration demonstrates the formation of conductive materials 540-1, 540-2, ..., 540-4 on a gate dielectric material 538 within a plurality of first vertical openings 500. By way of example and not limitation, the gate dielectric material 538 can be conformally deposited in the plurality of first vertical openings 500 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric material 538 can be deposited to a specific thickness (t1) suitable for a particular design rule, for example, a gate dielectric thickness of approximately 10 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, the gate dielectric material 538 can include... Figure 3 The silicon dioxide (SiO2) material, aluminum oxide (Al2O3) material, high dielectric constant (k) (e.g., high k), dielectric material and / or combinations thereof described herein.

[0074] Furthermore, such as Figure 5BAs shown, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited in the plurality of first vertical openings 500 on the surface of the gate dielectric material 538. By way of example and not limitation, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited in the plurality of first vertical openings 500 on the surface of the gate dielectric material 538 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings over the gate dielectric material 538. Conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a specific thickness (t2) to form as shown in the figure. Figure 1 Access lines 103-1, 103-2, ..., 103-Q (also referred to as word lines) and vertically oriented access lines as suited to specific design rules are shown below. For example, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, conductive materials 540-1, 540-2, ..., 540-4 may include metals such as tungsten (W), metal composites, titanium nitride (TiN), doped amorphous silicon, and / or Figure 3 It also describes some of its other combinations.

[0075] like Figure 5B As shown, conductive materials 540-1, 540-2, ..., 540-4 can be recessed backward to... Figure 5B In the cross-sectional view, the vertical sidewalls are maintained only along the elongated vertical column array now shown as 542-1, 542-2, and 542-3. Multiple individual vertical access lines formed of conductive materials 540-1, 540-2, ..., 540-4 can be recessed rearward using a suitable selective anisotropic etching process to emerge from the first vertical opening (e.g., Figure 5A The conductive materials 540-1, 540-2, ..., 540-4 are removed from the bottom surface of the 500, thereby exposing the gate dielectric material 538 on the bottom surface to form individual vertical access lines 540-1, 540-2, ..., 540-4. For example... Figure 5BAs shown, dielectric material 539 (such as oxide or other suitable spin-on dielectric (SOD)) can then be deposited in the first vertical opening 500 using a process such as CVD to fill the first vertical opening 500. The dielectric can be planarized to the top surface of a hard mask 535 of a vertical semiconductor stack using chemical mechanical polishing (CMP) or other suitable semiconductor manufacturing techniques. Subsequent photolithography material 536 (e.g., a hard mask) can be deposited using CVD and planarized using CMP to cover and close the first vertical opening 500 over the individual vertical access lines 540-1, 540-2, ..., 540-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0076] Figure 6A An example method is shown for forming a vertically stacked array of memory cells having channels and body regions of semiconductor devices at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure. Figure 6A A top view at a specific point in time is shown in a semiconductor manufacturing process, according to one or more embodiments. Figure 6A In an example embodiment, the method includes patterning using a photolithography process. Figure 5B The photolithography hard masks in the middle are 636 and 536. Figure 6A The method further demonstrates the use of selective isotropic etching processes to remove portions of the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z to separate and independently form multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z, for example... Figure 1 And access lines 103-1, 103-2, ..., 103-Q as described below. Therefore, the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are in... Figure 5B The cross-sectional view is shown along the sidewalls of the elongated vertical columns (e.g., along the sidewalls of elongated vertical columns 542-1, 542-2 and 542-3).

[0077] like Figure 6A As shown in the examples, the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be back-removed to the first vertical opening using a suitable selective isotropic etching process (e.g., Figure 5A The gate dielectric material 638 in (500) is as follows. Figure 6AAs shown, subsequent dielectric material 641, such as oxide or other suitable spin-on dielectric (SOD), can be deposited to fill the remaining openings of the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, which have been removed using processes such as CVD or other suitable techniques. Dielectric material 641 can be planarized into a vertical semiconductor stack using processes such as CMP or other suitable techniques (e.g., Figure 4A The top surface of the previous hard mask 635 (shown as 401). In some embodiments, subsequent photolithography material 637 (e.g., a hard mask) can be deposited using CVD and planarized using CMP to cover and enclose the surface. Figure 4A Multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are located on the working surface of the vertical semiconductor stack 401, thereby protecting the multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z along the sidewalls of the elongated vertical column. However, the embodiments are not limited to these process examples.

[0078] Figure 6B Showing along Figure 6A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6B The cross-sectional view shown is away from multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and illustrates the repeated iteration of alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N on semiconductor substrate 600 to form a vertical stack, for example as... Figure 4A As shown in 401. Figure 6B As shown, vertical direction 611 is displayed as... Figure 1-3 The third direction (D3) 111 shown in the first direction, second direction, and third direction is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. The drawing plane extending to the left and right is on the first direction (D1) 609. Figure 6B In the example embodiment, dielectric material 641 is shown as filling a vertical opening in the deposition of residual gate dielectric material 638. The hard mask 637 described above covers the structure shown.

[0079] Figure 6C Showing along Figure 6A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6C The cross-sectional view shown illustrates that the axis of repeated iterations along alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N extends in a second direction (D2) 605, along said alternating layers, and within said alternating layers, horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) can be formed within the layers of semiconductor material 632-1, 632-2, ..., 632-N. Figure 6C In the middle, the adjacent relative vertical access lines 640-3 are shown by dashed lines indicating the position from the plane of the drawing and towards the set position.

[0080] Figure 6D Showing along Figure 6A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6D The cross-sectional view shown illustrates a repeating, iterative axis along alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N, extending in a second direction (D2) 605 outside a certain region, in which horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) will be formed within layers of semiconductor material 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, dielectric material 641 is shown filling the space between horizontally oriented access devices and horizontally oriented memory nodes, which can be spaced along a first direction (D1) 611, extending into and outward from the drawing plane of a three-dimensional array of vertically oriented memory cells. The left end of the drawing shows a repeated iteration of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N, at which point horizontally oriented digital lines (e.g., ... Figure 1The digital lines 107-1, 107-2, ..., 107-P shown below can be integrated to form electrical contacts with the second source / drain region or the digital line conductive contact material as described in the following detailed description.

[0081] Figure 6E Showing along Figure 6A The cross-sectional view taken by the cutting line D-D' in the drawing shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process according to an embodiment of this disclosure. It is shown from right to left in the plane of the drawing. Figure 6E The cross-sectional view shown indicates that the plane extends along the axis of repeated iterations of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N in the first direction (D1) 609, intersecting across the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and intersecting the regions of semiconductor materials 632-1, 632-2, ..., 632-N, in which channels and body regions separated by gate dielectric material 638 from the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1). Figure 6E In the diagram, the first dielectric filling material 639 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes, as described in more detail below. The horizontally oriented access devices and horizontally oriented memory nodes can extend into and out of the drawing plane, and can be spaced apart along a first direction (D1) 609 and vertically stacked in a three-dimensional (3D) memory in an array extending in a third direction (D3) 611.

[0082] Figure 7A An example method is shown for forming a vertically stacked array of memory cells having channels and body regions of semiconductor devices at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure. Figure 7A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 7A In an example embodiment, the method includes patterning photomasks 735, 736, and / or 737 using a photolithography process, for example... Figures 6A-6E 635, 636 and / or 637. Figure 7A The method further demonstrates the use of one or more etching processes in the memory node region 750 (and Figure 7A and7C Vertical openings 751-1, 751-N, 751-(N+1), and 751-Z (respectively or collectively referred to as vertical openings 751) are formed in 744) through the vertical stack and extending primarily in the first horizontal direction (D1) 709. The one or more etching processes form the vertical openings 751 to... Figures 7B-7E The third sidewall is exposed in a vertical stack of adjacent semiconductor materials in a repeating iteration of alternating layers of first dielectric material 730-1, 730-2, ..., 730-N, semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N. Other numbered components can be similarly combined. Figures 6A-6E The components shown and discussed.

[0083] In some embodiments, this process is performed after selectively removing semiconductor material from access device regions (e.g., transistor regions) to form horizontally oriented first source / drain regions, channel regions, and second source / drain regions of the access device. In other embodiments, this process is performed after selectively removing semiconductor material from access device regions to form horizontally oriented first source / drain regions, channel regions, and second source / drain regions of the access device.

[0084] according to Figures 7B-7E The example embodiment shown includes a method comprising vertically stacking ( Figure 4A In the 401), a second vertical opening 751 is formed and a second region 744 of semiconductor material 732-1, 732-2, ..., 732-N is selectively etched to form a vertically stacked ( Figure 4A A second horizontal opening 734 (D2 opening) is formed rearward from the vertical opening 751 in 401) at a second horizontal distance. According to an embodiment, selectively etching the second regions 744 of the semiconductor materials 732-1, 732-2, ..., 732-N includes using an atomic layer etching (ALE) process. (As in...) Figure 7C To explain in more detail, a second source / drain region 778 can be formed in semiconductor material 732-1, 732-2, ..., 732-N at the distal end of the second horizontal opening 734, which is far from the vertical opening.

[0085] Figure 7B Showing along Figure 7A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7BThe cross-sectional view shown is away from multiple individual vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1), and illustrates the repeated iteration of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1), semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N separated by openings 751 on a semiconductor substrate 700 to form a vertical stack. Figure 7B As shown, the vertical direction 711 is displayed as... Figure 1-3 The third direction (D3) 111 shown in the first direction, second direction, and third direction is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. The drawing plane extending to the left and right is on the first direction (D1) 709. Figure 7B In an example embodiment, the materials within the vertical stack are dielectric materials 730-1, 730-2, ..., 730-(N+1), semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N, extending in the second direction (D2) into and out of the plane of the drawing and along the orientation axis of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0086] Figure 7C Showing along Figure 7A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7C The cross-sectional view shown illustrates a repeating iterative axis along alternating layers of first dielectric material 730-1, 730-2, ..., 730-N, semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N, extending to the left and right along the drawing plane in the second direction (D2) 705. In these alternating layers, horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) can be formed within the semiconductor material layers 732-1, 732-2, ..., 732-N. Figure 7C In an example embodiment, opening 756 is shown in a region where horizontally oriented memory nodes (e.g., capacitor cells) can be formed later in this semiconductor manufacturing process.

[0087] exist Figure 7C In the example embodiment, the vertical opening 751 and the horizontal opening 734 are shown as being combined Figure 7AThe masking, patterning, and etching processes described above are used to form the image. Figure 7C As shown, semiconductor materials 732-1, 732-2, ..., 732-N in the second region 744 have been selectively removed to form a horizontal opening 734. In one example, the semiconductor materials 732-1, 732-2, ..., 732-N are selectively etched using an atomic layer etching (ALE) process, and a second distance (D2 opening) is removed backward from the vertical opening 751. Figures 8A-8E As shown, it can be relative to the second horizontal opening 734. Figures 4A-4F The manufacturing process shown forms horizontally oriented memory nodes (e.g., capacitor cells) either later or first.

[0088] According to an example embodiment, such as Figure 7C As shown, a second source / drain region 778 can be formed by flowing a high-energy vapor dopant, such as phosphorus (P), used in n-type transistors into a second horizontal opening 734, to inject the dopant from a vertical opening 751 into semiconductor materials 732-1, 732-2, ..., 732-N at the distal end of the second horizontal opening 734. In one example, vapor-phase doping can be used to achieve high isotropy (e.g., non-directional doping) to form a horizontally oriented second source / drain region 778 of the access device in region 742. In another example, thermal annealing with a dopant gas, such as phosphorus, can be used in conjunction with high-energy plasma-assisted annealing. However, the embodiments are not limited to these, and other suitable semiconductor manufacturing techniques can be utilized.

[0089] like Figure 8C As further shown, the first electrode (e.g., 861) for the horizontally oriented memory node is coupled to the second source / drain region 778 of the horizontal access device. Figure 8C As shown later, a horizontally oriented storage node of this type is illustrated in a second horizontal opening 734, which extends on the left and right sides in a second direction (D2) in the drawing plane and is a second distance (D2 opening) from the vertical opening 751, which is in vertical stack (e.g., Figure 4A In 401), and along the orientation axis of the vertically stacked memory cell array of the three-dimensional (3D) memory, horizontal access devices and horizontal storage nodes are formed. Figure 7C In the drawing, adjacent relative vertical access lines 740-3 are shown by dashed lines indicating the positions set inward from the plane of the drawing and the orientation.

[0090] Figure 7D Showing along Figure 7A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7D The cross-sectional view shown illustrates the repeated iterations of the alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, the semiconductor material 732-1, 732-2, ..., 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N outside a certain region, extending on the left and right sides in the plane of the drawing in a second direction (D2) 705, in which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) will be formed within the layers of semiconductor material 732-1, 732-2, ..., 732-N. The left end of the drawing shows a repeated iteration of alternating layers of first dielectric material 730-1, 730-2, ..., 730-N, semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N. At this location, horizontally oriented digital lines (e.g., Figure 1 The digit lines 107-1, 107-2, ..., 107-P shown below can be integrated to form a combination of the above. Figures 4A-4F The aforementioned electrical contact or digital line conductive contact material having a first source / drain region.

[0091] Furthermore, while the references to "first source / drain region" and "second source / drain region" are used herein to refer to two separate and distinct source / drain regions, the use of "first" and / or "second" source / drain regions is not intended to have any particular meaning. One source / drain region is intended only to be connected to a bit line (e.g., 107-2), and the other source / drain region may be connected to a memory node.

[0092] Figure 7E Showing along Figure 7A The cross-sectional view taken by the cutting line D-D' in the drawing shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process according to an embodiment of this disclosure. It is shown from right to left in the plane of the drawing. Figure 7EThe cross-sectional view shown indicates that the plane extends along the axis of repeated iterations of alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N in the first direction (D1) 709, intersecting across the plurality of individual vertical access lines 740-1, 740-2, ..., 740-4, and intersecting the regions of semiconductor materials 732-1, 732-2, ..., 732-N, in which channels and body regions separated from the plurality of individual vertical access lines 740-1, 740-2, ..., 740-4 by gate dielectric 738 can be formed. Figure 7E In the middle, the first dielectric filling material 739 is shown to separate the space between adjacent horizontally oriented access devices, such as in combination. Figures 4A-4F As described, the horizontally oriented access device can extend into and out of the drawing plane, and is spaced apart along a first direction (D1) 709 and vertically stacked in a three-dimensional (3D) memory in an array extending in a third direction (D3) 711.

[0093] Figure 8A An example method is shown for forming a vertically stacked array of memory cells having channels and body regions of semiconductor devices at another stage of a semiconductor manufacturing process, according to many embodiments of the present disclosure. Figure 8A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 8A In an example embodiment, the method includes patterning photomasks 835, 836, and / or 837 using a photolithography process, for example, Figures 6A-6E 635, 636 and / or 637, or Figures 7A-7E 735, 736 and / or 737. Figure 8A The method further demonstrates the use of one or more etching processes in the memory node region 850 (and Figure 8A and 8C A vertical opening 851 is formed in 844) through the vertical stack and extending primarily in the first horizontal direction (D1) 809. The one or more etching processes form the vertical opening 851 to... Figures 8B-8E The third sidewall is exposed in a vertical stack of adjacent semiconductor materials in a repeating iteration of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N. Other numbered components can be combined similarly. Figures 6A-6EAnd those components shown and discussed in 7A-7E.

[0094] In some embodiments, such as Figures 7A-7E As shown, this process is performed after selectively removing semiconductor material from the access device region, in which a first source / drain region, a channel region, and a second source / drain region of a horizontally oriented access device are formed. According to... Figures 8B-8E In an example embodiment, the method includes selectively etching second regions of semiconductor material 832-1, 832-2, ..., 832-N to deposit second source / drain regions and capacitor cells through a second horizontal opening, the second horizontal opening being a second horizontal distance backward from a vertical opening 851 in the vertical stack. In some embodiments, such as Figures 8B-8E As shown, the method includes forming a capacitor cell as a storage node in a second horizontal opening. By way of example and not limitation, forming the capacitor includes sequentially depositing a first electrode 861 and a second electrode 856 separated by a cell dielectric 863 in the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor fabrication techniques and / or storage node structures may be used.

[0095] Figure 8B Showing along Figure 8A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8B The cross-sectional view shown is away from the multiple individual vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1), and illustrates the repeated iteration of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and second dielectric materials 833-1, 833-2, ..., 833-N separated by horizontally oriented capacitor cells. These horizontally oriented capacitor cells have a first electrode 861 (e.g., a bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., a top common node electrode) on a semiconductor substrate 800 to form a vertical stack. Figure 8B As shown, vertical direction 811 is displayed as... Figure 1-3 The third direction (D3) 111 shown in the first, second, and third directions is similar to the third direction (D3), for example, the z-direction in the xyz coordinate system. The drawing plane extending to the left and right is on the first direction (D1) 809. Figure 8BIn an example embodiment, a first electrode 861 (e.g., a bottom electrode) is coupled to the source / drain region of a horizontal access device, and a second electrode 856 is shown separated by a cell dielectric material 863 that extends in and out of the plane of the drawing in a second direction (D2) and extends along the oriented axis of the horizontal access devices and horizontal memory nodes in an array of vertically stacked memory cells of a three-dimensional (3D) memory.

[0096] Figure 8C Showing along Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8C The cross-sectional view shown illustrates a repeating iterative axis along alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N, extending along the drawing plane on the left and right in a second direction (D2) 805. Horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) are formed within the semiconductor material layers 832-1, 832-2, ..., 832-N. Figure 8C In the example embodiment, the horizontally oriented memory node (e.g., capacitor cell) is shown as having already been formed in this semiconductor manufacturing process, and a first electrode 861 (e.g., bottom electrode) coupled to the source / drain regions of the horizontal access device and a second electrode 856 (e.g., top electrode) coupled to a common electrode plane such as a ground plane are shown, separated by cell dielectric 863. However, the embodiments are not limited to this example. In other embodiments, the formation of the first electrode 861 (e.g., bottom electrode) to be coupled to the source / drain regions of the horizontal access device and the second electrode 856 (e.g., top electrode) to be coupled to a common electrode plane such as a ground plane, separated by cell dielectric 863, is after the formation of the first source / drain regions, channel and body regions, and second source / drain regions in the regions of semiconductor material 832-1, 832-2, ..., 832-N intended to be positioned (e.g., arranged) for the horizontally oriented access device described below.

[0097] exist Figure 8C In an example embodiment, a second horizontal opening is shown (e.g., Figure 7CThe diagram shows a horizontally oriented storage node (734) having a first electrode 861 (e.g., bottom electrode) to be coupled to the source / drain regions of a horizontal access device and a second electrode 856 (e.g., top electrode) to be coupled to a common electrode plane such as a ground plane. The second horizontal opening extends in the plane of the drawing to the left and right in a second direction (D2) with the vertical opening (e.g., Figure 7C 751) is separated by a second distance (D2 opening), the vertical opening being in the vertical stack and along the vertical stack of the three-dimensional (3D) memory (e.g., Figure 4A The horizontal access devices and horizontal storage nodes in the array of memory cells (401) are oriented along the axis. Figure 8C In the drawing, adjacent relative vertical access lines 840-3 are shown by dashed lines indicating the positions set from the plane of the drawing and the direction inward.

[0098] Figure 8D Showing along Figure 8A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8D The cross-sectional view shown depicts a region outside a certain area, extending in a second direction (D2) 805 on the left and right sides of the drawing plane, along the axis of repeated iterations of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N. In this region, horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) will be formed within the layers of semiconductor material 832-1, 832-2, ..., 832-N. Figure 8C In the drawing, dielectric material 841 is shown filling the space between horizontally oriented access devices, which are spaced along a first direction (D1) and extend into and out of the plane of a three-dimensional array of vertically oriented memory cells. However, in Figure 8D In the cross-sectional view, the second electrode 856 (e.g., the top common electrode) of the capacitor cell structure is further shown as existing in the space between horizontally adjacent devices. The left end of the drawing shows a repeating iteration of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N, at which point horizontally oriented digital lines (e.g., ... Figure 1The digital lines 107-1, 107-2, ..., 107-P shown below can be integrated to form electrical contacts with the second source / drain region or the digital line conductive contact material as described in the following detailed description.

[0099] Figure 8E Showing along Figure 8A The cross-sectional view taken by the cutting line D-D' in the drawing shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process according to an embodiment of this disclosure. It is shown from right to left in the plane of the drawing. Figure 8E The cross-sectional view shown indicates that the plane extends along the axis of repeated iterations of alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N in the first direction (D1) 809, intersecting across the plurality of individual vertical access lines 840-1, 840-2, ..., 840-4, and intersecting the regions of semiconductor materials 832-1, 832-2, ..., 832-N, in which channels and body regions separated from the plurality of individual vertical access lines 840-1, 840-2, ..., 840-4 by gate dielectric material 838 can be formed. Figure 8E In the diagram, the first dielectric filling material 839 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, as described in more detail below. The horizontally oriented access devices and horizontally oriented storage nodes can extend into and out of the drawing plane, and can be spaced apart along a first direction (D1) 809 and vertically stacked in a three-dimensional (3D) memory in an array extending in a third direction (D3) 811. Figures 8A-8E A cross-sectional view is shown of a portion of an example horizontally oriented access device according to many embodiments of the present disclosure, coupled to a horizontally oriented memory node and to vertically oriented access lines and horizontally oriented digital lines, such as those forming part of a vertically stacked memory cell array. The horizontally oriented access device 801 may have a first source / drain region and a second source / drain region separated by a channel and a body region, and a gate opposite to the channel region and separated from it by a gate dielectric.

[0100] Figure 9This is a block diagram of a device in the form of a computing system 900 including a memory device 903, according to several embodiments of the present disclosure. As used herein, for example, the memory device 903, memory array 910, and / or host 902 may also be considered as "devices". According to embodiments, the memory device 903 may include at least one memory array 910 having memory cells forming digit lines and body contacts according to embodiments described herein.

[0101] In this example, system 900 includes a host 902, which is coupled to memory device 903 via interface 904. In various other types of systems, computing system 900 may be a personal laptop computer, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device. Host 902 may include multiple processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing memory 903. System 900 may include a separate integrated circuit, or both host 902 and memory device 903 may reside on the same integrated circuit. For example, host 902 may be a system controller for a memory system including multiple memory devices 903, wherein system controller 905 provides access to the respective memory devices 903 via another processing resource such as a central processing unit (CPU).

[0102] exist Figure 1 In the illustrated example, host 902 is responsible for executing the operating system (OS) and / or various applications (e.g., processes) that can be loaded into the operating system (e.g., from memory device 903 via controller 905). The OS and / or various applications can be loaded from memory device 903 by providing access commands from host 902 to memory device 903 to access data including the OS and / or various applications. Host 902 can also access data used by the OS and / or various applications by providing access commands to memory device 903 to retrieve the data used in the execution of the OS and / or various applications.

[0103] For clarity, system 900 has been simplified to focus on features particularly relevant to this disclosure. Memory array 910 may be a DRAM array comprising at least one memory cell having digit lines and body contacts formed according to the techniques described herein. For example, memory array 910 may be an unshielded DL4F2 array such as a 3D-DRAM memory array. Array 910 may include memory cells arranged in rows coupled by word lines (which may be referred to herein as access lines or select lines) and columns coupled by digit lines (which may be referred to herein as read lines or data lines). Although in Figure 1A single array 910 is shown, but the embodiments are not limited thereto. For example, memory device 903 may contain a plurality of arrays 910 (e.g., a plurality of DRAM cell libraries).

[0104] Memory device 903 includes an address circuitry system 906 for latching address signals provided on interface 904. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). Such a protocol may be custom or proprietary, or interface 904 may employ standardized protocols such as PCIe, Gen-Z, CCIX, etc. Address signals are received and decoded via row decoder 908 and column decoder 912 to access memory array 910. Data can be read from memory array 910 by reading voltage and / or current changes on read lines using read circuitry system 911. Read circuitry system 911 may include, for example, a read amplifier capable of reading and latching a page (e.g., a row) of data from memory array 910. I / O circuitry system 907 can be used for bidirectional data communication with host 902 via interface 904. Read / write circuitry system 913 is used for writing data to or reading data from memory array 910. As an example, circuit system 913 may include various driver, latch circuit systems, etc.

[0105] The control circuitry 905 includes register 918 and decodes signals provided by host 902. These signals can be commands provided by host 902. These signals can include chip enable signals, write enable signals, and address latch signals, which control operations performed on memory array 910, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry 905 is responsible for executing instructions from host 902. Control circuitry 905 can include a state machine, a sequencer, and / or some other type of control circuitry, which can be implemented in hardware, firmware, or software, or any combination of these three. In some instances, host 902 can be a controller external to memory device 103. For example, host 902 can be a memory controller coupled to the processing resources of a computing device.

[0106] The term semiconductor can refer to, for example, materials, wafers, or substrates, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when semiconductors are referred to in the preceding description, regions / junctions may have been formed in the substrate semiconductor structure using prior process steps, and the term semiconductor can include an underlying material containing such regions / junctions.

[0107] The accompanying drawings follow a numbering convention, wherein one or more first digits correspond to the drawing number, and the remaining digits identify elements or components in the drawings. Similar (e.g., identical) elements or components between different drawings may be identified by using similar digits. As will be understood, elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide multiple additional embodiments of this disclosure. Furthermore, it should be understood that the scale and / or relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be taken in a limiting sense.

[0108] As used herein, “many” or “a certain amount” of things can refer to one or more of such things. For example, many or a certain amount of memory cells can refer to one or more memory cells. Multiple things means two or more. As used herein, multiple actions performed jointly refer to actions that overlap or at least partially overlap over a specific time period. The term “coupled” as used herein can include electrical coupling without intermediate elements, direct coupling and / or direct connection (e.g., through direct physical contact), indirect coupling and / or connection with intermediate elements, or wireless coupling. The term “coupled” can further include two or more elements that cooperate or interact with each other (e.g., as in causality). An element coupled between two elements can be between and coupled to each of the two elements.

[0109] It should be recognized that the term "vertical" interprets variations in verticality due to routine manufacturing, measurement, and / or assembly variations, and those skilled in the art should understand the meaning of the term "vertical." For example, "vertical" can correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be located on top of the other element, or may be located to the side of the other element and / or may be in direct physical contact with the other element. "Located to the side" can refer, for example, to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0110] Although specific embodiments have been shown and described herein, those skilled in the art will understand that arrangements intended to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of the various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. After reading the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims together with the full scope of their equivalents.

Claims

1. A semiconductor manufacturing method, comprising: In repeated iterations, layers of a first dielectric material (430, 530, 630, 730, 830), a semiconductor material (432, 532, 632, 732), and a second dielectric material (433, 533, 633, 733, 833) are vertically formed to form a vertical stack (401); A vertical opening (471) is formed using an etching process to expose the vertical sidewalls in the vertical stack (401); Seed material (416) is deposited on the vertical sidewalls of the vertical stack (401); as well as The vertical stack (401) is processed under temperature and time parameters such that the seed material (416) on the sidewall of the semiconductor material (432, 532, 632, 732) advances a first distance (DIST1) toward the semiconductor material (432, 532, 632, 732) to transform a portion of the semiconductor material (432, 532, 632, 732) at the first distance (DIST1) into a crystal structure.

2. The semiconductor manufacturing method according to claim 1, wherein vertically forming layers of the first dielectric material (430, 530, 630, 730, 830), the semiconductor material (432, 532, 632, 732), and the second dielectric material (433, 533, 633, 733, 833) in repeated iterations to form the vertical stack (401) comprises: The oxide material is deposited as the first dielectric material (430, 530, 630, 730, 830); Amorphous silicon material is deposited as the semiconductor material (432, 532, 632, 732); as well as Nitride materials are deposited as the second dielectric material (433, 533, 633, 733, 833).

3. The semiconductor manufacturing method according to claim 2, wherein the seed material (416) comprises nickel as the seed material (416), and processing the vertical stack (401) under the temperature and time parameters comprises forming a nickel silicide (415) with nickel (Ni) and the amorphous silicon (432, 532, 632, 732) at a first distance (DIST1) from the vertical opening (471).

4. The semiconductor manufacturing method according to claim 2, wherein the seed material (416) comprises cobalt as the seed material (416), and processing the vertical stack (401) under the temperature and time parameters comprises forming a cobalt silicide (415) with cobalt (Co) and the amorphous silicon (432, 532, 632, 732) at a first distance (DIST1) from the vertical opening (471).

5. The semiconductor manufacturing method according to claim 2, wherein the seed material (416) comprises silver as the seed material (416), and processing the vertical stack (401) under the temperature and time parameters comprises forming a silver silicide (415) with silver (Ag) and the amorphous silicon (432, 532, 632, 732) at a first distance (DIST1) from the vertical opening (471).

6. The semiconductor manufacturing method according to any one of claims 1 to 2, further comprising processing the vertical stack (401) under temperature and time parameters such that as the seed material (416) advances within the semiconductor material (432, 532, 632, 732), the seed material transforms the crystal structure of said portion of the semiconductor material (432, 532, 632, 732) into a single-crystal silicon material (417).

7. The semiconductor manufacturing method according to any one of claims 1 to 2, further comprising processing the vertical stack (401) under temperature and time parameters such that as the seed material (416) advances within the semiconductor material (432, 532, 632, 732), the seed material transforms the crystal structure of said portion of the semiconductor material (432, 532, 632, 732) to increase the size of individual crystals in said portion of the semiconductor material (432, 532, 632, 732).

8. A semiconductor manufacturing method, comprising: In repeated iterations, layers of oxide materials (430, 530, 630, 730, 830), silicon materials (432, 532, 632, 732) and nitride materials (433, 533, 633, 733, 833) are vertically deposited to form a vertical stack (401); A vertical opening (471) is formed using an etching process to expose the vertical sidewalls in the vertical stack (401); Selectively depositing a metal seed material (416) to form a metal silicide (415) on the vertical sidewalls of the silicon material (432, 532, 632, 732) in the vertical opening (471) of the vertical stack (401); and The vertical stack (401) is processed under temperature and time parameters such that the metal silicide (415) advances horizontally through the silicon material (432, 532, 632, 732) defined by the oxide material (430, 530, 630, 730, 830) and the nitride material (433, 533, 633, 733, 833), and a portion of the silicon material (432, 532, 632, 732) is transformed from an amorphous silicon structure (432, 532, 632, 732) to a monocrystalline silicon structure (417) along a length of a first distance (DIST1) from the vertical opening (471).

9. The semiconductor manufacturing method of claim 8, further comprising processing the vertical stack (401) such that the metal silicide (415) advances horizontally through the silicon material (432, 532, 632, 732) at the first distance (DIST1) and provides a separating interface between the monocrystalline silicon (417) and the amorphous silicon structure (432, 532, 632, 732), wherein the crystal on the monocrystalline (417) side of the interface is larger than the crystal in the amorphous silicon structure (432, 532, 632, 732).

10. A semiconductor manufacturing method, comprising: In repeated iterations, layers of oxide materials (430, 530, 630, 730, 830), amorphous silicon materials (432, 532, 632, 732), and nitride materials (433, 533, 633, 733, 833) are vertically deposited to form a vertical stack (401). A vertical opening (471) is formed using an etching process to expose the vertical sidewalls in the vertical stack (401); Metal seed material (416) is selectively deposited on the vertical sidewalls of the amorphous silicon (432, 532, 632, 732) to form metal silicide (415) using atomic layer deposition (ALD) process; as well as The vertical stack (401) is processed under temperature and time parameters such that the metal silicide (415) advances horizontally through the amorphous silicon (432, 532, 632, 732) at a first distance (DIST1) from the vertical opening (471), and the amorphous silicon (432, 532, 632, 732) is recrystallized into a single-crystal silicon structure (417) to define a first region (742, 842) in the vertical stack (401).

11. The semiconductor manufacturing method according to claim 10, further comprising: The horizontally oriented access device (330) in the vertical stack (401) is formed using the recrystallized single-crystal silicon structure (417) in the first region (742, 842); and The metal silicide (415) at the first distance (DIST1) from the vertical opening (471) is used as an etch stop, while the amorphous silicon (432, 532, 632, 732) is selectively removed from the second region (744) of the vertical stack (401) to form a memory node (227).

12. The semiconductor manufacturing method according to any one of claims 10 to 11, further comprising: Horizontal capacitor cells (227) are formed in amorphous silicon (432, 532, 632, 732) selectively removed from the second region (744) of the vertical stack (401) using an atomic layer deposition (ALD) process; and The metal silicide material (415) is used as the ohmic contact of the first electrode (861) of the capacitor (227) formed in the second region (744).

13. The semiconductor manufacturing method according to any one of claims 10 to 11, further comprising processing the vertical stack (401) under temperature and time parameters to advance the metal silicide (415) horizontally, thereby recrystallizing the amorphous silicon (432, 532, 632, 732) into a single-crystal silicon structure (417) to have subgrain boundaries.

14. A memory cell array, comprising: A plurality of access transistors (230, 330) stacked on top of each other, each of the access transistors (230, 330) comprising a first source / drain region (221, 321), a second source / drain region (223, 323, 778) arranged horizontally therebetween and a channel region (225, 325) and a body region (326), wherein the channel region (225, 325) and the body region (326) are each formed of a single crystal semiconductor material (432, 532, 632, 732); Metal silicide, which is present in each of the plurality of access transistors (230, 330), wherein the single-crystal semiconductor material (432, 532, 632, 732) of each of the access transistors is on the side of the metal silicide opposite to the amorphous semiconductor material of each of the access transistors; At least one access line (103, 203, 303, 540, 640, 740, 840), the at least one access line extending vertically and coupled to each of the channel regions (225, 325) of the plurality of access transistors (230, 330) with the intervention of a gate dielectric (304, 538, 638, 738, 838); Multiple storage capacitors (227) stacked on top of each other, each of the multiple storage capacitors (227) being placed horizontally and coupled to a corresponding second source / drain region (223, 323, 778) of the multiple access transistors (230, 330); Multiple digital lines (107, 207, 477), each of the multiple digital lines (107, 207, 477) is coupled to a corresponding first source / drain region in the first source / drain region (221, 321) of the multiple access transistors (230, 330); as well as Body contacts (295, 495) extend vertically and are coupled to each of the body regions (326) of the plurality of access transistors (230, 330).

15. The memory cell array of claim 14, wherein the access transistor (230, 330) has three nodes, the three nodes including a first source / drain region (221, 321) (1) having direct electrical contacts (295, 495), a second source / drain region (223, 323, 778) (2) and the channel region (225, 325) (3).

16. The memory cell array according to any one of claims 14 to 15, wherein the storage capacitor (227) comprises a capacitor cell (227) having a first horizontally oriented electrode (861) electrically coupled to the first source / drain region (221, 321) of the access transistor (230, 330) and a second electrode (856) separated from the first horizontally oriented electrode (861) by a cell dielectric (863).

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