Channel integration in a three-node access device for vertical three-dimensional (3D) memory

Abstract

This application relates to channel integration in a three-node access device of a vertical 3D memory. An example method includes a method for forming a vertically stacked array of memory cells having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of dielectric and sacrificial materials in repeated iterations to form a vertical stack. An etching process is used to form a first vertical opening exposing a vertical sidewall adjacent to a first region in the vertical stack. The first region is selectively etched to form a first horizontal opening removing the sacrificial material, extending a first horizontal distance backward from the first vertical opening. A first source / drain material, an alternative channel material with back channel passivation, and a second source / drain material are deposited in the first horizontal opening to form the three-node access device of the memory cells in the vertically stacked memory cell array.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to channel integration in a three-node access device for a vertical three-dimensional (3D) memory. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, cell phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), or the like.

[0003] With shrinking design rules, less semiconductor space is available for manufacturing memories containing DRAM arrays. A corresponding memory cell for DRAM may include access means, such as transistors, having first and second source / drain regions separated by a channel region. A gate may be opposite to and separated from the channel region by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. A DRAM cell may include memory nodes, such as capacitor cells, coupled to digital lines via access means. Access means may be activated (e.g., for selecting a cell) via access lines coupled to access transistors. Capacitors may store charge corresponding to the data value (e.g., logic "1" or "0") of the corresponding cell. Summary of the Invention

[0004] One aspect of this disclosure relates to a method for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines, the method comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack; forming a first vertical opening using a first etching process that exposes a vertical sidewall in the vertical stack adjacent to a first portion of the sacrificial material; selectively etching the first portion of the sacrificial material to form a first horizontal opening that removes the sacrificial material in a first region and extends backward by a first horizontal distance from the first vertical opening; and depositing a first source / drain material, an alternative channel material having back channel passivation, and a second source / drain material in the first horizontal opening to form a three-node access means for memory cells in the vertically stacked memory cell array.

[0005] Another aspect of this disclosure relates to a method for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines, the method comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, extending through the vertical stack and primarily in the second horizontal direction to form an elongated column of vertical struts with sidewalls in the vertical stack; and conformally depositing a first conductive material in the first vertical openings onto a gate dielectric material. Above; removing a portion of the first conductive material to form a plurality of separated vertical access lines along the sidewalls of the elongated vertical strut array; forming a second vertical opening that exposes the vertical sidewalls of the first portion of the sacrificial material in the vertical stack; selectively removing the first portion of the sacrificial material to form a first horizontal opening in a first region that extends a first horizontal distance backward from the second vertical opening; and depositing a first source / drain material, a multilayer channel material with back channel passivation, and a second source / drain material in the first horizontal opening to form a three-node access device for memory cells in a vertically stacked memory cell array.

[0006] Another aspect of this disclosure relates to a method for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines, the method comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, extending through the vertical stack and primarily in the second horizontal direction to form an elongated column of vertical struts with sidewalls in the vertical stack; and conformally depositing a first conductive material on a gate dielectric material in the first vertical openings. The process involves: removing a portion of the first conductive material to form a plurality of separated vertical access lines along the sidewalls of an elongated vertical strut column; forming a second vertical opening that exposes the vertical sidewalls of the first portion of the sacrificial material in the vertical stack; selectively removing the first portion of the sacrificial material to form a first horizontal opening in a first region, extending a first horizontal distance backward from the second vertical opening; and depositing a first source / drain material, a gradient channel material with back channel passivation, and a second source / drain material in the first horizontal opening to form a three-node access device for memory cells in a vertically stacked memory cell array.

[0007] Another aspect of this disclosure relates to a memory device comprising a vertically stacked memory cell array, the vertically stacked memory cell array comprising: a horizontally oriented three-node access device having a first source / drain region and a second source / drain region separated by a replacement channel region having a back channel passivation, and a gate opposite to the replacement channel region and separated from the replacement channel region by a gate dielectric, wherein the three-node access device does not have direct electrical body contact with the body region of the three-node access device or the replacement channel region; a vertically oriented access line coupled to the gate and separated from the replacement channel region by a gate dielectric; a horizontally oriented memory node electrically coupled to the first source / drain region of the three-node access device; and a horizontally oriented digital line electrically coupled to the second source / drain region of the three-node access device. Attached Figure Description

[0008] Figure 1 This is a schematic illustration of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0009] Figure 2 This is a perspective view of a portion of a three-node access device in a vertical three-dimensional (3D) memory array according to several embodiments of the present disclosure.

[0010] Figure 3 This is a perspective view of a portion of a three-node access device in a vertical three-dimensional (3D) memory cell, according to several embodiments of the present disclosure.

[0011] Figure 4 This invention describes an example method, according to several embodiments of the present disclosure, for forming a vertically stacked memory cell array at a stage of a semiconductor manufacturing process to form a three-node access device.

[0012] Figures 5A to 5B This invention describes an example method, according to several embodiments of the present disclosure, for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process.

[0013] Figures 6A to 6E This invention describes an example method, according to several embodiments of the present disclosure, for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process.

[0014] Figures 7A to 7E This invention describes an example method, according to several embodiments of the present disclosure, for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process.

[0015] Figures 8A to 8EThis invention describes an example method, according to several embodiments of the present disclosure, for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process.

[0016] Figures 9A to 9F This invention describes an example method, according to several embodiments of the present disclosure, for forming a vertically stacked memory cell array having horizontally oriented three-node access means and vertically oriented access lines at another stage of the semiconductor manufacturing process.

[0017] Figure 10 This invention describes an example method for forming a channel region with back channel passivation using an atomic layer deposition (ALD) process to form a three-node access device, according to several embodiments of the present disclosure.

[0018] Figure 11 This invention describes another example method for forming a channel region with back channel passivation using an atomic layer deposition (ALD) process to form a three-node access device, according to several embodiments of the present disclosure.

[0019] Figure 12 This invention describes another example method for forming a channel region with back channel passivation using an atomic layer deposition (ALD) process to form a three-node access device, according to several embodiments of the present disclosure.

[0020] Figure 13 Examples of a horizontally oriented three-node access device coupled to a horizontally oriented memory node and coupled to a vertically oriented access line and a horizontally oriented digital line, according to several embodiments of the present disclosure, are described.

[0021] Figure 14 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0022] Embodiments of this disclosure describe a three-node access device for a vertical three-dimensional (3D) memory. The three-node horizontal access device is formed without body region contacts. As used herein, three-node is intended to refer to an access device comprising (1) a first source / drain region and (2) a second source / drain region separated by a channel region, and (3) one or more gates opposite the channel region. In the three-node access device, there are no direct electrical contacts from the body contact line to the body region and / or channel of the access device for controlling the body region or channel of the access device. Therefore, semiconductor manufacturing overhead is reduced by eliminating the need to form such body contacts.

[0023] The three-node horizontal access device is integrated with the vertical access line and the horizontal digital line. According to an embodiment, the three-node horizontal access device can be formed using alternative channels, such that the channel region has fewer minority carriers, allowing operation, for example, without minority carriers, thus eliminating the need to control the body potential of the access device's body region. Thin-film transistor (TFT) access devices using oxide semiconductor materials can exhibit current leakage through a back channel region of the oxide semiconductor, which is furthest from the gate electrode. Material configurations are provided to suppress leakage current in the back channel region. Advantages of the structures and processes described herein may include lower cutoff current (Ioff) for the access device (compared to silicon-based (Si-based) access devices) and / or reduced gate / drain induced leakage (GIDL) for the access device.

[0024] In some embodiments, channel and / or source / drain region replacement fabrication steps can be performed after the capacitor cell formation process, thus reducing the thermal budget. Digital line integration can be more easily achieved during fabrication because no body contact to the body region of the access device is used. Additionally, the embodiments described herein achieve better lateral scaling paths than those achieved using channel regions based on doped polysilicon, due to shorter channel lengths and lower source / drain semiconductor fabrication process overhead. Another benefit is the avoidance (e.g., non-use) of gas phase doping (GPD) during source / drain region formation.

[0025] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number of the accompanying drawing, and the remaining numbers identify elements or components in the drawing. Similar elements or components between different figures can be identified by using similar numbers. For example, reference numeral 104 in... Figure 1 The term "04" can refer to component "04", and similar components can be found in [the following text is incomplete and likely refers to another component]. Figure 2 The Chinese character for "symbol" is 204. Multiple similar elements within a diagram can be represented by a number followed by a hyphen and another number or letter. For example, 302-1 could refer to... Figure 3 Component 302-1 and 302-2 may refer to component 302-2, which may be similar to component 302-1. Such similar components may be generally referred to without hyphens and additional numbers or letters. For example, components 302-1 and 302-2 or other similar components may be generally represented as 302.

[0026] Figure 1 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 1 The illustration shows a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 1The cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each sub-cell array (e.g., sub-cell array 101-2) can contain multiple access lines 103-1, 103-2, ..., 103-Q (which may also be called word lines). Additionally, each sub-cell array (e.g., sub-cell array 101-2) can contain multiple digital lines 107-1, 107-2, ..., 107-Q (which may also be called bit lines, data lines, or sensing lines). Figure 1 The text describes digital lines 107-1, 107-2, ..., 107-Q extending in a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, access lines 103-1, 103-2, ..., 103-Q extend in, for example, the vertical direction of the third direction (D3) 111.

[0027] The memory cell (e.g., 110) may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 103-1, 103-2, ..., 103-Q and each digital line 107-1, 107-2, ..., 107-Q. The memory cell can be written to or read from using the access lines 103-1, 103-2, ..., 103-Q and the digital lines 107-1, 107-2, ..., 107-Q. Digital lines 107-1, 107-2, ..., 107-Q can electrically interconnect memory cells along the horizontal columns of each sub-cell array 101-1, 101-2, ..., 101-N, and access lines 103-1, 103-2, ..., 103-Q can electrically interconnect memory cells along the vertical rows of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) can be located between an access line (e.g., 103-2) and a digital line (e.g., 107-2). Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-Q.

[0028] Digital lines 107-1, 107-2, ..., 107-Q may be or comprise conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 107-1, 107-2, ..., 107-Q may extend in a first direction (D1) 109. Digital lines 107-1, 107-2, ..., 107-Q in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0029] Access lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending relative to the substrate in a vertical direction (e.g., on a third direction (D3) 111). Access lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0030] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 103-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a digital line (e.g., 107-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node, such as a capacitor. The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a storage node, such as a capacitor. Although the references to first and second source / drain regions are used herein to denote two independent and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" source / drain regions have a particular meaning. It is only desirable that one of the source / drain regions is connected to a digital line, such as 107-2, and the other may be connected to a storage node.

[0031] Figure 2 The illustration shows a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure (e.g., Figure 1 The perspective view shown is a portion of the sub-cell array 101-2 as a vertically oriented stack of memory cells in the array. Figure 3 Explanation and display Figure 2 The unit cell of the 3D semiconductor memory device shown in the image (e.g.) Figure 1 A perspective view of the memory cell 110 shown in the image.

[0032] like Figure 2 As shown, bonding can be formed on substrate 200. Figure 1 One of the described array of sub-cells (e.g., 101-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0033] like Figure 2 As shown in the example embodiments, memory cells extending in a vertical direction, such as a third direction (D3) 111, can be fabricated on the substrate 200 (e.g. Figure 1 The memory cells 110 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 1 The memory cells 110 are formed on multiple vertical levels, such as a first level (L1), a second level (L2), and a third level (L3). Repeating vertical levels L1, L2, and L3 can be arranged (e.g., "stacked") on, for example... Figure 1 The vertical direction of the third-party (D3) 111 shown in the figure. Each of the repeating vertical levels L1, L2, and L3 may contain multiple discrete components (e.g., areas) of laterally oriented access devices 230 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 103-1, 103-2, ..., 103-Q connectors and digital lines 107-1, 107-2, ..., 107-Q connectors. Horizontally oriented three-node access devices (e.g. Figure 1 Multiple discrete components of transistor 110 in the transistor can be formed in multiple iterations of a vertically repeating layer within each level, as described below. Figure 4 A more detailed description is available, and it can be found in similar formats. Figure 1 The second direction (D2) 105 shown in the middle extends horizontally on the second direction (D2) 205.

[0034] A plurality of discrete components of a horizontally oriented three-node access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 extending laterally in a second direction (D2) 205. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first and second source / drain regions 221 and 223 may include an n-type dopant region (e.g., semiconductor material) formed adjacent to a p-type doped channel region (e.g., semiconductor material) of the access device to form an n-type conductive transistor. In some embodiments, the first and second source / drain regions 221 and 223 may include a p-type conductivity (e.g., doped semiconductor material) formed adjacent to an n-type conductive channel region (e.g., doped semiconductor material) of the access device to form a p-type conductive transistor. By way of example, but not limitation, n-type dopants may contain phosphorus (P) atoms and p-type dopants may contain boron (B) atoms formed in a relatively doped host region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0035] Storage node 227 (e.g., a capacitor) can be connected to a corresponding end of the access device. For example... Figure 2 As shown, storage node 227 (e.g., a capacitor) can be connected to the second source / drain region 223 of the access device. A storage node can be or contains a memory element capable of storing data. Each of the storage nodes can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 1 Each memory node associated with an access device in memory cell 110 can be similarly located in a memory node with a memory node ... Figure 1 The second direction (D2) 105 shown in the middle extends upwards from the second direction (D2) 205.

[0036] like Figure 2 As shown, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P are similar to... Figure 1 The first direction (D1) of 109 extends upwards from 209. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P can be similar to... Figure 1 The digital lines 107-1, 107-2, ..., 107-Q are shown in the diagram. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P may be arranged (e.g., "stacked") along a third direction (D3) 211. The multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P may contain a conductive material. For example, the conductive material may include one or more of the following: doped semiconductors, such as doped silicon, doped germanium, etc.; conductive metal nitrides, such as titanium nitride, tantalum nitride, etc.; metals, such as tungsten (W), titanium (Ti), tantalum (Ta), etc.; and / or metal semiconductor compounds, such as tungsten silicide, cobalt silicide, titanium silicide, etc. However, the embodiments are not limited to these examples.

[0037] In each of the vertical levels (L1) 213-1, (L2) 213-2, and (L3) 213-P, the horizontally oriented memory cells (e.g.) Figure 1 The memory cells 110 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4As described in more detail, multiple discrete components of the laterally oriented access device 230, such as a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 extending laterally in the second direction (D2) 205, and multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally in the first direction (D1) 209, can be formed in different vertical layers within each level. For example, the multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally in the first direction (D1) 209 can be disposed on and electrically contacted on the top surface of the first source / drain region 221, and orthogonal to the laterally oriented access device 230 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 are formed in a higher vertical layer within a layer hierarchy (e.g., within layer (L1)), which is further away from the substrate 200 than the layer in which discrete components of laterally oriented access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by channel region 225) are formed. In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 may be connected directly and / or through additional contacts comprising metal silicide to the top surface of the first source / drain region 221.

[0038] like Figure 2 As shown in the example embodiments, access lines 203-1, 203-2, ..., 203-Q extend vertically relative to substrate 200, for example, on third-direction (D3) 211. Furthermore, as... Figure 2 As shown, a sub-cell array (e.g.) Figure 1 Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 101-2 can be spaced apart from each other in a first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can be configured to extend vertically in a third direction (D3) 211 relative to the substrate 200 between a pair of horizontally oriented three-node access devices 230 (e.g., transistors, extending laterally in a second direction (D2) 205), but adjacent to each other in the first direction (D1) 209 at a level such as a first layer (L1). Each of access lines 203-1, 203-2, ..., 203-Q can extend vertically in a third direction (D3) on the sidewall of the corresponding of a plurality of vertically stacked horizontally oriented three-node access devices 230 (e.g., transistors).

[0039] For example, and such Figure 3 As shown in more detail, the first of the vertically extending access lines (e.g., 203-1) may be adjacent to the sidewall of the channel region 225 of the first horizontally oriented three-node access device 230 (e.g., transistor) in the first level (L1) 213-1, the sidewall of the channel region 225 of the first horizontally oriented three-node access device 230 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the first horizontally oriented three-node access device 230 (e.g., transistor) in the third level (L3) 213-P, etc. Similarly, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the first level (L1) 213-1, which is spaced apart from the first horizontally oriented three-node access device 230 (e.g., transistor) in the first direction (D1) 209. Furthermore, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the second level (L2) 213-2 and the sidewall of the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the third level (L3) 213-P, etc. The embodiments are not limited to a specific number of levels.

[0040] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 1 The word line (WL) of the description.

[0041] like Figure 2 As shown in the example embodiment, the insulating layer dielectric (ILD) 250 may be formed such that the end surfaces of the horizontally oriented three-node access devices 230 (e.g., transistors) in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200 extend in a first direction (D1) 209. The ILD 250 may isolate and separate vertically stacked memory cell arrays along a second direction (D2) 205, for example... Figure 1 The ILD 250 may contain an insulating material, such as a dielectric material, such as an oxide material, a silicon oxide (SiO2) material, a silicon nitride (SiN) material, a silicon oxynitride material, and / or a combination thereof.

[0042] although Figure 2 Not shown, but insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0043] Figure 3 A more detailed description of vertically stacked memory cell arrays according to some embodiments of the present disclosure (e.g.) Figure 1 (Unit cells within sub-cell array 101-2, for example) Figure 1 Memory unit 110 in the middle. For example... Figure 3 As shown, the first and second source / drain regions 321 and 323 may be impurity-doped regions of a horizontally oriented three-node access device 330 (e.g., a transistor). The first and second source / drain regions 321 and 323 may also include metals and / or metal composites formed using processes such as atomic layer deposition containing: ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor material means a semiconductor material, such as polycrystalline silicon, containing a high level of doping that utilizes significant interactions between dopants such as phosphorus (P), boron (B), etc. In contrast, non-degenerate semiconductors contain a moderate level of doping, wherein the dopant atoms are well separated from each other in the semiconductor bulk lattice with negligible interactions. The first and second source / drain regions 321 and 323 may be similar to Figure 2 The first and second source / drain regions 221 and 223 are shown in the figure.

[0044] The first and second source / drain regions may be separated by a channel 325 (e.g., a channel region) of a horizontally oriented three-node access device 330 (e.g., a transistor). The channel may be a lightly doped (p-) polycrystalline silicon material. In some embodiments, the channel 325 may be a lightly doped (p-) polycrystalline germanium (Ge) material. In some embodiments, the channel 325 may be a lightly doped (p-) polycrystalline silicon germanium (polycrystalline SiGe) material. However, in some embodiments, the channel 325 may include a semiconductor oxide (also referred to herein as “oxide semiconductor” or “oxide semiconductor material”). The semiconductor oxide may include any suitable composition; and in some embodiments, it may include one or more of indium, zinc, tin, and gallium. Examples of oxide semiconductor materials and / or compositions comprising one or more of indium, zinc, tin, and gallium, as used herein, may include, for example, materials such as ZnO.x 、InO x 、SnO2, Zn x O y 、N, Mg x Zn y O z 、In x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、In x Ga y Si z O a 、Zr x In y Zn z O a 、Hf x In y Zn z O a 、Sn x In y Zn z O​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​In an additional embodiment, channel 325 may comprise a two-dimensional (2D) material. The 2D material may comprise any suitable composition; and in some embodiments, it may comprise one or more transition metal dichalcogenides, including molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum distelluride (MoTe2), tungsten sulfide (WS2), and tungsten selenide (WSe2). However, the embodiments are not limited to these examples.

[0046] In some embodiments, channel 325 may comprise a composite material, such as indium gallium zinc oxide (In2Ga2ZnO7) material (also referred to herein as "IGZO"). In some embodiments, the composite IGZO material is a multilayer I2G2ZnO7 channel that is indium (In) rich in the first layer, which is closest to the channel and opposite to the gate dielectric, relative to the plurality of layers. In some embodiments, the composite IGZO material is a multilayer I2G2ZnO7 channel that is gallium (Ga) rich in the outer layer, which is furthest from the channel and opposite to the gate dielectric, relative to the plurality of layers. And, in some embodiments, the composite IGZO material is a multilayer I2G2ZnO7 channel that is zinc (Zn) rich in the outer layer, which is furthest from the channel and opposite to the gate dielectric, relative to the plurality of layers, and so on. However, the embodiments are not limited to these examples.

[0047] Similar to Figure 2 The number lines 207-1, 207-2, ..., 207-P and Figure 1 The digital lines 107-1, 107-2, ..., 107-Q shown (e.g., 307-1) can be configured to make electrical contact with the first source / drain region 321. For example... Figure 3 As shown in the example embodiments, similar to Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1Access lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) may be adjacent to the sidewalls of the channel region 325, which is horizontally conductive between the first and second source / drain regions 321 and 323 along a second direction (D2) 305 of the horizontally oriented three-node access device 330 (e.g., a transistor), extending vertically in a third direction (D3) 311. A gate dielectric material 304 may be inserted between the access line 303-1 (a portion of which forms the gate of the horizontally oriented three-node access device 330 (e.g., a transistor)) and the channel region 325. The gate dielectric material 304 may comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof. Embodiments are not limited thereto. For example, in high-k dielectric material examples, the gate dielectric material 304 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0048] Figure 4 Explanation for example Figures 1 to 3 Example methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines at a stage of a semiconductor manufacturing process, as described in and according to several embodiments of this disclosure. Figure 4 In the example embodiments shown in the examples, the method includes depositing alternating layers of dielectric material 430-1, 430-2, ..., 430-N (also independently and / or collectively referred to herein as "430") and sacrificial material 432-1, 432-2, ..., 432-N (also independently and / or collectively referred to as "432") in repeated iterations to form a vertical stack 401 on a processing surface of semiconductor substrate 400. In one embodiment, dielectric material 430 may be deposited having a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm, for example, a vertical height in a third direction (D3). In one embodiment, sacrificial material 432 may be deposited having a thickness in the range of twenty (20) nm to one hundred (100) nm, for example, a vertical height. However, the embodiments are not limited to these examples.

[0049] In one example, the sacrificial materials 432-1, 432-2, ..., 432-N may comprise, for example, a sacrificial semiconductor material of polycrystalline silicon (Si) or even an oxide-based semiconductor composition. While examples of sacrificial semiconductor materials will be mentioned in the discussion herein, the embodiments are not limited to this example. It is desirable that the sacrificial materials can be selectively etched relative to alternating layers of dielectric materials 430-1, 430-2, ..., 430-N.

[0050] like Figure 4As shown in the diagram, the vertical direction 411 is described as similar to... Figures 1 to 3 The third direction (D3) among the first, second, and third directions shown is, for example, the z-direction in the xyz coordinate system. Figure 4 In this example, four layers of repeated iterations of the vertical stack 401 are shown, numbered 1, 2, 3, and 4. However, the embodiments are not limited to this example and may include more or fewer repeated iterations. A photolithographic hard mask (HM) layer 435 may be deposited as a top layer on the repeated iterations of the vertical stack 401.

[0051] In some embodiments, dielectric materials 430-1, 430-2, ..., 430-N may be interlayer dielectrics (ILDs). By way of example, but not limitation, dielectric materials 430-1, 430-2, ..., 430-N may include silicon dioxide (SiO2) material. In another embodiment, dielectric materials 430-1, 430-2, ..., 430-N may include silicon nitride (Si3N4) material (also referred to herein as “SiN”). In yet another embodiment, dielectric materials 430-1, 430-2, ..., 430-N may include silicon carbide (SiO2). x C y The material (also referred to herein as "SiOC"). In another example, the dielectric materials 430-1, 430-2, ..., 430-N may comprise silicon oxynitride (SiO2). x N y The materials used are (also referred to herein as "SiON") and / or combinations thereof. Embodiments are not limited to these examples. In some embodiments, the sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may comprise polycrystalline and / or amorphous silicon (Si) materials. In another example, the sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon nitride (SiN) materials. However, embodiments are not limited to these examples.

[0052] Alternating layers of dielectric material 430-1, 430-2, ..., 430-N and sacrificial semiconductor material 432-1, 432-2, ..., 432-N can be deposited in a semiconductor manufacturing apparatus according to a semiconductor manufacturing process such as chemical vapor deposition (CVD). However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of dielectric material 430-1, 430-2, ..., 430-N and sacrificial semiconductor material 432-1, 432-2, ..., 432-N in repeated iterations to form a vertical stack 401, such as... Figure 4 As shown in the image.

[0053] Figure 5A Explanation for example Figures 1 to 3Examples of methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, as described in the present disclosure and according to several embodiments thereof. Figure 5A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 5A In the example embodiments shown in the examples, the method includes using an etching process to form a plurality of first vertical openings 500 extending through a vertical stack to a substrate, having a first horizontal orientation (D1) 509 and a second horizontal orientation (D2) 505. In one example, as Figure 5A As shown, a plurality of first vertical openings 500 extend primarily in the second horizontal direction (D2) 505 and can form elongated vertical strut columns 513 together with sidewalls 514 in the vertical stack. The plurality of first vertical openings 500 can be formed using photolithography to pattern a photomask 535 on the vertical stack, for example, to form a hard mask (HM), prior to etching the plurality of first vertical openings 500.

[0054] Figure 5B It is along Figure 5A The image shows a cross-sectional view of the semiconductor structure at a specific point in the semiconductor manufacturing process, cut along line A-A'. Figure 5B The conductive materials 540-1, 540-2, ..., 540-4 can be formed on the gate dielectric material 538 within the plurality of first vertical openings 500. By way of example, but not limitation, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes can be used to conformally deposit the gate dielectric material 538 within the plurality of first vertical openings 500 to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 can be deposited to a specific thickness (t1) suitable for a particular design rule, for example, a gate dielectric thickness of approximately 10 nanometers (nm). However, the embodiments are not limited to this example. By way of example, but not limitation, the gate dielectric 538 may include silicon dioxide (SiO2) material, alumina (Al2O3) material, high dielectric constant (k) (e.g., high k) dielectric material, and / or combinations thereof, as also... Figure 3 As described in the text.

[0055] In addition, such as Figure 5BAs shown, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited in a plurality of first vertical openings 500 on the surface of the gate dielectric material 538. By way of example, but not limitation, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes can be used to conformally deposit conductive materials 540-1, 540-2, ..., 540-4 in the plurality of first vertical openings 500 on the surface of the gate dielectric material 538 to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings above the gate dielectric 538. Conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a specific thickness (t2) to form vertically oriented access lines, for example, as shown in... Figure 1 The access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines) shown in the examples are suitable for specific design rules. For example, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example, but not by limitation, conductive materials 540-1, 540-2, ..., 540-4 may include, for example, metals such as tungsten (W), metal compositions, titanium nitride (TiN), doped polycrystalline silicon, and / or some other combination thereof, as also shown in the examples. Figure 3 As described in the text.

[0056] like Figure 5B As shown, conductive materials 540-1, 540-2, ..., 540-4 can be recessed rearward to remain only along the vertical sidewalls of the elongated vertical strut column, which is now... Figure 5B The cross-sectional views are shown as 542-1, 542-2, and 542-3. The first vertical opening (e.g., [missing information]) can be created using a suitable selective anisotropic etching process. Figure 5A The bottom surface of the 500) is modified by removing conductive materials 540-1, 540-2, ..., 540-4 to cause the multiple vertical access lines separated by conductive materials 540-1, 540-2, ..., 540-4 to be recessed backward, thereby exposing the gate dielectric 538 on the bottom surface to form the vertical access lines 540-1, 540-2, ..., 540-4. Figure 5B As shown, a dielectric material 539, such as an oxide or other suitable spin dielectric (SOD), can then be deposited in the first vertical opening 500 using a process such as CVD to fill the first vertical opening 500. Chemical mechanical planarization (CMP) or other suitable semiconductor fabrication techniques can be used to planarize the dielectric into a vertical semiconductor stack (e.g., Figure 4The top surface of the hard mask 535 (401) shown herein. CVD can be used to deposit and CMP can be used to planarize subsequent photolithography material 536 (e.g., the hard mask) to cover and close the first vertical opening 500 above the separating vertical access lines 540-1, 540-2, ..., 540-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0057] Figure 6A Explanation for example Figures 1 to 3 Examples of methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, as described in the present disclosure and according to several embodiments thereof. Figure 6A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 6A In an example embodiment, the method includes using a photolithography process to pattern... Figure 5B The photolithography masks in the middle are 636 and 536. Figure 6A The method further illustrates the use of a selective isotropic etching process to remove portions of the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, to separate and individually form multiple separating vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, for example... Figure 1 Access lines 103-1, 103-2, ..., 103-Q are shown in the diagram. Therefore, multiple separating vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are shown along the sidewalls of a slender vertical column, for example along... Figure 5B The sidewalls of the slender vertical strut rows 542-1, 542-2 and 542-3 in the cross-sectional view.

[0058] like Figure 6A As shown in the examples, a suitable selective isotropic etching process can be used to etch the first vertical opening (e.g., Figure 5A In the 500), the gate dielectric material 638 is removed to expose the conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z. For example... Figure 6AAs shown, a subsequent dielectric material 641, such as an oxide or other suitable spin dielectric (SOD), can be deposited to fill the remaining openings. From these remaining openings, the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be removed using processes such as CVD or other suitable techniques. The dielectric material 641 can be planarized onto a vertical semiconductor stack (e.g., using processes such as CMP or other suitable techniques). Figure 4 The top surface of the previous hard mask 635 (shown as 401). In some embodiments, CVD can be used to deposit and CMP can be used to planarize subsequent photolithography material 537 (e.g., a hard mask) to cover and close it. Figure 4 A plurality of separated vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are arranged above the processing surface of the vertical semiconductor stack 401, such that the plurality of separated vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are protected along the sidewalls of the elongated vertical pillar column. However, the embodiments are not limited to these process examples.

[0059] Figure 6B Explanation along Figure 6A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of this disclosure. Figure 6B The cross-sectional view shown is away from multiple separating vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and shows repeated iterations of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N on the semiconductor substrate 400 to form a vertical stack, for example... Figure 4 The 401 error shown in the image. Figure 6B As shown in the diagram, the vertical direction 611 is described as similar to... Figures 1 to 3 The third direction (D3) 111 shown in the diagram is, for example, the z-direction in the xyz coordinate system. The drawing plane extending to the right and left lies on the first direction (D1) 609. Figure 6B In an example embodiment, dielectric material 641 is shown filling a vertical opening in the remaining gate dielectric 638 deposition. The hard mask 637 described above covers the illustrated structure.

[0060] Figure 6C Explanation along Figure 6AThe cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of this disclosure. Figure 6C The cross-sectional view shown illustrates that the axis of repeated iterations along the alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N extends in a second direction (D2) 605, along which and within which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, the adjacent relative vertical access lines 640-3 are indicated by dashed lines that show the position of the plane and orientation settings from the drawing.

[0061] Figure 6D Explanation along Figure 6A The cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of the present disclosure. Figure 6D The cross-sectional view shown illustrates that the axis of repeated iterations along the alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N extends in a second direction (D2) 605, outside the area where horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) will be formed within the layers of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N. Figure 6D In the drawing, dielectric material 641 is shown filling the space between horizontally oriented access devices and horizontally oriented memory nodes, which are spaced apart along a first direction (D1) of the three-dimensional array of vertically oriented memory cells, extending in and out of the plane of the drawing. At the left end of the drawing, a repetitive iteration of alternating layers of dielectric materials 630-1, 630-2, ..., 630-(N+1) and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N is shown, at which point horizontally oriented digital lines (e.g., Figure 1 The digital lines 107-1, 107-2, ..., 107-Q shown in the figure can be integrated to form an electrical contact with the second source / drain region, which is described in more detail below.

[0062] Figure 6E Explanation along Figure 6A The cutting line D-D' in the figure shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of the present disclosure. From right to left on the plane of the drawing, Figure 6EThe cross-sectional view shown illustrates that the axis of repeated iterations along alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N extends in a first direction (D1) 609, traversing multiple separated vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and intersecting with regions of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, wherein channel regions may be formed through gate dielectric 638 to separate the multiple separated vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1). Figure 6E In the diagram, a first dielectric filling material 639 is shown as a space separating adjacent horizontally oriented access devices and horizontally oriented storage nodes (which may be formed to extend into and out of the plane of the drawing, as described in more detail below), and may be spaced apart along a first direction (D1) 609 and vertically stacked in an array extending along a third direction (D3) 611 in a three-dimensional (3D) memory.

[0063] Figure 7A Explanation for example Figures 1 to 3 Examples of methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, as described in the present disclosure and according to several embodiments thereof. Figure 7A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 7A In example embodiments, the method includes using a photolithography process to pattern photomasks 735, 736, and / or 737, for example... Figures 6A to 6E 635, 636 and / or 637. Figure 7A The method further illustrates the use of one or more etching processes to form the memory node region 750 (and Figure 7A and 7C A vertical opening 751 (in 744) extends through the vertical stack and primarily in the first horizontal direction (D1) 709. One or more etching processes form the vertical opening 751 to expose... Figures 7B to 7E The third sidewall in the repeated iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-N and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N in a vertically stacked configuration is adjacent to the second region of the sacrificial semiconductor material. Other numerical components can be similarly combined. Figures 6A to 6E Components for presentation and discussion.

[0064] According to embodiments, a second region of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N can be removed from alternating layers of dielectric materials 730-1, 730-2, ..., 730-N in a vertically stacked manner to form a memory node. In some embodiments, this process is performed before selectively removing the sacrificial semiconductor material from access device regions (e.g., transistor regions) where horizontally oriented first source / drain regions, channel regions, and second source / drain regions of the access device are formed. In other embodiments, this process is performed after selectively removing the sacrificial semiconductor material from access device regions where horizontally oriented first source / drain regions, channel regions, and second source / drain regions of the access device are formed. Figures 7B to 7E The example embodiment shown in the diagram includes a method that selectively etches second regions of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N to form a second horizontal opening extending rearward a second horizontal distance from a vertical opening 751 in a vertical stack. In some embodiments, such as Figures 7B to 7E As shown, the method includes forming a capacitor cell as a storage node in a second horizontal opening. By way of example, but not limitation, forming the capacitor includes using an atomic layer deposition (ALD) process to sequentially deposit a first electrode 761 and a second electrode 756 separated by a cell dielectric 763 in the second horizontal opening. Other suitable semiconductor fabrication techniques and / or storage node structures may be used.

[0065] Figure 7B Explanation along Figure 7A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of this disclosure. Figure 7B The cross-sectional view shown is away from multiple separating vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1), and shows repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1) separated by horizontally oriented capacitor cells on a semiconductor substrate 700 to form a vertical stack. The horizontally oriented capacitor cells have a first electrode 761 (e.g., a bottom cell contact electrode), a cell dielectric 763, and a second electrode 756 (e.g., a top common node electrode). Figure 7B As shown in the diagram, the vertical direction 711 is similar to... Figures 1 to 3 The third direction (D3) 111 shown in the diagram is one of the first, second, and third directions, such as the z-direction in the xyz coordinate system. The drawing plane extending to the right and left lies on the first direction (D1) 709. Figure 7B In example embodiments, for instance, the first electrode 761 and the second electrode 756 coupled to the bottom electrode of the source / drain region of the horizontal access device are illustrated as being separated by a cell dielectric material 763, which extends in and out of the plane of the drawing in a second direction (D2) and along the oriented axis of the horizontal access device and the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0066] Figure 7C Explanation along Figure 7A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of this disclosure. Figure 7C The cross-sectional view shown illustrates that the axis of repeated iterations along the alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N extends left and right along the plane of the drawing in the second direction (D2) 705. Along this axis, and within it, horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N. Figure 7C In the example embodiment, the horizontally oriented memory node (e.g., capacitor cell) is illustrated as having been formed during this semiconductor manufacturing process, and shows a first electrode 761 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 756 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 763. However, the embodiments are not limited to this example. In other embodiments, after forming the first source / drain region, channel region, and second source / drain region in the regions of the sacrificial semiconductor material 732-1, 732-2, ..., 732-N intended for positioning (e.g., placement formation) of the horizontally oriented access device (described below), the first electrode 761 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 756 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 763 may be formed.

[0067] exist Figure 7CIn an example embodiment, a horizontally oriented memory node having a first electrode 761 (e.g., a bottom electrode to be coupled to the source / drain region of a horizontal access device) and a second electrode 756 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) is shown as being formed in a second horizontal opening, the second horizontal opening extending to the left and right in a second direction (D2), a second distance from a vertical opening formed in the vertical stack, and along the orientation axis of the horizontal access device and the horizontal memory node of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 7C In the drawing, the adjacent relative vertical access lines 740-3 are indicated by dashed lines that show the positions set inward from the plane and orientation of the drawing.

[0068] Figure 7D Explanation along Figure 7A The cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of the present disclosure. Figure 7D The cross-sectional view shown illustrates that the axis of repeated iterations along the alternating layers of dielectric materials 730-1, 730-2, ..., 730-N, 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N extends left and right in the plane of the drawing in the second direction (D2) 705, outside the area where horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) will be formed within the layers of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N. Figure 7D In the drawing, dielectric material 741 is shown filling the space between horizontally oriented access devices that are spaced apart along a first direction (D1) of a three-dimensional array of vertically oriented memory cells, extending in and out of the plane of the drawing. However, in Figure 7D In the cross-sectional view, a second electrode 756 (e.g., the top common electrode of a capacitor cell structure) is also shown existing in the space between horizontally adjacent devices. At the left end of the drawing, a repeating iteration of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N is shown, at which point horizontally oriented digital lines (e.g., ...) are also depicted. Figure 1 The digital lines 107-1, 107-2, ..., 107-Q shown in the figure can be integrated to form an electrical contact with the second source / drain region, which is described in more detail below.

[0069] Figure 7E Explanation along Figure 7AThe cutting line D-D' in the figure shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of the present disclosure. From right to left on the plane of the drawing, Figure 7E The cross-sectional view shown illustrates that the axis of repeated iterations along alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N extends in a first direction (D1) 709, crossing multiple partitioned vertical access lines 740-1, 740-2, ..., 740-4 and intersecting with regions of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N, wherein channel regions may be formed through gate dielectric 738 to separate the multiple partitioned vertical access lines 740-1, 740-2, ..., 740-4. Figure 7E In the diagram, a first dielectric filling material 739 is shown as a space separating adjacent horizontally oriented access devices and horizontally oriented storage nodes (which may be formed to extend into and out of the plane of the drawing, as described in more detail below), and may be spaced apart along a first direction (D1) 709 and vertically stacked in an array extending along a third direction (D3) 711 in a three-dimensional (3D) memory.

[0070] Figure 8A Explanation for example Figures 1 to 3 Examples of methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, as described in the present disclosure and according to several embodiments thereof. Figure 8A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 8A In example embodiments, the method includes using photolithography to pattern photomasks 835, 836, and / or 837, such as... Figures 6A-6E As described in 7A-7E. Figure 8A The method further illustrates the use of one or more etching processes to etch the access device area (e.g., Figure 7C 742 and Figure 8C Vertical openings 871-1 and 871-2 are formed in section 842) to allow passage through the vertically stacked replacement channels and source / drain transistor regions. The vertical openings 871-1 and 871-2 are illustrated as extending primarily in the first horizontal direction (D1) 709. One or more etching processes form the vertical openings 871-1 and 871-2 to expose... Figures 8B to 8EThe third sidewall in the repeated iterations of alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) and sacrificial semiconductor material 832-1, 832-2, ..., 832-N in the vertically stacked structure is adjacent to the first region of the sacrificial semiconductor material. Other numerical components can be similarly combined. Figures 6A-6E The components shown and discussed in 7A-7E.

[0071] According to an embodiment, the access device region can be removed from repeated iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and sacrificial semiconductor materials 832-1, 832-2, ..., 832-N in a vertically stacked configuration. Figure 8A and 8C (e.g., 842) Figure 7C Transistor regions of sacrificial semiconductor material 732-1, 732-2, ..., 732-N are used to form access devices, such as transistors. In some embodiments, this process is performed before the selective removal of the sacrificial semiconductor material in memory node regions where capacitor cells are formed. In other embodiments, this process is performed after the selective removal of the sacrificial semiconductor material in memory node regions where capacitor cells are formed. Figures 8B to 8E The example embodiment shown in the diagram includes a method that selectively etches access device regions of sacrificial semiconductor materials 832-1, 832-2, ..., 832-N to form a first horizontal opening extending rearward a first horizontal distance from vertical openings 871-1 and 871-2 in a vertical stack. In some embodiments, such as Figures 8B to 8E As illustrated, the method includes forming a transistor having a first source / drain region, a channel region, and a second source / drain region as an access device in a first horizontal opening. By way of example, but not limitation, forming the first source / drain region, the channel region, and the second source / drain region includes using an atomic layer deposition (ALD) process to sequentially deposit the first source / drain region, the channel region, and the second source / drain region in the first horizontal opening. Other suitable semiconductor manufacturing techniques and / or memory node structures may be used.

[0072] Figure 8B Explanation along Figure 8A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of this disclosure. Figure 8BThe cross-sectional view shown is away from multiple separating vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1), and shows repeated iterations of alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) separated by capacitor cells on a semiconductor substrate 800 to form a vertical stack. The capacitor cells have a first electrode 861 (e.g., a bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., a top common node electrode). Figure 8B As shown in the diagram, the vertical direction 811 is similar to... Figures 1 to 3 The third direction (D3) 111 shown in the diagram is one of the first, second, and third directions, such as the z-direction in the xyz coordinate system. The drawing plane extending to the right and left lies on the first direction (D1) 809. Figure 8B In example embodiments, for instance, the first electrode 861 and the second electrode 856 coupled to the bottom electrode of the source / drain region of the horizontal access device are illustrated as being separated by a cell dielectric material 863, which extends in and out of the plane of the drawing in a second direction (D2) and along the oriented axis of the horizontal access device and the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0073] Figure 8C Explanation along Figure 8A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of this disclosure. Figure 8C The cross-sectional view shown illustrates that the axis of the repeated iterations along the alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) extends to the left and right along the plane of the drawing in the second direction (D2) 805. However, it is now shown that the sacrificial semiconductor material in the access device region 842 of the vertically stacked alternating layers has been selectively removed to form horizontal openings 833-1, 833-2, ..., 833-N, wherein horizontally oriented access devices having a first source / drain region, a channel region, and a second source / drain region can be formed between the vertically alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1). In one example embodiment, an atomic layer etching (ALE) process can be used to selectively remove the sacrificial semiconductor material in the access device region 842 to form horizontal openings 833-1, 833-2, ..., 830-(N+1). Figure 7C The sacrificial semiconductor materials used are 732-1, 732-2, ..., 732-N. However, the embodiments are not limited to this example.

[0074] exist Figure 8CIn an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is illustrated as having been formed in memory node region 844 during this semiconductor manufacturing process, and exhibiting a first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by cell dielectric 863. However, the embodiment is not limited to this example. In other embodiments, after forming the first source / drain region, channel region, and second source / drain region in the horizontal openings 833-1, 833-2, ..., 833-N, the first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by cell dielectric 863 may be formed.

[0075] exist Figure 8C In an example embodiment, the horizontal openings 833-1, 833-2, ..., 833-N forming access devices having a first source / drain region, a channel region, and a second source / drain region are shown as extending to the left and right in the second direction 805 (D2), at a distance from the vertical openings 871-1 and 871-2 formed in the vertical stack, and along the oriented axis of the horizontal access devices and horizontal memory nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 8C In the drawing, adjacent relative vertical access lines 840-3 are indicated by dashed lines pointing inward from the plane and orientation of the drawing, and the gate dielectric 838 is visible.

[0076] Figure 8D Explanation along Figure 8A The cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of the present disclosure. Figure 8D The cross-sectional view shown illustrates that the axis of the repeated iterations along the alternating layers of dielectric materials 830-1, 830-2, ..., 830-N, 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N extends to the left and right in the plane of the drawing in the second direction (D2) 805, outside the area where horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) will be formed. Figure 8D In the drawing, dielectric material 841 is shown filling the space between horizontally oriented access devices that are spaced apart along a first direction (D1) of a three-dimensional array of vertically oriented memory cells, extending in and out of the plane of the drawing. However, in Figure 8DIn the cross-sectional view, a second electrode 856 (e.g., the top common electrode of a capacitor cell structure) is also shown existing in the space between horizontally adjacent devices. At the left end of the drawing, a repeating iteration of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N is shown, at which point horizontally oriented digital lines (e.g., ...) are... Figure 1 The digital lines 107-1, 107-2, ..., 107-Q shown in the figure can be integrated to form an electrical contact with the second source / drain region of the formed horizontal access device.

[0077] Figure 8E Explanation along Figure 8A The cutting line D-D' in the figure shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of the present disclosure. From right to left on the plane of the drawing, Figure 8E The cross-sectional view shown illustrates that the axis of repeated iterations along alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N extends in a first direction (D1) 809, wherein a channel region separating multiple vertical access lines 840-1, 840-2, ..., 840-4 will be formed through the gate dielectric 838. Figure 8E In the diagram, a first dielectric filling material 839 is shown as a space separating adjacent horizontally oriented access devices and horizontally oriented storage nodes (which may be formed to extend into and out of the plane of the drawing, as described in more detail below), and may be spaced apart along a first direction (D1) 809 and vertically stacked in an array extending in a third direction (D3) 811 in a three-dimensional (3D) memory.

[0078] Figure 9A Explanation for example Figures 1 to 3 Examples of methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines at another stage of the semiconductor manufacturing process, as described in the present disclosure and according to several embodiments thereof. Figure 9A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 9A In the example embodiments, Figures 8A to 8E The vertical openings 971-1 and 971-2 still exist. However, in Figures 9A to 9F In, it has in Figure 9CThe horizontal access devices 998-1, 998-2, ..., 998-N, shown as 998-1A, 998-1B, and 998-1C respectively, with their first source / drain region, channel region, and second source / drain region, have been formed in... Figure 8C and 8D The horizontal openings 833-1, 833-2, ..., 833-N shown in the diagram. Horizontal access devices 998-1, 998-2, 998-N are formed to extend in the second direction 905 (D2) within the vertically stacked horizontal access device region 942. Additionally, horizontal digital lines 999-1, 999-2, 999-N are formed and integrated to contact the second source / drain region (e.g., 998-1C), such as... Figure 9C and 9E As shown in the diagram. Other numerical components can be combined in a similar manner. Figures 6A-6E The components shown and discussed in 7A-7E and 8A-8E.

[0079] According to an embodiment, in the access device region 942 (e.g., the transistor region), [the following has been removed] Figures 8A to 8E The sacrificial semiconductor materials 832-1, 832-2, ..., 832-N are used to retain Figures 8A-8E Alternating layers of vertically stacked dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontally openable layers 833-1, 833-2, ..., 833-N are repeatedly iterated to form an access device, such as a transistor. In some embodiments, this process is performed before the selective removal of sacrificial semiconductor material in a memory node region 944, in which capacitor cells are formed. In other embodiments, this process is performed after the selective removal of sacrificial semiconductor material in a memory node region 944, in which capacitor cells are formed. Figures 9B to 9F The example embodiment shown in the figure includes a method that involves selectively depositing a first source / drain region 938-1A, a channel region 938-1B, and a second source / drain region 938-1C onto an atomic layer deposition (ALD) process or other suitable deposition technique. Figures 8A to 8EIn each of the horizontal openings 833-1, 833-2, ..., 833-N. By way of example, but not limitation, the formation of the first source / drain region, channel region, and second source / drain region includes the process and techniques described in U.S. Patent Application No. 16 / 986,510, co-filed with at least one co-inventor, entitled “Source / Drain Integration in a Three-Node Access Device for Vertical Three-Dimensional (3D) Memory,” filed by Attorney General No. 1013.0570001, using an atomic layer deposition (ALD) process to sequentially deposit the first source / drain region, channel region, and second source / drain region in the first horizontal opening. Other suitable semiconductor manufacturing techniques and / or memory node structures may be used.

[0080] Figure 9B Explanation along Figure 9A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of this disclosure. Figure 9B The cross-sectional view shown is away from multiple separating vertical access lines 940-1, 940-2, ..., 940-N, 940-(N+1), ..., 940-(Z-1), and shows repeated iterations of alternating layers of dielectric material 930-1, 930-2, ..., 930-(N+1) separated by capacitor cells on a semiconductor substrate 900 to form a vertical stack. The capacitor cells have a first electrode 961 (e.g., a bottom cell contact electrode), a cell dielectric 963, and a second electrode 956 (e.g., a top common node electrode). Figure 9B As shown in the diagram, the vertical direction 911 is similar to... Figures 1 to 3 The third direction (D3) 111 shown in the diagram is one of the first, second, and third directions, such as the z-direction in the xyz coordinate system. The drawing plane extending to the right and left lies on the first direction (D1) 909. Figure 9B In example embodiments, for instance, the first electrode 961 and the second electrode 956 coupled to the bottom electrode of the source / drain region of the horizontal access device are illustrated as being separated by a cell dielectric material 963, which extends in and out of the plane of the drawing in a second direction (D2) and along the oriented axis of the horizontal access device and the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0081] Figure 9C Explanation along Figure 9A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of this disclosure. Figure 9C The cross-sectional view shown illustrates that the axis of repeated iterations along the alternating layers of dielectric materials 930-1, 930-2, ..., 930-(N+1) extends to the left and right along the plane of the drawing in the second direction (D2) 905. However, it is now shown that the first source / drain region material, the channel region material, and the second source / drain region materials 998-1, 998-2, ..., 998-N have been deposited on... Figures 8A to 8E The horizontal openings 833-1, 833-2, ..., 833-N extend in the second direction 905 (D2). As an example, the first source / drain region 998-1, channel region 998-1B, and 998-1C are clearly illustrated. Furthermore, horizontal digital lines 999-1, 999-2, ..., 999-N that contact the second source / drain region (e.g., 998-1C) are integrated, extending in the first direction (D1), for example, in the direction (D3) 911 in the form of alternating vertical layers of dielectric material 930-1, 930-2, ..., 930-(N+1), extending into and out of the plane of the drawing.

[0082] Therefore, three-node horizontal access devices 938-1, 938-2, ..., 938-N have been formed and integrated into vertical access lines 940-1, 940-2, ..., 940-(Z+1) and into digital lines 999-1, 999-2, ..., 999-N without body contacts. Advantages of the structure and process described herein may include lower cutoff current (Ioff) for the access devices (compared to silicon-based (Si-based) access devices). For example, the channel region of 938-1B may not contain minority carriers for the access devices, and therefore, there is no need to control the body potential of the body region of the access devices, and / or reduce gate / drain induced leakage (GIDL) for the access devices. In some embodiments, channel and / or source / drain region replacement manufacturing steps can be performed after the capacitor cell formation process, thus reducing the thermal budget. Since no body contacts to the body region of the access devices are used, digital line integration can be more easily achieved during manufacturing. Furthermore, due to the shorter channel length and lower source / drain semiconductor manufacturing process overhead, the embodiments described herein achieve better lateral scaling paths than those achieved using channel regions based on doped polysilicon.

[0083] Similarly, the processes and techniques described in U.S. Patent Application No. 16 / 986,510, co-filed with at least one co-inventor and entitled "Source / Drain Integration in a Three-Node Access Device for Vertical Three Dimensional (3D) Memory," Agent's Case No. 1013.0570001, can be used to perform the integration of the first source / drain region, channel region, and second source / drain region of horizontal access devices 998-1, 998-2, ..., 998-N, and horizontal digital lines 999-1, 999-2, ..., 999-N. According to various embodiments, another advantage is the avoidance (e.g., non-use) of gas phase doping (GPD) in the formation of the source / drain regions. Other suitable semiconductor manufacturing techniques and / or memory node structures can be used.

[0084] exist Figure 9C In an example embodiment, horizontal access devices 998-1, 998-2, ..., 989-N having a first source / drain region, a channel region, and a second source / drain region are shown as extending in a second direction 905 (D2), to the left and right in the plane of the drawing, at a distance from the vertical openings 971-1 and 971-2 formed in the vertical stack, and along the oriented axis of the horizontal access devices and horizontal memory nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 10 As shown, a dielectric material can be deposited to fill the vertical openings 971-1 and 971-3. Figure 9C In the drawing, the adjacent relative vertical access lines 940-3 are indicated by dashed lines that show the positions set inward from the plane and orientation of the drawing.

[0085] Figure 9D Explanation along Figure 9A The cut line B-B' in the diagram shows a cross-sectional view of another embodiment of a two-dimensional (2D) channel material comprising one or more transition metal dichalcogenides, including molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum distelluride (MoTe2), tungsten sulfide (WS2), and tungsten selenide (WSe2). However, the embodiments are not limited to these examples of 2D channel materials. Figure 9D Examples and embodiments illustrate the deposition on Figures 8A to 8E Examples of 2D channel materials in horizontal openings 833-1, 833-2, ..., 833-N in semiconductor manufacturing processes at this specific point in the semiconductor structure. Figure 9DThe cross-sectional view shown illustrates that the axis of repeated iterations along the alternating layers of dielectric materials 930-1, 930-2, ..., 930-(N+1) extends to the left and right along the plane of the drawing in the second direction (D2) 905. However, it is now shown that the first source / drain region material, the channel region material, and the second source / drain region materials 998-1, 998-2, ..., 998-N have been deposited using 2D material 997. Figures 8A to 8E In the horizontal openings 833-1, 833-2, ..., 833-N, it extends in the second direction 905(D2).

[0086] In one embodiment, an atomic layer deposition (ALD) process can be used to deposit 2D material 997 onto... Figures 8A to 8E The horizontal openings 833-1, 833-2, ... 833-N in the middle are covered Figures 8A to 8E The surfaces of the horizontal openings 833-1, 833-2, ..., 833-N in the middle are in contact with the bottom electrode 961. In one example embodiment, an insulating material 995 is deposited as a back channel passivation material using an atomic layer deposition (ALD) process, as more... Figures 10 to 12 As described.

[0087] Furthermore, it achieves connection with the second source / drain region (as described above). Figure 9C As described in the example embodiment, horizontal digital lines 999-1, 999-2, ..., 999-N are integrated on the surface of the deposited 2D material 997 in contact with and on the surface of the material. According to this embodiment, the 2D material 997 in contact with the digital lines 999-1, 999-2, ..., 999-N can provide more contact area for better electrical connection to the digital lines 999-1, 999-2, ..., 999-N. Similarly, the horizontal digital lines 999-1, 999-2, ..., 999-N extend in a first direction (D1), for example, in direction (D3) 911 in the form of alternating vertical layers of dielectric material 930-1, 930-2, ..., 930-(N+1) from the plane of the drawing.

[0088] As in Figure 9CIn the embodiments shown, a three-node horizontal access device is formed and integrated as vertical access lines (e.g., 940-3) and as digital lines 999-1, 999-2, ..., 999-N, without body contacts. The structures and processes described herein may include lower cutoff current (Ioff) for the access device (compared to silicon-based (Si-based) access devices). The 2D channel material 997 may be free of minority carriers for the access device, and therefore, there is no need to control the body potential of the body region of the access device. Since no body contacts are used on the body region of the access device, this reduces gate / drain induced leakage (GIDL) for the access device and makes digital line integration easier during manufacturing. According to various embodiments, another benefit is the avoidance (e.g., non-use) of vapor phase doping (GPD) in the formation of the source / drain regions. Other suitable semiconductor manufacturing techniques and / or memory node structures may be used. Figure 13 As shown in the figure, a dielectric material can be deposited to fill the vertical opening 971-1.

[0089] Figure 9E Explanation along Figure 9A The cut-off line C-C' in the diagram is shown in Figure 9C Following the example embodiments, another cross-sectional view of a semiconductor structure at a specific point in the semiconductor manufacturing process is shown. Figure 9E The cross-sectional view shown illustrates that the axis of repeated iterations along the alternating layers of dielectric materials 930-1, 930-2, ..., 930-N, 930-(N+1) and horizontal digital lines 999-1, 999-2, ..., 999-N extends left and right in the plane of the drawing in the second direction (D2) 905, and extends in and out of the plane of the drawing in the first direction (D1), outside the areas forming the horizontally oriented access devices 938-1, 938-2, ..., 938-N and horizontally oriented storage nodes (e.g., capacitor cells) in the access device area 942 and the storage node area 944. Figure 9E In the drawing, dielectric material 941 is shown filling the space between horizontally oriented access devices that are spaced apart along a first direction (D1) of a three-dimensional array of vertically oriented memory cells, extending in and out of the plane of the drawing. However, in Figure 9E In the cross-sectional view, a second electrode 956 (e.g., the top common electrode of a capacitor cell structure) is also shown existing in the space between horizontally adjacent devices. Dielectric materials 930-1, 930-2, ..., 930-(N+1) and horizontal numerical lines 999-1, 999-2, ..., 999-N (e.g., ...) are shown at the left end of the drawing. Figure 1The repeated iterations of alternating layers of digital lines 107-1, 107-2, ..., 107-Q shown in the figure are integrated to form an electrical contact with the second source / drain region (e.g., 938-1C) of the formed horizontal access device.

[0090] Figure 9F Explanation along Figure 9A The cutting line D-D' in the figure shows another cross-sectional view of the semiconductor structure at this specific point in the semiconductor manufacturing process, illustrating an embodiment of the present disclosure. From right to left on the plane of the drawing, Figure 9F The cross-sectional view shown illustrates a first direction (D1) 909 extending along the axis of repeated iterations of alternating layers of channel regions of dielectric materials 930-1, 930-2, ..., 930-(N+1) and horizontal access devices 998-1, 998-2, ..., 998-N, which are formed through gate dielectric 938 to separate multiple vertical access lines 940-1, 940-2, ..., 940-4. Figure 9F In the diagram, a first dielectric filling material 939 is shown as a space separating adjacent horizontally oriented access devices and horizontally oriented storage nodes (which may be formed to extend into and out of the plane of the drawing, as described in more detail below), and may be spaced apart along a first direction (D1) 909 and vertically stacked in an array extending in a third direction (D3) 911 in a three-dimensional (3D) memory.

[0091] Figure 10 This document describes an example method for forming a three-node access device by using an atomic layer deposition (ALD) process to form a channel region with back channel passivation, the channel region being, for example... Figure 9C and 9F The trench area 938-1B shown in the image. For example... Figure 10 As illustrated in the examples, the method may include using an atomic layer deposition (ALD) process to form a three-node access device of a memory cell with a gate dielectric 1038 (e.g., deposited on...). Figures 8A to 8E Within the horizontal openings 833-1, 833-2, ..., 833-N, extending in the second direction 905 (D2), the first layer 1098 (e.g.) contacts the first layer 1098. Figure 9C(998-1B in the original text). The method further includes using an ALD process to form (e.g., deposit) a leakage suppression layer 1071 on the first layer 1098 as an "outer layer" on a surface further away from the channel region (e.g., the first layer 1098 opposite the gate dielectric 1038). In one example embodiment, the first layer 1098 may be a two-dimensional (2D) channel material comprising one or more transition metal dichalcogenides, including molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum distelluride (MoTe2), tungsten sulfide (WS2), and tungsten selenide (WSe2). The leakage suppression layer 1071 may be an insulating material, such as... Figure 9D The example embodiments show insulating material 995. However, the embodiments are not limited to these 2D channel material examples.

[0092] In some embodiments, forming the first layer 1098 using an ALD process includes depositing an indium (In)-rich indium gallium zinc oxide (In2Ga2ZnO7) material as a channel material to form the first layer 1098. In this example, the first layer 1098 contacts the gate dielectric 1038 and forms the main transistor channel. The first layer has a higher charge carrier mobility and a lower electronic bandgap relative to the leakage suppression layer 1071.

[0093] In some embodiments, forming the leakage suppression layer 1071 using an ALD process includes depositing an indium gallium zinc oxide (In2Ga2ZnO7) material that is indium-deficient (In) relative to the first layer 1098 as the leakage suppression layer 1071. In some embodiments, forming the leakage suppression layer 1071 using an ALD process includes depositing an indium gallium zinc oxide (In2Ga2ZnO7) material that is gallium-rich (Ga) relative to the first layer 1098 as the leakage suppression layer 1071. In some embodiments, forming the leakage suppression layer 1071 using an ALD process includes depositing an indium gallium zinc oxide (In2Ga2ZnO7) material that is zinc-rich (Zn) relative to the first layer 1098 as the leakage suppression layer 1071. In some embodiments, forming the leakage suppression layer 1071 using an ALD process includes depositing only gallium oxide (Ga2O3) as the leakage suppression layer 1071. The leakage suppression layer 1071 has a lower charge carrier mobility and a higher electronic bandgap relative to the first layer 1098.

[0094] According to various embodiments, the first layer 1098 of the channel is formed using an ALD process, such that the width (W) 1079 of the first layer 1098 of the channel is greater than the thickness (t) 1077 of the first layer 1098 of the channel material. For example... Figure 10 As shown in the figure, void 1073 can still form in Figures 8A to 8EWithin the central portion of the horizontal openings 833-1, 833-2, ..., 833-N, extending in the second direction 905 (D2), generated by the ALD process.

[0095] Figure 11 This document describes another example method for forming a three-node access device by using an atomic layer deposition (ALD) process to form a channel region with back channel passivation, the channel region being, for example... Figure 9C and 9F The trench area 938-1B shown in the image. For example... Figure 11 As illustrated in the examples, methods may include using an atomic layer deposition (ALD) process to form a multilayer channel material with back channel passivation, such as... Figure 9C and 9F The channel region 938-1B shown in the image. Similarly, the method may include using an ALD process to form a three-node access device for a memory cell with a gate dielectric 1038 (e.g., deposited on...). Figures 8A to 8E The first layer 1198 (e.g., within the horizontal openings 833-1, 833-2, ..., 833-N) contacts the first layer 1198. Figure 9C (Ref. 998-1B). The method further includes using an ALD process to form (e.g., deposit) a dielectric layer 1171 as an “outer layer” on the surface furthest from the channel region (e.g., a first layer 1198 opposite the gate dielectric 1138). In some embodiments, the dielectric layer 1171 (e.g., back channel passivation) is an oxide material. For example, the dielectric layer 1171 may be a silicon dioxide (SiO2) material and / or an aluminum oxide (Al2O3) material, etc. In some embodiments, the dielectric layer 1171 may be a silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another example, the dielectric material 1171 may include silicon carbide (SiO2). x C y The material (also referred to herein as "SiOC"). In another example, the dielectric material 1171 may comprise silicon oxynitride (SiO2). x N y Materials (also referred to as "SiON" in this article) and / or combinations thereof.

[0096] like Figure 11As shown, in some embodiments, the method may include using an ALD process to form at least one intermediate layer 1172 as an interface layer between a first layer 1198 in contact with the gate dielectric 1138 of a three-node device and an Nth layer (e.g., dielectric layer 1171) spaced further away from the first layer 1198 than the intermediate layer 1172. In some embodiments, the method includes using an ALD process to deposit an interface layer 1172 having a carrier mobility and electronic bandgap between those of the first layer 1198 and the Nth layer (e.g., dielectric 1171, spaced furthest from the first layer 1198). According to embodiments, the intermediate layer suppresses the concentration of unbound valence electrons at the interface layer 1172 relative to the concentration of unbound valence electrons at the first layer 1198 and the dielectric layer 1171. In some embodiments, the method includes using an ALD process to deposit an interface layer 1172 between a first layer 1198 and a dielectric layer 1171, which reduces electron trapping and decreases variations (Δ) in threshold voltage (Vt) offset, such as ΔVt offset, during fast access operation modes and in the case of bias temperature instability (BTI) for a three-node access device.

[0097] In some embodiments, forming the first layer 1198 using an ALD process includes depositing an indium (In)-rich indium gallium zinc oxide (In2Ga2ZnO7) material as a channel material to form the first layer 1198. In this example, the first layer 1198 contacts the gate dielectric 1138 and forms the main transistor channel. The first layer has a higher charge carrier mobility and a lower electronic bandgap relative to the leakage suppression layer 1171.

[0098] In some embodiments, forming the intermediate layer 1172 using an ALD process includes depositing an indium gallium zinc oxide (In2Ga2ZnO7) material that is indium-deficient (In) relative to the first layer 1198 as the intermediate layer 1172. In some embodiments, forming the intermediate layer 1172 using an ALD process includes depositing an indium gallium zinc oxide (In2Ga2ZnO7) material that is gallium-rich (Ga) relative to the first layer 1198 as the intermediate layer 1172. In some embodiments, forming the intermediate layer 1172 using an ALD process includes depositing an indium gallium zinc oxide (In2Ga2ZnO7) material that is zinc-rich (Zn) relative to the first layer 1198 as the intermediate layer 1172. In some embodiments, forming the intermediate layer 1172 using an ALD process includes depositing gallium oxide (Ga2O3) as the intermediate layer 1172. The leakage suppression layer 1171 has a lower charge carrier mobility and a higher electronic bandgap relative to the first layer 1198.

[0099] According to various embodiments, multilayer channel materials 1198, 1172, 1171, etc., are formed using the ALD process, such that the width (W) 1179 of the multilayer channel is greater than the thickness (t) 1177 of the multilayer channel materials 1198, 1172, 1171, etc. For example... Figure 11 As shown, gaps 1074 and / or voids may still form in Figures 8A to 8E The horizontal openings 833-1, 833-2, ..., 833-N in the center are generated by the ALD process.

[0100] Figure 12 This document describes another example method for forming a three-node access device by using an atomic layer deposition (ALD) process to form a channel region with back channel passivation, the channel region being, for example... Figure 9C and 9F The trench area 938-1B shown in the image. Figure 12 In exemplary embodiments, the method may include using an atomic layer deposition (ALD) process to form a gradient channel material 1275 with a back channel passivation. Similarly, the method may include using an ALD process to deposit a gradient conductive channel material 1275 to have a three-node access device of the memory cell adjacent to the gate dielectric 1238 (e.g., deposited on...). Figures 8A to 8E The back channel passivation configuration is characterized by having the highest carrier mobility in the gradient channel material 1275 within the horizontal openings 833-1, 833-2, ..., 833-N and the lowest conductivity (e.g., lowest carrier mobility) in the gradient channel material 1275 furthest from the gate dielectric 1238. In this example, the gradient channel 1275 can be deposited using ALD to achieve an increased electronic bandgap, an increased conduction band offset, and a decreased carrier mobility in all directions away from the gate dielectric 1238.

[0101] In some embodiments, the ALD process is used to deposit an indium gallium zinc oxide (In2Ga2ZnO7) gradient channel material 1275 with a reduced indium (In) concentration (e.g., back channel passivation) in the gradient channel 1275 in the inward direction of the gate dielectric 1238 of the three-node access device away from the memory cell. In some embodiments, the ALD process is used to deposit an indium gallium zinc oxide (In2Ga2ZnO7) gradient channel material 1275 with an increased gallium (Ga) concentration (e.g., back channel passivation) in the gradient channel 1275 in the inward direction of the gate dielectric 1238 of the three-node access device away from the memory cell. In some embodiments, the ALD process is used to deposit an indium gallium zinc oxide (In2Ga2ZnO7) gradient channel material 1275 with an increased zinc (Zn) concentration (e.g., back channel passivation) in the gradient channel 1275 in the inward direction of the gate dielectric 1238 of the three-node access device away from the memory cell.

[0102] According to various embodiments, an ALD process is used to form a gradient channel material 1275 such that the width (W) 1279 of the gradient channel 1275 is greater than the thickness (t) 1277 of the gradient channel 1275. In some embodiments, the ALD process may also be used to form (e.g., deposit) a dielectric layer (not shown) as an “outer layer”, which is furthest from the surface of the gradient channel region 1275 opposite to the gate dielectric 1238. This dielectric layer may also be an oxide material, such as silicon dioxide (SiO2) and / or aluminum oxide (Al2O3). Alternatively, this dielectric layer may include silicon nitride (Si3N4) (also referred to herein as “SiN”), silicon carbide (SiO2), etc. x C y Materials (also referred to as "SiOC" in this article), silicon oxynitride (SiO) x N y Materials (also referred to as "SiON" in this article) and / or combinations thereof.

[0103] like Figure 12 As shown, the gaps 1274 and / or voids may still exist in the central region of the gradient channel material 1275, furthest from the gate dielectric 1238, using the ALD process. The methods described herein may include using the ALD process to... Figure 9C The first source / drain material 998-1A, the alternative channel material 1275 with back channel passivation, and Figure 9C The second source / drain material 998-1C is sequentially deposited on the substrate. Figures 8A to 8E The horizontal openings 833-1, 833-2, ..., 833-N are described herein. The method described herein may further include integration. Figure 9C The horizontal directional digital line 999 and Figure 13The 1399 in the middle forms an electrical contact with the second source / drain material 998-1C, and integrates, for example, word lines 1240-2 and 1240-3, vertically oriented access lines (opposite to the gradient channel material 1275 with back channel passivation and separated from the gradient channel material 1275 by the gate dielectric 1238) to form a three-node access device for memory cells without body contact.

[0104] Figure 13 This describes a horizontally oriented three-node access device 1342, according to an embodiment of the present disclosure, coupled to a horizontally oriented storage node 1344 of a vertical three-dimensional (3D) memory. Figure 13 In the diagram, the horizontally oriented three-node access device 1342 is described as extending to the left and right in a second direction (D2) 1305 in the plane of the drawing. The horizontally oriented access device 1342 is described as having a first source / drain region 1398-1A that is electrically in contact with a first electrode 1361 (e.g., bottom electrode) of a horizontally oriented storage node 1344 (e.g., a capacitor cell). The storage node 1344 is further described as having a dielectric material 1363 that separates the first electrode 1361 from a second electrode 1356 (e.g., the top common node electrode of a capacitor cell).

[0105] Channel region 1398-1B is shown as being in electrical contact with the first source / drain region 1398-1A. Vertically oriented access line 1340-3 is opposite to channel region 1398-1B and separated from it by a gate dielectric. Vertically oriented access line 1340-2 is illustrated by a dashed line indicating its entry and / or exit from the plane of the drawing. Vertically oriented access line 1340 may be formed having a length (L) 1378, which, according to specific design rules, extends longer than and / or shorter than the length of the channel region in the second direction (D2) 1305 (e.g., with source / drain overlap and / or under-overlap).

[0106] The second source / drain region 1398-1C is described as being in electrical contact with the channel region 1398-1B, and also in electrical contact with and integrated into the horizontally oriented digital line 1399 extending from the plane of the drawing. For example... Figure 13 As shown, the horizontally oriented digital line 1399 is in direct electrical contact with the second source / drain region 1398-1C on the "same plane," for example, flush with the second source / drain region 1398-1C extending in the second direction (D2) 1305, and not in electrical contact on the top or bottom surface of the second source / drain region 1398-1C, above or below the second source / drain region 1398-1C. This is advantageous for easier digital line integration in the semiconductor manufacturing process. Figure 13As shown, the horizontally oriented access device 1342 and the horizontally oriented storage node 1344 are horizontally spaced from adjacent memory cells along the second direction (D2) 1305 via interlayer dielectric material 1380, and are vertically spaced from stacked adjacent cells in the three-dimensional (3D) memory via dielectric layers 1330-1 and 1330-2.

[0107] Figure 14 This is a block diagram of a device in the form of a computing system 1400 including a memory device 1403, according to several embodiments of the present disclosure. As used herein, for example, the memory device 1403, memory array 1410, and / or host 1402 may also be considered as a "device". According to an embodiment, the memory device 1402 may include at least one memory array 1410 having a three-node access means of vertical three-dimensional (3D) memory, as described herein.

[0108] In this example, system 1400 includes a host 1402 coupled to memory device 1403 via interface 1404. The computing system 1400 may be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. Host 1402 may include several processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory 1403. System 1400 may include separate integrated circuits, or host 1402 and memory device 1403 may both be on the same integrated circuit. For example, host 1402 may be a system controller for a memory system including multiple memory devices 1403, wherein the system controller 1405 provides access to the respective memory devices 1403 by another processing resource, such as a central processing unit (CPU).

[0109] exist Figure 14 In the example shown, host 1402 is responsible for executing an operating system (OS) and / or various applications (e.g., processes), which may be loaded onto host 1402 (e.g., from memory device 1403 via controller 1405). The OS and / or various applications can be loaded from memory device 1403 by providing access commands from host 1402 to memory device 1403 for accessing data including the OS and / or various applications. Host 1402 can also access data used by the OS and / or various applications by providing access commands to memory device 1403 for retrieving data used in the execution of the OS and / or various applications.

[0110] For clarity, system 1400 has been simplified to focus on features particularly relevant to this disclosure. Memory array 1410 may be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and / or NOR flash array, comprising at least one three-node access device of three-dimensional (3D) memory. For example, memory array 1410 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1410 may include memory cells arranged in rows coupled via word lines (which may be referred to herein as access lines or select lines) and columns coupled via digital lines (which may be referred to herein as sense lines or data lines). Although in Figure 14 The illustration shows a single array 1410, but the embodiments are not limited thereto. For example, the memory device 1403 may include several arrays 1410 (e.g., arrays of DRAM cells).

[0111] Memory device 1403 includes address circuitry 1406 to latch address signals provided via interface 1404. The interface may include a physical interface employing, for example, a suitable protocol (e.g., a data bus, address bus, and command bus, or a combination of data / address / command buses). Such protocols may be custom or proprietary, or interface 1404 may utilize standardized protocols such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z, CCIX, etc. Row decoder 1408 and column decoder 1412 receive and decode address signals to access memory array 1410. Data can be read from memory array 1410 by sensing voltage and / or current changes on a sensing line using sensing circuitry 1411. Sensing circuitry 1411 may include, for example, a sensing amplifier that can read and latch pages (e.g., rows) of data from memory array 1410. I / O circuitry 1407 can be used for bidirectional data communication with host 1402 via interface 1404. The read / write circuit 1413 is used to write data to or read data from the memory array 1410. As an example, the circuit 1413 may include various drivers, latch circuits, etc.

[0112] Control circuitry 1405 decodes signals provided by host 1402. These signals may be commands provided by host 1402. These signals may include chip enable signals, write enable signals, and address latch signals, which control operations performed on memory array 1410, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry 1405 is responsible for executing instructions from host 1402. Control circuitry 1405 may include a state machine, sequencer, and / or some other type of control circuitry, which may be implemented in hardware, firmware, or software, or any combination thereof. In some instances, host 1402 may be a controller external to memory device 1403. For example, host 1402 may be a memory controller coupled to the processing resources of a computing device.

[0113] For example, the term semiconductor can refer to a material, wafer, or substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referenced to semiconductor in the foregoing description, prior processing steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term semiconductor may include a base material containing these regions / junctions.

[0114] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number, and the remaining numbers identify elements or components in the figures. Similar (e.g., identical) elements or components between different figures can be identified by using similar numbers. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0115] As used herein, “several” or “a certain number” of something can refer to one or more of such things. For example, “several” or “a certain number” of memory cells can refer to one or more memory cells. “A certain number” of something means two or more. As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period. As used herein, the term “coupling” can include electrical coupling, direct coupling and / or direct connection (e.g., through direct physical contact) without intermediate elements, or indirect coupling and / or connection with intermediate elements, or wireless coupling. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., causally related). An element coupled between two elements can be between and coupled to each of the two elements.

[0116] It should be recognized that the term "vertical" refers to variations in verticality due to routine manufacturing, measurement, and / or assembly variations, and the meaning of the term "vertical" will be understood by those skilled in the art. For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, be above or laterally to the other element, and / or be in direct physical contact with the other element. For example, laterally to may refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0117] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A method for forming an array (101) of vertically stacked memory cells, the array (101) having horizontally oriented access devices (230, 330, 998, 1342) and vertically oriented access lines (103, 203, 303, 540, 640, 740, 840, 940, 1240, 1340), the method comprising: depositing, in repeated iterations, alternating layers of a dielectric material (430, 530, 630, 730, 830, 930) and a sacrificial material (432, 532, 632, 732) to form a vertical stack (401); forming a first vertical opening (500) using a first etch process that exposes a vertical sidewall of the vertical stack (401) adjacent to a first portion of the sacrificial material (432, 532, 632, 732); selectively etching the first portion of the sacrificial material (432, 532, 632, 732) to form a first horizontal opening (833) that removes the sacrificial material (432, 532, 632, 732) in a first region (742, 842, 942) and that is back a first horizontal distance from the first vertical opening (500); and depositing, in the first horizontal opening (833), a first source / drain material (998-1A), a replacement channel material (1275) having back channel passivation, and a second source / drain material (998-1C) to form a three-node access device (230, 330, 998, 1342) of a memory cell (110) among the array (101) of vertically stacked memory cells.

2. The method of claim 1, wherein depositing the replacement channel material (1275) comprises: depositing an indium-rich indium gallium zinc oxide (IGZO) channel material to form a first layer (1098, 1198); and depositing the indium gallium zinc oxide (IGZO) channel material as an indium-poor layer (1071, 1171) relative to the first layer (1098, 1198).

3. The method of claim 2, further comprising depositing the replacement channel material (1275) having a back channel passivation layer having a lower charge mobility than the first layer (1098, 1198) of contact gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238).

4. The method of claim 2, further comprising depositing the replacement channel material (1275) having a back channel passivation material having a higher electron bandgap than the first layer (1098, 1198) of contact gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238). ​ 5. A method for forming an array (101) of vertically stacked memory cells, the array (101) having horizontally oriented access devices (230, 330, 998, 1342) and vertically oriented access lines (103, 203, 303, 540, 640, 740, 840, 940, 1240), the method comprising: depositing, in repeated iterations, alternating layers of a dielectric material (430, 530, 630, 730, 830, 930) and a sacrificial material (432, 532, 632, 732) to form a vertical stack (401); forming a plurality of first vertical openings (500) having a first horizontal direction (109, 209, 509, 609, 709, 809, 909) and a second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1305) through the vertical stack (401) and extending predominantly in the second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1305) to form, in the vertical stack (401), elongated columns of vertical pillars (513, 542) having sidewalls (514); depositing a first conductive material conformally on a gate dielectric material (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) in the first vertical openings (500); removing portions of the first conductive material to form a plurality of separate vertical access lines (103, 203, 303, 540, 640, 740, 840, 940, 1240, 1340) along the sidewalls (514) of the elongated columns of vertical pillars (513, 542); forming second vertical openings (871-1, 871-2) that expose vertical sidewalls of the vertical stack (401) adjacent to a first portion of the sacrificial material (432, 532, 632, 732); selectively removing the first portion of the sacrificial material (432, 532, 632, 732) to form a first horizontal opening (833) in a first region (742, 842, 942) a first horizontal distance back from the second vertical openings (871-1, 871-2); and depositing a first source / drain material (998-1A), a multi-layer channel material (1275) having back channel passivation, and a second source / drain material (998-1C) in the first horizontal opening (833) to form a three-node access device (230, 330, 998, 1342) of a memory cell (110) among the array (101) of vertically stacked memory cells.

6. The method of claim 5, further comprising depositing the multi-layer channel material (1275) with a first semiconductor material as a first layer (1098, 1198) in contact with a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) of the tri-node access device (230, 330, 998, 1342) of the memory cell (110) using an atomic layer deposition (ALD) process, and depositing a second semiconductor material as a second layer (1071, 1171) further away from the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) having an electronic bandgap higher than the first layer (1098, 1198) to act as the back channel passivation.

7. The method of claim 6, further comprising depositing the multi-layer channel material (1275) to have at least one intermediate layer (1172) as an interface layer (1172) between the first layer (1098, 1198) in contact with the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) of the tri-node access device (230, 330, 998, 1342) and an Nth layer spaced further away from the first layer (1098, 1198).

8. The method of claim 6, further comprising depositing the multi-layer channel material (1275) to have an interface semiconductor material having a charge carrier mobility and an electronic bandgap between a charge carrier mobility and an electronic bandgap of the first layer (1098, 1198) in contact with the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) and an Nth layer spaced further away from the first layer (1098, 1198).

9. The method of any one of claims 5-6, further comprising depositing the multi-layer channel material (1275) to have an interface layer (1172) between a first semiconductor layer (1098, 1198) and a second semiconductor layer (1071, 1171) to suppress a concentration of unbound valence electrons at the interface layer (1172) relative to a concentration of unbound valence electrons at the first semiconductor layer (1098, 1198) and the second semiconductor layer (1071, 1171).

10. The method of any one of claims 5-6, further comprising depositing the multi-layer channel material (1275) to have an interface layer (1172) between a first semiconductor layer (1098, 1198) and a second dielectric layer (1071, 1171) to reduce electron trapping and reduce threshold voltage Vt shifts of the tri-node access device (230, 330, 998, 1342).

11. A method for forming an array (101) of vertically stacked memory cells, the array (101) having horizontally oriented access devices (230, 330, 998, 1342) and vertically oriented access lines (103, 203, 303, 540, 640, 740, 840, 940, 1240, 1340), the method comprising: depositing, in repeated iterations, alternating layers of a dielectric material (430, 530, 630, 730, 830, 930) and a sacrificial material (432, 532, 632, 732) to form a vertical stack (401); forming a plurality of first vertical openings (500) having a first horizontal direction (109, 209, 509, 609, 709, 809, 909) and a second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1305) through the vertical stack (401) and extending predominantly in the second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1305) to form, in the vertical stack (401), elongated columns of vertical pillars (513, 542) having sidewalls; depositing a first conductive material conformally on a gate dielectric material (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) in the first vertical openings (500); removing portions of the first conductive material to form a plurality of separate vertical access lines (103, 203, 303, 540, 640, 740, 840, 940, 1240, 1340) along the sidewalls (514) of the elongated columns of vertical pillars (513, 542); forming a second vertical opening (871) that exposes a vertical sidewall in the vertical stack (401) adjacent to a first portion of the sacrificial material (432, 532, 632, 732); selectively removing the first portion of the sacrificial material (432, 532, 632, 732) to form a first horizontal opening (833) in a first region (742, 842, 942) a first horizontal distance back from the second vertical opening (871); and depositing a first source / drain material (998-1A), a gradient channel material (1275) having back channel passivation, and a second source / drain material (998-1C) in the first horizontal opening (833) to form a three-node access device (230, 330, 998, 1342) of a memory cell (110) among the array (101) of vertically stacked memory cells.

12. The method of claim 11, depositing the graded channel material (1275) using an atomic layer deposition (ALD) process to have a highest charge carrier mobility in the graded channel (1275) proximate to a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) of the three-node access device (230, 330, 998, 1342) and a lowest charge carrier mobility in the graded channel (1275) farthest from the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238).

13. The method of claim 11, further comprising depositing a graded semiconductor channel material (1275) having at least one of an increasing electron bandgap, an increasing conduction band offset, and a decreasing charge carrier mobility in a direction away from a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) of the three-node access device (230, 330, 998, 1342).

14. The method of claim 11, further comprising depositing an indium gallium zinc oxide (IGZO) graded channel material (1275) having a decreasing indium (In) concentration in the graded channel material (1275) in a direction away from a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) of the three-node access device (230, 330, 998, 1342).

15. The method of claim 11, further comprising depositing an indium gallium zinc oxide (IGZO) graded channel material (1275) having an increasing gallium (Ga) concentration in the graded channel material (1275) in a direction away from a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) of the three-node access device (230, 330, 998, 1342).

16. The method of claim 11, further comprising depositing an indium gallium zinc oxide (IGZO) graded channel material (1275) having an increasing zinc (Zn) concentration in the graded channel material (1275) in a direction away from a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) of the three-node access device (230, 330, 998, 1342).

17. The method of claim 11, further comprising: selectively etching a second portion of the sacrificial material (432, 532, 632, 732) in a second region of the vertical stack (401) to form a storage node (227, 327, 1344) of the memory cell (110) prior to depositing the first source / drain material (998-1A), the graded channel material (1275), and the second source / drain material (998-1C).

18. The method of claim 11, further comprising integrating horizontally oriented digit lines (107, 207, 307, 999, 1399) to form electrical contact on the same plane as the second source / drain material (998-1C).

19. A memory device comprising: a vertical stack memory cell array (101) comprising: a horizontally oriented three-node access device (230, 330, 998, 1342) having a first source / drain region (221, 321, 998-1A, 1398-1A) and a second source / drain region (223, 323, 998-1C, 1398-1C) separated by a replacement channel region (998-1B, 1398-1B) having back channel passivation, and a gate opposite the replacement channel region (998-1B, 1398-1B) and separated from the replacement channel region (998-1B, 1398-1B) by a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238), wherein the three-node access device (230, 330, 998, 1342) does not have a direct electrical body contact to a bulk region of the three-node access device (230, 330, 998, 1342) or the replacement channel region (998-1B, 1398-1B); a vertically oriented access line (103, 203, 303, 540, 640, 740, 840, 940, 1240, 1340), coupled to the gate and separated from the replacement channel region (998-1B, 1398-1C) by the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238); a horizontally oriented storage node (227, 327, 1344) electrically coupled to the first source / drain region (221, 321, 998-1A, 1398-1A) of the three-node access device (230, 330, 998, 1342); and a horizontally oriented digit line (107, 207, 307, 999, 1399) electrically coupled to the second source / drain region (223, 323, 998-1C, 1398-1C) of the three-node access device (230, 330, 998, 1342).

20. The memory device of claim 19, wherein: The replacement channel region (998-1B, 1398-1B) includes a two-dimensional, 2D, channel material (997) including one or more of transition metal dichalcogenides; and The 2D channel material (997) further extends and covers a surface of the horizontally oriented digit line (107, 207, 307, 999, 1399) electrically coupled to the second source / drain region (223, 323, 998-1C, 1398-1C) to provide more contact surface area.

21. The memory device of claim 19, wherein the replacement channel region (998-1B, 1398-1C) includes an indium gallium zinc oxide, IGZO, channel material (1275) having an increased zinc, Zn, concentration in a direction away from the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238) of the three-node access device (230, 330, 998, 1342).

22. The memory device of any one of claims 19-20, wherein the horizontally oriented memory node (227, 327, 1344) is in direct electrical contact with the first source / drain region (221, 321, 998-1A, 1398-1A) of the three-node access device (230, 330, 998, 1342) on a same plane as the first source / drain region (221, 321, 998-1A, 1398-1A).

23. The memory device of any one of claims 19-20, wherein the horizontally oriented digit line (107, 207, 307, 999, 1399) is in direct electrical contact with the second source / drain region (223, 323, 998-1C, 1398-1C) of the three-node access device (230, 330, 998, 1342) on a same plane as the second source / drain region (223, 323, 998-1C, 1398-1C).

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