Semiconductor package

Abstract

A semiconductor package includes a redistribution substrate including a first redistribution pattern and a second redistribution pattern at different horizontal levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first redistribution pattern and the second redistribution pattern. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and sidewalls of the second metal pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0096147, filed on July 31, 2020, and Korean Patent Application No. 10-2021-0007625, filed on January 19, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to semiconductor packages, and more specifically, to semiconductor packages comprising a redistributed substrate having high integration and increased reliability. Background Technology

[0004] A semiconductor package is provided to implement an integrated circuit chip in accordance with standards for use in electronic products. Typically, the semiconductor package is configured such that the semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the PCB. With the development of the electronics industry, various studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide semiconductor packages with high integration and increased reliability.

[0006] The purpose of this invention is not limited to the foregoing, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to some exemplary embodiments of the present invention, a semiconductor package may include: a redistribution substrate including a first redistribution pattern and a second redistribution pattern, the bottom surfaces of the first redistribution pattern and the second redistribution pattern being at different distances from the bottom surface of the redistribution substrate in a vertical direction perpendicular to the bottom surface of the redistribution substrate; and a semiconductor chip located on the redistribution substrate and including a plurality of chip pads electrically connected to the first redistribution pattern and the second redistribution pattern. The first redistribution pattern may include: a first metal pattern located on a first dielectric layer; and a first barrier pattern located between the first dielectric layer and the bottom surface of the first metal pattern. The second redistribution pattern may include: a second metal pattern located in a second dielectric layer; and a second barrier pattern located between the second dielectric layer and the bottom surface of the second metal pattern and between the second dielectric layer and the sidewalls of the second metal pattern.

[0008] According to some exemplary embodiments of the present invention, a semiconductor package may include: a redistribution substrate including a plurality of first redistribution layers and a plurality of second redistribution layers, the plurality of first redistribution layers and the plurality of second redistribution layers being stacked vertically and alternately in a vertical direction perpendicular to the bottom surface of the redistribution substrate; and a semiconductor chip located on the redistribution substrate. Each of the plurality of first redistribution layers may include: a first dielectric layer, and a first redistribution pattern including a first via portion and a first pad portion connected to the first via portion. The first via portion may penetrate the first dielectric layer. The first pad portion may be located on the top surface of the first dielectric layer. Each of the plurality of second redistribution layers may include: a second dielectric layer located on a lower first dielectric layer below the lower first redistribution layer, and a second redistribution pattern including a second via portion and a second pad portion connected to the second via portion. The second via portion may penetrate a portion of the second dielectric layer. The second pad portion may be located within the second dielectric layer.

[0009] According to some exemplary embodiments conceived in this invention, a semiconductor package may include: a lower redistribution substrate, the lower redistribution substrate including a first redistribution pattern on a first dielectric layer and a second redistribution pattern in a second dielectric layer on the first dielectric layer; a first semiconductor chip, the first semiconductor chip being located on the lower redistribution substrate and including a plurality of chip pads; a plurality of first connection terminals, the plurality of first connection terminals being located between the lower redistribution substrate and the plurality of chip pads of the first semiconductor chip; a molding layer, the molding layer being located on the lower redistribution substrate and covering the first semiconductor chip; and a plurality of metal pillars, the plurality of metal pillars surrounding the first semiconductor chip and connected to the lower redistribution substrate, and penetrating the molding layer. The second dielectric layer may cover the sidewalls of the first redistribution pattern. The top surface of the second dielectric layer may be coplanar with the top surface of the second redistribution pattern.

[0010] Details of other example embodiments are included in the specification and drawings. Attached Figure Description

[0011] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 The illustration shows a cross-sectional view of a method for manufacturing a redistributed substrate of a semiconductor package according to some exemplary embodiments of the invention.

[0012] Figure 15 The illustration shows a cross-sectional view of a semiconductor package that partially illustrates some exemplary embodiments of the concept according to the present invention.

[0013] Figure 16A and Figure 16B The illustration shows a plan view of an example of a first redistribution layer and a second redistribution layer in a redistribution substrate, illustrating some exemplary embodiments of the invention.

[0014] Figure 17 The illustration shows a cross-sectional view of a semiconductor package illustrating some exemplary embodiments of the invention.

[0015] Figure 18A The illustration shows Figure 17 A magnified view of part P1.

[0016] Figure 18B The illustration shows Figure 18A A magnified view of part P2.

[0017] Figure 19 , Figure 20 and Figure 21 The diagram shows Figure 17 The image depicts an enlarged cross-sectional view of portion P1, which illustrates a semiconductor package according to some exemplary embodiments of the concept of the present invention.

[0018] Figure 22 The illustration shows a cross-sectional view of a semiconductor package illustrating some example embodiments of the concept according to the present invention.

[0019] Figure 23 The illustration shows Figure 22 A magnified view of part P3.

[0020] Figure 24 , Figure 25 , Figure 26 and Figure 27 The illustration shows a cross-sectional view of a semiconductor package illustrating some example embodiments of the concept according to the present invention.

[0021] Figure 28 The illustration shows a simplified plan view of a semiconductor package illustrating some example embodiments of the concept according to the present invention.

[0022] Figure 29 The diagram illustrates along Figure 28The cross-sectional view taken along line A-A' shows a semiconductor package according to some exemplary embodiments of the concept of the present invention. Detailed Implementation

[0023] The following describes, with reference to the accompanying drawings, some exemplary embodiments of semiconductor packages and methods for manufacturing thereof according to the present invention.

[0024] As described herein, an element “located” on another element may be above, below, or adjacent to (e.g., horizontally adjacent) the other element. An element located on another element may be directly on the other element, such that the element is in direct contact with the other element. An element located on another element may be indirectly on the other element, such that the element is isolated from the other element by one or more intervening spaces and / or structures without direct contact.

[0025] It should be understood that elements and / or characteristics (e.g., structure, surface, orientation, etc.) that can be described as "perpendicular", "parallel", "coplanar" or other relative to other elements and / or their characteristics (e.g., structure, surface, orientation, etc.) can be "perpendicular", "parallel", "coplanar", etc., or relative to other elements and / or their characteristics can be "substantially perpendicular", "substantially parallel", "substantially coplanar", etc., respectively.

[0026] A component and / or its characteristics (e.g., structure, surface, orientation, etc.) that are “substantially perpendicular” to other components and / or their characteristics will be understood as being “perpendicular” to other components and / or their characteristics within manufacturing and / or material tolerances, and / or having a magnitude and / or angular deviation of 10% or less (e.g., a tolerance of ±10%) relative to other components and / or their characteristics.

[0027] A component and / or its characteristics that are “substantially parallel” to other components and / or their characteristics (e.g., structure, surface, orientation, etc.) will be understood as being “parallel” to other components and / or their characteristics within manufacturing and / or material tolerances, and / or having a magnitude and / or angular deviation of 10% or less (e.g., tolerance of ±10%) relative to other components and / or their characteristics.

[0028] Elements and / or characteristics that are “fundamentally coplanar” with respect to other elements and / or their characteristics (e.g., structure, surface, orientation, etc.) will be understood as being “coplanar” with respect to other elements and / or their characteristics within manufacturing tolerances and / or material tolerances, and / or having magnitude and / or angular deviations from other elements and / or their characteristics being “coplanar” with respect to other elements and / or their characteristics equal to or less than 10% (e.g., tolerance of ±10%).

[0029] It should be understood that the components and / or their characteristics described herein may be "identical" or "equivalent" to other components. It should also be understood that "identical," "equivalent," or "substantially" to other components may mean "substantially," "substantially," or "substantially" to other components and / or their characteristics, or "substantially," "substantially," or "substantially" to other components and / or their characteristics. Components and / or their characteristics that are "substantially," "substantially," or "substantially" identical to other components and / or their characteristics will be understood to include components and / or their characteristics that are identical, identical, or equivalent to other components and / or their characteristics within manufacturing tolerances and / or material tolerances. Components and / or their characteristics that are identical or substantially identical and / or identical or substantially the same as other components and / or their characteristics may be identical or substantially identical in structure, function, and / or composition.

[0030] It should be understood that the description herein of elements and / or characteristics as "substantially" identical and / or the same includes elements and / or characteristics whose relative size difference is equal to or less than 10%. Furthermore, regardless of whether the elements and / or characteristics are modified to be "substantially", it should be understood that these elements and / or characteristics should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) surrounding said elements and / or characteristics.

[0031] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes a tolerance of ±10% around the stated value. When a range is specified, the range includes all values ​​within that range, such as an increment of 0.1%.

[0032] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 The illustration shows a cross-sectional view of a method for manufacturing a redistributed substrate of a semiconductor package according to some exemplary embodiments of the invention.

[0033] Reference Figure 1 The adhesive layer ADL can be formed on the carrier substrate W1. The carrier substrate W1 can be a glass substrate or a semiconductor substrate. The adhesive layer ADL can be, for example, a polymer tape including a dielectric material.

[0034] A first dielectric layer 10 may be formed on the adhesive layer AD1, covering the conductive pads CP. The conductive pads CP can be formed by performing a deposition process, a patterning process, an electroplating process, or a chemical plating process. In some example embodiments, the conductive pads CP may be formed in trenches formed in the dielectric layer. The conductive pads CP may be formed of a metal or an alloy thereof, each metal or alloy thereof including at least one selected from copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C).

[0035] The first dielectric layer 10 can be formed by a coating process, such as spin coating or slot coating. The first dielectric layer 10 can be formed of a photoimageable dielectric. The first dielectric layer 10 can include, for example, a photosensitive polymer. The photosensitive polymer can include one or more of, for example, photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer. In some example embodiments, the first dielectric layer 10 can be formed of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0036] Subsequently, a first via VH1 can be formed in the first dielectric layer 10, which exposes the conductive pad CP.

[0037] When the first dielectric layer 10 comprises a photosensitive polymer, the first via VH1 can be formed by performing an exposure and development process on a portion of the first dielectric layer 10. After forming the first via VH1, a curing process can be performed on the first dielectric layer 10.

[0038] refer to Figure 2 The first barrier layer 11 can be formed on the first dielectric layer 10 in which the first via VH1 is formed.

[0039] The first barrier layer 11 can be deposited to have the same thickness as the first dielectric layer 10 in which the first via VH1 is formed. For example, the first barrier layer 11 can conformally cover the inner wall of the first via VH1 and the top surface of the first dielectric layer 10. The first barrier layer 11 can be in contact with the portion of the conductive pad CP exposed in the first via VH1. The first barrier layer 11 can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0040] The formation of the first barrier layer 11 may include sequentially depositing a barrier metal layer and a metal seed layer. The barrier metal layer may include, for example, a bilayer or a hybrid layer other than a bilayer, which may include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or titanium / titanium nitride. The metal seed layer may include, for example, copper (Cu).

[0041] After the first barrier layer 11 is formed, a first photoresist pattern PR1 with openings can be formed on the first barrier layer 11. The first photoresist pattern PR1 can be formed by forming a photoresist layer on the first barrier layer 11 and then performing an exposure and development process.

[0042] Some openings of the first photoresist pattern PR1 may overlap with the first via VH1. The first photoresist pattern PR1 may include a line-and-space pattern. The first photoresist pattern PR1 may have a linewidth of about 5.0 μm to about 10.0 μm.

[0043] Subsequently, a first metal pattern 14 can be formed in the opening and the first through-hole VH1 in which the first barrier layer 11 is formed.

[0044] The first metal pattern 14 can completely fill the opening and the first via VH1 in which the first barrier layer 11 is formed. The first metal pattern 14 can be formed on the top surface of the first barrier layer 11 exposed to the opening of the first photoresist pattern PR1. The first metal pattern 14 can be formed by performing an electroplating process, such as electroplating or pulse electroplating. The first metal pattern 14 can be grown from the surface of the metal seed layer. The first metal pattern 14 can include the same metal as the metal seed layer, such as copper (Cu).

[0045] Reference Figure 3 The first photoresist pattern PR1 can be removed, and then the first barrier layer 11 beneath the first photoresist pattern PR1 can be etched to expose the top surface of the first dielectric layer 10. The first photoresist pattern PR1 can be removed by performing an ashing process or a stripping process, and the first barrier layer 11 can be etched by performing a wet etching process. Therefore, a first redistribution pattern RDL1 can be formed, and each first redistribution pattern RDL1 can include a first barrier pattern 12 and a first metal pattern 14. The first metal pattern 14 can have sidewalls defined by the sidewalls of the first photoresist pattern PR1, and these sidewalls of the first metal pattern 14 can be linear sidewalls perpendicular to the top surface of the first dielectric layer 10. During the wet etching process performed on the first barrier layer 11, the sidewalls of the first barrier pattern 12 can be more recessed than the sidewalls of the first metal pattern 14.

[0046] The first redistribution pattern RDL1 may include a first pass portion RDL1a that penetrates the first dielectric layer 10, a first pad portion RDL1b located on the first dielectric layer 10 and connected to the first pass portion RDL1a, and a first line portion RDL1c that extends from the first pad portion RDL1b in one direction and is disposed on the first dielectric layer 10.

[0047] Reference Figure 4 The second dielectric layer 20 can be formed on the first dielectric layer 10, covering the first redistribution pattern RDL1. The second dielectric layer 20 can be thicker than the first dielectric layer 10.

[0048] The second dielectric layer 20 can be formed by a coating process, such as spin coating or slot coating. The second dielectric layer 20 can be formed of a photoimageable dielectric. The second dielectric layer 20 may include, for example, a photosensitive polymer. The photosensitive polymer may include one or more of, for example, photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. The second dielectric layer 20 may include the same or different polymeric material as the first dielectric layer 10. In some example embodiments, the second dielectric layer 20 may be formed of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0049] Subsequently, a preliminary via PVH can be formed in the second dielectric layer 20. The preliminary via PVH can expose a portion of the first redistribution pattern RDL1. The preliminary via PVH can be formed by performing an exposure and development process on the second dielectric layer 20. Afterward, a curing process can be performed on the second dielectric layer 20.

[0050] refer to Figure 5 A hard mask layer HML can be formed on the second dielectric layer 20, in which a preliminary via PVH is formed. The hard mask layer HML can conformally cover the inner wall of the preliminary via PVH and the top surface of the second dielectric layer 20. The hard mask layer HML can cover the first redistribution pattern RDL1 exposed on the top surface of the preliminary via PVH.

[0051] The hard mask layer HML can be formed of a material that has etch selectivity relative to the second dielectric layer 20. The hard mask layer HML can include metallic materials such as titanium, titanium nitride, tantalum, tantalum nitride, or tungsten. In some example embodiments, the hard mask layer HML can be a polysilicon layer, a silicon nitride layer, or a silicon oxynitride layer. The hard mask layer HML can be formed using PVD, CVD, or ALD.

[0052] refer to Figure 6 The second photoresist pattern PR2 can be formed on the hard mask layer HML. The second photoresist pattern PR2 can be formed by forming a photoresist layer on the hard mask layer HML, followed by exposure and development processes.

[0053] The second photoresist pattern PR2 may include openings that expose portions of the hard mask layer HML. Some openings of the second photoresist pattern PR2 may overlap with the initial via PVH. The second photoresist pattern PR2 may include a line space pattern. The second photoresist pattern PR2 may have a linewidth of approximately 0.5 μm to approximately 2.5 μm.

[0054] refer to Figure 7 The second photoresist pattern PR2 can be used as an etching mask to perform anisotropic etching processes on the hard mask layer HML. Therefore, a hard mask pattern HMP can be formed on the second dielectric layer 20. Anisotropic etching processes performed on the hard mask layer HML can include reactive ion etching (RIE), magnetically enhanced reactive ion etching (MERIE), inductively coupled plasma (ICP) etching, transformer-coupled plasma (TCP) etching, hollow anode plasma etching, or spiral resonator plasma etching.

[0055] C x F y Etching gases can be used in anisotropic etching processes performed on hard mask layers (HMLs). For example, etching gases may include CF4, C3F6, C4F6, C4F8, C5F8, CH3F, CHF3, CH2F2, or any combination thereof. Furthermore, inert gases, such as argon (Ar), can be used in anisotropic etching processes performed on hard mask layers (HMLs).

[0056] The second dielectric layer 20 can be partially over-etched during an anisotropic etching process performed on the hard mask layer HML. Therefore, preliminary trenches (not shown) can be formed on the second dielectric layer 20.

[0057] Subsequently, the hard mask pattern HMP can be used as an etching mask to perform anisotropic etching processes on the second dielectric layer 20. The anisotropic etching processes performed on the second dielectric layer 20 may include reactive ion etching (RIE), magnetically enhanced reactive ion etching (MERIE), inductively coupled plasma (ICP) etching, transformer coupled plasma (TCP) etching, hollow anode plasma etching, or spiral resonator plasma etching.

[0058] Therefore, a first trench T1 and a second trench T2 can be formed on the second dielectric layer 20, and a second via VH2 can be formed to expose the first pad portion RDL1b of the first redistribution pattern RDL1. The second via VH2 can be connected to the first trench T1, and the width of the first trench T1 can be greater than the width of the second trench T2.

[0059] When a first trench T1 and a second trench T2 with different widths are formed, the load effect may cause the second trench T2 to have a depth different from that of the first trench T1. In some example embodiments, the depth of the first trench T1 may be greater than the depth of the second trench T2.

[0060] Furthermore, since the first trench T1 is formed after the initial via PVH is formed, the initial via PVH and the first trench T1 may have a rounded corner portion (e.g., a position where the width changes) while performing anisotropic etching on the second dielectric layer 20. Additionally, the lower corner of the second trench T2 may also become rounded.

[0061] Furthermore, when performing the etching process to form the first trench T1 and the second trench T2, the arcuate phenomenon can cause the first trench T1 and the second trench T2 to have their own arcuate sidewalls. For example, the first trench T1 and the second trench T2 can have their laterally convex sidewalls.

[0062] refer to Figure 8 After forming the second via VH2 and the first trench T1 and the second trench T2, the second photoresist pattern PR2 and the hard mask pattern HMP can be removed. The second photoresist pattern PR2 can be removed by a stripping process including ashing and cleaning steps. The hard mask pattern HMP can be removed by a wet etching process.

[0063] Subsequently, the second barrier layer 21 and the second metal layer 23 can be sequentially formed on the second dielectric layer 20 on which the second via VH2, the first trench T1, and the second trench T2 are formed.

[0064] The second barrier layer 21 can be deposited to have the same thickness as the second dielectric layer 20 on which the second via VH2, the first trench T1, and the second trench T2 are formed. For example, the second barrier layer 21 can conformally cover the inner walls of the second via VH2, the inner walls of the first trench T1 and the second trench T2, and the top surface of the second dielectric layer 20. The second barrier layer 21 can be formed using PVD, CVD, or ALD.

[0065] The formation of the second barrier layer 21 may include sequentially depositing a barrier metal layer and a metal seed layer. The barrier metal layer may include, for example, a bilayer or a hybrid layer other than a bilayer, which may include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or titanium / titanium nitride. The metal seed layer may include, for example, copper (Cu).

[0066] The second metal layer 23 can completely fill the second via VH2, the first trench T1, and the second trench T2 in which the second barrier layer 21 is formed. The second metal layer 23 can also be formed on the top surface of the second dielectric layer 20. The second metal layer 23 can be formed by performing an electroplating process, such as electroplating or pulse electroplating. The second metal layer 23 can grow from the surface of a metal seed layer.

[0067] Reference Figure 9The second metal layer 23 and the second barrier layer 21 may undergo a planarization process to expose the top surface of the second dielectric layer 20. A chemical mechanical polishing (CMP) process may be performed as the planarization process. The planarization process can form second redistribution patterns RDL2 that are separated from each other. Each second redistribution pattern RDL2 may include a second barrier pattern 22 and a second metal pattern 24.

[0068] The planarization process allows the second redistribution pattern RDL2 to have a substantially flat top surface. Furthermore, the top surface of the second redistribution pattern RDL2 can be coplanar with the top surface of the second dielectric layer 20.

[0069] The second redistribution pattern RDL2 may include a second via portion RDL2a that penetrates a portion of the second dielectric layer 20 and a second pad portion RDL2b that is in the second dielectric layer 20 and connected to the second via portion RDL2a. Furthermore, the second redistribution pattern RDL2 may include second line portions RDL2c that extend in one direction and are separated from each other in the second dielectric layer 20.

[0070] Reference Figure 10 The third dielectric layer 30 can be formed on the second dielectric layer 20, covering the top surface of the second redistribution pattern RDL2.

[0071] The third dielectric layer 30 may be formed of a photoimageable dielectric (PID). The third dielectric layer 30 may include, for example, a photosensitive polymer. The photosensitive polymer may include one or more of, for example, photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. For example, the third dielectric layer 30 may be formed of the same polymeric material as the second dielectric layer 20. As another example, the third dielectric layer 30 may include the same polymeric material as the first dielectric layer 10 but different from the second dielectric layer 20. As another example, the third dielectric layer 30 may be formed of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0072] Subsequently, a third via VH3 can be formed in the third dielectric layer 30, exposing a portion of the second redistribution pattern RDL2. When the third dielectric layer 30 comprises a photosensitive polymer, the third via VH3 can be formed by performing an exposure and development process on a portion of the third dielectric layer 30. After forming the third via VH3, a curing process can be performed on the third dielectric layer 30.

[0073] Reference Figure 11 Similar to the above references Figure 2 and Figure 3 The formation of the first redistribution pattern RDL1 is discussed, and the third redistribution pattern RDL3 can be formed on the third dielectric layer 30.

[0074] For example, the formation of the third redistribution pattern RDL3 may include forming a third barrier layer covering the surface of the third via VH3 and the third dielectric layer 30, forming a photoresist pattern on the third barrier layer, forming a third metal layer filling the openings of the photoresist pattern, removing the photoresist pattern, and then etching the third barrier layer. Therefore, each third redistribution pattern RDL3 may include a third barrier pattern 32 and a third metal pattern 34. The third redistribution pattern RDL3 may have the same properties as the first redistribution pattern RDL1 described above.

[0075] Reference Figure 12 A fourth dielectric layer 40 may be formed on the third dielectric layer 30, covering the third redistribution pattern RDL3. The fourth dielectric layer 40 may be thicker than the third dielectric layer 30 and may cover the sidewalls of the pads and line portions included in the third redistribution pattern RDL3.

[0076] The fourth dielectric layer 40 may include a photoimageable dielectric (PID), such as a photosensitive polymer. For example, the fourth dielectric layer 40 may include the same polymer as the second dielectric layer 20.

[0077] Subsequently, similar references were made. Figures 4 to 9 The formation of the second redistribution pattern RDL2 discussed herein may include the formation of a fourth redistribution pattern RDL4 within a fourth dielectric layer 40. For example, after a hard mask pattern HMP is formed on the fourth dielectric layer 40, the fourth dielectric layer 40 may be patterned to form vias and trenches, and then a fourth barrier layer and a fourth metal layer may be formed within the vias and trenches. Therefore, each fourth redistribution pattern RDL4 may include a fourth barrier pattern 42 and a fourth metal pattern 44. The fourth redistribution pattern RDL4 may have the same properties as the second redistribution pattern RDL2 described above.

[0078] Reference Figure 13 The fifth dielectric layer 50 may be formed on the fourth dielectric layer 40, covering the fourth redistribution pattern RDL4. The fifth dielectric layer 50 may include a photoimageable dielectric, such as a photosensitive polymer. The fifth dielectric layer 50 may include the same polymer as the third dielectric layer 30.

[0079] A portion of the fifth dielectric layer 50 may undergo exposure and development processes to form a fifth via that exposes a portion of the fourth redistribution pattern RDL4.

[0080] Subsequently, a fifth barrier layer 51 can be formed to conformally cover the surface of the fifth dielectric layer 50 in which the fifth via is formed. A third photoresist pattern PR3 with openings can be formed on the fifth barrier layer 51. The openings of the third photoresist pattern PR3 can overlap with the fifth via.

[0081] refer to Figure 14As shown in the reference above Figure 2 The discussed process may involve electroplating, such as electroplating or pulse electroplating, to form a fifth metal pattern 54 that fills the opening of the third photoresist pattern PR3.

[0082] Subsequently, metal pads 56 can be formed on the fifth metal pattern 54. For example, the metal pads 56 can be formed of a metal or an alloy thereof, each metal or alloy thereof including at least one selected from copper (Cu), nickel (Ni) and gold (Au), and can have a multilayer structure including multiple metals selected from copper (Cu), nickel (Ni) and gold (Au).

[0083] After the metal pads 56 are formed, the third photoresist pattern PR3 can be removed by a stripping process that includes ashing and cleaning steps. Then, a wet etching process can be used to etch the fifth barrier layer 51 on the top surface of the fifth dielectric layer 50, thus forming the fifth barrier layer 51 as a fifth barrier pattern (see...). Figure 15 (of 52). Therefore, as Figure 15 As shown, a fifth redistribution pattern RDL5 can be formed, each of which includes a fifth blocking pattern 52, a fifth metal pattern 54, and a metal pad 56.

[0084] According to some example embodiments, an example in which the first redistribution pattern RDL1, the second redistribution pattern RDL2, the third redistribution pattern RDL3, the fourth redistribution pattern RDL4, and the fifth redistribution pattern RDL5 are vertically stacked is explained, but the inventive concept is not limited thereto, and the number of vertically stacked redistribution patterns can be 2 to 8.

[0085] After that, as Figure 15 As shown, the first connection terminal 150 can be attached to the metal pad 56 of the fifth redistribution pattern RDL5 to connect the first semiconductor chip 100 to the redistribution substrate 300.

[0086] Figure 15 The illustration shows a cross-sectional view of a semiconductor package illustrating some exemplary embodiments of the invention. Figure 16A and Figure 16B The illustration shows a plan view of an example of a first redistribution layer and a second redistribution layer in a redistribution substrate, illustrating some exemplary embodiments of the invention.

[0087] refer to Figure 15 The semiconductor package may include a redistribution substrate 300 and a first semiconductor chip 100 disposed on the redistribution substrate 300.

[0088] The redistribution substrate 300 may include at least one first redistribution layer and at least one second redistribution layer. For example, the redistribution substrate 300 may include vertically stacked first to fifth redistribution layers.

[0089] The first redistribution layer may include a first dielectric layer 10 and a first redistribution pattern RDL1. The first redistribution pattern RDL1 may have flat (e.g., linear) sidewalls LS perpendicular to the top surface of the first dielectric layer 10. Each first redistribution pattern RDL1 may include a first barrier pattern 12 and a first metal pattern 14. The first barrier pattern 12 may have a portion disposed between the top surface of the first dielectric layer 10 and the bottom surface of the first metal pattern 14. At least as Figure 15 As shown, the first blocking pattern 12 and the first metal pattern 14 may have sidewalls that are misaligned with each other, wherein the sidewalls are offset from each other in a horizontal direction extending parallel to the bottom surface 300a of the redistribution substrate 300. Therefore, at least as Figure 15 As shown, the sidewall of the first metal pattern 14 is not aligned with the sidewall of the first blocking pattern 12 (e.g., offset in the horizontal direction).

[0090] refer to Figure 15 and Figure 16A The first redistribution pattern RDL1 may include a first pass portion RDL1a penetrating the first dielectric layer 10, a first pad portion RDL1b located on the first dielectric layer 10 and connected to the first pass portion RDL1a, and a first line portion RDL1c located on the first dielectric layer 10 (e.g., on the top surface of the first dielectric layer) and extending in one direction from the first pad portion RDL1b (e.g., away from the first pad portion RDL1b). The first redistribution pattern RDL1 may have a first minimum width W1 at the first line portion RDL1c (e.g., the first line portion RDL1c may have a first minimum width W1), and the first minimum width W1 may be in the range of about 3.0 μm to about 10.0 μm. Adjacent first line portions RDL1c may be spaced apart from each other by a first interval S1. The first interval S1 may be equal to or substantially equal to or greater than the first minimum width W1. The first redistribution pattern RDL1 may have a thickness ranging from about 3.0 μm to about 4.5 μm at the first line portion RDL1c.

[0091] The second redistribution layer may include a second dielectric layer 20 and a second redistribution pattern RDL2. The second dielectric layer 20 may be disposed on the first dielectric layer 10 and is thicker than the first dielectric layer 10. The second dielectric layer 20 may cover the sidewalls of the first pad and the line portions RDL1b and RDL1c of the first redistribution pattern RDL1. At least as Figure 15As shown, the second dielectric layer 20 may be located on the first dielectric layer 10 and may cover the sidewalls (e.g., LS) of the first metal pattern 14 of the first redistribution pattern RDL1, and thus may cover the sidewalls of the underlying first redistribution pattern of the first redistribution layer. At least as Figure 15 As shown, the second dielectric layer 20 may have a portion between the bottom surface of the first metal pattern 14 and the top surface of the first dielectric layer 10 (e.g., based on the misalignment of the first metal pattern and the first barrier pattern).

[0092] Each of the second redistribution patterns RDL2 may include a second barrier pattern 22 and a second metal pattern 24. The second barrier pattern 22 may be disposed between the second metal pattern 24 and the second dielectric layer 20, thereby reducing or preventing the second dielectric layer 20 from receiving metallic material diffused from the second metal pattern 24. The second barrier pattern 22 may cover the sidewalls and bottom surface of the second metal pattern 24. The top surfaces of the second barrier pattern 22 and the second metal pattern 24 may be coplanar with the top surface of the second dielectric layer 20. Therefore, the top surface of the second dielectric layer 20 may be coplanar or substantially coplanar with the top surface of the second redistribution pattern RDL2.

[0093] refer to Figure 15 and Figure 16B The second blocking pattern RDL2 may include a second pass portion RDL2a that penetrates the second dielectric layer 20 (e.g., a portion of the second dielectric layer 20), a second pad portion RDL2b that is in the second dielectric layer 20 (e.g., inside) and connected (e.g., directly connected) to the second pass portion RDL2a, and a second line portion RDL2c that is located in the second dielectric layer 20 (e.g., inside) and extends in a direction away from the second pad portion RDL2b.

[0094] The second redistribution pattern RDL2 can be configured such that the top surfaces of the second pad portion RDL2b and the second line portion RDL2c are coplanar with the top surface of the second dielectric layer 20. To reiterate, as... Figure 15 As shown, the top surface of the second dielectric layer 20 can be at the same horizontal height as the top surface of the second distribution pattern RDL2 (e.g., at the same vertical distance from the bottom surface 300a). While the first metal pattern 14 of the first redistribution pattern RDL1 can have flat (e.g., linear) sidewalls LS, the second redistribution pattern RDL2 (e.g., second metal pattern 24) can have arcuate (e.g., non-linear, curved) sidewalls RS at each of the second pad portion RDL2b and the second line portion RDL2c. The second pad portion RDL2b and the second line portion RDL2c can have laterally convex sidewalls RS.

[0095] Therefore, it should be understood that in some example embodiments, the first pad portion RDL1b of the first redistribution pattern RDL1 may have linear (e.g., flat) sidewalls LS, and the second pad portion RDL2b of the second redistribution pattern RDL2 may have arcuate (e.g., non-linear, curved) sidewalls RS. At least as Figure 15 As shown, each of the second pad portion RDL2b and the second line portion RDL2c can have an arcuate sidewall RS.

[0096] The second thickness TH2 of the second pad portion RDL2b of the second redistribution pattern RDL2 in the vertical direction (perpendicular to the bottom surface 300a) can be greater than the first thickness TH1 of the second line portion RDL2c of the second redistribution pattern RDL2 in the vertical direction (perpendicular to the bottom surface 300a), such that the first thickness TH1 can be smaller than the second thickness TH2. The first thickness TH1 can be in the range of about 2.7 μm to about 3.5 μm, and the second thickness TH2 can be in the range of about 3.0 μm to about 4.3 μm. The difference between the first thickness TH1 and the second thickness TH2 can be about 0.3 μm to about 0.8 μm.

[0097] At least as Figure 15 As shown, the top surface of the second line portion RDL2c can be at substantially the same horizontal height as the top surface of the second pad portion RDL2b (e.g., at the same distance from the bottom surface 300a of the redistribution substrate 300 in the vertical direction), and the bottom surface of the second line portion RDL2c can be at a different horizontal height than the bottom surface of the second pad portion RDL2b (e.g., at a different distance from the bottom surface of the redistribution substrate in the vertical direction).

[0098] The second redistribution pattern RDL2 may have a second minimum width W2 at the second line portion RDL2c, and the second minimum width W2 may be in the range of approximately 0.5 μm to approximately 2.0 μm. Adjacent second line portions RDL2c may be spaced apart from each other by a second interval S2. The second minimum width W2 may be the same as or substantially the same as the second interval S2. For example, the second redistribution pattern RDL2 may have a second minimum width W2 at the top or bottom surface of the second line portion RDL2c. Furthermore, the second redistribution pattern RDL2 may have a maximum width at a horizontal height (e.g., at a position at a specific distance from the bottom surface in the vertical direction) between the top and bottom surfaces of the second line portion RDL2c. Therefore, the second line portion RDL2c may have a minimum width W2 at the top or bottom surface of the second line portion RDL2c, and a maximum width at a horizontal height between the top and bottom surfaces of the second line portion RDL2c. The aforementioned second minimum width W2 and maximum width of the second redistribution pattern RDL2 may correspond to the corresponding minimum width and maximum width of the second metal pattern 24. Therefore, it should be understood that the second metal pattern 24 may have a minimum width at the top surface or the bottom surface of the second metal pattern 24, and a maximum width at the horizontal height between the top surface and the bottom surface of the second metal pattern 24. There may be a difference of approximately 0.3 μm to approximately 0.5 μm between the maximum and minimum width of the second line portion RDL2c of the second redistribution pattern RDL2.

[0099] The width of the second path portion RDL2a of the second redistribution pattern RDL2 can be smaller than the width of the first path portion RDL1a of the first redistribution pattern RDL1. At least as Figure 15 As shown, the second redistribution pattern RDL2 may have an arcuate edge C between the sidewall of the second path portion RDL2a and the bottom surface of the second pad portion RDL2b. For example, the second path portion RDL2a may have a wider width in the region adjacent to the second pad portion RDL2b than in the region adjacent to the first pad pattern RDL1.

[0100] A third dielectric layer 30, a fourth dielectric layer 40, and a fifth dielectric layer 50, stacked sequentially, may be disposed on the second dielectric layer 20. A third redistribution pattern RDL3, a fourth redistribution pattern RDL4, and a fifth redistribution pattern RDL5 may be disposed within the third dielectric layer 30, the fourth dielectric layer 40, and the fifth dielectric layer 50, respectively. The third redistribution pattern RDL3 and the fifth redistribution pattern RDL5 may have the same properties as the first redistribution pattern RDL1, and the fourth redistribution pattern RDL4 may have the same properties as the second redistribution pattern RDL2. For example, the third redistribution pattern RDL3 may all include pad portions and line portions disposed on the third dielectric layer 30, and the fifth redistribution pattern RDL5 may all include pad portions and line portions disposed on the fifth dielectric layer 50. The fourth redistribution pattern RDL4 may all include pad portions and line portions disposed on the fourth dielectric layer 40.

[0101] Therefore, in some example embodiments, at least in Figure 15 The semiconductor package shown can be understood as comprising a plurality of first redistribution layers (each including at least RDL1 and RDL3) and a plurality of second redistribution layers (each including at least RDL2 and RDL4), which are stacked vertically and alternately in a vertical direction perpendicular to the bottom surface 300a of the redistribution substrate 300. At least as Figure 15 As shown, each first redistribution layer may include a first dielectric layer (e.g., first dielectric layer 10 or third dielectric layer 30) and a first redistribution pattern (e.g., RDL1 or RDL3), the first redistribution pattern including a first via portion and a first pad portion connected to the first via portion, wherein the first via portion of a given first redistribution layer penetrates at least a portion of the first dielectric layer of the given first redistribution layer, and the first pad portion of the given first redistribution layer is not the top surface of the first dielectric layer. At least as Figure 15 As shown, each second redistribution layer may include: a second dielectric layer (e.g., second dielectric layer 20 or fourth dielectric layer 40) located below (e.g., directly below) the first redistribution layer and above (e.g., directly below) the first dielectric layer (e.g., first dielectric layer 10 or third dielectric layer 30); and a second redistribution pattern (e.g., RDL2 or RDL4) including a second via portion and a second pad portion connected to the second via portion, wherein the second via portion of the given second redistribution layer penetrates a portion of the second dielectric layer of the given second redistribution layer, and is further within the second dielectric layer.

[0102] like Figure 15As shown, the first semiconductor chip 100 includes a plurality of chip pads 111, and the semiconductor package may include a first connection terminal 150 between the redistribution substrate 300 and the chip pads 111 of the first semiconductor chip 100. The fifth redistribution pattern RDL5 may include metal pads 56, and the metal pads 56 may be connected to the chip pads 111 of the first semiconductor chip 100 via the first connection terminal 150. As a result, the chip pads 111 may be electrically connected to at least two of the first to fifth redistribution patterns RDL1, RDL2, RDL3, RDL4, and RDL5.

[0103] like Figure 15 As shown, the first to fifth redistribution patterns RDL1, RDL2, RDL3, RDL4, and RDL5 are each located at different distances from the bottom surface 300a of the redistribution substrate 300 in a vertical direction extending perpendicular to the bottom surface 300a. The distance of a structure (e.g., the bottom surface, top surface, and / or its centroid) from the bottom surface 300a in the vertical direction can be referred to as the "horizontal height" of the structure. Therefore, it should be understood that some or all of the first to fifth redistribution patterns RDL1, RDL2, RDL3, RDL4, and RDL5 can each be at different horizontal heights from each other, such that, for example, some or all of the first to fifth redistribution patterns RDL1, RDL2, RDL3, RDL4, and RDL5 have their own bottom surfaces that are located at different distances from the bottom surface 300a of the redistribution substrate 300 in a vertical direction perpendicular to the bottom surface 300a of the redistribution substrate 300.

[0104] In some exemplary embodiments, a power supply voltage and / or a ground voltage may be provided to a first redistribution pattern RDL1 or a third redistribution pattern RDL3, each of which includes a line portion having a first minimum width W1 in a horizontal direction extending parallel to the bottom surface 300a of the redistribution substrate 300. Data signals and / or control signals may be provided to a second redistribution pattern RDL2 or a fourth redistribution pattern RDL4, each of which includes a line portion having a second minimum width W2 in a horizontal direction that is less than (e.g., less in amplitude than) the first minimum width W1.

[0105] Figure 17 The illustration shows a cross-sectional view of a semiconductor package illustrating some exemplary embodiments of the invention. Figure 18A The illustration shows Figure 17 A magnified view of part P1. Figure 18B The illustration shows Figure 18A A magnified view of part P2. Figure 19 , Figure 20 and Figure 21 The diagram shows Figure 17 The image depicts an enlarged cross-sectional view of portion P1, which illustrates a semiconductor package according to some exemplary embodiments of the concept of the present invention.

[0106] For the sake of brevity, references can be omitted. Figure 15 , Figure 16A and Figure 16B The embodiments discussed share the same technical features.

[0107] refer to Figure 17 According to some example embodiments, a semiconductor package may include a first semiconductor package 1000a and a second semiconductor package 1000b disposed on the first semiconductor package 1000a.

[0108] The first semiconductor package 1000a may include a lower redistribution substrate 300L, an upper redistribution substrate 300U, a first semiconductor chip 100, a metal pillar 360, and a molding layer 370.

[0109] As described above, the lower redistribution substrate 300L may include a first redistribution pattern RDL1, whose pad portion and line portion are located on the first dielectric layer 310, and the lower redistribution substrate 300L may also include a second redistribution pattern RDL2, whose pad portion and line portion are located in the second dielectric layer 320.

[0110] For example, refer to Figure 18A and Figure 18B The lower redistribution substrate 300L may include a first dielectric layer 310, a second dielectric layer 320, a third dielectric layer 330, a fourth dielectric layer 340, and a fifth dielectric layer 350, and may also include a first redistribution pattern RDL1, a second redistribution pattern RDL2, a third redistribution pattern RDL3, a fourth redistribution pattern RDL4, and a fifth redistribution pattern RDL5 in the first dielectric layer 310, the second dielectric layer 320, the third dielectric layer 330, the fourth dielectric layer 340, and the fifth dielectric layer 350. The first redistribution pattern RDL1, the third redistribution pattern RDL3, and the fifth redistribution pattern RDL5 may include respective pad portions and line portions disposed on the first dielectric layer 310, the third dielectric layer 330, and the fifth dielectric layer 350, respectively. The second redistribution pattern RDL2 and the fourth redistribution pattern RDL4 may include respective pad portions and line portions disposed in the second dielectric layer 320 and the fourth dielectric layer 340, respectively.

[0111] The first redistribution pattern RDL1, the third redistribution pattern RDL3, and the fifth redistribution pattern RDL5 may each include a line portion having a first minimum width (see [link to redistribution pattern]). Figure 16A(W1). The first minimum width can be in the range of about 5.0 μm to about 10.0 μm.

[0112] The second redistribution pattern RDL2 and the fourth redistribution pattern RDL4 may each include a fine-pitch line portion. The second redistribution pattern RDL2 and the fourth redistribution pattern RDL4 may each include a line portion, each line portion having a second minimum width less than the first minimum width (see [link to relevant documentation]). Figure 16B The second minimum width (e.g., the width of the second line portion RDL2c of the second redistribution pattern) can be in the range of about 0.5 μm to about 2.5 μm.

[0113] The first redistribution pattern RDL1, the third redistribution pattern RDL3, and the fifth redistribution pattern RDL5 can all have the same characteristics as the reference above. Figure 15 and Figure 16A The same properties are discussed. The second redistribution pattern RDL2 and the fourth redistribution pattern RDL4 can both possess the same properties as those mentioned above. Figure 15 and Figure 16B The same properties discussed.

[0114] The first redistribution pattern RDL1 may include a first blocking pattern 12 and a first metallic pattern 14. At least as Figure 15 As shown, the first metal pattern 14 can be located on the first dielectric layer 10, and the first barrier pattern 12 can be located between the bottom surface of the first dielectric layer 10 and the first metal pattern 14. The second redistribution pattern RDL2 can include the second barrier pattern 22 and the second metal pattern 24. At least as Figure 15 As shown, the second metal pattern 24 may be in the second dielectric layer 20 (e.g., between the top and bottom surfaces of the second dielectric layer 20), and the second barrier pattern 22 may be between the second dielectric layer 20 and the bottom surface of the second metal pattern 24, and further between the second dielectric layer 20 and the sidewalls of the second metal pattern 24. The third redistribution pattern RDL3 may include the third barrier pattern 32 and the third metal pattern 34. The fourth redistribution pattern RDL4 may include the fourth barrier pattern 42 and the fourth metal pattern 44. The fifth redistribution pattern RDL5 may include the fifth barrier pattern 52 and the fifth metal pattern 54.

[0115] The second redistribution pattern RDL2 can be configured such that the second blocking pattern 22 covers the sidewalls of the second metal pattern 24, and the fourth redistribution pattern RDL4 can be configured such that the fourth blocking pattern 42 covers the sidewalls of the fourth metal pattern 44. The second redistribution pattern RDL2 and the fourth redistribution pattern RDL4 can each have their own arcuate sidewalls RS. The first metal pattern 14 and the third metal pattern 34 can each have their own flat and substantially linear sidewalls LS, and the sidewalls of the first metal pattern 14 and the third metal pattern 34 can be covered by the second dielectric layer 320 and the fourth dielectric layer 340, respectively.

[0116] According to some exemplary embodiments, including Figure 19 In the exemplary embodiment shown, the first redistribution pattern RDL1 and the second redistribution pattern RDL2 may be adjacent to the conductive pad CP on the bottom surface of the redistribution substrate 300, and may respectively include line portions having a first minimum width on the first dielectric layer 310 and the second dielectric layer 320.

[0117] The third redistribution pattern RDL3 and the fourth redistribution pattern RDL4 adjacent to the first semiconductor chip 100 can be disposed in the third dielectric layer 330 and the fourth dielectric layer 340, respectively. The third redistribution pattern RDL3 and the fourth redistribution pattern RDL4 can each include line portions having a second minimum width that is less than the first minimum width.

[0118] According to some exemplary embodiments, including Figure 20 In the exemplary embodiment shown, each of the first redistribution pattern RDL1, the second redistribution pattern RDL2, and the third redistribution pattern RDL3 sequentially stacked on the conductive pad CP may include a line portion on the top surface of a corresponding one of the first dielectric layer 310, the second dielectric layer 320, and the third dielectric layer 330. A fourth redistribution pattern RDL4 may be disposed in the fourth dielectric layer 340 and may include a line portion whose linewidth is smaller than the linewidth of the line portion included in each of the first redistribution pattern RDL1, the second redistribution pattern RDL2, and the third redistribution pattern RDL3.

[0119] According to some example embodiments, including Figure 21In the illustrated example embodiment, the first redistribution pattern RDL1 may include line portions located on the first dielectric layer 310. Each of the sequentially stacked second redistribution patterns RDL2, third redistribution patterns RDL3, and fourth redistribution patterns RDL4 may be buried within a corresponding one of the second dielectric layer 320, third dielectric layer 330, and fourth dielectric layer 340. Each of the second redistribution patterns RDL2, third redistribution patterns RDL3, and fourth redistribution patterns RDL4 may include line portions whose linewidth is smaller than the linewidth of the line portions included in the first redistribution pattern RDL1.

[0120] The first metal pattern 14 of the first redistribution pattern RDL1 may have a sidewall that contacts the sidewall of the second dielectric layer 320, and each of the second blocking pattern 22, the third blocking pattern 32 and the fourth blocking pattern 42 in the second redistribution pattern RDL2, the third redistribution pattern RDL3 and the fourth redistribution pattern RDL4 may contact a corresponding one of the second dielectric layer 320, the third dielectric layer 330 and the fourth dielectric layer 340.

[0121] Reference Figure 17 A first semiconductor chip 100 may be disposed on a lower redistribution substrate 300L. When viewed in plan view, the first semiconductor chip 100 may be disposed in the central region of the lower redistribution substrate 300L. The first semiconductor chip 100 may have a plurality of chip pads 111 on its bottom surface. The first semiconductor chip 100 may be arranged such that its bottom surface faces the top surface of the lower redistribution substrate 300L, and the chip pads 111 of the first semiconductor chip 100 may be connected to a fifth redistribution pattern RDL5 of the lower redistribution substrate 300L. A first connection terminal 150 may be attached between the chip pads 111 of the first semiconductor chip 100 and the fifth redistribution pattern RDL5 of the lower redistribution substrate 300L.

[0122] The metal pillars 360 can be configured to surround the first semiconductor chip 100, can be connected to the lower redistribution substrate 300L, and can electrically connect the lower redistribution substrate 300L to the upper redistribution substrate 300U. The metal pillars 360 can penetrate the molding layer 370, and their top surfaces can be coplanar with the top surface of the molding layer 370. The bottom surface of the metal pillars 360 can be in direct contact with the fifth redistribution pattern RDL5 of the lower redistribution substrate 300L.

[0123] The molding layer 370 can be disposed between the lower redistribution substrate 300L and the upper redistribution substrate 300U, and therefore can be on the lower redistribution substrate 300L and can cover the first semiconductor chip 100. The molding layer 370 can be disposed on the top surface of the lower redistribution substrate 300L and can cover the sidewalls and top surface of the first semiconductor chip 100. The molding layer 370 can fill the gaps between the metal pillars 360 and can have a thickness the same as the length of each metal pillar 360. The molding layer 370 can include a dielectric polymer, such as an epoxy molding compound.

[0124] The second semiconductor package 1000b may be disposed on the upper redistribution substrate 300U. The upper redistribution substrate 300U may be on the molding layer 370 and may be electrically connected to the metal pillar 360. According to some example embodiments, similarly, the lower redistribution substrate 300L and the upper redistribution substrate 300U may include an upper redistribution pattern RDL and upper dielectric layers 310U, 320U and 330U.

[0125] Similarly, the lower redistribution substrate 300L and the upper redistribution substrate 300U can be configured such that the upper redistribution pattern RDL includes a first upper redistribution pattern, which includes pad portions and line portions located on the upper dielectric layer 310U, and also includes a second redistribution pattern, which includes pad portions and line portions located in the upper dielectric layer 320U.

[0126] The second semiconductor package 1000b may include a package substrate 710, a second semiconductor chip 200, and an upper molding layer 730. The package substrate 710 may be a printed circuit board. In some example embodiments, a redistribution substrate may be used as the package substrate 710. A lower conductive pad 705 may be disposed on the bottom surface of the package substrate 710.

[0127] The second semiconductor chip 200 may be disposed on the packaging substrate 710. The second semiconductor chip 200 may include an integrated circuit, and the integrated circuit may include memory circuits, logic circuits, or a combination thereof. The second semiconductor chip 200 may include chip pads 221, which are electrically connected to an upper conductive pad 703 on the top surface of the packaging substrate 710 via bonding wires. The upper conductive pad 703 on the top surface of the packaging substrate 710 may be electrically connected to a lower conductive pad 705 via internal wiring 715 in the packaging substrate 710.

[0128] An upper molding layer 730 covering the second semiconductor chip 200 may be disposed on the packaging substrate 710. The upper molding layer 730 may include a dielectric polymer, such as an epoxy polymer.

[0129] The third connection terminal 750 may be disposed between the lower conductive pad 705 of the package substrate 710 and the redistribution pattern RDL of the upper redistribution substrate 300U. The third connection terminal 750 may be formed of a low-melting-point metal including tin (Sn), such as solder, but this is merely an example and there is no limitation on the material of the third connection terminal 750. The third connection terminal 750 may be formed as a multilayer or a single layer. When the third connection terminal 750 is formed as a multilayer, the third connection terminal 750 may include, but is not limited to, solder, and when the third connection terminal 750 is formed as a single layer, the third connection terminal 750 may include, but is not limited to, tin-silver, solder, or copper.

[0130] Figure 22 The illustration shows a cross-sectional view of a semiconductor package illustrating some example embodiments of the concept according to the present invention. Figure 23 The illustration shows Figure 22 A magnified view of part P3. For the sake of brevity, references to the above can be omitted. Figures 17 to 21 The embodiments discussed share the same technical features.

[0131] refer to Figure 22 and Figure 23 Unlike including Figure 17 Some exemplary embodiments of the exemplary embodiments shown may be provided, and the semiconductor package according to some exemplary embodiments may be configured such that a lower redistribution substrate 300L is formed on the active surface of the first semiconductor chip 100.

[0132] The lower redistribution substrate 300L can be configured such that a first dielectric layer 310, a second dielectric layer 320, a third dielectric layer 330, a fourth dielectric layer 340, and a fifth dielectric layer 350 are sequentially stacked on the chip pads 111 of the first semiconductor chip 100, and a first redistribution pattern RDL1, a second redistribution pattern RDL2, a third redistribution pattern RDL3, and a fourth redistribution pattern RDL4 are respectively disposed in the first dielectric layer 310, the second dielectric layer 320, the third dielectric layer 330, and the fourth dielectric layer 340. The fifth dielectric layer 350 can be a passivation layer and is disposed on the bottom surface of the lower redistribution substrate 300L.

[0133] The first redistribution pattern RDL1 may each include a first pass portion connected to the chip pad 111 of the first semiconductor chip 100. Furthermore, the second redistribution pattern RDL2, the third redistribution pattern RDL3, and the fourth redistribution pattern RDL4 may include their respective second, third, and fourth pass portions, which are closer to the first semiconductor chip 100 than their respective second, third, and fourth pad portions.

[0134] For example, the first redistribution pattern RDL1 and the second redistribution pattern RDL2 may be closer to the first semiconductor chip 100 than the third redistribution pattern RDL3 and the fourth redistribution pattern RDL4. Each of the first redistribution pattern RDL1 and the second redistribution pattern RDL2 may include a line portion whose linewidth is smaller than the line portion included in one of the third redistribution patterns RDL3 and the fourth redistribution pattern RDL4. The first redistribution pattern RDL1 and the second redistribution pattern RDL2 may each include a first blocking pattern 12 and a second blocking pattern 22 covering the sidewalls of their respective first metal pattern 14 and second metal pattern 24. The third redistribution pattern RDL3 and the fourth redistribution pattern RDL4 may include their respective third metal pattern 34 and fourth metal pattern 44, whose sidewalls are in contact with the fourth dielectric layer 340 and the fifth dielectric layer 350, respectively. The first redistribution pattern RDL1 and the second redistribution pattern RDL2, each having a damascene structure, may have different varying horizontal heights as described above.

[0135] Figure 24 , Figure 25 , Figure 26 and Figure 27 The illustration shows a cross-sectional view of a semiconductor package illustrating some example embodiments of the concept according to the present invention. For the sake of brevity, the same technical features as those in the embodiments described above may be omitted.

[0136] refer to Figure 24 Unlike including Figure 17 Some exemplary embodiments of the illustrated embodiments are provided. According to some exemplary embodiments, the semiconductor package can be configured such that the second semiconductor package 1000b includes a first upper semiconductor chip 200a and a second upper semiconductor chip 200b. For example, the second semiconductor package 1000b may include a package substrate 710, the first upper semiconductor chip 200a and the second upper semiconductor chip 200b on the package substrate 710, and an upper molding layer 730.

[0137] Each of the first upper semiconductor chip 200a and the second upper semiconductor chip 200b may include a chip pad 221 on its bottom surface, and the chip pad 221 may be electrically connected to the lower conductive pad 705 via internal wiring 715 in the package substrate 710. The first upper semiconductor chip 200a and the second upper semiconductor chip 200b are described as being disposed side-by-side on the top surface of the package substrate 710; however, alternatively, the first upper semiconductor chip 200a and the second upper semiconductor chip 200b may be stacked sequentially on the top surface of the package substrate 710.

[0138] refer to Figure 25 Unlike including Figure 17Some exemplary embodiments of the exemplary embodiments shown may be configured such that the upper redistribution substrate is omitted from the first semiconductor package 1000a.

[0139] For example, the upper dielectric layer 380 may be disposed on the molding layer 370, and the third connection terminal 750 may be disposed between the lower conductive pad 705 of the package substrate 710 and the metal pillar 360 of the first semiconductor package 1000a.

[0140] The second semiconductor chip 200 can be disposed on the packaging substrate 710, and the chip pad 221 of the second semiconductor chip 200 can be adjacent to the top surface of the packaging substrate 710. The chip pad 221 of the second semiconductor chip 200 can be electrically connected to the lower conductive pad 705 through the internal wiring 715 in the packaging substrate 710.

[0141] refer to Figure 26 According to some example embodiments, a semiconductor package may include a lower redistribution substrate 300L, an upper redistribution substrate 300U, a first semiconductor chip 100, a metal pillar 360, a molding layer 370, and a second semiconductor chip 200.

[0142] The lower redistribution substrate 300L, the upper redistribution substrate 300U, the first semiconductor chip 100, the metal pillar 360, and the molding layer 370 can be referenced. Figure 17 Those of the first semiconductor package 1000a discussed are the same or substantially the same.

[0143] According to some example embodiments, the second semiconductor chip 200 may have a bottom surface that is in direct contact with the upper dielectric layer 330U of the upper redistribution substrate 300U, and the chip pads 221 of the second semiconductor chip 200 may be in direct contact with the corresponding uppermost pad portion of the upper redistribution pattern RDL. The chip pads 221 of the second semiconductor chip 200 may correspond to the uppermost pad portion of the upper redistribution pattern RDL and may have the same size and arrangement as the uppermost pad portion of the upper redistribution pattern RDL. The chip pads 221 of the second semiconductor chip 200 may include metals such as copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), or any alloy thereof.

[0144] refer to Figure 27 According to some example embodiments, a semiconductor package may include a first semiconductor package 1000a and a second semiconductor package 1000b disposed on the first semiconductor package 1000a.

[0145] The first semiconductor package 1000a may include a redistribution substrate 300, a connection substrate 400 on the redistribution substrate 300, a first semiconductor chip 100, and a molding layer 450.

[0146] As described above, the redistribution substrate 300 may include multiple dielectric layers and multiple redistribution patterns. For example, the redistribution substrate 300 may include a first dielectric layer 310, a second dielectric layer 320, a third dielectric layer 330, and a fourth dielectric layer 340 sequentially stacked on the bottom surface of the first semiconductor chip 100, and may also include a first redistribution pattern RDL1, a second redistribution pattern RDL2, a third redistribution pattern RDL3, and a fourth redistribution pattern RDL4 in the first dielectric layer 310, the second dielectric layer 320, the third dielectric layer 330, and the fourth dielectric layer 340. As described above, each of the first redistribution pattern RDL1, the second redistribution pattern RDL2, the third redistribution pattern RDL3, and the fourth redistribution pattern RDL4 may include a via portion, a pad portion, and a line portion, and the via portion of the first redistribution pattern to the fourth redistribution pattern RDL1 to RDL4 may be closer to the first semiconductor chip 100 than the pad portion of the first redistribution pattern to the fourth redistribution pattern RDL1 to RDL4. Furthermore, one or more of the first redistribution pattern RDL1, the second redistribution pattern RDL2, the third redistribution pattern RDL3, and the fourth redistribution pattern RDL4 may include redistribution patterns with a damascene structure. For example, the third redistribution pattern RDL3 may include a third metal pattern 34 disposed in the third dielectric layer 330 and a third blocking pattern 32 disposed between the third metal pattern 34 and the third dielectric layer 330.

[0147] The interconnect substrate 400 may have an opening that exposes the top surface of the redistribution substrate 300, and the first semiconductor chip 100 may be disposed in the opening of the interconnect substrate 400. The interconnect substrate 400 may be provided before or after the first semiconductor chip 100 is provided. For example, a hole may be formed in a printed circuit board, and a printed circuit board with holes may be used as the interconnect substrate 400. When viewed in a plan view, the first semiconductor chip 100 may be disposed on the central region of the redistribution substrate 300.

[0148] The connecting substrate 400 may include a base layer 410 and a conductive structure 420. The base layer 410 may include a dielectric material. For example, the base layer 410 may include a carbon-based material, ceramic, or polymer. The conductive structure 420 may include wiring patterns and wiring vias connecting the wiring patterns to each other. The conductive structure 420 of the connecting substrate 400 may be connected to a first redistribution pattern RDL1 of the redistribution substrate 300. The conductive structure 420 may include a metal. The conductive structure 420 may include at least one selected from, for example, copper, aluminum, gold, lead, stainless steel, silver, iron, and any alloy thereof.

[0149] A molding layer 450 may be formed on the first semiconductor chip 100 and the interconnect substrate 400. The molding layer 450 may extend to and fill the gap between the first semiconductor chip 100 and the interconnect substrate 400. The molding layer 450 may include a dielectric polymer, such as an epoxy polymer. The molding layer 450 may partially expose the conductive structure 420 of the interconnect substrate 400.

[0150] The second semiconductor package 1000b may include a package substrate 710, a second semiconductor chip 200, and an upper molding layer 730. The package substrate 710 may be a printed circuit board. In some example embodiments, a redistribution substrate 300 may be used as the package substrate 710. The package substrate 710 may have a lower conductive pad 705 disposed on its bottom surface.

[0151] The second semiconductor chip 200 may be disposed on the packaging substrate 710. The second semiconductor chip 200 may include an integrated circuit, and the integrated circuit may include memory circuitry, logic circuitry, or a combination thereof. The second semiconductor chip 200 may include a chip pad 221 electrically connected to a lower conductive pad 705 via internal wiring 715 in the packaging substrate 710. An upper molding layer 730 covering the second semiconductor chip 200 may be disposed on the packaging substrate 710. The upper molding layer 730 may include a dielectric polymer, such as an epoxy polymer.

[0152] The third connection terminal 750 can be disposed in the upper hole of the molding layer 450. The third connection terminal 750 can be disposed between the lower conductive pad 705 of the packaging substrate 710 and the conductive structure 420 of the connecting substrate 400.

[0153] Figure 28 The illustration shows a simplified plan view of a semiconductor package illustrating some example embodiments of the concept according to the present invention. Figure 29 The diagram illustrates along Figure 28 The cross-sectional view taken along line A-A' shows a semiconductor package according to some exemplary embodiments of the concept of the present invention.

[0154] refer to Figure 28 and Figure 29 The semiconductor package may include a first semiconductor chip 100, a second semiconductor chip 200, a redistribution substrate 300, a packaging substrate 500, and a thermal radiation structure 600.

[0155] The first semiconductor chip 100 and the second semiconductor chip 200 can be disposed on the top surface of the redistribution substrate 300.

[0156] The first semiconductor chip 100 may include chip pads 111 located on its bottom surface. The first semiconductor chip 100 may be a logic chip including a processor, such as a microelectromechanical system (MEMS) device, an optoelectronic device, a central processing unit (CPU), a graphics processing unit (GPU), a mobile application, or a digital signal processor (DSP). The first semiconductor chip 100 may have a thickness of about 700 μm to about 775 μm.

[0157] A second semiconductor chip 200, spaced apart from the first semiconductor chip 100, may be disposed on the redistribution substrate 300. Each second semiconductor chip 200 may include a plurality of vertically stacked memory chips 210. The plurality of memory chips 210 may be electrically connected to each other via upper and lower chip pads 221 and 223, vias 225, and connecting bumps 230. The memory chips 210 may be stacked on the redistribution substrate 300 to achieve alignment of their sidewalls. An adhesive layer 235 may be disposed between the memory chips 210. The adhesive layer 235 may be, for example, a polymer strip comprising a dielectric material. The adhesive layer 235 may be inserted between the connecting bumps 230, thereby reducing or preventing electrical short circuits between the connecting bumps 230.

[0158] The first semiconductor chip 100 and the second semiconductor chip 200 can be connected to the redistribution substrate 300 via a first connection terminal 150. The first connection terminal 150 can be attached to chip pads 111 and 221 of the first semiconductor chip 100 and the second semiconductor chip 200. The first connection terminal 150 can be one or more of solder balls, conductive bumps, and conductive pillars. The first connection terminal 150 can include one or more of copper, tin, and lead. The first connection terminal 150 can all have a thickness of, for example, from about 30 μm to about 70 μm.

[0159] The redistribution substrate 300 may have a molding layer 370 thereon covering the first semiconductor chip 100 and the second semiconductor chip 200. The molding layer 370 may have sidewalls aligned with the sidewalls of the redistribution substrate 300. The molding layer 370 may have a top surface coplanar with the top surfaces of the first semiconductor chip 100 and the second semiconductor chip 200. The molding layer 370 may include a dielectric polymer, such as an epoxy molding compound (EMC).

[0160] A first bottom filler layer may be located between the first semiconductor chip 100 and the redistribution substrate 300, and between the second semiconductor chip 200 and the redistribution substrate 300. The first bottom filler layer 160 may fill the gap between the first connection terminals 150. The first bottom filler layer may include, for example, a thermosetting resin or a photocurable resin. The first bottom filler layer may further include inorganic or organic fillers. In some exemplary embodiments, the first bottom filler layer may be omitted, and instead, the molding layer 370 may fill the gap between the redistribution substrate 300 and the bottom surfaces of the first semiconductor chip 100 and the second semiconductor chip 200.

[0161] The redistribution substrate 300 can be disposed on the packaging substrate 500 and can be connected to the packaging substrate 500 via the second connection terminal 390. The redistribution substrate 300 may include a chip region and an edge region on the circumference of the chip region. The first semiconductor chip 100 and the second semiconductor chip 200 can be disposed on the chip region of the redistribution substrate 300.

[0162] The redistribution substrate 300 may include multiple dielectric layers 310, 320, 330, 340, and 350, and may further include redistribution patterns RDL1, RDL2, RDL3, RDL4, and RDL5 in each dielectric layer 310, 320, 330, 340, and 350. (Refer to the above) Figure 17 The redistribution patterns RDL1, RDL2, RDL3, RDL4, and RDL5 may have an edging structure. For example, the first redistribution pattern RDL1 may include a first metal pattern 14 whose sidewalls are in contact with the second dielectric layer 320, and the second redistribution pattern RDL2 may include a second metal pattern 24 and a second blocking pattern 22 between the second metal pattern 24 and the second dielectric layer 320.

[0163] The second connection terminal 390 can be attached to the conductive pad CP of the redistribution substrate 300. The second connection terminal 390 can be a solder ball formed of one or more of tin, lead, and copper. The second connection terminal 390 can all have a thickness of about 40 μm to about 80 μm.

[0164] The packaging substrate 500 can be, for example, a printed circuit board, a flexible substrate, or a strip substrate. For example, the packaging substrate 500 can be a flexible printed circuit board, a rigid printed circuit board, or any combination thereof, each board including internal wiring 521 formed therein.

[0165] The package substrate 500 may have a top surface and a bottom surface opposite to each other, and may include an upper pad 511, an outer pad 513, and internal wiring 521. The upper pad 511 may be disposed on the top surface of the package substrate 500, and the outer pad 513 may be disposed on the bottom surface of the package substrate 500. The upper pad 511 may be electrically connected to the outer pad 513 via the internal wiring 521. An external bonding terminal 550 may be attached to the outer bonding pad 513. A ball grid array (BGA) may be provided as the external bonding terminal 550.

[0166] The thermal radiating structure 600 may include a thermally conductive material. The thermally conductive material may include a metallic material (e.g., copper and / or aluminum) or a carbon-containing material (e.g., graphene, graphite, and / or carbon nanotubes). The thermal radiating structure 600 may have a relatively high thermal conductivity. For example, a single metal layer or multiple stacked metal layers may be used as the thermal radiating structure 600. As another example, the thermal radiating structure 600 may include a heat sink or heat pipe. As yet another example, the thermal radiating structure 600 may be configured to use water cooling.

[0167] A thermally conductive layer 650 may be situated between the thermal radiating structure 600 and the first semiconductor chip 100 and the second semiconductor chip 200. The thermally conductive layer 650 may contact the top surface of the semiconductor package and the bottom surface of the thermal radiating structure 600. The thermally conductive layer 650 may include a thermal interface material (TIM). The thermal interface material may include, for example, a polymer and thermally conductive particles. The thermally conductive particles may be dispersed in the polymer. When the semiconductor package is in operation, heat generated from the semiconductor package can be transferred to the thermal radiating structure 600 through the thermally conductive layer 650.

[0168] According to some exemplary embodiments conceived in this invention, a redistribution substrate may include a first redistribution pattern and a second redistribution pattern located at different horizontal levels. When forming the first redistribution pattern with a linewidth greater than that of the second redistribution pattern, a planarization process can be omitted, thus reducing or preventing irregular thickness of the first redistribution pattern caused by recesses. The second redistribution pattern with a linewidth smaller than that of the first redistribution pattern can be formed in trenches formed by an anisotropic etching process, in which a hard mask pattern is used to anisotropically etch the dielectric layer, so that the metal pattern of the second redistribution pattern can have sidewalls covered by a blocking pattern. Therefore, due to the contact between the metal pattern and the dielectric layer, oxidation of the second redistribution pattern can be reduced or prevented. Thus, the redistribution substrate can increase integration density and reliability.

[0169] Although the inventive concept has been described with reference to some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor package, the semiconductor package comprising: A redistribution substrate, the redistribution substrate including a first redistribution pattern and a second redistribution pattern, wherein the bottom surfaces of the first redistribution pattern and the second redistribution pattern are at different distances from the bottom surface of the redistribution substrate in a vertical direction perpendicular to the bottom surface of the redistribution substrate; as well as A semiconductor chip, located on the redistribution substrate, includes a plurality of chip pads electrically connected to the first redistribution pattern and the second redistribution pattern. The first redistribution pattern includes: A first metal pattern, the first metal pattern being located on a first dielectric layer; and A first blocking pattern is located between the bottom surface of the first dielectric layer and the first metal pattern. The second redistribution pattern includes: A second metal pattern, the second metal pattern being in a second dielectric layer; and The second barrier pattern is located between the bottom surface of the second dielectric layer and the second metal pattern, and between the sidewalls of the second dielectric layer and the second metal pattern. The second dielectric layer is located on the first dielectric layer and directly contacts the sidewall of the first metal pattern. Wherein, the sidewall of the first metal pattern is not aligned with the sidewall of the first blocking pattern, such that the sidewall of the first metal pattern is offset relative to the sidewall of the first blocking pattern in a horizontal direction parallel to the bottom surface of the redistribution substrate. A portion of the second dielectric layer is located between the bottom surface of the first metal pattern and the top surface of the first dielectric layer.

2. The semiconductor package according to claim 1, wherein, The top surface of the second dielectric layer and the top surface of the second redistribution pattern are at the same distance from the bottom surface of the redistribution substrate in the vertical direction.

3. The semiconductor package according to claim 1, wherein, The first redistribution pattern has a first minimum width in a horizontal direction parallel to the bottom surface of the redistribution substrate. The second redistribution pattern has a second minimum width in the horizontal direction, and The second minimum width is smaller than the first minimum width.

4. The semiconductor package according to claim 1, wherein, The second redistribution pattern includes: The pathway portion penetrates a portion of the second dielectric layer; The pad portion is located in the second dielectric layer and is connected to the via portion; and The line portion is located in the second dielectric layer and extends away from the pad portion. Wherein, the pad portion has a first thickness in the vertical direction, and The line portion has a second thickness in the vertical direction, and the second thickness is smaller in size than the first thickness.

5. The semiconductor package according to claim 4, wherein, The top surface of the line portion and the top surface of the pad portion are equidistant from the bottom surface of the redistributed substrate in the vertical direction, and The bottom surface of the line portion and the bottom surface of the pad portion are at different distances from the bottom surface of the redistributed substrate in the vertical direction.

6. The semiconductor package according to claim 4, wherein, The second redistribution pattern has an arcuate edge located between the sidewall of the passage portion and the bottom surface of the pad portion.

7. The semiconductor package according to claim 1, wherein, The first metal pattern has linear sidewalls, and The second metal pattern has arc-shaped sidewalls.

8. The semiconductor package according to claim 1, wherein, The minimum width of the second metal pattern is located at either the top surface or the bottom surface of the second metal pattern; and The maximum width of the second metal pattern is at the horizontal height between the top surface and the bottom surface of the second metal pattern.

9. The semiconductor package according to claim 1, wherein, The second redistribution pattern includes: The pathway portion penetrates a portion of the second dielectric layer; The pad portion is located in the second dielectric layer and is connected to the via portion; and The line portion is located in the second dielectric layer and extends away from the pad portion. The line portion of the second redistribution pattern has a width of 0.5 μm to 2.5 μm.

10. A semiconductor package, the semiconductor package comprising: A redistribution substrate, the redistribution substrate comprising a plurality of first redistribution layers and a plurality of second redistribution layers, the plurality of first redistribution layers and the plurality of second redistribution layers being alternately stacked in a vertical direction perpendicular to the bottom surface of the redistribution substrate; as well as A semiconductor chip, located on the redistribution substrate, Each of the first redistribution layers includes: First dielectric layer; and A first redistribution pattern, comprising a first via portion and a first pad portion connected to the first via portion, the first via portion penetrating the first dielectric layer, and the first pad portion located on the top surface of the first dielectric layer. Each of the second redistribution layers includes: The second dielectric layer is located on the first dielectric layer of the underlying first redistribution layer, and The second redistribution pattern includes a second via portion and a second pad portion connected to the second via portion, the second via portion penetrating a portion of the second dielectric layer, and the second pad portion being within the second dielectric layer. The first redistribution pattern includes: A first metal pattern, the first metal pattern being located on the first dielectric layer; and A first barrier pattern is located between the bottom surface of the first dielectric layer and the first metal pattern. The second redistribution pattern includes: A second metal pattern, the second metal pattern being contained in the second dielectric layer; and The second barrier pattern is located between the bottom surface of the second dielectric layer and the second metal pattern, and between the sidewalls of the second dielectric layer and the second metal pattern. The second dielectric layer is located on the first dielectric layer and directly contacts the sidewall of the first metal pattern. Wherein, the sidewall of the first metal pattern is not aligned with the sidewall of the first blocking pattern, such that the sidewall of the first metal pattern is offset relative to the sidewall of the first blocking pattern in a horizontal direction parallel to the bottom surface of the redistribution substrate. A portion of the second dielectric layer is located between the bottom surface of the first metal pattern and the top surface of the first dielectric layer.

11. The semiconductor package of claim 10, wherein, The second dielectric layer also directly covers the sidewalls of the first blocking pattern of the first redistribution pattern, and The top surface of the second dielectric layer is coplanar with the top surface of the second redistribution pattern.

12. The semiconductor package of claim 10, wherein, The first pad portion of the first redistribution pattern has linear sidewalls, and The second pad portion of the second redistribution pattern has an arcuate sidewall.

13. The semiconductor package of claim 10, wherein, The second redistribution pattern also includes line portions extending in the second dielectric layer and away from the second pad portion, and The minimum width of the line portion of the second redistribution pattern is located at the top surface or the bottom surface of the line portion, and The maximum width of the line portion of the second redistribution pattern is at the horizontal height between the top surface and the bottom surface of the line portion.

14. The semiconductor package of claim 13, wherein, Both the second pad portion and the line portion have arc-shaped sidewalls.

15. The semiconductor package of claim 10, wherein, The second redistribution pattern also includes line portions extending in the second dielectric layer and away from the second pad portion. The top surface of the line portion of the second redistribution pattern and the top surface of the second pad portion of the second redistribution pattern are equidistant from the bottom surface of the redistribution substrate in the vertical direction, and The bottom surface of the line portion of the second redistribution pattern and the bottom surface of the second pad portion of the second redistribution pattern are at different distances from the bottom surface of the redistribution substrate in the vertical direction.

16. The semiconductor package of claim 10, wherein, The first redistribution pattern also includes a first line portion located on the top surface of the first dielectric layer and extending away from the first pad portion. The second redistribution pattern also includes a second line portion extending in the second dielectric layer and away from the second pad portion. The first line portion of the first redistribution pattern has a first minimum width. The second line portion of the second redistribution pattern has a second minimum width, and The second minimum width is smaller than the first minimum width.

17. A semiconductor package, the semiconductor package comprising: A lower redistribution substrate, the lower redistribution substrate including a first redistribution pattern on a first dielectric layer and a second redistribution pattern in a second dielectric layer, the second dielectric layer being located on the first dielectric layer; A first semiconductor chip, located on the lower redistribution substrate, includes a plurality of chip pads; A plurality of first connection terminals are located between the lower redistribution substrate and the plurality of chip pads of the first semiconductor chip; A molding layer is located on the lower redistribution substrate and covers the first semiconductor chip; as well as Multiple metal pillars are disposed around the first semiconductor chip, connected to the lower redistribution substrate, and penetrating the molding layer. Wherein, the second dielectric layer covers the sidewalls of the first redistribution pattern, and In this configuration, the top surface of the second dielectric layer is coplanar with the top surface of the second redistribution pattern. The first redistribution pattern includes: A first metal pattern, the first metal pattern being located on the first dielectric layer; and A first barrier pattern is located between the bottom surface of the first dielectric layer and the first metal pattern. The second redistribution pattern includes: A second metal pattern, the second metal pattern being contained in the second dielectric layer; and The second barrier pattern is located between the bottom surface of the second dielectric layer and the second metal pattern, and between the sidewalls of the second dielectric layer and the second metal pattern. The second dielectric layer is located on the first dielectric layer and directly contacts the sidewall of the first metal pattern. Wherein, the sidewall of the first metal pattern is not aligned with the sidewall of the first blocking pattern, such that the sidewall of the first metal pattern is offset relative to the sidewall of the first blocking pattern in a horizontal direction parallel to the bottom surface of the lower redistribution substrate. A portion of the second dielectric layer is located between the bottom surface of the first metal pattern and the top surface of the first dielectric layer.

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