Semiconductor packaging structure and manufacturing method

Abstract

The semiconductor packaging structure and manufacturing method disclosed herein involve bonding a second electronic component to a redistribution layer. First, the solder on the second electronic component is misaligned with the pads of the redistribution layer. Then, during the reflow process, the cohesive force of the solder brings the second electronic component closer to the first electronic component until the sidewall of the second electronic component adheres to the sidewall of the first electronic component. Therefore, there is no gap between the first and second electronic components, and there is no bottom filler between them. The gap is filled by the second electronic component with higher rigidity, thereby overcoming the fracture problem caused by thermal stress.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures and their manufacturing methods. Background Technology

[0002] In FOCoS (Fan Out Chip on Substrate) structures, the mismatch of CTE (Coefficient of Thermal Expansion) between various materials in the entire semiconductor package structure causes the underfill material beneath the chip gaps to be unable to release thermal stress during thermal cycling, resulting in cracking in the area beneath the chip gaps in the redistribution layer. If a reinforcing structure is added to the redistribution layer to block the cracking path, the stress will extend to the sidewalls of the reinforcing structure, causing delamination between the sidewalls of the reinforcing structure and the underfill material. Summary of the Invention

[0003] This disclosure provides a semiconductor packaging structure and a method for manufacturing the same.

[0004] In a first aspect, this disclosure provides a semiconductor packaging structure, including:

[0005] Rewire layer;

[0006] A first electronic component and a second electronic component are arranged side by side on the redistribution layer and electrically connected to the redistribution layer, with the sidewall of the first electronic component contacting the sidewall of the second electronic component.

[0007] In some alternative embodiments, the sidewall of the first electronic component or the sidewall of the second electronic component includes a buffer layer.

[0008] In some alternative implementations, it also includes:

[0009] A first filler is filled between the first electronic component, the second electronic component, and the redistribution layer.

[0010] In some alternative implementations, the rigidity of the buffer layer is greater than that of the first filler material.

[0011] In some alternative embodiments, a barrier layer is disposed between the buffer layer and the first electronic component / second electronic component.

[0012] In some alternative implementations, the second electronic component is electrically connected to the redistribution layer via a first interconnect structure.

[0013] In some alternative implementations, the first interconnect structure is a solder element.

[0014] In some alternative embodiments, the center of the upper surface of the first interconnect structure and the center of the lower surface of the first interconnect structure are located on different vertical planes.

[0015] In some alternative implementations, the side of the first interconnect structure is inclined relative to the upper surface of the redistribution layer.

[0016] In some optional embodiments, the first electronic component is an application-specific integrated circuit (ASIC) chip, and the second electronic component is a high-bandwidth memory chip; or

[0017] The second electronic component is a dedicated integrated circuit chip, and the first electronic component is a high-bandwidth memory chip.

[0018] In some alternative implementations, it also includes:

[0019] A molding layer covers the first electronic component and the second electronic component.

[0020] In some alternative implementations, it also includes:

[0021] The substrate, wherein the redistribution layer is disposed on the substrate.

[0022] In some alternative embodiments, the substrate has a recess.

[0023] In some alternative implementations, it also includes:

[0024] A bridging chip is placed within the recess, and the bridging chip is electrically connected to the first electronic component and the second electronic component.

[0025] In some alternative implementations, it also includes:

[0026] A second filler is used to fill the space between the recess and the bridging chip.

[0027] In some alternative implementations, the bridging chip includes a first bridging line.

[0028] In some alternative implementations, the bridging chip is electrically connected to the first electronic component and the second electronic component via the redistribution layer.

[0029] In some optional implementations, the redistribution layer further includes:

[0030] The second bridging line is located below the gap between the first electronic component and the second electronic component.

[0031] In some alternative implementations, the first electronic component is electrically connected to the redistribution layer via a second interconnect structure.

[0032] In some alternative implementations, the second interconnect structure is a pad, a conductive pillar, solder, or a wire.

[0033] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging structure, including:

[0034] Form a redistribution layer;

[0035] The first electronic component is bonded to the redistribution layer;

[0036] A second electronic component having a first interconnect structure is placed on the redistribution layer, and the pads of the first interconnect structure and the redistribution layer are in a non-aligned state, with the second electronic component arranged side by side with the first electronic component;

[0037] The reflow process aligns the second electronic component with the pads bonded to the redistribution layer and moves the second electronic component toward the first electronic component until the sidewall of the first electronic component contacts the sidewall of the second electronic component.

[0038] In some alternative implementations, prior to forming the redistribution layer, the following steps are also included:

[0039] Provide substrate; and

[0040] The formation of the redistribution layer includes:

[0041] The redistribution layer is formed on the substrate.

[0042] In some alternative implementations, the redistribution layer includes a second bridging line located below the gap between the first electronic component and the second electronic component.

[0043] In some alternative embodiments, after providing the substrate, the method further includes:

[0044] A recess is provided on the substrate;

[0045] A bridging chip is disposed within the recess, and the bridging chip includes a first bridging line.

[0046] The semiconductor packaging structure and manufacturing method disclosed herein involve bonding a second electronic component to a redistribution layer. First, the solder on the second electronic component is misaligned with the pads of the redistribution layer. Then, during the reflow process, the cohesive force of the solder brings the second electronic component closer to the first electronic component until the sidewall of the second electronic component adheres to the sidewall of the first electronic component. Therefore, there is no gap between the first and second electronic components, and there is no bottom filler between them. The gap is filled by the second electronic component with higher rigidity, thereby overcoming the fracture problem caused by thermal stress. Attached Figure Description

[0047] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0048] Figures 1 to 6 These are first to sixth structural schematic diagrams of semiconductor packaging structures according to embodiments of the present disclosure;

[0049] Figures 7 to 18 This is a schematic diagram of the manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure.

[0050] Symbol explanation:

[0051] 1-First electronic component, 2-Second electronic component, 3-Rewiring layer, 31-Second bridging line, 4-First filler, 5-Barrier layer, 6-First interconnect structure, 7-Molding layer, 8-Substrate, 81-Recess, 9-Bridging chip, 91-First bridging line, 92-Wafer, 921-Die, 93-Adhesive layer, 94-Insulating layer, 95-Seed layer, 10-Second filler, 11-Second interconnect structure, 12-External electrical connector, 13-Buffer layer. Detailed Implementation

[0052] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0053] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0054] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0055] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0056] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0057] Figure 1 This is a first structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor package structure includes a redistribution layer 3, a first electronic component 1, a second electronic component 2, a buffer layer 13, a first filler 4, and a substrate 8. The first electronic component 1 and the second electronic component 2 are arranged side-by-side on the redistribution layer 3 and are electrically connected to it. The sidewall of the first electronic component 1 can contact the sidewall of the second electronic component 2. The redistribution layer 3 can be disposed on the substrate 8. The sidewall of the first electronic component 1 or the sidewall of the second electronic component 2 may include the buffer layer 13.

[0058] In this embodiment, the first electronic component 1 can be electrically connected to the redistribution layer 3 via the second interconnect structure 11. The second electronic component 2 can be electrically connected to the redistribution layer 3 via the first interconnect structure 6. The first interconnect structure 6 can be a solder component. The side of the first interconnect structure 6 can be inclined relative to the upper surface of the redistribution layer 3. The center of the upper surface of the first interconnect structure 6 can be on a different vertical plane from the center of the lower surface of the first interconnect structure 6. The longitudinal cross-section of the first interconnect structure 6 can be a parallelogram. The above structural features of the first interconnect structure 6 can be formed by reflow soldering during the manufacturing process. In the manufacturing process, the first interconnect structure 6 of the second electronic component 2 is first misaligned with the pads of the redistribution layer 3 (relatively offset position). During the reflow soldering process, due to the cohesive force of the solder, the second electronic component 2 moves towards the first electronic component 1, and the first interconnect structure 6 deforms, presenting a shape inclined relative to the upper surface of the redistribution layer 3. In addition, the second interconnect structure 11 can also have the same structural features as the first interconnect structure 6 (see reference). Figure 3 ).

[0059] In this embodiment, the first filler 4 can be filled between the first electronic component 1, the second electronic component 2, and the redistribution layer 3. The first filler 4 can fill the gaps between the three components to improve the overall structural strength.

[0060] In this embodiment, the buffer layer 13 can cover the second electronic component 2, or vice versa; the buffer layer 13 can also cover the first electronic component 1, thereby protecting either the first electronic component 1 or the second electronic component 2. The buffer layer 13 can be made of non-metallic materials, such as organic and inorganic materials. Organic materials include polyimide (PI), epoxy resin, acrylic acid, molding compounds, etc., while inorganic materials include oxides (SiOx, SiNx, TaOx), glass, silicon, ceramics, etc. The rigidity of the buffer layer 13 can be greater than that of the first filler 4. The use of a highly rigid buffer layer 13 between the first electronic component 1 and the second electronic component 2 helps resist deformation and breakage.

[0061] In this embodiment, the external electrical connector 12 may be, for example, a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, or a microbump.

[0062] In this embodiment, the substrate 8 may contain fibers to improve the strength and support capacity of the substrate 8, thereby improving the stability of the entire structure.

[0063] In this embodiment, the second bridging line 31 in the redistribution layer 3 can be located below the gap between the first electronic component 1 and the second electronic component 2. The material of the second bridging line 31 in the redistribution layer 3 is, for example, copper (Cu), silver (Ag), gold (Au), aluminum (Al), nickel (Ni), titanium (Ti), or lead (Pb).

[0064] Figure 2 This is a second structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 1 The difference in the semiconductor packaging structures shown is that, Figure 2 The substrate 8 in the semiconductor package structure shown may have a recess 81 and may also include a bridging chip 9 disposed in the recess 81 and a second filler 10 filled between the recess 81 and the bridging chip 9.

[0065] In this embodiment, the recess 81 can be in the form of a through hole or blind hole of various shapes. The recess 81 can provide a space for accommodating the bridging chip 9, reducing the thickness of the entire structure. The second filler 10 can fill the gap between the recess 81 and the bridging chip 9, thereby enhancing the stability of the overall structure.

[0066] and Figure 1 The difference in the semiconductor packaging structures shown also lies in, Figure 2 The bridging chip 9 in the semiconductor package structure shown may include a first bridging line 91. The bridging chip 9 can be electrically connected to the first electronic component 1 and the second electronic component 2 through the redistribution layer 3. Figure 1 The semiconductor package structure shown incorporates bridging circuitry within the redistribution layer, while Figure 2 The semiconductor package structure shown incorporates bridging circuitry within the bridging chip.

[0067] Figure 3 This is a third structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 2 The difference in the semiconductor packaging structures shown is that, Figure 3The semiconductor package structure shown may further include a barrier layer 5. The barrier layer 5 may be disposed between the buffer layer 13 and the first electronic component 1 / second electronic component 2. The barrier layer 5 may be made of non-metallic materials, such as organic and inorganic materials. Organic materials include polyimide (PI), epoxy resin, acrylic acid, molding compounds, etc., while inorganic materials include oxides (SiOx, SiNx, TaOx), glass, silicon, ceramics, etc. The barrier layer 5 may be made of the same material as the buffer layer 13, or it may be made of a material with better rigidity than the buffer layer 13, thereby further improving its resistance to breakage. Furthermore, by designing the barrier layer 5, the displacement distance of the second electronic component 2 during reflow soldering can be better controlled and compensated. When the second electronic component 2 is attached to the barrier layer 5, gaps between the first electronic component 1 and the second electronic component 2 can be avoided.

[0068] Figure 4 This is a fourth structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 5 This is a fifth structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 2 , Figure 4 as well as Figure 5 Different implementations of the second interconnect structure 11 are shown. Figure 2 The second interconnect structure 11 in the semiconductor package structure shown can be a conductive pillar and a solder element. Figure 4 The second interconnect structure 11 in the semiconductor package structure shown can be a pad and a solder element. Figure 5 The second interconnect structure 11 in the semiconductor package structure shown can be a wire, that is, the second electronic component 2 is bonded to the redistribution layer 3 by wire bonding.

[0069] Figure 6 This is a sixth structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 2 The difference in the semiconductor packaging structures shown is that, Figure 6The semiconductor package structure shown may further include a molding layer 7. The molding layer 7 can encapsulate the first electronic component 1 and the second electronic component 2. The molding material used in the molding layer 7 may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc. The molding layer 7 serves to fix the first electronic component 1 and the second electronic component 2.

[0070] Figures 7 to 18 This is a schematic diagram of the manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure.

[0071] Please refer to Figure 7 A wafer 92 is provided, an adhesive layer 93 is provided on one side of the wafer 92, and an insulating layer 94, a seed layer 95 and a first bridging line 91 are sequentially provided on the other side of the wafer 92.

[0072] Here, the adhesive layer 93 can be a die-attach film (DAF).

[0073] Please refer to Figure 8 The wafer 92 is then cut.

[0074] Please refer to Figure 9 Multiple dies 921 are formed, resulting in multiple bridge chips 9.

[0075] Please refer to Figure 10 A substrate 8 is provided. A recess 81 is formed in the substrate 8.

[0076] Here, the recess 81 can be formed by processes such as laser or etching.

[0077] Please refer to Figure 11 Pick up Figure 9 The bridging chip 9 is placed in the recess 81 of the substrate 8.

[0078] Please refer to Figure 12 The second filler 10 is filled between the recess 81 and the bridging chip 9.

[0079] Please refer to Figure 13 A redistribution layer 3 is formed on substrate 8.

[0080] The redistribution layer 3 can be formed using currently known or future-developed redistribution layer 3 technologies. This disclosure does not specifically limit the technology used. For example, redistribution layer 3 can be formed using methods including but not limited to photolithography, electroplating, and electroless plating.

[0081] Please refer to Figure 14 The first electronic component 1 is soldered to the redistribution layer 3. Specifically, it can be soldered to the redistribution layer 3 via the second interconnection structure 11 on the first electronic component 1.

[0082] Please refer to Figure 15 The second electronic component 2, which has the first interconnect structure 6, is placed above the redistribution layer 3, and the pads of the first interconnect structure 6 and the redistribution layer 3 are misaligned. The second electronic component 2 and the first electronic component 1 can be arranged side by side.

[0083] Please refer to Figure 16 The process involves reflow soldering to align the second electronic component 2 with the pads on the redistribution layer 3, and moving the second electronic component 2 closer to the first electronic component 1 until the sidewall of the first electronic component 1 contacts the sidewall of the second electronic component 2. This yields a semiconductor package structure.

[0084] Please refer to Figure 17 The first filler material 4 is filled between the first electronic component 1, the second electronic component 2 and the redistribution layer 3.

[0085] Please refer to Figure 18 This yields a semiconductor packaging structure.

[0086] The semiconductor packaging structure and manufacturing method disclosed herein, in the process of bonding the second electronic component 2 to the redistribution layer 3, firstly, the solder on the second electronic component 2 is misaligned with the pads of the redistribution layer 3. Then, during the reflow process, due to the cohesive force of the solder, the second electronic component 2 is brought close to the first electronic component 1 until the sidewall of the second electronic component 2 is attached to the sidewall of the first electronic component 1. Therefore, there is no gap between the first electronic component 1 and the second electronic component 2, and there is no bottom filler between them. The gap between them is replaced by the second electronic component 2 with higher rigidity, thereby overcoming the fracture problem caused by thermal stress.

[0087] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A method for manufacturing a semiconductor package structure, comprising multiple steps: Step 1: Provide a wafer, set an adhesive layer on one side of the wafer, and set an insulating layer, a seed layer and a first bridging circuit on the other side of the wafer in sequence; Step 2: The wafer is cut into multiple dies to obtain multiple bridging chips; Step 3: Provide a substrate, form a recess in the substrate, pick up the bridging chip, place it in the recess of the substrate, and fill the space between the recess and the bridging chip with a second filler. Step 4: Form a redistribution layer on the substrate, and solder the first electronic component to the redistribution layer. The second electronic component having the first interconnect structure is placed above the redistribution layer. And make the first interconnect structure and the pads of the redistribution layer misaligned; Step 5: Reflow soldering to align the second electronic component with the pads on the redistribution layer, and Move the second electronic component toward the first electronic component until the sidewall of the first electronic component contacts the sidewall of the second electronic component; as well as Step 6: Fill the space between the first electronic component, the second electronic component, and the redistribution layer with the first filler material to obtain a semiconductor package structure.

2. The method for manufacturing a semiconductor packaging structure according to claim 1, wherein, The second electronic component is arranged side by side with the first electronic component.

3. The method for manufacturing a semiconductor packaging structure according to claim 1, wherein, The adhesive layer is a die-attach film (DAF).

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