Integrated circuit devices including metal wiring and methods for forming the same

Abstract

An integrated circuit device and a method for forming the same are provided. The integrated circuit device may include a first insulating layer and a plurality of metal wirings on the first insulating layer. The plurality of metal wirings may include a first metal wiring and a second metal wiring. The first metal wiring includes a first upper surface and a first lower surface facing the first insulating layer. The second metal wiring includes a second upper surface and a second lower surface facing the first insulating layer and coplanar with the first lower surface. The first metal wiring may have a first width that monotonically decreases from the first lower surface to the first upper surface, and the second metal wiring may have a second width that monotonically increases from the second lower surface to the second upper surface.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 062,690, filed August 7, 2020, with the USPTO, entitled “Hybrid Metallization with Subtractive and Damascene Processes,” and U.S. Non-Provisional Application No. 17 / 066,526, filed October 9, 2020, with the USPTO, entitled “Integrated Circuit Devices Including Metal Wires and Methods of Forming the Same,” the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates generally to the field of electronics, and more specifically to integrated circuit devices. Background Technology

[0003] As the size of metal wiring in integrated circuit devices decreases, it may become difficult to form metal wiring with low resistance and structural stability. Summary of the Invention

[0004] According to some embodiments of the present invention, an integrated circuit device may include: a first insulating layer; and a plurality of metal wirings located on the first insulating layer. The plurality of metal wirings may include: a first metal wiring including a first upper surface and a first lower surface facing the first insulating layer; and a second metal wiring including a second upper surface and a second lower surface facing the first insulating layer and coplanar with the first lower surface. The first metal wiring may have a first width that monotonically decreases from the first lower surface to the first upper surface, and the second metal wiring may have a second width that monotonically increases from the second lower surface to the second upper surface.

[0005] According to some embodiments of the present invention, an integrated circuit device may include: a first insulating layer and a second insulating layer stacked sequentially; a bottom etch stop layer extending between the first insulating layer and the second insulating layer; and a plurality of metal wirings located on the first insulating layer and within the second insulating layer. The plurality of metal wirings may include the first metal wirings and the second metal wirings. The bottom etch stop layer may extend from the lower surface to the upper surface of the first metal wirings on the sidewalls of the first metal wirings, and the second metal wirings may extend through the bottom etch stop layer.

[0006] According to some embodiments of the present invention, an integrated circuit device may include: an insulating layer; and a plurality of metal wirings located on the insulating layer. Each of the plurality of metal wirings may include a lower surface that contacts an upper surface of the insulating layer. The plurality of metal wirings may include a first metal wiring and a second metal wiring. The second metal wiring may include a first metal element, and the first metal wiring may lack the first metal element.

[0007] According to some embodiments of the present invention, a method of forming an integrated circuit device may include: forming a first metal wiring on a first insulating layer; forming a second insulating layer on the first metal wiring and the first insulating layer; forming an opening extending through the second insulating layer; and forming a second metal wiring in the opening. The first metal wiring has a first lower surface facing the first insulating layer, and the second metal wiring has a second lower surface facing the first insulating layer and coplanar with the first lower surface. Attached Figure Description

[0008] Figure 1A It is based on some embodiments of the inventive concept along Figure 1B A cross-sectional view of an integrated circuit device taken by line A-A'. Figure 1B These are some embodiments based on the inventive concept. Figure 1A A schematic layout of integrated circuit devices.

[0009] Figure 2A It is based on some embodiments of the inventive concept along Figure 2B A cross-sectional view of an integrated circuit device taken by line B-B'. Figure 2B These are some embodiments based on the inventive concept. Figure 2A A schematic layout of integrated circuit devices.

[0010] Figure 3 and Figure 4 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0011] Figures 5 to 8 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0012] Figures 9 to 13 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept. Detailed Implementation

[0013] When metal wiring at the same level includes both narrow and wide wiring, it may be difficult to form both with low resistance and structural stability using the same process. If a damascene process is used to form the narrow and wide wiring, the narrow wiring may shift during the process, potentially leading to defects. If an etching process is used to form the narrow and wide wiring, the number of metal layers included in both the narrow and wide wiring may be limited, and the wide wiring may have high resistance.

[0014] According to some embodiments of the present invention, two separate processes can be used to form narrow and wide wirings at the same level. In some embodiments, narrow wirings can be formed by an etching process, and wide wirings can be formed by a damascene process.

[0015] Figure 1A It is based on some embodiments of the inventive concept along Figure 1B A cross-sectional view of an integrated circuit device taken by line A-A'. Figure 1B These are some embodiments based on the inventive concept. Figure 1A A schematic layout of integrated circuit devices.

[0016] Reference Figure 1A and Figure 1B The integrated circuit device may include an upper wiring 460 and a lower wiring including a first metal wiring 210 and a second metal wiring 310. The first metal wiring 210 and the second metal wiring 310 may be spaced apart from each other in a first direction D1. A plurality of first metal wirings 210 (e.g., four first metal wirings 210) may be disposed between two second metal wirings 310. Each of the first metal wirings 210 and the second metal wiring 310 may extend in a second direction D2. The second direction D2 may be perpendicular to the first direction D1. As used herein, "element A extends in direction X" (or similar language) may mean that element A extends longitudinally in direction X. The first direction D1 and the second direction D2 may be a first horizontal direction and a second horizontal direction, respectively.

[0017] The widest width of the first metal wiring 210 in the first direction D1 can be narrower than the widest width of the second metal wiring 310 in the first direction D1. For example, the spacing P of the first metal wiring 210 can be approximately 24 nm.

[0018] The lower wirings 210 and 310 and the upper wiring 460 can be stacked on a third direction D3. The third direction D3 can be perpendicular to both the first direction D1 and the second direction D2. The third direction D3 can be vertical. The upper wiring 460 can extend along the first direction D1. Although... Figure 1A A single top wiring 460 is shown, but multiple top wirings 460 can be configured.

[0019] Each of the first metal wirings 210 can be electrically connected to a component of the transistor (e.g., source / drain region or gate). Each of the second metal wirings 310 can be electrically connected to a power supply (e.g., Vdd or Vss) of the integrated circuit device. The upper wiring 460 can be electrically connected to at least one of the first metal wirings 210 and the second metal wirings 310.

[0020] Reference Figure 1A The integrated circuit device may include a first insulating layer 190, a second insulating layer 290, and a third insulating layer 390 stacked sequentially. Each of the first insulating layer 190, the second insulating layer 290, and the third insulating layer 390 may include an insulating material (e.g., silicon oxide or a low-dielectric material). Lower contacts 160 may be disposed in the first insulating layer 190. Each of the lower contacts 160 may include a conductive material and may electrically connect one of the first metal wirings 210 or one of the second metal wirings 310 to an element of the integrated circuit device.

[0021] The first metallic wiring 210 and the second metallic wiring 310 may be disposed on the first insulating layer 190 and within the second insulating layer 290. Each of the lower wirings includes contact with the lower surface of the first insulating layer 190.

[0022] In some embodiments, the lower surface 210L of the first metal wiring 210 may be coplanar with the lower surface 310L of the second metal wiring 310, such as... Figure 1A As shown in the diagram, the first metal wiring 210 may have a first width that monotonically decreases from its lower surface 210L to its upper surface 210U in the first direction D1. The second metal wiring 310 may have a second width that monotonically increases from its lower surface 310L to its upper surface 310U in the first direction D1. The first width of the lower surface 210L of the first metal wiring 210 may be narrower than the second width of the upper surface 310U of the second metal wiring 310.

[0023] although Figure 1A The first metal wiring 210 and the second metal wiring 310 are shown to have inclined sidewalls, but in some embodiments, at least some of the first metal wiring 210 and the second metal wiring 310 may have vertical sidewalls and may have a uniform width in the first direction D1 along the third direction D3.

[0024] In some embodiments, the upper surface 210U of the first metal wiring 210 may be farther away from the first insulating layer 190 than the upper surface 310U of the second metal wiring 310, such as... Figure 1A As shown in the figure. In some embodiments, the upper surface 210U of the first metal wiring 210 may be coplanar with the upper surface 310U of the second metal wiring 310.

[0025] The first metallic wiring 210 may include a first adhesive layer 220 and a first metallic layer 260 sequentially stacked. The first adhesive layer 220 may include, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiO), titanium (Ti), and / or tantalum (Ta). The first metallic layer 260 may include, for example, ruthenium (Ru), molybdenum (Mo), cobalt (Co), and / or tungsten (W). As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0026] The second metal wiring 310 may include a second adhesive layer 320, a first thin metal layer 340, and a second metal layer 360. The second adhesive layer 320 may include, for example, TiN, TaN, TiO, Ti, and / or Ta. The first thin metal layer 340 may include, for example, Ru, Mo, Co, and / or W. The second metal layer 360 may include, for example, copper (Cu). In some embodiments, both the first metal layer 260 and the first thin metal layer 340 may include the same metal element (e.g., Ru). In some embodiments, the first metal layer 260 may not include the metal element contained in the second metal layer 360. In some embodiments, the first metal layer 260 may lack the metal element contained in the second metal layer 360.

[0027] A first etch stop layer 270 may extend between a first insulating layer 190 and a second insulating layer 290. The first etch stop layer 270 may contact both the first insulating layer 190 and the second insulating layer 290. The first etch stop layer 270 may have a uniform thickness, such as... Figure 1A As shown in the diagram. The first etch stop layer 270 may extend on the sidewall of the first metal wiring 210. In some embodiments, the first etch stop layer 270 may contact the entire sidewall of the first metal wiring 210, such as... Figure 1A As shown in the diagram. The second metal wiring 310 can extend through the first etch stop layer 270 and can contact the first insulating layer 190, as... Figure 1A As shown in the image.

[0028] The second etch stop layer 370 may extend over the first metal wiring 210 and the second metal wiring 310. The second etch stop layer 370 may extend between the second insulating layer 290 and the third insulating layer 390. The lower surface of the second etch stop layer 370 may contact the upper surface 210U of the first metal wiring 210. The upper surface 310U of the second metal wiring 310 may not be higher than the lower surface of the second etch stop layer 370. In some embodiments, the upper surface 310U of the second metal wiring 310 may contact the lower surface of the second etch stop layer 370, such as... Figure 1A As shown in the image.

[0029] Each of the first etch stop layer 270 and the second etch stop layer 370 may include, for example, silicon carbon nitride (SiCN), aluminum oxide (AlO), and / or aluminum nitride (AlN). In some embodiments, the first etch stop layer 270 and / or the second etch stop layer 370 may be a SiCN layer.

[0030] The upper wiring 460 may include contact portions 460c and pad portions 460w. Each of the contact portions 460c may contact one of the first metal wirings 210 or one of the second metal wirings 310. The upper wiring 460 may include, for example, Cu. Although Figure 1A The upper wiring 460 is shown to include three contacts 460c, but the upper wiring 460 may include a single contact 460c, two contacts 460c, or more than three contacts 460c.

[0031] The third adhesive layer 420 and the second thin metal layer 440 may be disposed between the upper wiring 460 and the third insulating layer 390. The third adhesive layer 420 may include, for example, TiN, TaN, TiO, Ti and / or Ta. The second thin metal layer 440 may include, for example, Ru, Mo, Co and / or W.

[0032] Figure 2A It is based on some embodiments of the inventive concept along Figure 2B A cross-sectional view of an integrated circuit device taken by line B-B'. Figure 2B These are some embodiments based on the inventive concept. Figure 2A A schematic layout of integrated circuit devices.

[0033] The first metal wiring 210 may include a high first metal wiring 210', which may have a distance from the upper surface 210'U of the remaining first metal wiring 210 to the upper surface 210'U of the first insulating layer 190, and may include a contact portion 260c disposed above the upper surface 210U of the remaining first metal wiring 210. The high first metal wiring 210' may include a high first metal layer 260'. The high first metal layer 260' may include the contact portion 260c. The upper surface 210'U of the high first metal wiring 210' may contact the lower surface of the upper etch stop layer 370.

[0034] In some embodiments, the upper surface 310U of the second metal wiring 310 may be closer to the first insulating layer 190 than the upper surface 210'U of the first metal wiring 210', such as... Figure 2A As shown in the image.

[0035] Figure 3 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept. Figures 5 to 8This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0036] Reference Figure 3 and Figure 5 The method may include forming a first metallic wiring 210 (frame 120) on a first insulating layer 190, which may include a lower contact 160. The first metallic wiring 210 may be formed by depositing a first adhesive layer 220 and a first metal layer 260 and then patterning the first adhesive layer 220 and the first metal layer 260. Each of the first adhesive layer 220 and the first metal layer 260 may be formed by, for example, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or plating processes (e.g., electroplating). The first adhesive layer 220 and the first metal layer 260 may be patterned by an etching process (e.g., dry etching or wet etching).

[0037] The first metallic wiring 210 may include a lower surface 210L facing and / or contacting the first insulating layer 190 and an upper surface 210U opposite to the lower surface 210L. The lower surface 210L of the first metallic wiring 210 may contact the lower contact 160 and may be electrically connected to the lower contact 160.

[0038] Reference Figure 3 and Figure 6 A second insulating layer 290 (frame 140) can be formed on the first metal wiring 210 and the first insulating layer 190. In some embodiments, a bottom etch stop layer 270 can be formed prior to the formation of the second insulating layer 290. The bottom etch stop layer 270 can be conformally formed on the underlying elements (e.g., the first metal wiring 210 and the first insulating layer 190) and can have a uniform thickness, such as... Figure 6 As shown in the figure. The second insulating layer 290 may include, for example, a flowable low dielectric material (e.g., SiCOH) and may be formed by a coating process (e.g., spin coating).

[0039] An opening 290o may be formed in the second insulating layer 290 and the lower etch stop layer 270. Each of the openings 290o may extend through the second insulating layer 290 and the lower etch stop layer 270. The opening 290o may expose the upper surface of the lower contact 160. The second insulating layer 290 may be formed to overlap with the upper surface 210U of the first metal wiring 210.

[0040] Reference Figure 3 and Figure 7 The second metal wiring 310 (frame 160) can be formed in the second insulating layer 290 (specifically, in the opening 290°). The second metal wiring 310 can be formed by, for example, an inlay process.

[0041] In some embodiments, a second adhesive layer 320 and a first thin metal layer 340 may be sequentially formed on the second insulating layer 290. Each of the second adhesive layer 320 and the first thin metal layer 340 may be conformally formed on the underlying element and may have a uniform thickness in the opening 290°, such as... Figure 7 As shown in the diagram. Subsequently, a second metal layer 360 can be formed on the first thin metal layer 340. Each of the second adhesive layer 320, the first thin metal layer 340, and the second metal layer 360 can be formed by, for example, PVD, ALD, CVD, and / or plating processes. After the second metal layer 360 is formed, a planarization process (e.g., chemical mechanical polishing (CMP) or etching) can be performed until the upper surface of the second insulating layer 290 is exposed.

[0042] Reference Figure 8 A first etching process can be performed to remove a portion of the second insulating layer 290 and a portion of the lower etch stop layer 270. The first etching process can be performed until the upper surface 210U of the first metal wiring 210 is exposed. A second etching process can be performed to remove a portion of the second metal wiring 310. The second etching process can be performed until the upper surface 310U of the second metal wiring 310 is recessed relative to the upper surface 210U of the first metal wiring 210 toward the first insulating layer 190. The first and second etching processes can be performed sequentially or simultaneously.

[0043] After performing the first and second etching processes, an upper etch stop layer 370 can be formed on the first metal wiring 210, the second metal wiring 310, and the second insulating layer 290. The upper etch stop layer 370 can be conformally formed on the underlying components and can have a uniform thickness, such as... Figure 8 As shown in the image.

[0044] Reference Figure 1A and Figure 3 A third insulating layer 390 and an upper wiring 460 (frame 180) can be formed on the first metal wiring 210 and the second metal wiring 310. The upper wiring 460 can be formed by, for example, a damascene process or an etching process.

[0045] Figure 4 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept. Figures 9 to 13 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0046] Reference Figure 4 and Figure 9The method may include forming a high first metal wiring 210' (frame 120') on a first insulating layer 190, and then forming a mask layer 265 covering at least one of the high first metal wirings 210'. This can be achieved by referring to... Figure 5 The process for forming the first metal wiring 210 discussed is similar to the process for forming the high first metal wiring 210'. The mask layer 265 may comprise different materials than the first metal layer 260 and the first adhesive layer 220 to have etch selectivity relative to the first metal layer 260 and the first adhesive layer 220. The mask layer 265 may comprise, for example, TiN or a metal oxide.

[0047] Reference Figure 4 and Figure 10 The upper portion (frame 130) of the first metal wiring 210' not covered by the mask layer 265 can be removed to form the first metal wiring 210. The upper portion of the first metal wiring 210' can be removed by a dry etching process and / or a wet etching process.

[0048] Reference Figure 4 and Figure 11 The mask layer 265 can be removed, and then a lower etch stop layer 270 and a second insulating layer 290 (frame 140') can be sequentially formed on the first metal wiring 210 and the high first metal wiring 210'. An opening 290o can be formed in the second insulating layer 290 and the lower etch stop layer 270. Each of the openings 290o can extend through the second insulating layer 290 and the lower etch stop layer 270.

[0049] Reference Figure 3 and Figure 12 It can be compared with the reference Figure 7 The process for forming the second metal wiring 310 discussed is similar to that for forming the second metal wiring 310 in the opening 290°.

[0050] Reference Figure 13 It can be executed and referenced. Figure 8 The processes discussed are similar. A first etching process can be performed to remove a portion of the second insulating layer 290 and a portion of the lower etch stop layer 270. The first etching process can be performed until the upper surface 210'U of the higher first metal wiring 210' is exposed. A second etching process can be performed to remove a portion of the second metal wiring 310. The second etching process can be performed until the upper surface 310U of the second metal wiring 310 becomes closer to the first insulating layer 190 than the upper surface 210'U of the higher first metal wiring 210'. The first and second etching processes can be performed sequentially or simultaneously.

[0051] After performing the first and second etching processes, an upper etch stop layer 370 can be formed on the first metal wiring 210, the second metal wiring 310, and the second insulating layer 290. The upper etch stop layer 370 can be conformally formed on the underlying components and can have a uniform thickness, such as... Figure 13 As shown in the image.

[0052] Reference Figure 2A and Figure 3 An upper wiring 460 (frame 180) can be formed on the first metal wiring 210 and the second metal wiring 310. The upper wiring 460 can be formed by, for example, a damascene process or an etching process.

[0053] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of this disclosure, and therefore the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0054] Example embodiments of the inventive concept are described herein with reference to sectional or plan views of idealized embodiments and intermediate structures as exemplary embodiments. Thus, variations in the illustrated shape are expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the example embodiments of the inventive concept should not be construed as limited to the specific shapes shown herein, but rather include, for example, shape deviations caused by manufacturing processes.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0056] It should be noted that in some alternative embodiments, the functions / actions indicated in the flowchart boxes herein may not occur in the order shown in the flowchart. For example, depending on the functions / actions involved, two consecutively shown boxes may actually be executed substantially simultaneously, or sometimes the boxes may be executed in reverse order. Furthermore, the function of a given box in the flowchart and / or block diagram may be divided into multiple boxes, and / or the functions of two or more boxes in the flowchart and / or block diagram may be integrated at least partially. Finally, without departing from the scope of the inventive concept, other boxes may be added / inserted between the shown boxes, and / or boxes / operations may be omitted.

[0057] The subject matter disclosed above is intended to be illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of the inventive concept. Therefore, to the maximum extent permitted by law, the scope will be determined by the broadest permissible interpretation of the claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

Claims

1. An integrated circuit device comprising: a first insulating layer; and a plurality of metal wires on the first insulating layer, wherein the plurality of metal wires comprises: a first metal wire comprising a first upper surface and a first lower surface facing the first insulating layer, the first metal wire having a first width monotonically decreasing from the first lower surface to the first upper surface; and a second metal wire comprising a second upper surface and a second lower surface facing the first insulating layer and coplanar with the first lower surface, the second metal wire having a second width monotonically increasing from the second lower surface to the second upper surface, wherein the integrated circuit device further comprises: a second insulating layer on the first insulating layer; and a lower etch stop layer extending between the first insulating layer and the second insulating layer and extending on sidewalls of the first metal wire, wherein the second metal wire extends through the lower etch stop layer.

2. The integrated circuit device of claim 1, wherein, The first width of the first lower surface of the first metal wire is smaller than the second width of the second upper surface of the second metal wire.

3. The integrated circuit device of claim 1, wherein, The first metal wire comprises a plurality of first metal wires spaced apart from each other in a first direction, and the second metal wire comprises two second metal wires spaced apart from each other in the first direction, and the plurality of first metal wires are between the two second metal wires.

4. The integrated circuit device of any one of claims 1-3, wherein, The second metal wire comprises a first metal element, and the first metal wire lacks the first metal element.

5. The integrated circuit device of claim 4, wherein, Both the first metal wire and the second metal wire comprise a second metal element.

6. The integrated circuit device of claim 5, wherein, The second metal element is ruthenium, molybdenum, cobalt, or tungsten.

7. The integrated circuit device of claim 5, wherein, The second metal wire comprises a first metal layer and a second metal layer, the first metal layer comprises the first metal element, the second metal layer comprises the second metal element, and the second metal layer extends from a lower surface of the first metal layer to sidewalls of the first metal layer.

8. The integrated circuit device of claim 4, wherein, The first metal element is copper.

9. The integrated circuit device of claim 1, further comprising: an upper etch stop layer on the first metal wire, wherein the upper etch stop layer comprises a lower surface contacting the first upper surface of the first metal wire, and the second upper surface of the second metal wire is not higher than the lower surface of the upper etch stop layer.

10. An integrated circuit device comprising: a first insulating layer and a second insulating layer stacked in sequence; a lower etch stop layer extending between the first insulating layer and the second insulating layer; a plurality of metal wires on the first insulating layer and in the second insulating layer, the plurality of metal wires comprising a first metal wire and a second metal wire; and an upper etch stop layer on the first metal wire, wherein the lower etch stop layer extends on sidewalls of the first metal wire from a lower surface of the first metal wire to an upper surface of the first metal wire, and the second metal wire extends through the lower etch stop layer, wherein the upper etch stop layer comprises a lower surface contacting the upper surface of the first metal wire, and an upper surface of the second metal wire is not higher than the lower surface of the upper etch stop layer. The lower surface of the first metal wire is coplanar with the lower surface of the second metal wire.

11. The integrated circuit device of claim 10, wherein, The second metal wire comprises a first metal element, and the first metal wire lacks the first metal element.

12. The integrated circuit device of any one of claims 10-11, wherein, Both the first metal wire and the second metal wire comprise a second metal element.

13. The integrated circuit device of claim 12, wherein, The second metal element is ruthenium, molybdenum, cobalt, or tungsten.

14. A method of forming an integrated circuit device, the method comprising: forming a first metal line on a first insulating layer, the first metal line including a first lower surface facing the first insulating layer; forming a lower etch stop layer on the first metal line and the first insulating layer; forming a second insulating layer on the first metal line and the first insulating layer, wherein the first metal line is located in the second insulating layer; forming an opening extending through the second insulating layer and the lower etch stop layer; and forming a second metal line in the opening, the second metal line including a second lower surface facing the first insulating layer and co-planar with the first lower surface, removing a portion of the second insulating layer and a portion of the lower etch stop layer to expose an upper surface of the first metal line; forming an upper etch stop layer on the first metal line, the second metal line, and the second insulating layer.

15. The method of claim 14, wherein, The step of forming the first metal line includes: forming a first metal layer on the first insulating layer; and etching the first metal layer to form the first metal line.

16. The method of any one of claims 14 and 15, wherein, The step of forming the second metal line includes: forming a second metal layer on an upper surface of the second insulating layer and in the opening; and removing the second metal layer until the upper surface of the second insulating layer is exposed, wherein a first width of the first lower surface of the first metal line is less than a second width of the second upper surface of the second metal line.

17. The method of claim 16, wherein, The second metal layer includes a first metal element, and the first metal line lacks the first metal element.

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