Semiconductor chip module

Abstract

A semiconductor chip module includes a PCB including a first face and a second face; a buffer on the first face; a first chip on the first face and including a first connection terminal and a second connection terminal, the first connection terminal being provided with a first signal and the second connection terminal being provided with a second signal; and a second chip on the second face and including a third connection terminal provided with the first signal and a fourth connection terminal provided with the second signal. The first connection terminal and the third connection terminal can simultaneously receive the first signal from the buffer. The first connection terminal can be closer to the buffer than the second connection terminal. The third connection terminal can be closer to the buffer than the fourth connection terminal.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0098372, entitled "Semiconductor Chip Module", filed on August 6, 2020 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiment relates to a semiconductor chip module. Background Technology

[0004] In the memory module, the buffer can receive signals provided by the external host and can be re-driven using the left / right channels. Summary of the Invention

[0005] This embodiment relates to a semiconductor chip module, comprising: a printed circuit board (PCB) including a first side and a second side facing each other; a buffer on the first side of the PCB; a first chip on the first side of the PCB, including a first connection terminal and a second connection terminal, providing a first signal to the first connection terminal and providing a second signal different from the first signal to the second connection terminal; and a second chip on the second side of the PCB, including a third connection terminal provided with the first signal and a fourth connection terminal provided with the second signal. The first connection terminal of the first chip and the third connection terminal of the second chip can simultaneously receive the first signal from the buffer. The first connection terminal can be disposed closer to the buffer than the second connection terminal. The third connection terminal can be disposed closer to the buffer than the fourth connection terminal.

[0006] The embodiment also relates to a semiconductor chip module including a printed circuit board (PCB) having a first side and a second side facing each other. The semiconductor chip module includes: a first chip on the first side of the PCB, including a first connection terminal for receiving a first signal; a second chip on the second side of the PCB, including a second connection terminal for receiving the first signal; and a buffer including a first pin electrically connected to the first connection terminal and a second pin electrically connected to the second connection terminal. The PCB may include: a first wiring structure connecting the first connection terminal and the first pin, and a second wiring structure connecting the second connection terminal and the second pin. Based on a viewpoint observing the PCB in a plane, the first wiring structure and the second wiring structure may be symmetrically arranged based on a centerline extending between the first chip and the second chip. No mirroring operation is performed on the first chip and the second chip.

[0007] The embodiment also relates to a semiconductor chip module, comprising: a printed circuit board (PCB) including a first side and a second side facing each other; a buffer on the first side of the PCB; a plurality of first memory chips on the first side of the PCB, each first memory chip including a first connection terminal provided with a first signal and performing a first operation in response to the first signal and a first chip select signal; a plurality of second memory chips on the second side of the PCB, each second memory chip including a second connection terminal provided with a first signal and performing the first operation in response to the first signal and the first chip select signal; a plurality of third memory chips on the first side of the PCB, each third memory chip including a third connection terminal provided with a second signal and performing a second operation in response to the second signal and the second chip select signal; and a plurality of fourth memory chips on the second side of the PCB, each fourth memory chip including a fourth connection terminal provided with a second signal and performing the second operation in response to the second signal and the second chip select signal. The first connection terminals of the plurality of first memory chips and the second connection terminals of the plurality of second memory chips can simultaneously receive the first signal from the buffer. The third connection terminals of the plurality of third memory chips and the fourth connection terminals of the plurality of fourth memory chips can simultaneously receive the second signal from the buffer. Attached Figure Description

[0008] The features will become clear to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating an electronic system according to some example embodiments;

[0010] Figure 2 This is a block diagram illustrating a memory system according to some example embodiments;

[0011] Figure 3 This is a perspective view showing a portion of a memory system according to some example embodiments;

[0012] Figure 4 It is used for explanation Figure 3 A diagram of one side of the memory module shown;

[0013] Figure 5 This is a perspective view used to illustrate a semiconductor chip according to some example embodiments;

[0014] Figure 6 This is a simplified plan view of the lower surface of a semiconductor chip according to some example embodiments;

[0015] Figure 7 This means being assigned to Figure 6A diagram illustrating an example of signals at the connection terminals (solder balls) of a semiconductor chip;

[0016] Figure 8 This means being assigned to Figure 6 A diagram illustrating an example of signals at the connection terminals (solder balls) of a semiconductor chip;

[0017] Figure 9 It is along Figure 3 A cross-sectional view taken from line A-A';

[0018] Figure 10 It is used to explain in Figure 3 A diagram of the wiring structure included in the PCB in region R1;

[0019] Figure 11 This is a diagram used to illustrate a memory module in some other example embodiments;

[0020] Figure 12 This is a diagram used to illustrate a memory module in some other example embodiments;

[0021] Figure 13 It is along Figure 12 A cross-sectional view taken from line B-B';

[0022] Figure 14 This is a diagram used to illustrate a memory module in some other example embodiments;

[0023] Figure 15 It is along Figure 14 A cross-sectional view taken from line C-C'; and

[0024] Figure 16 This is a diagram used to illustrate a part of an electronic system according to some other example embodiments. Detailed Implementation

[0025] Figure 1 This is a block diagram illustrating an electronic system 1 according to some example embodiments. Figure 2 This is a block diagram illustrating a memory system 20 according to some example embodiments.

[0026] refer to Figure 1 and Figure 2 ,include Figure 2 The electronic system 1 of the memory system 20 shown can be implemented as, for example, a personal computer or a network server.

[0027] Electronic system 1 may include a host 10, a memory system 20, a display 12, and an input device 13. Memory system 20 may include a memory module 200 and a memory controller 100 for controlling the data processing operations of memory module 200.

[0028] The host 10 can display the data stored in the memory system 20 through the display 12 based on the data input through the input device 13.

[0029] Input device 13 can be implemented as a pointing device, such as a touchpad or computer mouse, keypad, or keyboard. Host 10 can control the overall operation of electronic system 1 and can control the operation of memory controller 100. Memory controller 100 can be... Figure 4 , Figure 11 , Figure 12 and Figure 14 The memory controller 100 shown is shown.

[0030] The memory controller 100 can be implemented as part of the host 10, or it can be implemented as a separate chip from the host 10.

[0031] The memory controller 100 may include a clock (CK) generator 101, a clock (CK) buffer 102, a command (CMD) / address (ADD) generator 103, a command (CMD) / address (ADD) transmitter 104, a phase / timing controller 105, and a data I / O unit 106.

[0032] The memory controller 100 can send the clock signal CK generated by the clock generator 101 to the clock buffer 102 to buffer the received clock signal CK, and provide the buffered clock signal CK_b to the memory module 200 through the clock signal line 301.

[0033] Command / address generator 103 can generate an initial command / address signal CMD / ADD0 and provide it to command / address transmitter 104. Command / address transmitter 104 can receive the initial command / address signal CMD / ADD0 and adjust the phase or timing of the initial command / address signal CMD / ADD0 in response to the control signal CTRL of phase / timing controller 105 to generate a first command / address signal CMD / ADD1, and can provide the first command / address signal CMD / ADD1 to memory module 200 through command / address bus 302.

[0034] In the following text, although not shown, the first command / address signal CMD / ADD1 can be provided to the register and comparator, its value can be stored in the register, and the stored value can be used when performing calibration.

[0035] The first command / address signal CMD / ADD1 can be provided to the memory module 200 together with the buffered clock signal CK_b.

[0036] During normal operation, the data I / O unit 106 can receive read data R_Data_1 sent from the memory module 200 via the DQ bus 303, and / or send write data W_Data_1 to be written to the memory module 200 via the DQ bus 303.

[0037] Although not shown, when calibrating the command / address signal CMD / ADD, the data I / O unit 106 can receive the second command / address signal CMD / ADD2 from the memory module 200 via the DQ bus 303. The second command / address signal CMD / ADD2 corresponds to the value of the first command / address signal CMD / ADD1 received by the memory module 200.

[0038] The memory module 200 may include a command (CMD) / address (ADD) receiver 201 and a data I / O unit 202.

[0039] The command / address receiver 201 can respond to the buffered clock signal CK_b and generate a second command / address signal CMD / ADD2 based on the chip select signal / CS, the clock enable signal CKE, and the first command / address signal CMD / ADD1 sent through the command / address bus 302. The command / address receiver 201 can be configured separately from the command / address bus 302 (e.g., ...). Figure 2 (as shown), and can be configured in the memory module 200 by being included in the command / address bus 302, such as Figure 4 , Figure 11 , Figure 12 and Figure 14 The first chip select signal / CS1 and the second chip select signal / CS2 shown are input without passing through separate features.

[0040] The clock enable signal CKE can be used as a pseudo-command, which acts as a read command for the first command / address signal CMD / ADD1 sent via the command / address bus 302. The command / address receiver 201 can generate a second command / address signal CMD / ADD2 based on the first command / address signal CMD / ADD1 received when the clock enable signal CKE is enabled.

[0041] Although not shown, the second command / address signal CMD / ADD2 can be provided to the data I / O unit 202 to perform calibration.

[0042] Typically, the data I / O unit 202 can receive read data R_Data_2 sent from the internal circuit block of the memory module 200 during a read operation and send it to the DQ bus 303, or send the second command / address signal CMD / ADD2 to the DQ bus 303 during calibration.

[0043] In a normal write operation, the data I / O unit 202 can read the write data W_Data_2 to be written to the memory module 200 via the DQ bus 303 and send it to the internal circuit block of the memory module 200.

[0044] Although not shown, the second command / address signal CMD / ADD2 output from memory module 200 can be provided to memory controller 100 via DQ bus 303. Data I / O unit 106 of memory controller 100 and data I / O unit 202 of memory module 200 can be connected to each other via DQS bus and DQ bus 303.

[0045] Figure 3 This is a perspective view showing a portion of a memory system according to some example embodiments. Figure 4 It is used for explanation Figure 3 A diagram of one side of the memory module shown.

[0046] refer to Figure 3 and Figure 4 The memory system 20_1 may include a motherboard 41, a memory module 200, and a connector 43.

[0047] One of the memory devices applied to memory system 20-1 according to some example embodiments is DRAM (Dynamic Random Access Memory). Examples of DRAM include SDRAM (Synchronous Dynamic Random Access Memory), DDR DRAM (Double Data Rate Dynamic Random Access Memory), etc. DRAM specifications may include DDR-3 SDRAM, DDR-4 SDRAM, and DDR-5 SDRAM. DRAM can be synchronous DRAM, such as RDRAM (Rambus DRAM), etc.

[0048] Furthermore, one of the memory devices applied to the memory system 20-1 according to some example embodiments can be selected from a variety of memories such as SRAM (Static Random Access Memory) and non-volatile memory.

[0049] Memory such as DRAM can be installed in a computer system in the form of memory modules, where a large number of memory chips form a rank to achieve high performance and large capacity. Memory module 200 according to some example embodiments has a DIMM (Dual In-line Memory Module) structure. Descriptions related to the rank will be described below.

[0050] Connector 43 can be attached to motherboard 41, and connector 43 can electrically connect memory module 200 and motherboard 41. Memory module 200 can be inserted into connector 43 and electrically connected to motherboard 41. Each connector 43 can be referred to as a slot.

[0051] The memory module 200 may include a printed circuit board (PCB) 210, a re-driving buffer 220, and a plurality of first semiconductor memory chips 230 and a plurality of second semiconductor memory chips 240.

[0052] PCB 210 may include a first surface 210a and a second surface 210b facing each other. PCB 210 may include a first wiring structure 211 to a fourth wiring structure 214 disposed between the first surface 210a and the second surface 210b (see...). Figure 9 A description of the wiring structure will be provided below.

[0053] The plurality of first semiconductor memory chips 230 and the plurality of second semiconductor memory chips 240 may be volatile memory devices or non-volatile memory devices. Volatile memory devices may be RAM (Random Access Memory), DRAM (Dynamic RAM), SRAM (Static RAM), T-RAM (Thyristor RAM), Z-RAM (Zero Capacitor RAM), or TTRAM (Dual Transistor RAM). Non-volatile memory devices may be EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, MRAM (Magnetic RAM), Spin-Torque MRAM, FeRAM (Ferroelectric RAM), PRAM (Phase-Change RAM), or resistive memory (Resistive RAM (RRAM)). In some example embodiments, the plurality of first semiconductor memory chips 230 and the plurality of second semiconductor memory chips 240 may be DRAM.

[0054] Each of the plurality of first semiconductor memory chips 230 and the plurality of second semiconductor memory chips 240 can be a semiconductor memory package. The semiconductor memory package can be PoP (PoP, stacked package), BGA (Ball Grid Array), CSP (Chip Scale Package), PLCC (Plastic Chip Carrier with Leads), PDIP (Plastic Dual In-line Package), COB (Chip on Board), CERDIP (Ceramic Dual In-line Package), MQFP (Plastic Metric Quad Flat Package), TQFP (Thin Quad Flat Package), SOIC (Small Outline Integrated Circuit), SSOP (Shrink Small Outline Package), TSOP (Thin Small Outline Package), SIP (System in Package), MCP (Multi-Chip Package), WLP (Wafer Level Package), or WSP (Wafer Level Processed Stacked Package).

[0055] Multiple first semiconductor memory chips 230 can be disposed on a first surface 210a of PCB 210. Multiple second semiconductor memory chips 240 can be disposed on a second surface 210b of PCB 210. Based on the viewpoint of viewing PCB 210 in a plane, the multiple first semiconductor memory chips 230 and the multiple second semiconductor memory chips 240 can be disposed along a first straight line L1 extending in a first direction D1.

[0056] Multiple first semiconductor memory chips 230 and multiple second semiconductor memory chips 240 can all be enabled by the first chip select signal / CS1 and perform the same memory operations within a single memory bank. For example, refer to... Figure 4 Eight DRAM chips can form a memory bank and can be arranged along a first straight line L1 on both sides of the substrate. The DRAM chips can input and output 8-bit data signals DQ0, DQ1, ..., DQ6, DQ7 (see...). Figure 7 and Figure 8 Therefore, a memory bank can have a data I / O bus width of ×64 (DQ bus width).

[0057] Multiple first semiconductor memory chips 230 and multiple second semiconductor memory chips 240 can enter an enabled state in response to a first chip select signal / CS1 applied by the memory controller 100, and can simultaneously receive inputs such as command signals, address signals, and power signals. In response, the multiple first semiconductor memory chips 230 and multiple second semiconductor memory chips 240 can perform operations simultaneously. Therefore, eight DRAM chips can share the first chip select signal / CS1. Thus, the chip select signal / CS1 of the memory module 200 can be provided to all eight DRAM chips.

[0058] According to some example embodiments, the plurality of first semiconductor memory chips 230 and the plurality of second semiconductor memory chips 240 do not perform mirror operations relative to each other, except that they operate within the same memory bank. This will be explained in conjunction with the following. Figures 5 to 8 Describe it.

[0059] The re-drive buffer 220 can be set on, for example, the first side 210a of PCB 210.

[0060] The redrive buffer 220 can transmit signals sent from the tab (TAP) to each of the plurality of first semiconductor memory chips 230 and the plurality of second semiconductor memory chips 240. The signals may include at least one of the following: a data signal DQ, an address signal ADD, a command signal CMD, and a first chip select signal / CS1 output from the memory controller 100.

[0061] Although not shown, according to embodiments, the redrive buffer 220 may include registers and PLL circuitry. The PLL circuitry may be replaced by a DLL (Delay-Locked Loop) circuitry. In some example embodiments, the redrive buffer 220 may store address signals ADD and / or command signals CMD (output from memory controller 100) in registers and may provide clock signals CK (output from PLL circuitry (not shown)) to each of a plurality of first semiconductor memory chips 230 and a plurality of second semiconductor memory chips 240.

[0062] The tongue TAP connected to connector 43 can be formed on one edge of PCB 210.

[0063] The memory module 200 can receive a clock signal CLK, an address signal ADD, and a command signal CMD from the memory controller 100 via a tab TAP. The memory module 200 can send / receive a data signal DQ and a data strobe signal DQS to / from the memory controller 100 via the tab TAP. The tab TAP can be implemented as, for example, copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au), and / or combinations thereof. In some example embodiments, the tab TAP may include gold (Au) coated on the surface of copper (Cu).

[0064] The tab TAP can be electrically connected in series or parallel to multiple first semiconductor memory chips 230 and multiple second semiconductor memory chips 240, as well as the redrive buffer 220. The tab TAP can be electrically connected to multiple first semiconductor memory chips 230 and multiple second semiconductor memory chips 240 attached to the memory module 200. The tab TAP can be a pin.

[0065] Figure 5 This is a perspective view used to illustrate a semiconductor chip according to some example embodiments. Figure 6 This is a simplified plan view of the lower surface of a semiconductor chip according to some example embodiments.

[0066] refer to Figure 5 The plurality of first semiconductor memory chips 230 may include a first connection terminal 231, a second connection terminal 232, a third connection terminal 233, a fourth connection terminal 234, a fifth connection terminal 235, a sixth connection terminal 236 and a seventh connection terminal 237 included in the ball grid array (BGA) on the lower surface.

[0067] The first connection terminals 231 to the seventh connection terminals 237 can be implemented as multiple solder balls. These solder balls can connect multiple first semiconductor memory chips 230 and the PCB 210. The solder balls can be made of a conductive material.

[0068] refer to Figure 6 A ball grid array (BGA) may include a plurality of solder balls arranged at equal intervals in the row direction and at equal intervals in the column direction. As an example, a ball grid array (BGA) may include a plurality of solder balls arranged in 11 rows and 7 columns on the lower surface of a plurality of first semiconductor memory chips 230. The 11 rows of the ball grid array (BGA) may be defined as rows A to K, respectively. The 7 columns of the ball grid array (BGA) may be defined as columns one through seven, respectively.

[0069] The plurality of second semiconductor memory chips 240 may include structures corresponding to the plurality of first semiconductor memory chips 230, and therefore may include first connection terminals 241, second connection terminals 242, third connection terminals 243, fourth connection terminals 244, fifth connection terminals 245, sixth connection terminals 246 and seventh connection terminals 237 corresponding to the first connection terminals 231 to seventh connection terminals 237 of the plurality of first semiconductor memory chips 230, and may include the same ball grid array (BGA) structure.

[0070] The arrangement of the number of rows and columns of solder balls can vary relative to the arrangement shown.

[0071] Figure 7 This means being assigned to Figure 6 A diagram illustrating an example of signals at the connection terminals (solder balls) of a semiconductor chip. The positions of the signals can vary relative to the positions shown.

[0072] refer to Figure 7 Signals for the operation of multiple first semiconductor memory chips 230 can be assigned to each solder ball of the ball grid array (BGA).

[0073] The first to fourth solder balls in row A can be assigned to the I / O power supply voltage VDDQ, the DQS_c signal, the TDQS_c signal, and the high voltage VPP. When multiple first semiconductor memory chips 230 are used for x4 I / O, the TDQS_c signal may not be used. The solder balls in the fifth column of row A can be assigned to the DM_n signal, the DBI signal, and the TDQS_t signal. When multiple first semiconductor memory chips 230 are used for x4 I / O, the TDQS_t signal may not be used. The solder balls in the sixth and seventh columns of row A can be assigned to the first data signal DQ1 and the I / O power supply voltage VDDQ.

[0074] The solder balls in columns 1 through 7 of row B can be assigned to the 0th data signal DQ0, the DQS_t signal, the ground voltage VSS, the I / O ground voltage VSSQ, the ground voltage VSS, the power supply voltage VDD, and the ground voltage VSS, respectively. The solder balls in columns 1 through 7 of row B can correspond to the first connection terminal 231 through the seventh connection terminal 237.

[0075] The solder balls in columns 1 through 7 of row C can be assigned to the fourth data signal DQ4, the second data signal DQ2, the power supply voltage VDD, the ZQ signal, the I / O ground voltage VSSQ, the third data signal DQ3, and the fifth data signal DQ5, respectively. When multiple first semiconductor memory chips 230 are used for x4 I / O, the fourth data signal DQ4 and the fifth data signal DQ5 may not be used.

[0076] The solder balls in columns 1 through 7 of row D can be assigned to I / O power supply voltage VDDQ, sixth data signal DQ6, I / O power supply voltage VDDQ, mirror function (MF), I / O power supply voltage VDDQ, seventh data signal DQ7, and I / O power supply voltage VDDQ, respectively. When multiple first semiconductor memory chips 230 are used for x4 I / O, the sixth data signal DQ6 and the seventh data signal DQ7 may not be used. In the example embodiment, the signal applied to the mirror function (MF) is 0, and the signals assigned to the solder balls of the ball grid array (BGA) are not asymmetrically inverted.

[0077] The solder balls in the first column of row E can be assigned to the C2 signal and the ODT1 signal. The solder balls in the second to seventh columns of row E can be assigned to the ODT signal, I / O ground voltage VSSQ, ground voltage VSS, I / O ground voltage VSSQ, CK_t signal, and CK_c signal, respectively.

[0078] The solder balls in the first column of row F can be assigned to the C0 and CKE1 signals. The solder balls in the second through sixth columns of row F can be assigned to the CKE signal, ground voltage VSS, power supply voltage VDD, ground voltage VSS, and the first selection signal / CS1, respectively. The solder balls in the seventh column of row F can be assigned to the C1 signal.

[0079] The solder balls in the first column of row G can be assigned to the WE_n signal and the fourteenth address signal A14. The solder balls in columns two through five of row G can be assigned to the ACT_n signal, power supply voltage VDD, ground voltage VSS, and power supply voltage VDD. The solder balls in the sixth column of row G can be assigned to the CAS_n signal and the fifteenth address signal A15. The solder balls in the seventh column of row G can be assigned to the CAS_n signal and the sixteenth address signal A16.

[0080] The solder balls in the first to seventh columns of row H can be assigned to the 0th block group address signal BA0, the tenth address signal A10, the VREFCA signal, the power supply voltage VDD, the ground voltage VSS, the twelfth address signal A12, and the first block group address signal BG1.

[0081] The solder balls in columns 1 through 4 of row I can be assigned to address signal BA0 (block 0), address signal A4 (block 4), RESET_n signal, and ground voltage VSS, respectively. The solder ball in column 5 of row I can be assigned to the ALERT_n signal and can be used for voltage monitoring. The solder balls in columns 6 and 7 of row I can be assigned to address signal A3 (block 3) and address signal BA1 (block 1), respectively.

[0082] The solder balls in the first to seventh columns of row J can be assigned to the sixth address signal A6, the 0th address signal A0, the eleventh address signal A11, the power supply voltage VDD, the thirteenth address signal A13, the first address signal A1, and the fifth address signal A5, respectively.

[0083] The solder balls in columns 1 through 7 of row K can be assigned to the eighth address signal A8, the second address signal A2, the PARITY signal, the high voltage VPP, the seventeenth address signal A17, the ninth address signal A9, and the seventh address signal A7, respectively. When multiple first semiconductor memory chips 230 are used for x8 I / O, the seventeenth address signal A17 may not be used.

[0084] Signals for the operation of the plurality of second semiconductor memory chips 240 can be assigned to ball grid arrays (BGAs) on the lower surface of the plurality of second semiconductor memory chips 240, and the assignment positions can be the same as the assignment positions of the plurality of first semiconductor memory chips 230.

[0085] In the fourth column of row D, the signal applied to the mirror function MF is 0, and the assignment position is not symmetrically reversed. Therefore, even when the lower surfaces of the plurality of first semiconductor memory chips 230 face the lower surfaces of the plurality of second semiconductor memory chips 240, the ball grid arrays disposed on the lower surfaces of the respective chips do not stack and do not completely overlap each other.

[0086] However, when the signal for the mirror function (MF) applied to the plurality of second semiconductor memory chips 240 is 1, the operation controller (not shown) included in the plurality of second semiconductor memory chips 240 can be operated to perform mirror function operation for the plurality of first semiconductor memory chips 230.

[0087] For example, when the signal applied to the mirror function (MF) is 1, the signal assigned to the sixth column of row A of the plurality of second semiconductor memory chips 240 is not the first data signal DQ1, but rather the signal symmetrically assigned to the second column of row A, namely the DQS_c signal. Therefore, when the lower surfaces of the plurality of first semiconductor memory chips 230 face the lower surfaces of the plurality of second semiconductor memory chips 240, the ball grid arrays disposed on the lower surfaces of each chip are stacked and can completely overlap each other.

[0088] The mirror function (MF) signal applied to the plurality of first semiconductor memory chips 230 and the plurality of second semiconductor memory chips 240 of this disclosure may be 0, and the plurality of first semiconductor memory chips 230 and the plurality of second semiconductor memory chips 240 may not perform mirror function operations against each other.

[0089] Figure 8 This means being assigned to Figure 6 A diagram illustrating an example of signals at the connection terminals (solder balls) of a semiconductor chip. The positions of the signals can vary relative to the positions shown.

[0090] Settings Figure 8 The signal assignment of the ball grid array on the lower surface of the plurality of first semiconductor memory chips 230' and the plurality of second semiconductor memory chips 240' can correspond to Figure 7 The assignment of multiple first semiconductor memory chips 230 and multiple second semiconductor memory chips 240. Referring below... Figure 8 This describes the signal assignment of a ball grid array disposed on the lower surface of a semiconductor memory chip according to some other example embodiments. The main description will be related to... Figure 7 The signal assignments of the ball grid arrays shown are different.

[0091] In this example embodiment, the mirroring function (MF) signal is not assigned to Figure 8The ball grid array (BGA) comprises a plurality of first semiconductor memory chips 230' and a plurality of second semiconductor memory chips 240'. Therefore, the plurality of first semiconductor memory chips 230' and the plurality of second semiconductor memory chips 240' do not include an operation controller for performing mirroring operations. Therefore, regardless of the signals applied to the plurality of first semiconductor memory chips 230' and the plurality of second semiconductor memory chips 240', even when the lower surfaces of the plurality of first semiconductor memory chips 230' face the lower surfaces of the plurality of second semiconductor memory chips 240', the ball grid arrays (BGA) disposed on the lower surfaces of each chip do not stack and do not completely overlap each other.

[0092] Figure 9 It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 10 It is used to explain in Figure 3 The diagram shows the wiring structure included in the PCB in region R1.

[0093] refer to Figure 9 and Figure 10 PCB 210 may include a first wiring structure 211, a second wiring structure 212, a third wiring structure 213 and a fourth wiring structure 214.

[0094] The first wiring structure 211, the second wiring structure 212, the third wiring structure 213, and the fourth wiring structure 214 may include at least some of the first conductive film M1, the second conductive film M2, the third conductive film M3, the fourth conductive film M4, and the fifth conductive film M5 in the PCB 210. However, the number of conductive film layers shown in the figures is only an example, and the number of conductive film layers may vary.

[0095] The first wiring structure 211 can electrically connect the first connection terminals 231 of multiple first semiconductor memory chips 230 and the first pin 221 of the redrive buffer 220, and can provide the first data signal (DQ0, see [link]) provided by the first pin 221 of the redrive buffer 220 and corresponding to the operation signal. Figure 7 It is provided to the first connection terminal 231.

[0096] The first wiring structure 211 may include a first via 211a, a first conductive pattern 211b, a second conductive pattern 211c, a third conductive pattern 211d, and a fourth conductive pattern 211e.

[0097] The second wiring structure 212 can electrically connect the first connection terminals 241 of multiple second semiconductor memory chips 240 and the second pins 222 of the redrive buffer 220, and can provide a first data signal (DQ0, see [link]) provided by the second pins 222 of the redrive buffer 220 and corresponding to the operation signal. Figure 7 It is provided to the first connection terminal 241.

[0098] The second wiring structure 212 may include a first via 212a, a first conductive pattern 212b, a second conductive pattern 212c, a third conductive pattern 212d, and a fourth conductive pattern 212e.

[0099] The first connection terminals 231 of multiple first semiconductor memory chips 230 and the first connection terminals 241 of multiple second semiconductor memory chips 240 can receive the same first data signal (DQ0, see redrive buffer 220) from the redrive buffer 220. Figure 7 ).

[0100] In this example embodiment, when viewed from the first plane D1-D2, the first wiring structure 211 and the second wiring structure 212 are symmetrical about the centerline CL of the redrive buffer 220. The first connection terminals 231 of the plurality of first semiconductor memory chips 230 and the first connection terminals 241 of the plurality of second semiconductor memory chips 240 are also symmetrically arranged about the centerline CL of the redrive buffer 220. Therefore, when viewed from the first plane D1-D2, the distance d1 between the first connection terminals 231 of the plurality of first semiconductor memory chips 230 and the centerline CL of the redrive buffer 220 is the same as the distance d1 between the first connection terminals 241 of the plurality of second semiconductor memory chips 240 and the centerline CL of the redrive buffer 220.

[0101] The third wiring structure 213 can electrically connect the third connection terminals 233 of multiple first semiconductor memory chips 230 and the third pin 223 of the redrive buffer 220, and can provide the ground voltage (VSS, see [link]) provided by the third pin 223 of the redrive buffer 220 and corresponding to the power supply signal. Figure 7 Provided to the third connection terminal 233.

[0102] The fourth wiring structure 214 can electrically connect the third connection terminals 243 of multiple second semiconductor memory chips 240 and the fourth pin 224 of the redrive buffer 220, and can provide the ground voltage (VSS, see [link]) provided by the fourth pin 224 of the redrive buffer 220 and corresponding to the power supply signal. Figure 7 Provided to the third connection terminal 243.

[0103] The third connection terminals 233 of the plurality of first semiconductor memory chips 230 and the third connection terminals 243 of the plurality of second semiconductor memory chips 240 can receive the same ground voltage (VSS, see below) from the redrive buffer 220. Figure 7 ).

[0104] In this example embodiment, when viewed from the first plane D1-D2, the third wiring structure 213 and the fourth wiring structure 214 are symmetrical about the center line CL of the redrive buffer 220. The third connection terminals 233 of the plurality of first semiconductor memory chips 230 and the third connection terminals 243 of the plurality of second semiconductor memory chips 240 are also symmetrically arranged about the center line CL of the redrive buffer 220. Therefore, when viewed from the first plane D1-D2, the distance d2 between the third connection terminals 233 of the plurality of first semiconductor memory chips 230 and the center line CL of the redrive buffer 220 is the same as the distance d2 between the third connection terminals 243 of the plurality of second semiconductor memory chips 240 and the center line CL of the redrive buffer 220. Furthermore, the distance d1 between the first connection terminals 231 of the plurality of first semiconductor memory chips 230 and the center line CL of the redrive buffer 220 is shorter than the distance d2 between the third connection terminals 233 of the plurality of first semiconductor memory chips 230 and the center line CL of the redrive buffer 220.

[0105] In the redrive buffer 220 according to some example embodiments, the first pin 221 and the second pin 222 can be arranged symmetrically based on the center line CL, and the third pin 223 and the fourth pin 224 can also be arranged symmetrically based on the center line CL. Furthermore, the pin arrangement on the lower surface of the redrive buffer 220 can be arranged symmetrically based on the center line CL of the redrive buffer 220.

[0106] Figure 9 and Figure 10 The wiring structure shown is just an example, and some parts can be omitted.

[0107] According to some example embodiments, the efficiency of a semiconductor chip module can be improved by performing symmetrical wiring in a semiconductor chip module that does not perform mirroring.

[0108] Figure 11 This is a diagram used to illustrate memory module 200_2 according to some other example embodiments. The main description will be related to... Figure 4 The memory module 200 is different.

[0109] and Figure 4 Compared to memory module 200, memory module 200_2 further includes a plurality of third semiconductor memory chips 250 and a plurality of fourth semiconductor memory chips 260. The plurality of third semiconductor memory chips 250 and the plurality of fourth semiconductor memory chips 260 may be arranged to extend in a first direction D1 and may be disposed along a second straight line L2 spaced apart from the first straight line L1 in a second direction D2.

[0110] In this example embodiment, a plurality of third semiconductor memory chips 250 correspond to a plurality of first semiconductor memory chips 230, and a plurality of fourth semiconductor memory chips 260 correspond to a plurality of second semiconductor memory chips 240. However, the plurality of third semiconductor memory chips 250 and the plurality of fourth semiconductor memory chips 260 simultaneously perform memory operations in a single memory bank via a second chip select signal / CS2.

[0111] According to this example embodiment, the second chip select signal / CS2 is provided by the memory controller 100 and can then be provided to a plurality of third semiconductor memory chips 250 and a plurality of fourth semiconductor memory chips 260 via the redrive buffer 220.

[0112] Above Figure 11 In the case of an embodiment, when operating with two or more memory banks in a memory module without performing mirroring, the wiring can be performed symmetrically.

[0113] Figure 12 This is a diagram used to illustrate memory module 200_3 according to some other example embodiments. Figure 13 It is along Figure 12 A cross-sectional view taken from line B-B'. The main explanation will be... Figure 11 The memory module 200_2 is different.

[0114] In this example embodiment, the first semiconductor memory chip 250a, the second semiconductor memory chip 260a, the third semiconductor memory chip 270a, and the fourth semiconductor memory chip 280a can be arranged along a first straight line L1. Based on the viewpoint of the first plane D1-D2, the first semiconductor memory chip 250a to the fourth semiconductor memory chip 280a do not overlap with each other. Therefore, based on the viewpoint of viewing PCB 210 in the plane, the connection terminals of the plurality of first semiconductor memory chips 250a do not overlap with the plurality of fourth semiconductor memory chips 280a, and based on the viewpoint of viewing PCB 210 in the plane, the connection terminals of the plurality of second semiconductor memory chips 260a do not overlap with the plurality of third semiconductor memory chips 270a.

[0115] According to some example embodiments, the PCB 210 may include a first through-hole 210V1_3 and a second through-hole 210V3_3, as well as a blind through-hole 210V2_3, penetrating a first surface 210a and a second surface 210b of the PCB 210. The first through-hole 210V1_3 and the blind through-hole 210V2_3 may be electrically connected to a plurality of fourth semiconductor memory chips 280a. The second through-hole 210V3_3 may be electrically connected to a plurality of first semiconductor memory chips 250a.

[0116] Without performing a mirroring operation on the first semiconductor memory chip 250a to the fourth semiconductor memory chip 280a, since the first semiconductor memory chip 250a to the fourth semiconductor memory chip 280a do not overlap each other based on the viewpoint of the first plane D1-D2, the PCB 210 may include through vias.

[0117] Figure 14 This is a diagram used to illustrate memory module 200_4 according to some other example embodiments. Figure 15 It is along Figure 14 A cross-sectional view taken along line C-C'. The main explanation will be... Figure 12 and Figure 13 The memory module 200_3 is different.

[0118] In this example embodiment, based on the viewpoint of the first plane D1-D2, the first semiconductor memory chip 250b, the second semiconductor memory chip 260b, the third semiconductor memory chip 270b, and the fourth semiconductor memory chip 280b overlap each other. Therefore, based on the viewpoint of viewing PCB 210 in the plane, the connection terminals of the plurality of first semiconductor memory chips 250b overlap with at least a portion of the plurality of fourth semiconductor memory chips 280b, and based on the viewpoint of viewing PCB 210 in the plane, the connection terminals of the plurality of second semiconductor memory chips 260b overlap with at least a portion of the plurality of third semiconductor memory chips 270b.

[0119] According to some example embodiments, the PCB 210 may include a first blind via 210V1_4 and a second blind via 210V2_4. The first blind via 210V1_4 may be electrically connected to a plurality of first semiconductor memory chips 250b and the second blind via 210V2_4 may be electrically connected to a plurality of fourth semiconductor memory chips 280b.

[0120] Without performing a mirroring operation on the first semiconductor memory chip 250b to the fourth semiconductor memory chip 280b, since the first semiconductor memory chip 250b to the fourth semiconductor memory chip 280b overlap each other based on the viewpoint of the first plane D1-D2, the PCB 210 cannot include through vias and can only include blind vias.

[0121] Multiple first semiconductor memory chips 250b and multiple fourth semiconductor memory chips 280b, which overlap each other through blind vias, can be electrically isolated from each other.

[0122] Figure 16 This is a diagram used to illustrate a portion of an electronic system according to some other example embodiments. The main description will be related to... Figures 1 to 3 The electronic system 1 is different.

[0123] When with Figures 1 to 3 When comparing electronic system 1, electronic system 2 may further include main buffer 40, first re-drive buffer chip 50, second re-drive buffer chip 60, and first motherboard wiring structure 411 to fourth motherboard wiring structure 414.

[0124] Motherboard 410 corresponds to Figure 4 PCB 210, main buffer 40 corresponds to Figure 4 The redrive buffer 220, the first redrive buffer chip 50 corresponds to Figure 4 The multiple first semiconductor memory chips 230, the second re-drive buffer chip 60 corresponding to Figure 4 Multiple second semiconductor memory chips 240, and the first motherboard wiring structure 411 to the fourth motherboard wiring structure 414 correspond to Figure 4 The first wiring structure 211 to the fourth wiring structure 214.

[0125] The first re-drive buffer chip 50 can be disposed on the first side 410a of the motherboard 410, and the second re-drive buffer chip 60 can be disposed on the second side 410b of the motherboard 410. The first re-drive buffer chip 50 and the second re-drive buffer chip 60 do not perform mirror operation on each other.

[0126] Therefore, based on the viewpoint of the first plane D1-D2, the first re-drive buffer chip 50 and the second re-drive buffer chip 60 can be symmetrically arranged based on the center line CL of the main buffer 40. Therefore, the first motherboard wiring structure 411 and the second motherboard wiring structure 412 can be symmetrically arranged based on the center line CL of the main buffer 40, and the third motherboard wiring structure 413 and the fourth motherboard wiring structure 414 can be symmetrically arranged based on the center line CL of the main buffer 40.

[0127] The first redrive buffer chip 50 and the second redrive buffer chip 60 correspond to buffer chips (i.e., semiconductor chips) rather than semiconductor memory devices.

[0128] In summary, the left / right pins of a buffer can be configured in a symmetrical structure based on the buffer. In the case of DRAM, the pin arrangement can be reconfigured symmetrically based on the buffer using either a mirrored pin feature or a mirrored configuration. However, in semiconductor chips that do not support mirroring or where mirroring is disabled, the wiring lengths between the buffer and the semiconductor chip may differ on the left and right sides, and the signal transmission on the left and right sides, as well as the layer arrangement of the underlying substrate, can change. This can lead to inefficiencies due to asymmetrical signal transmission and layer / wiring arrangements.

[0129] As described above, embodiments may provide a semiconductor chip module in which semiconductor chips that do not perform mirroring operations are disposed on the upper and lower surfaces of the module. Embodiments may also provide a semiconductor chip module in which wiring between the semiconductor chips and buffers is symmetrically arranged based on the buffers in a module including semiconductor chips that do not perform mirroring operations.

[0130] Example embodiments have been disclosed herein, and while specific terminology has been used, it should be used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing this application that, unless expressly stated otherwise, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art should understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor chip module, comprising: A printed circuit board (PCB) includes a first side and a second side that face each other. A buffer is located on the first surface of the PCB. A first chip is located on the first surface of the PCB and includes a first connection terminal and a second connection terminal. A first signal is provided to the first connection terminal, and a second signal different from the first signal is provided to the second connection terminal. The second chip is located on the second side of the PCB and includes a third connection terminal for providing the first signal and a fourth connection terminal for providing the second signal. in, The first connection terminal of the first chip and the third connection terminal of the second chip simultaneously receive the first signal from the buffer. The first connection terminal is positioned closer to the buffer than the second connection terminal, and The third connection terminal is positioned closer to the buffer than the fourth connection terminal.

2. The semiconductor chip module according to claim 1, wherein, Both the first chip and the second chip are DRAM.

3. The semiconductor chip module according to claim 2, wherein, The first chip and the second chip receive the same chip selection signal.

4. The semiconductor chip module according to claim 2, wherein, The first signal is an operation signal and the second signal is a power signal.

5. The semiconductor chip module according to claim 1, wherein, Based on a viewpoint observing the PCB in a plane, the first connection terminal and the third connection terminal are symmetrically arranged based on the centerline of the buffer extending between the first chip and the second chip, and Based on the viewpoint of observing the PCB in a plane, the second connection terminal and the fourth connection terminal are symmetrically arranged based on the centerline.

6. The semiconductor chip module according to claim 1, wherein, The first chip and the second chip are not mirrored.

7. The semiconductor chip module according to claim 6, wherein, The first chip and the second chip do not include an operation controller that performs the mirroring function operation.

8. The semiconductor chip module according to claim 1, wherein, The buffer has a first pin and a third pin that provide the first signal to the first connection terminal and the third connection terminal respectively, and a second pin and a fourth pin that provide the second signal to the second connection terminal and the fourth connection terminal respectively.

9. The semiconductor chip module according to claim 8, wherein, The first pin and the third pin are symmetrically arranged based on the centerline of the buffer extending between the first chip and the second chip, and The second pin and the fourth pin are symmetrically arranged based on the centerline of the buffer.

10. The semiconductor chip module according to claim 8, wherein, The PCB includes a first wiring structure connecting the first connection terminal and the first pin, and a second wiring structure connecting the third connection terminal and the third pin. Based on the viewpoint of observing the PCB in a plane, the first wiring structure and the second wiring structure are symmetrically arranged based on the centerline of the buffer extending between the first chip and the second chip.

11. A semiconductor chip module, comprising a printed circuit board (PCB), the PCB including a first side and a second side facing each other, the semiconductor chip module comprising: A first chip is located on the first surface of the PCB and includes a first connection terminal for receiving a first signal. The second chip is located on the second side of the PCB and includes a second connection terminal for receiving the first signal. as well as The buffer includes a first pin electrically connected to the first connection terminal and a second pin electrically connected to the second connection terminal. in, The PCB includes a first wiring structure connecting the first connection terminal and the first pin, and a second wiring structure connecting the second connection terminal and the second pin. Based on the viewpoint of observing the PCB in a plane, the first wiring structure and the second wiring structure are symmetrically arranged based on the centerline of the buffer extending between the first chip and the second chip, and The first chip and the second chip are not mirrored.

12. The semiconductor chip module according to claim 11, wherein, The first pin and the second pin are symmetrically arranged based on the centerline.

13. The semiconductor chip module according to claim 11, wherein, The first chip and the second chip do not include an operation controller that performs the mirroring function operation.

14. The semiconductor chip module according to claim 11, wherein, Both the first chip and the second chip are DRAM.

15. The semiconductor chip module according to claim 14, wherein, The same chip select signal is provided to both the first chip and the second chip.

16. The semiconductor chip module according to claim 11, wherein, The buffer is a re-drive buffer chip.

17. A semiconductor chip module, comprising: A printed circuit board (PCB) includes a first side and a second side that face each other. A buffer is located on the first surface of the PCB. A plurality of first memory chips are located on the first surface of the PCB. Each first memory chip includes a first connection terminal that is provided with a first signal and performs a first operation in response to the first signal and a first chip selection signal. A plurality of second memory chips are located on the second side of the PCB. Each second memory chip includes a second connection terminal that is provided with the first signal and performs the first operation in response to the first signal and the first chip selection signal. Multiple third memory chips are located on the first side of the PCB. Each of the third memory chips includes a third connection terminal that is provided with a second signal and performs a second operation in response to the second signal and a second chip selection signal. as well as Multiple fourth memory chips are located on the second side of the PCB. Each of the fourth memory chips includes a fourth connection terminal that is provided with the second signal, and performs the second operation in response to the second signal and the second chip select signal. in, The first connection terminals of the plurality of first memory chips and the second connection terminals of the plurality of second memory chips simultaneously receive the first signal from the buffer, and The third connection terminals of the plurality of third memory chips and the fourth connection terminals of the plurality of fourth memory chips simultaneously receive the second signal from the buffer.

18. The semiconductor chip module according to claim 17, wherein, The plurality of first memory chips are arranged along a first straight line extending in a first direction. The plurality of second memory chips are arranged along the first straight line. The plurality of third memory chips are arranged along a second straight line that is spaced apart from the first straight line in a second direction different from the first direction and extends in the first direction. The plurality of fourth memory chips are arranged along the second straight line. Based on the viewpoint of observing the PCB in a plane, the distance between the centerline of the first connection terminal and the buffer is the same as the distance between the centerline of the second connection terminal and the buffer, and Based on the viewpoint of observing the PCB in a plane, the distance between the third connection terminal and the center line of the buffer is the same as the distance between the fourth connection terminal and the center line of the buffer.

19. The semiconductor chip module according to claim 17, wherein, The plurality of first memory chips to the plurality of fourth memory chips are arranged along a first straight line extending in a first direction. Based on the viewpoint of observing the PCB in a plane, the first connection terminals of the plurality of first memory chips do not overlap with the plurality of fourth memory chips, and Based on the viewpoint of observing the PCB in a plane, the second connection terminals of the plurality of second memory chips do not overlap with the plurality of third memory chips.

20. The semiconductor chip module according to claim 17, wherein, The plurality of first memory chips to the plurality of fourth memory chips are arranged along a first straight line extending in a first direction. Based on the viewpoint of observing the PCB in a plane, the first connection terminals of the plurality of first memory chips overlap with at least a portion of the plurality of fourth memory chips. Based on the viewpoint of observing the PCB in a plane, the second connection terminals of the plurality of second memory chips overlap with at least a portion of the plurality of third memory chips. The overlapping first connection terminal is connected to the blind via, and The overlapping second connection terminal is connected to the blind via.

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