Semiconductor device having multi-channel active region

Abstract

A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertically stacked spaced-apart insulating gate electrode is also provided, buried within the semiconductor active layer. The vertically stacked spaced-apart insulating gate electrode includes a first insulating gate electrode extending adjacent the electrically insulating layer and an (N-1)th insulating gate electrode spaced apart from a surface of the semiconductor active layer, where N is a positive integer greater than 2. An Nth insulating gate electrode is provided on the surface of the semiconductor active layer. A pair of source / drain regions are provided within the semiconductor active layer. The source / drain regions extend adjacent opposite sides of the vertically stacked spaced-apart insulating gate electrode. In some of these aspects, the semiconductor active layer extends between the pair of source / drain regions and the electrically insulating layer, while the first insulating gate electrode contacts the electrically insulating layer.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0097389, filed on August 4, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and methods of forming the same, and more specifically, to field-effect transistors and methods of forming field-effect transistors. Background Technology

[0004] Semiconductor devices can include integrated circuits, which include metal-oxide-semiconductor field-effect transistors (MOSFETs), and these MOSFETs include complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs). As the size and design rules of semiconductor devices decrease, the layout size (e.g., footprint) of MOSFETs also shrinks. Unfortunately, due to the reduction in MOSFET size, many operating characteristics of semiconductor devices may degrade. Therefore, various methods have been developed for forming semiconductor devices to achieve superior performance while overcoming many limitations associated with high integration. Summary of the Invention

[0005] Embodiments of the present invention can provide semiconductor devices with improved reliability and electrical characteristics.

[0006] In one aspect, the semiconductor device may include: a supporting substrate; an insulating layer located on the supporting substrate; a semiconductor pattern located on the insulating layer and in contact with the insulating layer; and a pair of source / drain patterns located on the semiconductor pattern. A channel structure is also provided between the pair of source / drain patterns. The channel structure includes channel patterns stacked and spaced apart from each other. A gate electrode is also provided, intersecting the channel structure and extending in a first direction. The gate electrode may include a first portion disposed between the channel structure and the insulating layer, and the horizontal level of the bottom surface of the first portion may be lower than the horizontal level of the bottommost surface of the source / drain patterns.

[0007] In another aspect, the semiconductor device may include: a supporting substrate; an insulating layer located on the supporting substrate; and a semiconductor pattern disposed on and in contact with the insulating layer. A pair of source / drain patterns are also provided on the semiconductor pattern, and a channel structure is provided between the pair of source / drain patterns. The channel structure includes at least one channel pattern. A gate electrode is provided, intersecting the channel structure and extending in a first direction. The gate electrode may include a portion disposed between the insulating layer and the lowermost portion of the channel structure, and the portion may penetrate the semiconductor pattern. The lower portion of the source / drain pattern may be located within the semiconductor pattern. The source / drain pattern may be spaced apart from the insulating layer, and the semiconductor pattern is located between the source / drain pattern and the insulating layer.

[0008] In another aspect, the semiconductor device may include: a supporting substrate; an insulating layer located on the supporting substrate; and a first semiconductor pattern and a second semiconductor pattern disposed on the insulating layer, each including a PMOSFET region and an NMOSFET region adjacent to each other in a first direction. A pair of first source / drain patterns are disposed on the first semiconductor pattern, and a pair of second source / drain patterns are disposed on the second semiconductor pattern. A first channel structure is disposed between the pair of first source / drain patterns, and a second channel structure is disposed between the pair of second source / drain patterns. Furthermore, both the first channel structure and the second channel structure include: a first channel pattern, a second channel pattern, and a third channel pattern sequentially stacked and spaced apart from each other. Additionally, a first gate electrode and a second gate electrode are disposed, extending in the first direction and intersecting the first channel structure and the second channel structure, respectively. Both the first gate electrode and the second gate electrode include a first portion located between the insulating layer and the first channel pattern, a second portion located between the first channel pattern and the second channel pattern, a third portion located between the second channel pattern and the third channel pattern, and a fourth portion located on the third channel pattern. A first gate insulating layer and a second gate insulating layer are disposed, respectively between the first channel structure and the first gate electrode and between the second channel structure and the second gate electrode. A first gate spacer and a second gate spacer are respectively disposed on the sidewalls of the first gate electrode and the second gate electrode. A first gate cover pattern and a second gate cover pattern are respectively disposed on the top surfaces of the first gate electrode and the second gate electrode. A first interlayer insulating layer is disposed on the first gate cover pattern and the second gate cover pattern. Furthermore, a source / drain contact is provided, which penetrates the first interlayer insulating layer to connect to the first source / drain pattern and the second source / drain pattern. Additionally, a gate contact penetrates the first interlayer insulating layer and the first gate cover pattern and the second gate cover pattern to connect to the first gate electrode and the second gate electrode, respectively. A second interlayer insulating layer is disposed on the first interlayer insulating layer, and a first metal layer is disposed within the second interlayer insulating layer. The first metal layer includes a first interconnect electrically connected to the source / drain contact and the gate contact. The first interconnect extends parallel to each other in a second direction intersecting the first direction. A third interlayer insulating layer is disposed on the second interlayer insulating layer. A second metal layer is disposed within the third interlayer insulating layer.The second metal layer may include a second interconnect electrically connected to the first interconnect, and the second interconnect may extend parallel to each other in the first direction. A first portion of the first gate electrode may penetrate the first semiconductor pattern, and a first portion of the second gate electrode may penetrate the second semiconductor pattern. The first source / drain pattern may penetrate the upper portion of the first semiconductor pattern, and the second source / drain pattern may penetrate the upper portion of the second semiconductor pattern.

[0009] In another aspect, a multi-channel semiconductor-on-insulator (SOI) transistor is provided, comprising: a substrate having an electrically insulating layer and a semiconductor active layer located on the electrically insulating layer. A vertically stacked arrangement of spaced-apart insulated gate electrodes is also provided, the vertically stacked arrangement being buried within the semiconductor active layer. The vertically stacked arrangement includes a first insulated gate electrode extending adjacent to the electrically insulating layer and a (N-1)th insulated gate electrode spaced apart from a surface of the semiconductor active layer, where N is a positive integer greater than 2. The Nth insulated gate electrode is also disposed on the surface of the semiconductor active layer. Pairs of source / drain regions are disposed within the semiconductor active layer. These source / drain regions extend adjacent to opposite sides of the vertically stacked arrangement of the spaced-apart insulated gate electrodes. In some aspects of these aspects, the semiconductor active layer extends between the paired source / drain regions and the electrically insulating layer, with the first insulated gate electrode contacting the electrically insulating layer. Attached Figure Description

[0010] The inventive concept will become more readily understood in view of the accompanying drawings and detailed description.

[0011] Figure 1 This is a top view illustrating some embodiments of a semiconductor device according to the present invention.

[0012] Figure 2A , Figure 2B , Figure 2C and Figure 2D They are respectively along Figure 1 The cross-sectional views taken from lines A-A', B-B', C-C', and D-D'.

[0013] Figure 3A yes Figure 2A A magnified image of part of the letter "aa".

[0014] Figure 3B yes Figure 2B A magnified image of part of the "bb".

[0015] Figure 4A This corresponds to some embodiments of the concept of the present invention. Figure 2A A magnified image of part of the letter "aa".

[0016] Figure 4B This corresponds to some embodiments of the concept of the present invention. Figure 2B A magnified image of part of the "bb".

[0017] Figure 5A This corresponds to some embodiments of the concept of the present invention. Figure 2A A magnified image of part of the letter "aa".

[0018] Figure 5B This corresponds to some embodiments of the concept of the present invention. Figure 2B A magnified image of part of the "bb".

[0019] Figures 6A to 14C This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0020] Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 14A It corresponds to Figure 1 A cross-sectional view of line A-A'.

[0021] Figure 10B , Figure 11B , Figure 12B , Figure 13B and Figure 14B It corresponds to Figure 1 A cross-sectional view of line B-B'.

[0022] Figure 6B , Figure 7B , Figure 8B , Figure 10C , Figure 11C and Figure 12C It corresponds to Figure 1 A cross-sectional view of line C-C'.

[0023] Figure 6C , Figure 7C , Figure 8C , Figure 9B , Figure 12D , Figure 13C and Figure 14C It corresponds to Figure 1 A cross-sectional view of line D-D'.

[0024] Figures 15A to 15C This illustrates the formation of some embodiments based on the concept of the present invention. Figure 6A A cross-sectional view of the method of the sacrificial line.

[0025] Figure 16A and Figure 16B They are respectively along Figure 1 The cross-sectional views taken along lines A-A' and B-B' are used to illustrate semiconductor devices according to some embodiments of the concept of the present invention.

[0026] Figure 17A yes Figure 16A A magnified image of part of the "cc".

[0027] Figure 17B yes Figure 16B A magnified image of part of the "dd".

[0028] Figure 18A , Figure 18B and Figure 18C They are respectively along Figure 1 The cross-sectional views taken along lines A-A', B-B', and D-D' illustrate semiconductor devices according to some embodiments of the concept of the present invention. Detailed Implementation

[0029] Figure 1 This is a top view illustrating some embodiments of a semiconductor device according to the present invention, and Figure 2A , Figure 2B , Figure 2C and Figure 2D They are respectively along Figure 1 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'. Figure 1 In the text, some components have been omitted to clearly show the components shown.

[0030] Reference Figure 1 as well as Figures 2A to 2D The semiconductor device may include a support substrate 100, an insulating layer 101 on the support substrate 100, and a first semiconductor pattern 102a and a second semiconductor pattern 102b on the insulating layer 101. A portion of the top surface of the insulating layer 101 may be exposed through the first semiconductor pattern 102a and the second semiconductor pattern 102b.

[0031] The support substrate 100 may be a semiconductor substrate or a compound semiconductor substrate including silicon. For example, the support substrate 100 may be a silicon substrate. The insulating layer may be, for example, a silicon oxide layer. The first semiconductor pattern 102a and the second semiconductor pattern 102b may both be, for example, silicon layers. The support substrate 100, the insulating layer 101, and the first semiconductor pattern 102a and the second semiconductor pattern 102b may be part of a silicon-on-insulator (SOI) substrate. The top surface of the insulating layer 101 may be exposed through the first semiconductor pattern 102a and the second semiconductor pattern 102b. The first semiconductor pattern 102a and the second semiconductor pattern 102b may be spaced apart from each other in a first direction D1, with the exposed top surface of the insulating layer 101 located between the first semiconductor pattern 102a and the second semiconductor pattern 102b.

[0032] A logic cell LC can be disposed on a first semiconductor pattern 102a, a second semiconductor pattern 102b, and an insulating layer 101. Logic transistors for constituting a logic circuit can be disposed in the logic cell LC. The logic cell LC may include a PMOSFET region PR and an NMOSFET region NR. The PMOSFET region PR may be defined on the first semiconductor pattern 102a, and the NMOSFET region NR may be defined on the second semiconductor pattern 102b.

[0033] exist Figure 2A In this process, the first channel structure CH1 can be disposed on the first semiconductor pattern 102a. Figure 2B In this configuration, the second channel structure CH2 can be disposed on the second semiconductor pattern 102b. Both the first channel structure CH1 and the second channel structure CH2 can comprise a first channel pattern SP1, a second channel pattern SP2, and a third channel pattern SP3 stacked sequentially. The first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3 can be spaced apart from each other in the vertical direction (i.e., the third direction D3). The first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3 can all comprise, for example, silicon (Si).

[0034] exist Figure 2A In the first semiconductor pattern 102a, multiple first recesses RS1 can be disposed in the upper part. First source / drain patterns SD1 can be disposed in the first recesses RS1 respectively. The first source / drain patterns SD1 can be doped regions having a first conductivity type (e.g., P-type). A first channel structure CH1 can be disposed between pairs of first source / drain patterns SD1. The first channel pattern SP1, second channel pattern SP2, and third channel pattern SP3 of the first channel structure CH1 can electrically connect the pairs of first source / drain patterns SD1 to each other.

[0035] exist Figure 2BIn the second semiconductor pattern 102b, multiple second recesses RS2 can be disposed in the upper part. Second source / drain patterns SD2 can be disposed in the second recesses RS2 respectively. The second source / drain patterns SD2 can be doped regions having a second conductivity type (e.g., N-type). A second channel structure CH2 can be disposed between pairs of second source / drain patterns SD2. The first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3 of the second channel structure CH2 can electrically connect the pairs of second source / drain patterns SD2 to each other.

[0036] In some embodiments, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be disposed at substantially the same horizontal height as the top surface of the third channel pattern SP3. In some embodiments, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surface of the third channel pattern SP3.

[0037] The first source / drain pattern SD1 may include semiconductor elements (e.g., SiGe) with a lattice constant greater than that of the semiconductor elements in the first semiconductor pattern 102a. Therefore, the paired first source / drain patterns SD1 can provide compressive stress to the first channel structure CH1 therebetween, thereby improving device performance. The paired first source / drain patterns SD1 can each form a heterojunction with the first semiconductor pattern 102a.

[0038] For example, each first source / drain pattern SD1 may include a low-concentration silicon-germanium (SiGe) layer covering the inner surface of the first recess RS1 and a high-concentration silicon-germanium (SiGe) layer covering the low-concentration silicon-germanium (SiGe) layer. The volume ratio of the high-concentration silicon-germanium layer to the total volume of the first source / drain pattern SD1 may be greater than the volume ratio of the low-concentration silicon-germanium layer to the total volume of the first source / drain pattern SD1. In contrast, the second source / drain pattern SD2 may include the same semiconductor element (e.g., silicon) as the second semiconductor pattern 102b.

[0039] The gate electrode GE may intersect with the first semiconductor pattern 102a and the second semiconductor pattern 102b, and may extend in the first direction D1. The gate electrode GE may be arranged in the second direction D2 with a first pitch P1. Each gate electrode GE may vertically overlap with the first channel structure CH1 and the second channel structure CH2. As shown, the gate electrode GE may include a first portion PO1 disposed between the insulating layer 101 and the first channel pattern SP1, a second portion PO2 disposed between the first channel pattern SP1 and the second channel pattern SP2, a third portion PO3 disposed between the second channel pattern SP2 and the third channel pattern SP3, and a fourth portion PO4 located on the third channel pattern SP3. The first portion PO1 may be disposed in each of the first semiconductor pattern 102a and the second semiconductor pattern 102b. The first portion PO1 will be described in detail later.

[0040] Reference Figure 2D The gate electrode GE can be disposed on the top surface TS, bottom surface BS, and two sidewalls SW of each of the first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3. In other words, the logic transistor according to this embodiment can be a gate-all-around type field-effect transistor in which the gate electrode GE three-dimensionally surrounds the channel.

[0041] The gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3. The first metal pattern may include a work function metal for adjusting the threshold voltage of the logic transistor. The desired threshold voltage of the logic transistor can be obtained by adjusting the thickness and composition of the first metal pattern.

[0042] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). Additionally, the first metal pattern may also include carbon (C). In some embodiments, the first metal pattern may include a plurality of stacked work function metal layers. Furthermore, the second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0043] A gate insulating layer GI can be disposed between the gate electrode GE and the first channel structure CH1, and between the gate electrode GE and the second channel structure CH2. The gate insulating layer GI can cover the top surface TS, bottom surface BS, and two sidewalls SW of each of the first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3. The gate insulating layer GI can also be disposed between the gate electrode GE and the semiconductor patterns 102a and 102b. Specifically, the gate insulating layer GI can be disposed between the first portion PO1 of the gate electrode GE and each of the semiconductor patterns 102a and 102b. The gate insulating layer GI can cover the insulating layer 101 (see...). Figure 2D The gate insulating layer GI may include a high-k dielectric material. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0044] Reference Figure 2A and Figure 2B The paired gate spacers GS can be respectively disposed on the two sidewalls of the fourth part PO4 of the gate electrode GE. The gate spacers GS can be... Figure 1 The gate spacer GS extends along the gate electrode GE in a first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer insulating layer 110, which will be described later. The gate spacer GS may include at least one of SiCN, SiCON, or SiN. In some embodiments, each gate spacer GS may have a multilayer structure formed of at least two of SiCN, SiCON, or SiN.

[0045] A gate overlay pattern GP may be disposed on the gate electrode GE. The gate overlay pattern GP may extend along the gate electrode GE in a first direction D1. The gate overlay pattern GP may include a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described later. For example, the gate overlay pattern GP may include at least one of SiON, SiCN, SiCON, or SiN.

[0046] Reference Figure 2B The insulating pattern IP can be disposed on the NMOSFET region NR. The insulating pattern IP can be disposed between the second source / drain pattern SD2 and the second portion PO2 and the third portion PO3 of the gate electrode GE, respectively. The insulating pattern IP can be in direct contact with the second source / drain pattern SD2. The second portion PO2 and the third portion PO3 of the gate electrode GE can both be separated from the second source / drain pattern SD2 by the insulating pattern IP.

[0047] exist Figure 2C In this configuration, a first interlayer insulating layer 110 may be disposed on insulating layer 101. The first interlayer insulating layer 110 may cover the gate spacer GS, the first source / drain pattern SD1, and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate overlay pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 and the gate overlay pattern GP. For example, both the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may comprise a silicon oxide layer.

[0048] The source / drain contact AC can penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110, thereby electrically connecting to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The paired source / drain contacts AC can be respectively disposed on both sides of the gate electrode GE. When viewed in a top view, the source / drain contact AC can have a stripe extending in the first direction D1.

[0049] The source / drain contact AC can be a self-aligned contact. In other words, the source / drain contact AC can be formed as a self-aligned contact using a gate cover pattern GP and a gate spacer GS. For example, the source / drain contact AC can cover at least a portion of the sidewall of the gate spacer GS. Even if not shown in the figures, the source / drain contact AC can also cover a portion of the top surface of the gate cover pattern GP.

[0050] The silicide pattern SC can be disposed between the source / drain contact AC and the first source / drain pattern SD1, and between the source / drain contact AC and the second source / drain pattern SD2. The source / drain contact AC can be electrically connected to the source / drain pattern SD1 or SD2 through the silicide pattern SC. The silicide pattern SC can include metal silicides, and can include at least one of, for example, titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0051] The gate contact GC can penetrate the second interlayer insulating layer 120 and the gate cover pattern GP, ​​thereby electrically connecting to the gate electrode GE. For example, as... Figure 2B As shown, the upper region of each source / drain contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. Therefore, process defects caused by short circuits due to contact between the gate contact GC and the source / drain contact AC adjacent to the gate contact GC can be prevented.

[0052] Both the source / drain contact AC and the gate contact GC can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM can include at least one metal selected from aluminum, copper, tungsten, molybdenum, or cobalt. The barrier pattern BM can cover the bottom surface and sidewalls of the conductive pattern FM. The barrier pattern BM can include a metal layer and / or a metal nitride layer. The metal layer can include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer can include at least one selected from titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, nickel nitride (NiN) layer, cobalt nitride (CoN) layer, or platinum nitride (PtN) layer.

[0053] The first metal layer M1 can be disposed in the third interlayer insulating layer 130, which is disposed on the second interlayer insulating layer 120. The first metal layer M1 may include a first lower power interconnect M1_R1, a second lower power interconnect M1_R2, and a lower interconnect M1_I. The lower interconnect M1_I can be disposed between the first lower power interconnect M1_R2 and the second lower power interconnect M1_R2. Each lower interconnect M1_I may have a linear or strip shape extending in the second direction D2.

[0054] The first metal layer M1 may further include a lower path VI1. The lower path VI1 may be disposed below the interconnects M1_R1, M1_R2, and M1_I of the first metal layer M1. Some lower paths VI1 may be disposed between the source / drain contact AC and the corresponding interconnects M1_R1, M1_R2, and M1_I of the first metal layer M1, respectively. Other lower paths VI1 may be disposed between the gate contact GC and the corresponding interconnects M1_R1, M1_R2, and M1_I of the first metal layer M1, respectively.

[0055] The second metal layer M2 can be disposed within the fourth interlayer insulating layer 140, which is disposed on the third interlayer insulating layer 130. The second metal layer M2 may include an upper interconnect M2_I. (See reference...) Figure 2B and Figure 2C Each upper interconnect M2_I of the second metal layer M2 may have a linear or strip shape extending in the first direction D1. In other words, the upper interconnects M2_I may extend parallel to each other in the first direction D1. The second metal layer M2 may also include an upper pass VI2. The upper pass VI2 may be disposed below the upper interconnect M2_I. The upper pass VI2 may be disposed between the upper interconnect M2_I and the interconnects M1_R1, M1_R2 and M1_I of the first metal layer M1.

[0056] The interconnects of the first metal layer M1 and the second metal layer M2 may comprise the same or different conductive materials. For example, the interconnects of both the first metal layer M1 and the second metal layer M2 may comprise at least one metallic material selected from the group consisting of aluminum, copper, tungsten, molybdenum, and cobalt. Even if not shown in the figures, stacked metal layers (e.g., M3, M4, M5, etc.) may be additionally disposed on the fourth interlayer insulating layer 140. Each stacked metal layer may comprise wiring interconnects.

[0057] Figure 3A yes Figure 2A A magnified image of part of the letter "aa". Figure 3B yes Figure 2B A magnified image of part of the "bb" character. (See reference) Figure 3A and Figure 3B The first portion PO1 of the gate electrode GE can be disposed in each semiconductor pattern 102a and 102b. The first portion PO1 of the gate electrode GE can correspond to the bottommost portion of the gate electrode GE. The first portion PO1 of the gate electrode GE can penetrate each semiconductor pattern 102a and 102b.

[0058] Reference Figure 3A The first portion PO1 of the gate electrode GE may have a bottom surface L1 and a top surface L2 opposite to each other between the insulating layer 101 and the first channel pattern SP1. The horizontal height of the bottom surface L1 of the first portion PO1 may be lower than the horizontal height of the bottom surface B1 of the first source / drain pattern SD1. The horizontal height of the top surface L2 of the first portion PO1 of the gate electrode GE may be higher than the horizontal height of the bottom surface B1 of the first source / drain pattern SD1. In other words, the horizontal height of the bottom surface B1 of the first source / drain pattern SD1 may be between the horizontal height of the bottom surface L1 and the horizontal height of the top surface L2 of the first portion PO1.

[0059] The horizontal height of the bottom surface B2 of the second source / drain pattern SD2 can also be located between the horizontal height of the bottom surface L1 and the top surface L2 of the first part PO1 (see...). Figure 3B ).

[0060] The thickness H1 of the first part PO1 may differ from the thickness H2 of the second part PO2 and the thickness H3 of the third part PO3. The thickness H1 of the first part PO1 may be greater than the thickness H2 of the second part PO2 and the thickness H3 of the third part PO3. The thickness H1 of the first part PO1 may be within 200% to 300% of each of the thickness H2 of the second part PO2 and the thickness H3 of the third part PO3.

[0061] exist Figure 3AIn this configuration, the gate insulating layer GI surrounding the second portion PO2 and the third portion PO3 of the gate electrode GE may contact the first source / drain pattern SD1. The gate insulating layer GI surrounding the first portion PO1 of the gate electrode GE may not contact the first source / drain pattern SD1. The gate insulating layer GI surrounding the first portion PO1 may be spaced apart from the first source / drain pattern SD1, with the first semiconductor pattern 102a positioned between them.

[0062] exist Figure 3B In this configuration, the insulating pattern IP can be disposed between each of the second portion PO2 and the third portion PO3 and the second source / drain pattern SD2, but the insulating pattern IP may not be disposed between the first portion PO1 and the second source / drain pattern SD2. The first portion PO1 may be spaced apart from the second source / drain pattern SD2 in the second direction D2, with the second semiconductor pattern 102b situated between them.

[0063] exist Figure 3A and Figure 3B In the PMOSFET region PR, the width of the first portion PO1 of the gate electrode GE in the second direction D2 can be substantially equal to the width of the first portion PO1 of the gate electrode GE in the second direction D2 of the NMOSFET region NR. Conversely, the width of the second portion PO2 of the gate electrode GE in the PMOSFET region PR in the second direction D2 can be different from the width of the second portion PO2 of the gate electrode GE in the second direction D2 of the NMOSFET region NR. The width of the third portion PO3 of the gate electrode GE in the PMOSFET region PR in the second direction D2 can also be different from the width of the third portion PO3 of the gate electrode GE in the second direction D2 of the NMOSFET region NR. Furthermore, the distance from the insulating layer 101 to each source / drain pattern SD1 and SD2 in the third direction D3 can be greater than the distance from the insulating layer 101 to the first portion PO1 of the gate electrode GE in the third direction D3.

[0064] According to an embodiment of the invention, semiconductor patterns 102a and 102b may not be disposed below the first portion PO1 corresponding to the lowest portion of the gate electrode GE. As a result, no channel may be formed below the first portion PO1, thus preventing leakage current from flowing below the gate electrode GE (e.g., preventing punch-through effect).

[0065] Furthermore, according to an embodiment of the present invention, the bottom surfaces B1 and B2 of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located at a horizontal height between the bottom surface L1 and the top surface L2 of the first portion PO1 of the gate electrode GE, thereby improving the reliability of the device. Specifically, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be spaced apart from the insulating layer 101 on a third-direction D3, with semiconductor patterns 102a and 102b interposed therebetween. When the source / drain patterns SD1 and SD2 are epitaxially grown from the semiconductor patterns 102a and 102b along the third-direction D3, as will be discussed later... Figures 11A to 11C As described above, no stacking failures will occur, thus improving reliability. If epitaxial growth is performed from insulating layer 101, stacking defects may occur in the first source / drain pattern SD1, and the compressive stress applied to the first channel structure CH1 may be reduced. In this case, the reliability of the device may deteriorate.

[0066] Figure 4A This corresponds to some embodiments of the concept of the present invention. Figure 2A A magnified image of part of the letter "aa". Figure 4B This corresponds to some embodiments of the concept of the present invention. Figure 2B A magnified image of part of the "bb". For the sake of brevity and convenience, the details of the part will be omitted in the following text. Figure 3A and Figure 3B The same features are described in the embodiments.

[0067] Reference Figure 4A The width W1 of the first portion PO1 of the gate electrode GE in the second direction D2 can increase with the increase of the height from the insulating layer 101 in the third direction D3. The gate insulating layer GI surrounding the first portion PO1 can contact the first source / drain pattern SD1. In some embodiments, the gate insulating layer GI surrounding the first portion PO1 may not contact the first source / drain pattern SD1. (This will be discussed later in...) Figures 13A to 13C When etching the upper part of the first semiconductor pattern 102a surrounding the first sacrificial pattern 200P in the etching process described herein, the width W1 of the first portion PO1 of the gate electrode GE in this embodiment in the second direction D2 can be increased.

[0068] Reference Figure 4B The insulating pattern IP can be disposed between the first portion PO1 of the gate electrode GE and the second source / drain pattern SD2. (This will be discussed later.) Figures 13A to 13C When etching the upper part of the second semiconductor pattern 102b surrounding the first sacrificial pattern 200P in the process described herein, the insulating pattern IP can be set in the upper part of the etched second semiconductor pattern 102b.

[0069] Figure 5A This corresponds to some embodiments of the concept of the present invention. Figure 2A A magnified image of part of the letter "aa". Figure 5B This corresponds to some embodiments of the concept of the present invention. Figure 2B A magnified image of part of the "bb". For the sake of brevity and convenience, the details of the part will be omitted in the following text. Figure 3A and Figure 3B The same features are described in the embodiments.

[0070] Reference Figure 5A and Figure 5B The thickness H1 of the first part PO1 can be smaller than the thickness H2 of the second part PO2 and the thickness H3 of the third part PO3. Figure 5A In the first source / drain pattern SD1, the width W1 of the first portion PO1 in the second direction D2 can be greater than the width W2 of the second portion PO2 in the second direction D2 and the width W3 of the third portion PO3 in the second direction D2. Figure 5B In the second source / drain pattern SD2, the width J1 of the first part PO1 in the second direction D2 can be greater than the width J2 of the second part PO2 in the second direction D2 and the width J3 of the third part PO3 in the second direction D2.

[0071] Figures 6A to 14C This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 14A It corresponds to Figure 1 A cross-sectional view of line A-A'. Figure 10B , Figure 11B , Figure 12B , Figure 13B and Figure 14B It corresponds to Figure 1 A cross-sectional view of line B-B'. Figure 6B , Figure 7B , Figure 8B , Figure 10C , Figure 11C and Figure 12C It corresponds to Figure 1 A cross-sectional view of line C-C'. Figure 6C , Figure 7C , Figure 8C , Figure 9B , Figure 12D , Figure 13C and Figure 14C It corresponds to Figure 1 A cross-sectional view of the D-D' line.

[0072] Reference Figure 6A , Figure 6B and Figure 6C The system may provide a support substrate 100, an insulating layer 101, and a semiconductor layer 102. Sacrificial lines 200L may be formed in the semiconductor layer 102. The sacrificial lines 200L may comprise germanium (Ge) or silicon germanium (SiGe). The sacrificial lines 200L may have a linear shape extending in a first direction D1. The sacrificial lines 200L may be spaced apart from each other in a second direction D2.

[0073] Reference Figure 7A , Figure 7B and Figure 7C Alternating stacked active layers ACL and sacrificial layers SAL can be formed on the support substrate 100. The active layers ACL may include silicon (Si), and the sacrificial layers SAL may include germanium (Ge) or silicon-germanium (SiGe). As an example, three active layers ACL and two sacrificial layers SAL are shown. In some embodiments, the number of alternating stacked active layers ACL and sacrificial layers SAL may vary. In the figures, the bottommost active layer ACL1 is formed directly on the semiconductor layer 102. Alternatively, in some embodiments, a sacrificial layer SAL may be additionally formed between the semiconductor layer 102 and the bottommost active layer ACL1 (see Figure 1). Figure 16A and Figure 16B In this scenario, three sacrificial layers (SAL) and three active layers (ACL) can be formed.

[0074] A mask pattern MAP can be formed on each of the PMOSFET region PR and the NMOSFET region NR. The mask pattern MAP can have a line or strip shape extending in a second direction D2. For example, the mask pattern MAP can include silicon nitride.

[0075] Reference Figure 8A , Figure 8B and Figure 8C Patterning processes can be performed on the sacrificial layer SAL, active layer ACL, semiconductor layer 102, and sacrificial line 200L using a mask pattern (MAP) as an etching mask. A first semiconductor pattern 102a and a second semiconductor pattern 102b can be formed from semiconductor layer 102 through the patterning process. The second semiconductor pattern 102b can be substantially identical to the first semiconductor pattern 102a, thus omitting the pattern along... Figure 1A cross-sectional view taken from line B-B'. The first semiconductor pattern 102a and the second semiconductor pattern 102b can be formed on the PMOSFET region PR and the NMOSFET region NR, respectively. Through patterning processes, patterns can be formed from the sacrificial line 200L, the active layer ACL, and the sacrificial layer SAL, respectively. Figure 8C The first sacrificial pattern 200P, the active pattern ACP, and the second sacrificial pattern SAP are shown. A portion of the top surface of the insulating layer 101 can be exposed through a patterning process.

[0076] Reference Figure 9A and Figure 9B A third sacrificial pattern PP, intersecting with the first semiconductor pattern 102a and the second semiconductor pattern 102b, can be formed on the insulating layer 101. Each third sacrificial pattern PP can have a line or strip shape extending in a first direction D1. The third sacrificial patterns PP can be arranged at a predetermined pitch in a second direction D2. For example, forming the third sacrificial pattern PP may include: forming a sacrificial layer on the entire top surface of the support substrate 100; forming a hard mask pattern MP on the sacrificial layer; and using the hard mask pattern MP as an etching mask to pattern the sacrificial layer. The sacrificial layer may include polysilicon.

[0077] Pairs of gate spacers GS can be formed on the two sidewalls of each third sacrificial pattern PP. The formation of the gate spacers GS may include conformally forming a gate spacer layer on the support substrate 100 and anisotropically etching the gate spacer layer. For example, the gate spacer layer may include at least one of SiCN, SiCON, or SiN. In some embodiments, the gate spacer layer may be formed from a multilayer comprising at least two of SiCN, SiCON, or SiN.

[0078] Reference Figures 10A to 10C A first recess RS1 can be formed in the upper portion of the first semiconductor pattern 102a. A second recess RS2 can be formed in the upper portion of the second semiconductor pattern 102b. For example, a hard mask pattern MP and a gate spacer GS can be used as etching masks to etch the active pattern ACP, the second sacrificial pattern SAP, the upper portion of the first semiconductor pattern 102a, and the upper portion of the second semiconductor pattern 102b. The first recess RS1 can be formed between a pair of third sacrificial patterns PP. A first channel structure CH1 can be formed from the active pattern ACP by forming the first recess RS1.

[0079] The first channel structures CH1 can be spaced apart from each other in the second direction D2 and can be formed below the third sacrificial pattern PP. The first recess RS1 may not expose the insulating layer 101. An etching process for forming the first recess RS1 can be performed until the bottom surface of the first recess RS1 is at a horizontal height between the top and bottom surfaces of the first sacrificial pattern 200P. The second recess RS2 can be formed by the same method as the first recess RS1 described above.

[0080] exist Figure 10A and Figure 10B In some embodiments, the first sacrificial pattern 200P may not need to be etched. In some embodiments, when the width of the first sacrificial pattern 200P in the second direction D2 is greater than the width of the second sacrificial pattern SAP in the second direction D2, the upper edge portion of the first sacrificial pattern 200P may also be etched.

[0081] The second recess RS2 on the upper part of the second semiconductor pattern 102b can be formed using the same method as the first recess RS1 described above. The second channel structure CH2 can be formed from the active pattern ACP by forming the second recess RS2. The second channel structures CH2 can be spaced apart from each other in the second direction D2 and can be formed below the third sacrificial pattern PP respectively.

[0082] Reference Figures 11A to 11C A first source / drain pattern SD1 can be formed in the first recess RS1. A second source / drain pattern SD2 can be formed in the second recess RS2. The formation of the first source / drain pattern SD1 can be performed independently of the formation of the second source / drain pattern SD2. The formation of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be performed using a selective epitaxial growth (SEG) process. For example, the SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0083] The formation of the first source / drain pattern SD1 may include performing a SEG process using a first semiconductor pattern 102a and first channel patterns SP1, second channel patterns SP2, and third channel patterns SP3 as seed layers. Specifically, since the first recess RS1 does not expose the insulating layer 101 in the embodiments of the present invention, the first semiconductor pattern 102a can be used as a seed layer. Therefore, the first source / drain pattern SD1 can be grown in a

[100] direction parallel to the third direction D3, where crystal formation and crystal growth are advantageous. When the first source / drain pattern SD1 is grown in the

[100] direction, stacking defects of the first source / drain pattern SD1 can be reduced.

[0084] The first source / drain pattern SD1 can be formed from a material capable of providing compressive stress to the first channel structure CH1. For example, the first source / drain pattern SD1 can be formed from a semiconductor element (e.g., SiGe) with a lattice constant greater than that of the semiconductor element in the first semiconductor pattern 102a. The first source / drain pattern SD1 can be doped with a P-type dopant during (or after) the SEG process.

[0085] The formation of the second source / drain pattern SD2 may include performing a SEG process using the second semiconductor pattern 102b and the first channel pattern SP1, second channel pattern SP2, and third channel pattern SP3 on the second semiconductor pattern 102b as seed layers. For example, the second source / drain pattern SD2 may be formed from the same semiconductor element (e.g., silicon) as the second semiconductor pattern 102b. The second source / drain pattern SD2 may be doped with an N-type dopant during or after the SEG process.

[0086] Reference Figures 12A to 12D A first interlayer insulating layer 110 can be formed to cover a first source / drain pattern SD1, a second source / drain pattern SD2, a hard mask pattern MP, and a gate spacer GS. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0087] The first interlayer insulating layer 110 can be planarized until the top surface of the third sacrificial pattern PP is exposed. The planarization process of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask pattern MP can be completely removed during the planarization process. As a result, the top surface of the first interlayer insulating layer 110 can be substantially coplanar with the top surface of the third sacrificial pattern PP and the top surface of the gate spacer GS. Next, the exposed third sacrificial pattern PP can be selectively removed. The removal of the third sacrificial pattern PP can form the first blanking space ET1 of the exposed channel structures CH1 and CH2, the first sacrificial pattern 200P, and the second sacrificial pattern SAP (see...). Figure 12D ).

[0088] Reference Figures 13A to 13C The first sacrificial pattern 200P and the second sacrificial pattern SAP exposed through the first blank space ET1 can be selectively removed. An etching process that selectively etches the first sacrificial pattern 200P and the second sacrificial pattern SAP can be performed to remove only the first sacrificial pattern 200P and the second sacrificial pattern SAP, while leaving the first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3. The etching process can be a wet etching process.

[0089] Compared to silicon-germanium with a relatively high germanium concentration, the etching process can achieve a high etching rate. During the removal of the second sacrificial pattern SAP, the low-concentration silicon-germanium layer of the first source / drain pattern SD1 prevents the etchant from penetrating into and etching the high-concentration silicon-germanium layer. The etchant used in the etching process can quickly remove the first sacrificial pattern 200P and the second sacrificial pattern SAP with a relatively high germanium concentration, but may not remove most of the low-concentration silicon-germanium layer of the first source / drain pattern SD1 with a relatively low germanium concentration. The first sacrificial pattern 200P and the second sacrificial pattern SAP on the NMOSFET region NR can also be removed during the etching process. Meanwhile, the second source / drain pattern SD2 may contain silicon (Si) but not germanium, so the second source / drain pattern SD2 may not be removed but can be retained during the etching process. Due to the selective removal of the first sacrificial pattern 200P and the second sacrificial pattern SAP, the first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3 can be retained on each of the first semiconductor pattern 102a and the second semiconductor pattern 102b.

[0090] The second blanking space ET2 and the third blanking space ET3 can be formed by removing the first sacrificial pattern 200P and the second sacrificial pattern SAP, respectively. The second blanking space ET2 can be defined between the exposed inner surfaces of the first channel pattern SP1 and each of the semiconductor patterns 102a and 102b. The third blanking space ET3 can be defined between the first channel pattern SP1 and the second channel pattern SP2, and between the second channel pattern SP2 and the third channel pattern SP3.

[0091] Reference Figures 14A to 14C A gate insulating layer GI can be conformally formed in the first blank space ET1, the second blank space ET2, and the third blank space ET3. For example, an interface layer can be formed on the exposed surfaces of the first channel pattern SP1, the second channel pattern SP2, and the third channel pattern SP3, as well as on the exposed inner surfaces of the first semiconductor pattern 102a and the second semiconductor pattern 102b. The interface layer can be formed by a thermal oxidation process. A high-k dielectric layer can be conformally formed on the interface layer. The high-k dielectric layer can cover the interface layer. The interface layer and the high-k dielectric layer can constitute the gate insulating layer GI.

[0092] A gate electrode GE can be formed in the first empty space ET1, the second empty space ET2, and the third empty space ET3. The gate electrode GE may include a first portion PO1 filling the second empty space ET2. The gate electrode GE may include a second portion PO2 and a third portion PO3 filling the third empty space ET3, respectively. The gate electrode GE may also include a fourth portion PO4 filling the first empty space ET1. A gate overlay pattern GP can be formed on the gate electrode GE.

[0093] Simultaneously, before forming the gate insulating layer GI, an insulating pattern IP can be formed on the NMOSFET region NR. The insulating pattern IP can be formed as a part filling the third blank space ET3. Therefore, the second portion PO2 and the third portion PO3 of the gate electrode GE on the NMOSFET region NR can be spaced apart from the second source / drain pattern SD2, with the insulating pattern IP between them.

[0094] Refer again Figure 1 as well as Figures 2A to 2D A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. Source / drain contacts AC may be formed in the second interlayer insulating layer 120 and the first interlayer insulating layer 110. The source / drain contacts AC may penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110, thereby electrically connecting to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC may be formed. The gate contact GC may penetrate the second interlayer insulating layer 120 and the gate overlay pattern GP, ​​thereby electrically connecting to the gate electrode GE.

[0095] A third interlayer insulating layer 130 may be formed on the source / drain contact AC, the gate contact GC, and the second interlayer insulating layer 120. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0096] Figures 15A to 15C It is shown in Figure 6A A cross-sectional view of the method for forming sacrificial lines 200L in semiconductor layer 102. Figures 15A to 15C It corresponds to Figure 1 The cross-sectional view of line A-A'. (Refer to...) Figure 15A The system may provide a support substrate 100, an insulating layer 101 on the support substrate 100, and a semiconductor layer 102 on the insulating layer 101. The semiconductor layer 102 may be, for example, silicon-on-insulator (SOI). The thickness T1 of the semiconductor layer 102 may be related to the thickness of the first portion PO1 of the gate electrode GE.

[0097] In other words, when the thickness T1 of semiconductor layer 102 is greater than Figure 7A When determining the thickness of each sacrificial layer SAL, the thickness of the first part PO1 can be greater than the thicknesses of the second part PO2 and the third part PO3 (see [reference]). Figure 3A , Figure 3B , Figure 4A and Figure 4B When the thickness T1 of semiconductor layer 102 is less than Figure 7A When determining the thickness of each sacrificial layer SAL, the thickness of the first part PO1 can be less than the thicknesses of the second part PO2 and the third part PO3 (see [reference]). Figure 5A and Figure 5B ).

[0098] A sacrificial semiconductor layer 200 can be formed on the semiconductor layer 102. The sacrificial semiconductor layer 200 can be a silicon-germanium (SiGe) layer. The thickness T2 of the sacrificial semiconductor layer 200 can be greater than the thickness T1 of the semiconductor layer 102.

[0099] A mask pattern 300 may be formed on the sacrificial semiconductor layer 200. The mask pattern 300 may have a linear shape extending in a first direction D1. The mask patterns 300 may be spaced apart from each other in a second direction D2 to define an opening OP between them. The mask pattern 300 may include, for example, silicon nitride. The mask pattern 300 may be formed by, for example, a double patterning process. The width of the first portion PO1 of the gate electrode GE may be determined based on the width of the opening OP in the second direction D2.

[0100] Reference Figure 15B Oxygen can be injected into the exposed portion of the sacrificial semiconductor layer 200 through an opening OP during a heat treatment process performed at high temperature. In this process, silicon from semiconductor layer 102 can diffuse into the sacrificial semiconductor layer 200, and germanium from the sacrificial semiconductor layer 200 can diffuse into semiconductor layer 102. In the sacrificial semiconductor layer 200, silicon can react with oxygen to form a silicon oxide pattern 400 corresponding to the opening OP. Sacrificial lines 200L corresponding to the opening OP can be formed in semiconductor layer 102. Sacrificial lines 200L can include germanium or silicon-germanium. The amount of germanium per unit volume in sacrificial lines 200L can be greater than the amount of germanium per unit volume in the sacrificial semiconductor layer 200 (Ge condensation).

[0101] Reference Figure 15C The silicon oxide pattern 400 can be selectively removed, for example, by a wet etching process. Next, the mask pattern 300 can be removed, for example, by a stripping process. See again... Figure 6A The sacrificial semiconductor layer 200 can be removed. The sacrificial semiconductor layer 200 can be removed by, for example, a planarization process (e.g., CMP process). As a result, the top surface of the sacrificial line 200L and the top surface of the semiconductor layer 102 can be exposed.

[0102] Figure 16A and Figure 16B They are respectively along Figure 1 The cross-sectional views taken along lines A-A' and B-B' are used to illustrate semiconductor devices according to some embodiments of the concept of the present invention. Figure 17A yes Figure 16A A magnified image of part of the "cc". Figure 17B yes Figure 16B A magnified image of part of the "dd" symbol. For the sake of brevity and convenience, the parts related to "dd" will be omitted in the following text. Figures 2A to 2D The same features are described in the embodiments.

[0103] Reference Figure 16A and Figure 17A The first portion PO1 of the gate electrode GE on the PMOSFET region PR may further include a first extension EL1 extending along the top surface 102U of the first semiconductor pattern 102a. In other words, the first portion PO1 of the gate electrode GE may include a lower portion BL disposed in the first semiconductor pattern 102a and a first extension EL1 disposed on the top surface 102U of the first semiconductor pattern 102a. The width of the first extension EL1 in the second direction D2 may be greater than the width of the lower portion BL in the second direction D2.

[0104] The first extension EL1 can be disposed between the first source / drain patterns SD1. The gate insulating layer GI covering the first extension EL1 can contact the first source / drain patterns SD1. The edge portion of the first extension EL1 can be vertically spaced from the insulating layer 101, and the first semiconductor pattern 102a is located between them.

[0105] Reference Figure 16B and Figure 17B The first portion PO1 of the gate electrode GE on the NMOSFET region NR may further include a second extension EL2 protruding from the top surface 102T of the second semiconductor pattern 102b. In other words, the first portion PO1 of the gate electrode GE may include a lower portion BL disposed in the second semiconductor pattern 102b and a second extension EL2 protruding from the top surface 102T of the second semiconductor pattern 102b. The second extension EL2 may be disposed between the second source / drain pattern SD2. An insulating pattern IP may be disposed between the second extension EL2 and the second source / drain pattern SD2.

[0106] When forming Figures 7A to 7C When a sacrificial layer SAL is formed on semiconductor layer 102 before the bottom active layer ACL1, it can form Figure 16A , Figure 16B , Figure 17A and Figure 17BThe structure of the embodiment. In this case, the second sacrificial pattern SAP can be directly formed on... Figure 12A and Figure 12B The first sacrifice pattern in the picture is on 200P, therefore. Figure 13A and Figure 13B The shape of the second blank space ET2 in the middle can be changed.

[0107] Figure 18A , Figure 18B and Figure 18C They are respectively along Figure 1 The cross-sectional views taken along lines A-A', B-B', and D-D' illustrate semiconductor devices according to some embodiments of the present invention. In the following text, for the sake of brevity and convenience, the details of the cross-sections are omitted. Figures 2A to 2D The same features are described in the embodiments.

[0108] Reference Figures 18A to 18C According to this embodiment, both the first channel structure and the second channel structure may include a single channel pattern SP. The thickness of the channel pattern SP may be greater than the thickness of the first portion PO1 of the gate electrode GE. The gate electrode GE may include a first portion PO1 disposed between the insulating layer 101 and the channel pattern SP and a second portion PO2 located on the channel pattern SP. The gate electrode GE may surround the four surfaces of the single channel pattern SP to form a surrounding gate structure.

[0109] Reference Figures 7A to 7C Instead of alternating active layer ACL and sacrificial layer SAL on semiconductor layer 102, a single active layer ACL can be grown to a horizontal height corresponding to the top surface of the uppermost active layer ACL. Subsequent processes can be similar to those described above. Figures 8A to 14C The described process.

[0110] The semiconductor device according to the present invention can be fabricated using a silicon-on-insulator (SOI) substrate, and therefore the gate electrode can be directly disposed on the buried insulating layer. In this case, a channel does not need to be formed below the bottom portion of the gate electrode, thus preventing leakage current through fine patterning. Furthermore, the source / drain patterns can be spaced apart from the buried insulating layer, thereby reducing or minimizing stacking defects in the formation of the source / drain patterns to improve the reliability and electrical characteristics of the semiconductor device.

[0111] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Consequently, the scope of the inventive concept will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be limited or restricted by the foregoing description.

Claims

1. A semiconductor device, comprising: Electrical insulation layer; A semiconductor pattern that extends on and contacts the electrically insulating layer; Paired source / drain patterns that extend into the semiconductor pattern; A channel structure extending between the paired source / drain patterns, the channel structure comprising a stack of channel patterns spaced apart from each other; and A gate electrode extending in the space between the channel patterns, the gate electrode including a first gate portion extending between the channel structure and the electrical insulating layer, and the bottom surface of the first gate portion extending closer to the electrical insulating layer relative to the bottommost surface of each of the paired source / drain patterns.

2. The semiconductor device according to claim 1, wherein, The bottom surface of each of the paired source / drain patterns extends closer to the electrical insulation layer relative to the bottom surface of the channel structure.

3. The semiconductor device according to claim 1, wherein, The bottom surface of each of the paired source / drain patterns extends closer to the electrical insulating layer relative to the top surface of the first gate portion.

4. The semiconductor device according to claim 1, wherein, The first gate portion is separated from the channel structure by a gate insulating layer that surrounds at least a portion of the first gate portion and contacts the electrical insulating layer.

5. The semiconductor device according to claim 1, wherein, The stack of the channel patterns includes a first channel pattern and a second channel pattern; wherein the first gate portion extends between the electrically insulating layer and the first channel pattern; and wherein the gate electrode further includes a second gate portion extending between the first channel pattern and the second channel pattern.

6. The semiconductor device according to claim 1, wherein, The paired source / drain patterns form heterojunctions with the semiconductor pattern, respectively.

7. The semiconductor device according to claim 6, wherein, The paired source / drain patterns include SiGe; and wherein the semiconductor pattern includes single-crystal silicon.

8. The semiconductor device according to claim 1, wherein, The electrically insulating layer extends on the semiconductor substrate; and wherein the semiconductor pattern, the electrically insulating layer, and the semiconductor substrate together define a semiconductor substrate on an insulator.

9. A semiconductor device, comprising: Support substrate; An insulating layer located on the supporting substrate; A semiconductor pattern, wherein the semiconductor pattern is located on the insulating layer and is in contact with the insulating layer; Pairs of source / drain patterns, the pairs of source / drain patterns being located on the semiconductor pattern; A channel structure disposed between the paired source / drain patterns, the channel structure comprising channel patterns stacked and spaced apart from each other; and A gate electrode that intersects with the channel structure and extends in a first direction. The gate electrode includes a first portion disposed between the channel structure and the insulating layer, and The bottom surface of the first part is at a lower level than the bottom surface of the source / drain pattern.

10. The semiconductor device according to claim 9, wherein, The horizontal height of the bottom surface of the source / drain pattern is lower than the horizontal height of the bottom surface of the channel structure.

11. The semiconductor device according to claim 9, further comprising: A gate insulating layer, wherein the gate insulating layer is located between the gate electrode and the channel structure. The gate insulating layer is in contact with the insulating layer.

12. The semiconductor device according to claim 9, wherein, The channel pattern includes a first channel pattern and a second channel pattern stacked sequentially. The first portion is disposed between the insulating layer and the first channel pattern. The gate electrode further includes a second portion disposed between the first channel pattern and the second channel pattern. Wherein, the first portion of the gate electrode is located below the lowermost channel pattern in the channel pattern, and The first portion of the gate electrode penetrates the semiconductor pattern.

13. The semiconductor device according to claim 12, wherein, The bottom surface of the source / drain pattern is located at a horizontal height between the top surface of the first portion and the bottom surface of the first portion.

14. The semiconductor device according to claim 12, wherein, The thickness of the first part is greater than the thickness of the second part.

15. The semiconductor device according to claim 14, wherein, The thickness of the first portion is 200% to 300% of the thickness of the second portion.

16. The semiconductor device according to claim 12, wherein, The width of the first portion in the horizontal direction increases from the insulating layer toward the first channel pattern.

17. The semiconductor device according to claim 12, wherein, The thickness of the first part is less than the thickness of the second part.

18. The semiconductor device according to claim 12, wherein, The first portion further includes an extension that extends to and covers the top surface of the semiconductor pattern. The extension is disposed between the source / drain patterns, and The portion of the extension adjacent to the source / drain pattern is spaced apart from the insulating layer, and the semiconductor pattern is located between the portion of the extension and the insulating layer.

19. A semiconductor device, comprising: Support substrate; An insulating layer located on the supporting substrate; A semiconductor pattern disposed on and in contact with the insulating layer; Pairs of source / drain patterns, the pairs of source / drain patterns being located on the semiconductor pattern; A channel structure disposed between the paired source / drain patterns, the channel structure including at least one channel pattern; and A gate electrode that intersects the channel structure and extends in a first direction. The gate electrode includes a portion disposed between the insulating layer and the lowermost portion of the channel structure, and the portion penetrates the semiconductor pattern. Wherein, the lower part of the source / drain pattern is located within the semiconductor pattern, and The source / drain pattern is spaced apart from the insulating layer, and the semiconductor pattern is located between the source / drain pattern and the insulating layer.

20. The semiconductor device according to claim 19, wherein, The distance from the insulating layer to the source / drain pattern is greater than the distance from the insulating layer to the gate electrode.

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