Display device and method of manufacturing the same

Abstract

A display apparatus and a method of manufacturing a display apparatus are disclosed. A display apparatus according to an embodiment of the disclosure can include a base layer including a first surface and a second surface; a pixel circuit layer including a first wire on the first surface; a display element layer on the pixel circuit layer and including a display element; a thin film encapsulation layer on the display element layer; a first protection layer on the thin film encapsulation layer; and a second wire on the second surface to correspond to the first wire. The first protection layer can include a transparent insulating material.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0096338, filed on July 31, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to pixels and display devices, as well as methods of manufacturing display devices. Background Technology

[0004] With increasing interest in information display and growing demand for portable information media, the need for and commercialization of display devices (which can display information and / or are portable) is gaining attention. Summary of the Invention

[0005] This disclosure relates to a protective layer for protecting a display panel.

[0006] A display device according to an embodiment of the present disclosure includes: a base layer including a first surface and a second surface; a pixel circuit layer including a first line on the first surface; a display element layer located on the pixel circuit layer and including a display element; a thin film encapsulation layer located on the display element layer; a first protective layer located on the thin film encapsulation layer; and a second line located on the second surface corresponding to the first line. The first protective layer includes (e.g., a) a transparent insulating material.

[0007] The first protective layer may include (for example) molybdenum oxide (MoO3) or silicon oxide (SiO2). x ).

[0008] The display element layer may include light-emitting elements, and the light-emitting elements may include organic light-emitting diodes or inorganic light-emitting diodes.

[0009] The display device may also include a light conversion layer located between the display element layer and the thin-film encapsulation layer.

[0010] The light conversion layer may include a color conversion layer and a color filter. The color conversion layer is on the light-emitting element and includes color conversion particles that convert a first color light emitted by the light-emitting element into a second color light. The color filter is located on the display element layer or the color conversion layer.

[0011] The pixel circuit layer may include multiple insulating layers and at least one transistor. The at least one transistor may include: a first semiconductor layer located on a first surface of the base layer and including a channel region, a source region, and a drain region; a gate electrode positioned to overlap with the channel region; and a source electrode and a drain electrode respectively connected (e.g., connected) to the source region and the drain region. The multiple insulating layers may include: a gate insulating layer located between the first semiconductor layer and the gate electrode; and a first interlayer insulating layer located on the gate electrode.

[0012] The first line may include at least one selected from a first gate line located on the same layer as the gate electrode and a first data line located on the same layer as the source electrode or drain electrode.

[0013] The second line may include at least one selected from a second gate line and a second data line, wherein the second gate line is electrically connected (e.g., connected) to the first gate line through a base hole through the base layer, and the second data line is electrically connected (e.g., connected) to the first data line through a base hole.

[0014] The base hole can be filled with a conductive material, and the first and second wires can be physically and electrically connected (e.g., connected) to each other through the conductive material.

[0015] The display device may also include a lower protective layer that is entirely located on the second surface including the second line and exposes a portion of the second line in a predetermined or defined area (e.g., a defined area of ​​the lower protective layer).

[0016] The display device may also include a connecting film that contacts the portion of the second line exposed by the lower protective layer.

[0017] A method for manufacturing a display device according to an embodiment includes: preparing a base layer defining a base hole region, and irradiating the base hole region with a laser to form a base hole; filling the base hole formed by laser processing (e.g., irradiation) with a conductive material; attaching (e.g., attaching) a first surface protective film to a first surface of the base layer, and attaching (e.g., attaching) a second surface protective film to a second surface of the base layer; removing the first surface protective film, and sequentially forming a circuit element layer including a first line, a display element layer, and a thin film encapsulation layer on the first surface of the base layer; forming a first protective layer and a second protective layer on the thin film encapsulation layer; rotating the base layer up and down and removing the second surface protective film, and forming a second line on the second surface of the base layer; and rotating the base layer up and down and removing the second protective layer.

[0018] The first protective layer may be composed of (for example) molybdenum oxide (MoO3) or silicon oxide (SiO2). x Insulating materials are formed.

[0019] The second protective layer can be formed of a conductive material including (for example) aluminum (Al).

[0020] The second protective layer can be formed as follows: to The thickness.

[0021] The second wire may overlap with the first wire and may form a physical connection and electrical connection (e.g., a connection) to the first wire and the conductive material.

[0022] The method may also include: forming a second line and forming a lower protective layer covering the second line; and etching the lower protective layer to expose a portion of the second line.

[0023] The method may also include attaching (e.g., attaching) the connecting membrane to the exposed portion of the second line.

[0024] The method may also include forming a light-emitting element, including an organic light-emitting diode or an inorganic light-emitting diode, in the display element layer.

[0025] The method may also include forming a light conversion layer between the display element layer and the thin-film encapsulation layer.

[0026] According to an embodiment, by positioning a protective layer including (for example,) a transparent insulating material on the thin-film encapsulation layer of the display panel, the display panel can be protected from external static electricity, scratches, and other effects.

[0027] The aspects of the embodiments are not limited to those described above, and various aspects are included in this specification and / or will be recognized by those skilled in the art. Attached Figure Description

[0028] The above and other features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in more detail, in which:

[0029] Figure 1 This is a perspective view showing a display device according to an embodiment;

[0030] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment;

[0031] Figure 3A and Figure 3B Each is a schematic cross-sectional view showing the configuration of the display panel according to the embodiment;

[0032] Figure 4 This is a schematic plan view of the display panel according to the embodiment;

[0033] Figure 5 This is a cross-sectional view showing a portion of the display panel according to an embodiment;

[0034] Figure 6 This is a cross-sectional view showing a portion of a display panel according to another embodiment;

[0035] Figure 7 This is a cross-sectional view showing a portion of a display panel according to another embodiment;

[0036] Figures 8A to 8F This is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment;

[0037] Figure 9 The etching rate of the second protective layer according to the deposition voltage in the etching process of the display device according to an embodiment is shown; and

[0038] Figure 10 The transmittance of a first protective layer in a display device according to an embodiment is shown according to wavelength. Detailed Implementation

[0039] This disclosure may be modified differently and appropriately, and may take various suitable forms. Therefore, specific embodiments will be shown in the accompanying drawings and described in more detail in the specification. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed, and that this disclosure includes all suitable modifications, equivalents, and substitutions within the spirit and technical scope of this disclosure. As used herein, the term “may” is used to mean “one or more embodiments of this disclosure” when describing embodiments of this disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to allow for inherent deviations in measurements or calculations that will be recognized by those skilled in the art.

[0040] Terms such as “first” and “second” may be used to describe various components, but components should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0041] It should be understood that in this application, terms such as "comprising" and "having" are used to describe the presence of features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof. Furthermore, when a portion of a layer, film, region, plate, etc., is referred to as being "on" another portion, it includes not only the case where the portion is "directly" "on" the other portion, but also the case where there are other portions(s) between the portion and the other portion. Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. When a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there are other portions(s) between the portion and the other portion.

[0042] Furthermore, any numerical range described herein is intended to include all subranges with the same numerical precision contained within the described range. For example, the range "1.0 to 10.0" is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (inclusive), that is, minimum values ​​equal to or greater than 1.0 and maximum values ​​equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described herein is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification, including the claims, to clearly describe any subranges contained within the range expressly described herein.

[0043] In the following description, a display device according to an embodiment of the present disclosure is illustrated with reference to the accompanying drawings relating to embodiments of the present disclosure.

[0044] Figure 1 This is a perspective view showing a display device according to an embodiment. Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment. Figure 3A and Figure 3B Each is a schematic cross-sectional view illustrating the configuration of the display panel according to the embodiment, and Figure 4 This is a schematic plan view of the display panel according to the embodiment.

[0045] Reference Figure 1 According to the embodiments, the display device may be a multi-screen display device that includes multiple display devices.

[0046] A multi-screen display device (TDD), also known as a “tiled display,” comprises multiple display devices DD arranged in a matrix along a first direction DR1 and a second direction DR2, and a housing HS. The multiple display devices DD can display individual images or can be divided and displayed as a single image. For example, the display devices DD can collectively display a single, unified image, or each display device DD can individually display an image independent of one or more images displayed by other display devices DD. The multiple display devices DD may include, but are not limited to, display panels of the same type (e.g., variety), structure, size, or method.

[0047] The housing HS physically connects to the display devices DD, allowing multiple display devices DD to form a multi-screen display device TDD. The housing HS can support the display devices DD from below and can have fastening members, groove structures, etc., for stably fixing the display devices DD.

[0048] Referring to one of a plurality of display devices DD, the display device DD includes a display area DA and a non-display area NA. The display area DA is the area where an image is to be displayed, and the non-display area NA is the area other than the display area DA, and does not display an image. The non-display area NA may be a border area surrounding (e.g., partially or completely surrounding) the display area DA.

[0049] The display area DA can be located on one surface of the display device DD. For example, the display area DA can be located on the front surface (e.g., the top surface) of the display device DD, and can also be located on the side and rear surfaces of the display device DD. For example, the display area DA can be located on one or more surfaces of the display device DD.

[0050] The non-display area NA can be located around the display area DA, and may optionally include connections (e.g., links) to... Figure 4 The image shows the lines, pads, driving circuits, etc. of the pixel PX of the display area DA.

[0051] The image displayed on the screen of a multi-screen display device TDD can be discontinuous due to the non-display area NA (e.g., the seam area located in the boundary region between display devices DD). For example, when the width (or area) of the non-display area NA is relatively large, the perception of image discontinuity can be exacerbated in the boundary region between display devices DD. For example, the boundary (e.g., the non-display area NA) between adjacent display devices DD in a multi-screen display device TDD can be visually identifiable when adjacent display devices DD display images separately.

[0052] On the other hand, when the width (or area) of the non-display area NA is reduced, the size of the display area DA can be increased without increasing the size of the display device DD. Therefore, a larger display area DA can be provided. Furthermore, when the non-display area NA is reduced, when implementing a multi-screen display device TDD using multiple display devices DD, the visual recognition of the boundaries between the display devices DD can be minimized or reduced, and a more natural (e.g., seamless) screen can be configured. The structure of the non-display area NA of the display device DD according to this embodiment, which can minimize or reduce the size of the display device DD, is described in more detail below.

[0053] Display devices (DDs) can be implemented in various suitable shapes. Figure 1 In this disclosure, the display device DD has a rectangular plate shape, but this disclosure is not limited thereto, and the display device DD may have a shape such as a circle or an ellipse.

[0054] Reference Figure 2 A display device DD includes a display panel DP and a window WD disposed on the display panel DP.

[0055] The display panel (DP) may include features for displaying images. Figure 4 The display panel DP can be a pixel PX, and can be a display panel of various suitable types (e.g., varieties) and structures. For example, the display panel DP can be a self-emitting display panel, such as an organic light-emitting display panel (OLED panel) using organic light-emitting diodes as light-emitting elements, a nanoscale LED display panel (nanoLED panel) using nanoscale light-emitting diodes as light-emitting elements, a quantum dot organic light-emitting display panel (QD OLED panel) using organic light-emitting diodes and quantum dots, and a quantum dot nanoscale LED display panel (QD nanoLED panel) using nanoscale light-emitting diodes and quantum dots. In some embodiments, the display panel DP can be a non-emissive display panel, such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), or an electrowetting display panel (EWD panel). When a non-emissive display panel is used as the display panel DP, the display device DD may also include a separate light source device (e.g., a backlight unit) for providing light to the display panel DP.

[0056] The window WD is located on the display panel (DP). The window WD protects the display panel (DP) from external impacts and provides an input and / or display surface for the user. The window WD can be implemented using a variety of suitable materials, including glass and / or plastic, and can be configured as a single layer or multiple layers.

[0057] For example, the window WD can be manufactured integrally with the display panel DP. In some embodiments, the window WD can be formed directly on the surface of the display panel DP. According to embodiments, the window WD can be manufactured separately from the display panel DP and then attached to the display panel DP by an optically clear adhesive member (or adhesive) member OCA.

[0058] Furthermore, the sensing device can be located between the display panel (DP) and the optically transparent adhesive component (OCA). The sensing device may include a touch sensor, fingerprint sensor, pressure sensor, temperature sensor, etc.

[0059] Reference Figure 3A The display panel DP includes a base layer BSL. The display panel DP also includes a pixel circuit layer PCL, a display element layer DPL, and a thin film encapsulation layer TFE, which are sequentially disposed on the surface of the base layer BSL on a third-direction DR3.

[0060] The base layer (BSL) can be a rigid (e.g., appropriately rigid) substrate or a flexible (e.g., appropriately flexible) substrate. For example, when the base layer (BSL) is a rigid substrate, it can be implemented as a glass substrate, a quartz substrate, a glass-ceramic substrate, a crystalline glass substrate, etc. On the other hand, when the base layer (BSL) is a flexible substrate, it can be implemented as a polymer organic substrate including (e.g., polyimide, polyamide, etc.), a plastic substrate, etc.

[0061] The pixel circuitry layer (PCL) sits on top of the base layer (BSL). The PCL may include configuration options (e.g., providing...). Figure 4 Each pixel PX comprises the pixel circuitry elements and various suitable lines connected (e.g., linked) to the circuitry elements. For example, the pixel circuitry layer PCL may include at least one transistor, storage capacitor, gate line, data line, power line, etc.

[0062] The Display Element Layer (DPL) is located on the Pixel Circuit Layer (PCL). The Display Element Layer (DPL) may include configuration (e.g., providing). Figure 4 The light-emitting element LD of the light source for each pixel PX (see Figure 5 (or as shown in the accompanying diagram). For example, Figure 5 The light-emitting element LD in the following figures may be an organic light-emitting diode, an inorganic light-emitting diode, or an ultra-small inorganic light-emitting diode with nanometer or micrometer-scale dimensions. However, in this disclosure, the type (e.g., variety), structure, shape, and / or size of the light-emitting element LD disposed in each pixel PX is not particularly limited.

[0063] The thin-film encapsulation layer (TFE) is located on the display element layer (DPL). The TFE can be an encapsulation substrate or a multilayer encapsulation film. For example, the TFE can have a multilayer structure in which inorganic layers, organic layers, and inorganic layers are sequentially stacked. The TFE protects the display element layer (DPL) and pixel circuit layer (PCL) by preventing or blocking external air and / or moisture from penetrating into them. Figure 4 The pixel PX.

[0064] According to the implementation, the display element layer (DPL) may be located first on the base layer (BSL), and the pixel circuit layer (PCL) may be located on the display element layer (DPL). For example, the base layer (BSL), the display element layer (DPL), and the pixel circuit layer (PCL) may be stacked sequentially on a third-direction DR3.

[0065] The above embodiments describe a case where the thin-film encapsulation layer TFE is located on the display element layer DPL, but this disclosure is not limited thereto. According to embodiments, such as... Figure 3B As shown, the light conversion layer LCL can be located between the display element layer DPL and the thin film encapsulation layer TFE.

[0066] The light conversion layer (LCL) is used to convert light emitted from the display element layer (DPL) and may include a color filter and a color conversion layer. The color filter includes (e.g., is) a color filter material of a predetermined or set color (e.g., a color filter material configured to selectively transmit light of a color corresponding to the color of each pixel PX). The color conversion layer includes color conversion particles (e.g., quantum dots) corresponding to the predetermined or set color to convert the light generated in the display element layer (DPL). For example, the light conversion layer (LCL) may selectively transmit light of a set wavelength band from the light generated from the display element layer (DPL) and / or may convert the wavelength band of the light generated from the display element layer (DPL).

[0067] exist Figure 3A and Figure 3B In this disclosure, the configuration of the display panel DP is schematically described assuming that it is a light-emitting display panel, but the present disclosure is not limited thereto. For example, the configuration of the display panel DP can be varied and appropriately changed depending on the type (e.g., variety) of the display device DD.

[0068] Reference Figure 4 The display panel DP can include a base layer BSL and pixels PX located on the base layer BSL.

[0069] The base layer (BSL) can be formed from a region having an approximately rectangular shape (e.g., it can have a region having an approximately rectangular shape or can provide a region having an approximately rectangular shape). The number of regions provided in the base layer (BSL) can vary, and the shape of the base layer (BSL) can vary depending on the regions provided. In some implementations, the base layer (BSL) can be formed from one or more regions (e.g., it can have one or more regions or can provide one or more regions), and each of the one or more regions can have any suitable shape.

[0070] The base layer (BSL) can be formed from an insulating material such as glass and / or resin. Furthermore, the base layer (BSL) can be formed from a material with suitable flexibility so that it is bendable and / or foldable, and can have a single-layer or multi-layer structure.

[0071] The base layer (BSL) can include a display area (DA) and a non-display area (NA). The display area (DA) of the display panel (DP) can correspond to the display area (DA) of the display device (DD), and the non-display area (NA) of the display panel (DP) can correspond to the non-display area (NA) of the display device (DD).

[0072] In the non-display area NA, a driver for driving pixel PX and a portion of a line connecting (e.g., linking) pixel PX and the driver can be provided. The non-display area NA may correspond to the bezel area of ​​the display device DD.

[0073] Pixels (PX) can be set within the display area (DA) of the base layer (BSL). Each pixel (PX) can be the smallest unit for displaying an image (e.g., a base unit or fundamental unit). Pixels (PX) can include... Figure 5 The following figures may also show light-emitting elements (LDs) for emitting white and / or colored light. Each of the pixels PXs may emit light of any color, such as red, green, and blue, but is not limited thereto, and may also emit light of colors such as cyan, magenta, and yellow. Each of the pixels PXs may include a pixel circuit layer (PCL) disposed on the base layer (BSL) and a display element layer (DPL) disposed on the pixel circuit layer (PCL). In the figures, the pixels PXs have a rectangular shape, but this disclosure is not limited thereto, and the shape of the pixels PXs may be modified differently and appropriately.

[0074] For ease of description, Figure 4 Only one pixel PX is shown, but multiple pixels PX can be distributed and arranged within the display area DA. For example, pixels PX can be arranged in a matrix, stripes, or... The arrangement structure is set in the display area DA. In some embodiments, pixels PX can be arranged in the display area DA in an RGBG matrix structure. However, this disclosure is not limited thereto.

[0075] In the following text, see references Figures 5 to 7 Describe a specific configuration of the display panel according to an implementation method.

[0076] Figure 5 This is a cross-sectional view showing a portion of the display panel according to an embodiment. Figure 6 This is a cross-sectional view showing a portion of a display panel according to another embodiment, and Figure 7 This is a cross-sectional view showing a portion of a display panel according to another embodiment.

[0077] Reference Figure 5 The display panel DP includes a pixel circuit layer PCL, a display element layer DPL, and a thin film encapsulation layer TFE, which are sequentially disposed on the first surface BS1 of the base layer BSL in the third direction DR3. However, the relative positions of the pixel circuit layer PCL, the display element layer DPL, and the thin film encapsulation layer TFE (e.g., the relative positions of the pixel circuit layer PCL, the display element layer DPL, and the thin film encapsulation layer TFE) can vary depending on the implementation.

[0078] The base layer BSL includes a base hole BSH passing through the first surface BS1 and the second surface BS2, and a conductive material CM can be filled within the base hole BSH. Multiple base holes BSH can be provided, and these multiple base holes BSH can be separated from each other. The conductive material CM filling the base hole BSH can directly contact the first line FL and the second line RL located on the first surface BS1 and the second surface BS2, respectively, to electrically connect and / or physically connect (e.g., connect) the first line FL and the second line RL located on the first surface BS1 and the second surface BS2, respectively. For example, the base layer BSL can be formed of glass, quartz, glass ceramic, etc.

[0079] The pixel circuit layer (PCL) includes the configuration of pixels (see reference). Figure 4 The circuit elements of each pixel circuit in the PX) and the first line FL connected (e.g., connected) to the circuit elements.

[0080] The circuit elements may include transistors M, capacitors, etc., and the first line FL may include a first gate line GL_F (also called a "front gate line"), a first data line DL_F (also called a "front data line"), a first drive voltage line VDD_F (also called a "front drive voltage line"), etc., that can be electrically connected (e.g., connected) to the circuit elements. Furthermore, the first line FL may also include a front sensing line for detecting characteristic information of pixel PX.

[0081] The first line FL can be a line located on the first surface BS1 of the base layer BSL and can be electrically connected (e.g., connected) to the second line RL located on the second surface BS2 of the base layer BSL. The first bridging pattern BRP1 located on the first surface BS1 can electrically connect (e.g., connect) the post-drive voltage line, which will be described later, to the first drive voltage line VDD_F.

[0082] The second line RL may include a second gate line GL_R (also referred to as the "back gate line"), a second data line DL_R (also referred to as the "back data line"), and / or a second drive voltage line VDD_R (also referred to as the "back drive voltage line"). Additionally, the second line RL may also include a back sensing line for detecting characteristic information of pixel PX.

[0083] The second line RL can be formed to overlap with the first line FL at a position corresponding to the first line FL, for connection (e.g., connection) to the first line FL. The second gate line GL_R can be electrically and / or physically connected (e.g., connected) to the first gate line GL_F via a base via BSH (e.g., a corresponding base via BSH). The second data line DL_R can be electrically and / or physically connected (e.g., connected) to the first data line DL_F, for example, via a base via BSH (e.g., a corresponding base via BSH). In some embodiments, the second data line DL_R can be electrically and / or physically connected to the first data line DL_F via a corresponding base via BSH and a second bridging pattern BRP2. The second drive voltage line VDD_R can be electrically and / or physically connected (e.g., connected) to the first drive voltage line VDD_F via a base via BSH (e.g., a corresponding base via BSH) and a first bridging pattern BRP1. According to an embodiment, the second line RL can be integrally formed with the conductive material CM of the base via BSH.

[0084] A lower protective layer BPRL is located on the second surface BS2 of the base layer BSL to cover the second line RL. In some embodiments, the lower protective layer BPRL may be a lower protective film. In some embodiments, the lower protective layer BPRL may cover the side surfaces of the second line RL and may be on at least a portion of the lower surface of the second line RL. The lower protective layer BPRL may be an organic insulating film including (e.g., is) organic materials, but this disclosure is not limited thereto. According to embodiments, the lower protective layer BPRL may be an inorganic insulating film including (e.g., is) inorganic materials. The lower protective layer BPRL may be completely disposed on the second surface BS2 of the base layer BSL that includes the second line RL, and may expose a portion of the second line RL (e.g., all or a portion (e.g., the central portion) of the lower surface of the second line RL) in a predetermined or defined area (e.g., a defined area of ​​the lower protective layer BPRL corresponding to the second line RL). The portion exposed by the lower protective layer BPRL may contact the connecting film COF, which will be described later.

[0085] The second line RL can be electrically connected (e.g., connected) to a drive circuit (or driver) in a predetermined or defined area via a connecting film COF. A gate driver, a data driver, and a power driver can be mounted on the connecting film COF located on the rear surface of the second line RL. Here, the connecting film COF can be configured as a chip-on-film or a flexible printed circuit board (FPCB), but this disclosure is not limited thereto.

[0086] The second gate line GL_R can be electrically connected (e.g., connected) to the gate driver via the connecting film COF, the second data line DL_R can be electrically connected (e.g., connected) to the data driver via the connecting film COF, and the second drive voltage line VDD_R can also be electrically connected (e.g., connected) to the power driver via the connecting film COF.

[0087] In one embodiment, the gate driver, data driver, and power driver are mounted on one (or the same) connection film COF, but this disclosure is not limited thereto. According to another embodiment, the gate driver, data driver, etc., may be mounted on separate connection film COFs, and the rear gate line GL_R and the rear data line DL_R may be respectively coupled (e.g., connected) to different connection film COFs.

[0088] Additionally, the pixel circuit layer PCL may include signal lines of other types (e.g., varieties) connected to the pixel PX.

[0089] The pixel circuit layer PCL also includes multiple insulating layers. For example, the pixel circuit layer PCL also includes a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and a passivation layer PSV, which are sequentially disposed on the first surface BS1 of the base layer BSL in the third direction DR3.

[0090] The first bridging pattern BRP1 is located between the base layer BSL and the buffer layer BFL. For example, the buffer layer BFL may cover the first bridging pattern BRP1 and may have an opening that exposes a portion (e.g., the central portion) of the upper surface of the first bridging pattern BRP1. The first bridging pattern BRP1 may be physically connected and / or electrically connected (e.g., connected) to the first drive voltage line VDD_F and the second drive voltage line VDD_R.

[0091] A semiconductor layer is located on the buffer layer BFL. The semiconductor layer may include a first semiconductor layer SCP, and may include a semiconductor layer for each of a plurality of transistors M (e.g., a semiconductor layer corresponding to each transistor M). The first semiconductor layer SCP may include a channel region overlapping the first gate electrode GE, and a first source region and a first drain region disposed on both sides of the channel region. Furthermore, a first bridging pattern BRP1 may be located on the buffer layer BFL. In some embodiments, the first bridging pattern BRP1 may be above the buffer layer BFL, for example, between the buffer layer BFL and the gate insulating layer GI.

[0092] The gate insulating layer GI is located on the semiconductor layer. The gate insulating layer GI may include (e.g., is) an inorganic material, which includes (e.g., silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y )wait.

[0093] The gate conductor is located on the gate insulating layer GI. The gate conductor includes a first gate electrode GE. The first gate electrode GE may be positioned to overlap with the channel region of the first semiconductor layer SCP. The gate conductor may include the gate electrode of each of a plurality of transistors M (e.g., a gate electrode corresponding to each transistor M), an electrode of a storage capacitor, a first gate line GL_F, a second bridging pattern BRP2, etc.

[0094] The first interlayer insulating layer ILD1 is located on the gate conductor.

[0095] The first data conductor is located on the first interlayer insulating layer ILD1. The first data conductor includes a first electrode TE1 and a second electrode TE2 of transistor M. The first electrode TE1 may be a source electrode coupled (e.g., connected) to a first source region of the first semiconductor layer SCP, and the second electrode TE2 may be a drain electrode coupled (e.g., connected) to a first drain region of the first semiconductor layer SCP. In some embodiments, the first electrode TE1 may be the drain electrode of transistor M, and the second electrode TE2 may be the source electrode. The first data conductor may include the first electrode TE1 and the second electrode TE2 of each of a plurality of transistors M (e.g., first electrode TE1 and second electrode TE2 corresponding to each transistor M), and may include another electrode of a storage capacitor, a first data line DL_F, etc.

[0096] The second interlayer insulation layer ILD2 is located on the first data conductor.

[0097] The second data conductor is located on the second interlayer insulating layer ILD2. The second data conductor includes an anode connection pattern ACP that connects (e.g., links) the pixel circuit layer PCL and the display element layer DPL. The second data conductor may also include a first driving voltage line VDD_F, a driving low voltage line, etc. The anode connection pattern ACP can be connected (e.g., linked) through contact holes CH to the first electrode ELT1 of the light-emitting element LD of each pixel PX (e.g., each corresponding pixel PX). For example, the light-emitting element LD can be one or more organic light-emitting diodes and / or one or more ultra-miniature inorganic light-emitting diodes (e.g., one or more microLEDs).

[0098] A passivation layer PSV is located on the second data conductor. The display element layer DPL is located on the pixel circuit layer PCL, which includes the passivation layer PSV. The contact hole CH of the passivation layer PSV can connect (e.g., link) the anode connection pattern ACP of the pixel circuit layer PCL and the first electrode ELT1 of the display element layer DPL.

[0099] The display element layer (DPL) includes light-emitting elements (LDs) for pixels (PXs) and electrodes coupled (e.g., connected) to the light-emitting elements (LDs). The light-emitting elements (LDs) can be ultra-miniature inorganic light-emitting diodes ranging from nanometers to micrometers, formed from structures in which nitride-based semiconductors are grown. In some embodiments, each of the light-emitting elements (LDs) can be an ultra-miniature inorganic light-emitting diode with a columnar shape having an aspect ratio greater than 1, but is not limited thereto.

[0100] The display element layer DPL includes a first dam BNK1, a second dam BNK2, a first electrode ELT1, a second electrode ELT2, a first insulating layer INS1, a second insulating layer INS2, a first contact electrode CNE1, and a second contact electrode CNE2.

[0101] The first dam BNK1 is located on the passivation layer PSV. The first dam BNK1 may be located in the emission region from which light is emitted from each pixel PX. The first dam BNK1 may be disposed below a portion of the first electrode ELT1 and the second electrode ELT2 to guide light emitted from the light-emitting element LD in the image display direction of the display device (e.g., the upward direction of each pixel PX), and thus the first dam BNK1 may cause a portion of the first electrode ELT1 and the second electrode ELT2 to protrude in the upward direction (e.g., the third direction DR3). For example, the first electrode ELT1 and the second electrode ELT2 may cover the first dam BNK1, and thus, the portion of each of the first electrode ELT1 and the second electrode ELT2 covering the first dam BNK1 may protrude in the third direction DR3 respectively compared to the remaining portions of the first electrode ELT1 and the second electrode ELT2. The first dam BNK1 may comprise an inorganic insulating film formed of inorganic materials or an organic insulating film formed of organic materials. According to embodiments, the first dam BNK1 may comprise a single organic insulating film or a single inorganic insulating film, but is not limited thereto.

[0102] The second dam BNK2 is located on the passivation layer PSV. In some embodiments, the second dam BNK2 may be located on the first insulating layer INS1. The second dam BNK2 is a structure for dividing (e.g., separating or partitioning) the emission region of each of the pixels PX, and may be located in the non-emission region of each pixel PX and in the non-emission region between pixels PX, to surround (e.g., partially or completely surround) the emission region of each pixel PX. For example, the second dam BNK2 may be a pixel-defining film or a dam structure. The second dam BNK2 may be configured to include (e.g., is) a light-blocking material and / or a reflective material.

[0103] Each of the first electrode ELT1 and the second electrode ELT2 is located on the first dam BNK1 and has a surface corresponding to the shape of the first dam BNK1. The first electrode ELT1 and the second electrode ELT2 may comprise (for example, be) a material with uniform reflectivity. Therefore, light emitted from the light-emitting element LD can pass through the first electrode ELT1 and the second electrode ELT2 in the image display direction of the display device.

[0104] The first electrode ELT1 can be electrically connected (e.g., connected) to the second electrode TE2 of the transistor M through a contact hole CH passing through the passivation layer PSV. However, this disclosure is not limited thereto. For example, in some embodiments, the first electrode ELT1 can be electrically connected (e.g., connected) to the first electrode TE1 of the transistor M, for example, through a contact hole in the passivation layer PSV. The second electrode ELT2 can be connected (e.g., connected) to a drive power supply through at least one contact hole in the passivation layer PSV in a region (e.g., a defined region of the passivation layer PSV). In embodiments, the first electrode ELT1 can be an anode, and the second electrode ELT2 can be a cathode. Each of the first electrode ELT1 and the second electrode ELT2 can be an ohmic contact electrode or a Schottky contact electrode, but this disclosure is not limited thereto.

[0105] In some embodiments, each of the first electrode ELT1 and the second electrode ELT2 may be located between the first insulating layer INS1 and the passivation layer PSV. In some embodiments, a portion of the first insulating layer INS1 may lie between the first electrode ELT1 and the second electrode ELT2 along a horizontal direction (e.g., a first direction DR1), and the portion of the first insulating layer INS1 between the first electrode ELT1 and the second electrode ELT2 may lie above the passivation layer PSV (e.g., directly above the passivation layer PSV). The first insulating layer INS1 can stably support the light-emitting element LD by filling the space between the light-emitting element LD and the passivation layer PSV. For example, the first insulating layer INS1 may lie between the passivation layer PSV and the light-emitting element LD. The first insulating layer INS1 may comprise an inorganic insulating film and / or an organic insulating film, and may be configured as a single layer or multiple layers.

[0106] The light-emitting element LD is located on the first insulating layer INS1. At least one light-emitting element LD may be disposed between the first electrode ELT1 and the second electrode ELT2. For example, the light-emitting element LD may be located between the first electrode ELT1 and the second electrode ELT2 in a horizontal direction (e.g., the first direction DR1). Multiple light-emitting elements LD may be disposed between the first electrode ELT1 and the second electrode ELT2, and the multiple light-emitting elements LD may be connected in parallel with each other (e.g., connected).

[0107] Each of the light-emitting elements (LDs) can emit light of any suitable color, either predetermined or set, and / or white light. In an embodiment, the LDs can be arranged in a form that allows them to be dispersed in a solution and can be injected into each pixel (PX).

[0108] The light-emitting element (LD) includes a first semiconductor layer SCL1, an active layer ACT, and a second semiconductor layer SCL2 sequentially disposed in one direction (e.g., a horizontal direction, such as a first direction DR1). The light-emitting element (LD) may also include an insulating film surrounding the outer circumferential surface of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2.

[0109] The first semiconductor layer SCL1 may include a first conductivity type (e.g., class) semiconductor. For example, the first semiconductor layer SCL1 may include at least one p-type semiconductor layer. For example, the first semiconductor layer SCL1 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a first conductivity type (e.g., class) dopant (or p-type dopant) such as Mg.

[0110] The active layer ACT can be formed as a single quantum well structure or a multi-quantum well structure. Depending on the implementation, materials such as AlGaN or AlInGaN can be used to configure the active layer ACT, and in addition to the aforementioned materials, the active layer ACT can be formed from various suitable materials. The location of the active layer ACT can be varied and appropriately changed depending on the type (e.g., class) of the light-emitting element LD. The active layer ACT can emit light with wavelengths from 400 nm to 900 nm and can utilize a dual heterostructure. As used herein, the term nm can refer to an integer equal to 10 nm. -9 A distance of meters.

[0111] The second semiconductor layer SCL2 includes a semiconductor layer of a different type (e.g., class) than the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 may include at least one n-type semiconductor layer. For example, the second semiconductor layer SCL2 may include (e.g., be) InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, and may be an n-type semiconductor layer doped with a second conductivity type (e.g., class) dopant (or n-type dopant) such as Si, Ge, and / or Sn.

[0112] One end of the light-emitting element LD in the direction of the first semiconductor layer SCL1 can be referred to as the first end EP1, and the other end in the direction of the second semiconductor layer SCL2 can be referred to as the second end EP2 of the light-emitting element LD. For example, the first end EP1 can be located on the side of the light-emitting element LD along the first direction DR1 corresponding to the first semiconductor layer SCL1, and the second end EP2 can be located on the side of the light-emitting element LD along the first direction DR1 corresponding to the second semiconductor layer SCL2, and the second end EP2 can be opposite to the first end EP1.

[0113] The second insulating layer INS2 is located on a portion of the light-emitting element LD. The second insulating layer INS2 may cover a portion of the upper surface of each of the light-emitting elements LD (e.g., the central portion) and may expose the first end EP1 and the second end EP2 of each of the light-emitting elements LD. For example, the second insulating layer INS2 may expose a portion of the upper surface of the light-emitting element LD at each of the first end EP1 and the second end EP2 (e.g., a portion of the upper surface of the light-emitting element LD corresponding to each of the first end EP1 and the second end EP2 may be exposed). The second insulating layer INS2 can stably fix the light-emitting element LD in place. When there is a void between the first insulating layer INS1 and the light-emitting element LD before the formation of the second insulating layer INS2, the void may be at least partially filled by the second insulating layer INS2.

[0114] A first contact electrode CNE1 is located on the first electrode ELT1 at one end (e.g., the first end EP1) of each of the first electrode ELT1 and the light-emitting element LD, where the electrical connection and / or physical connection (e.g., connection) is made. The first contact electrode CNE1 may be positioned to overlap with a portion of the first insulating layer INS1, the second insulating layer INS2, and the light-emitting element LD. The first insulating layer INS1 may be removed or have an opening at the portion where the first electrode ELT1 and the first contact electrode CNE1 are connected (e.g., connected) (e.g., the portion where the first electrode ELT1 and the first contact electrode CNE1 are in direct contact).

[0115] A second contact electrode CNE2 is located on the second electrode ELT2, at one end (e.g., the second end EP2) of each of the second electrode ELT2 and the light-emitting element LD, for electrical and / or physical connections (e.g., connection). The second contact electrode CNE2 may be positioned to overlap with a portion of the first insulating layer INS1, the second insulating layer INS2, and the light-emitting element LD. The first insulating layer INS1 may be removed or have an opening at the portion where the second electrode ELT2 and the second contact electrode CNE2 are joined (e.g., connected) (e.g., the portion where the second electrode ELT2 and the second contact electrode CNE2 are in direct contact).

[0116] The first contact electrode CNE1 and the second contact electrode CNE2 can be configured with a transparent conductive material. Therefore, light emitted from each of the light-emitting elements LD and / or reflected by the first electrode ELT1 and the second electrode ELT2 can be emitted in the image display direction of the display device.

[0117] The light conversion layer (LCL) is located on the display element layer (DPL).

[0118] The light conversion layer LCL includes a color conversion layer CCL with quantum dots (QDs) and / or a color filter CF located on the display element layer DPL or on the color conversion layer CCL. In some embodiments, the light conversion layer LCL includes a color conversion layer CCL, a cover layer CVL, a first light-blocking pattern LBP1, a planarization film PLL, a color filter CF, and a second light-blocking pattern LBP2 sequentially disposed on the display element layer DPL.

[0119] In one embodiment, when the light conversion layer LCL is formed directly on the display element layer DPL, the display element layer DPL further includes a third insulating layer INS3. The third insulating layer INS3 may include at least one organic film and / or at least one inorganic film, and may be completely located on the surface of the display element layer DPL. In some embodiments, the third insulating layer INS3 may completely cover the display element layer DPL.

[0120] A color conversion layer (CCL) is disposed on a light-emitting element (LD) and includes color conversion particles (e.g., quantum dots (QDs) with predetermined or set colors) for converting light of a first color emitted from the LD into light of a second color.

[0121] For example, when at least one pixel PX is set as a red (or green) pixel PX and a blue light-emitting element LD is set as the light source for pixel PX, a color conversion layer CCL, including a red (or green) quantum dot QD for converting blue light into red (or green) light, can be set in pixel PX. Furthermore, a red (or green) color filter CF can be set on the color conversion layer CCL.

[0122] A cover layer CVL for protecting the color conversion layer CCL can be located on a first surface BS1 of the base layer BSL including the color conversion layer CCL. For example, the cover layer CVL can be located on the upper surface of the color conversion layer CCL. Furthermore, a first light-blocking pattern LBP1 can be disposed in an area corresponding to the outer side of the color conversion layer CCL. For example, the first light-blocking pattern LBP1 can be disposed on the cover layer CVL and can cover a portion of the color conversion layer CCL (e.g., a side or edge). Figure 5 An embodiment in which a color conversion layer CCL is first formed and then a first light-blocking pattern LBP1 is formed is shown, but this disclosure is not limited thereto. For example, the formation order of the color conversion layer CCL and the first light-blocking pattern LBP1 can be changed depending on the process method applied to the formation of the color conversion layer CCL, the performance of the equipment, etc.

[0123] The planarization film PLL can be located on the cover layer CVL and the first light-blocking pattern LBP1. The planarization film PLL can planarize the upper surface of the color conversion layer CCL and the first light-blocking pattern LBP1, and can include (e.g., is) organic and / or inorganic materials.

[0124] A color filter CF can be disposed in the emission region from which light is emitted from each pixel PX (e.g., it can overlap with the emission region). The color filter CF includes (e.g., is) a color filter material capable of selectively transmitting light of a color corresponding to the color of each pixel PX. A second light-blocking pattern LBP2 can be disposed outside the color filter CF. For example, the second light-blocking pattern LBP2 can be disposed on a planarization film PLL and can cover a portion of the color filter CF (e.g., a side or edge).

[0125] The thin-film encapsulation layer TFE is located on the light conversion layer LCL.

[0126] The thin-film encapsulation layer (TFE) can be formed from a single layer or multiple layers. In an embodiment, the thin-film encapsulation layer (TFE) may include multiple insulating films covering the display element layer (DPL). For example, the thin-film encapsulation layer (TFE) may include at least one inorganic film and at least one organic film.

[0127] For example, the thin-film encapsulation layer TFE can have a structure in which inorganic and organic films are alternately stacked. In an embodiment, the thin-film encapsulation layer TFE may include a first encapsulation layer ENC1, a second encapsulation layer ENC2, and a third encapsulation layer ENC3. The first encapsulation layer ENC1 may be disposed on the display element layer DPL and may be located on... Figure 1 Non-display area NA and Figure 1 The first encapsulation layer ENC1, the second encapsulation layer ENC2, and the third encapsulation layer ENC3 may be disposed on the first encapsulation layer ENC1 and may be located on at least a portion of the non-display area NA and the display area DA. The third encapsulation layer ENC3 may be disposed on the second encapsulation layer ENC2 and may be disposed on at least a portion of the non-display area NA and the display area DA. In some embodiments, the first encapsulation layer ENC1, the second encapsulation layer ENC2, and the third encapsulation layer ENC3 may be formed of an inorganic film comprising (e.g., is) inorganic materials. In some embodiments, the second encapsulation layer ENC2 may be formed of an organic film comprising (e.g., is) organic materials. In some embodiments, the first encapsulation layer ENC1 and the third encapsulation layer ENC3 may each be formed of an inorganic film comprising (e.g., is) inorganic materials, and the second encapsulation layer ENC2 may be formed of an organic film comprising (e.g., is) organic materials.

[0128] The first protective layer PRL1 is located on the thin-film encapsulation layer TFE. The first protective layer PRL1 may include a transparent insulating material (e.g., it may be formed of a transparent insulating material). For example, the first protective layer PRL1 may include (e.g., molybdenum oxide (MoO3) or silicon oxide (SiO2). xTherefore, because the first protective layer PRL1 can transmit light emitted from the light-emitting element LD, the first protective layer PRL1 can not affect (e.g., substantially not affect) the transmittance of the display panel DP. In an embodiment, the first protective layer PRL1 can be formed as follows: Or even thinner, but not limited to. As used herein, the terminology... Can be equal to 10 -10 A distance of meters.

[0129] The first protective layer PRL1 is a buffer (e.g., a buffer layer), and the first protective layer PRL1 can prevent or reduce the penetration of impurities, and is used as a buffer to prevent external impacts, etc. Therefore, by positioning the first protective layer PRL1, which includes (e.g., is) a transparent insulating material, on the thin film encapsulation layer TFE of the display panel DP, the display panel DP can be protected from the effects of static electricity, scratches, etc. introduced from the outside.

[0130] Reference Figure 6 According to another embodiment, the thin-film encapsulation layer TFE is located directly on the display element layer DPL of the display panel DP. Figure 6 The display panel DP does not include a light conversion layer LCL, but it can be protected from externally introduced static electricity, scratches, etc. by a first protective layer PRL1 located on the thin film encapsulation layer TFE. Furthermore, because the first protective layer PRL1 can include (e.g., is) a material with high transmittance, the first protective layer PRL1 can not affect (e.g., substantially not affect) the transmittance of the display panel DP.

[0131] Reference Figure 7 According to another embodiment, the display panel DP includes an organic light-emitting diode as a light-emitting element LD. Since the base layer BSL, pixel circuit layer PCL, and thin-film encapsulation layer TFE are the same as those described above (e.g., having the same composition and / or structure), the display element layer DPL will be mainly described below.

[0132] The display element layer DPL includes an organic light-emitting diode (OLED) as a light-emitting element (LD). The OLED includes a first electrode AE, an emission layer EML, and a second electrode CE.

[0133] One of the first electrode AE ​​and the second electrode CE can be an anode, and the other of the first electrode AE ​​and the second electrode CE can be a cathode. When the light-emitting element LD is a front surface emission type (e.g., type 1) organic light-emitting diode, the first electrode AE ​​can be a reflective electrode, and the second electrode CE can be a transmissive electrode. In embodiments of this disclosure, the case where the light-emitting element LD is a front surface emission type (e.g., type 2) organic light-emitting diode and the first electrode AE ​​is an anode is described as an example.

[0134] The first electrode AE ​​is connected (e.g., connected) to the second electrode TE2 of the transistor M in the pixel circuit layer PCL via a contact hole CH through the passivation layer PSV and an anode connection pattern ACP. For example, the first electrode AE ​​is connected (e.g., connected) to the anode connection pattern ACP via the contact hole CH, and the anode connection pattern ACP connects (e.g., connects) the first electrode AE ​​to the second electrode TE2. The first electrode AE ​​may include a reflective film capable of reflecting light and / or a transparent conductive film disposed on or below the reflective film. For example, the first electrode AE ​​may be configured with multiple layers of conductive film and reflective film, the multiple conductive films including a lower transparent conductive film and an upper transparent conductive film each formed of indium tin oxide (ITO), and a reflective film disposed between the lower transparent conductive film and the upper transparent conductive film and formed of silver (Ag).

[0135] The display element layer DPL may further include a pixel defining film PDL having an opening that exposes a portion of a first electrode AE ​​(e.g., the upper surface of the first electrode AE). For example, the pixel defining film PDL may be on the pixel circuit layer PCL and may cover a portion of the first electrode AE ​​(e.g., a side or edge) and may expose another portion of the first electrode AE ​​(e.g., a central portion). Here, the pixel defining film PDL may be related to the reference... Figure 5 The configuration corresponding to the second bank BNK2 of the described display panel DP. The pixel defining film PDL and the second bank BNK2 can be substantially similar or identical. For example, the pixel defining film PDL can have the same composition, structure, and / or configuration as the second bank BNK2. The pixel defining film PDL can be an organic insulating film including (e.g., is) organic materials. For example, the pixel defining film PDL can be formed from an organic insulating film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0136] The emitter layer EML can be disposed in a region corresponding to the opening of the pixel defining film PDL. In some embodiments, the emitter layer EML can be disposed on a surface of the exposed first electrode AE. The emitter layer EML can have a thin film structure comprising multiple layers including a light generation layer. The emitter layer EML may include: a hole injection layer for injecting holes; a hole transport layer having desired or superior hole transport characteristics and increasing the chance of recombination of holes and electrons by suppressing the movement of electrons not bound in the light generation layer; a light generation layer for emitting light through the recombination of injected holes and injected electrons; a hole blocking layer for suppressing the movement of holes not bound in the light generation layer; an electron transport layer for smoothly transporting electrons to the light generation layer; and an electron injection layer for injecting electrons.

[0137] The light-generating layer can be formed individually in the emission region of each pixel PX, and the hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron injection layer can be a common film connected (e.g., linked) in adjacent emission regions. However, in Figure 7 In the diagram, the emission layer EML is shown based on the light generation layer.

[0138] The second electrode CE is located on the emitter layer EML. The second electrode CE may be a common film provided to the pixel PX, but is not limited thereto. The second electrode CE may be a transmission electrode and may include (e.g., is) a transparent conductive material. The transparent conductive material may include (e.g., is) a transparent conductive oxide and / or a conductive polymer, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium tin zinc oxide (ITZO), and the conductive polymer may be such as PEDOT, but is not limited thereto.

[0139] Figure 7 The display panel DP can be protected from external static electricity, scratches, etc. by the first protective layer PRL1 located on the thin film encapsulation layer TFE.

[0140] Furthermore, because the first protective layer PRL1 may include (e.g., be) a material with high transmittance, the first protective layer PRL1 may not affect (e.g., substantially not affect) the transmittance of the display panel DP.

[0141] In the following text, see references Figures 8A to 8F A method for manufacturing a display device according to an embodiment is described.

[0142] Figures 8A to 8F This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0143] First, refer to Figure 8A Prepare a base layer BSL in which the area of ​​the base hole BSH is defined, and process the base layer BSL by irradiating the area of ​​the base hole BSH (e.g., the area where the base hole BSH is to be formed) with a laser.

[0144] In one embodiment, the base layer BSL can be a glass substrate formed of glass, but is not limited thereto. According to another embodiment, the base layer BSL can be a film substrate comprising (e.g., a polymeric organic material). When a laser irradiates a region of the base hole BSH, at least a portion of the base layer BSL can be removed from the region of the base hole BSH and / or the physical properties of the base hole BSH can be altered.

[0145] Reference Figure 8BThe conductive material CM is filled into the base hole BSH of the base layer BSL, which is processed by laser.

[0146] In this embodiment, the conductive material CM can be filled into the base hole BSH by methods such as metal inkjet printing, but is not limited thereto. The conductive material CM can be physically coupled and / or electrically coupled (e.g., connected) to each of the first line FL and the second line RL, which will be described later (see [link to documentation]). Figure 8E Therefore, the conductive material CM filling the base hole BSH can be the connection part of the first line FL and the second line RL.

[0147] Subsequently, a protective film is attached (e.g., attached) to each of the first surface BS1 and the second surface BS2 of the base layer BSL. The protective film attached (e.g., attached) to the first surface BS1 of the base layer BSL may be referred to as the first surface protective film PTF1, and the protective film attached (e.g., attached) to the second surface BS2 of the base layer BSL may be referred to as the second surface protective film PTF2. In an embodiment, because the first surface BS1 may define the upper surface of the base layer BSL, and the second surface BS2 may define the lower surface of the base layer BSL, the first surface protective film PTF1 may be referred to as the upper surface protective film, and the second surface protective film PTF2 may be referred to as the lower surface protective film.

[0148] Reference Figure 8C Remove the first surface protective film PTF1 that is attached (e.g., attached) to the first surface BS1 of the base layer BSL, and sequentially form a pixel circuit layer PCL, a display element layer DPL, a light conversion layer LCL, and a thin film encapsulation layer TFE on the first surface BS1 of the base layer BSL.

[0149] Pixel circuit layer PCL can be with Figures 5 to 7 The pixel circuit layer PCL shown corresponds to this. It is formed on... Figure 8C The first gate line GL_F, the first data line DL_F, and the first drive voltage line VDD_F on the first surface BS1 of the base layer BSL shown in the diagram can be referred to as the first line FL. Figure 8C In the diagram, the first gate line GL_F, the first data line DL_F, and the first drive voltage line VDD_F are located on the same layer, but these are shown schematically, and as... Figures 5 to 7As shown, the first gate line GL_F, the first data line DL_F, and the first drive voltage line VDD_F can be located on different layers. For example, the first interlayer insulating layer ILD1 can be located between the first gate line GL_F and the first data line DL_F, and the second interlayer insulating layer ILD2 can be located between the first data line DL_F and the first drive voltage line VDD_F. However, this disclosure is not limited thereto. For example, in some embodiments, the gate insulating layer GI can be located between the first gate line GL_F and the first data line DL_F, and the first interlayer insulating layer ILD1 can be located between the first data line DL_F and the first drive voltage line VDD_F.

[0150] Furthermore, the display element layer DPL, the light conversion layer LCL, and the thin-film encapsulation layer TFE can be respectively Figures 5 to 7 The diagram shows the display element layer DPL, the light conversion layer LCL, and the thin-film encapsulation layer TFE. For example, Figures 8C to 8F The display element layer DPL shown may include one of organic light-emitting diodes, inorganic light-emitting diodes, and ultra-small light-emitting diodes as light-emitting elements (LDs). According to an embodiment, when the light conversion layer LCL is not formed, the thin-film encapsulation layer TFE can be directly formed on the display element layer DPL.

[0151] Reference Figure 8D A protective layer PRL is formed on the thin-film encapsulation layer TFE.

[0152] The protective layer PRL includes a first protective layer PRL1 formed directly on the upper surface of the thin film encapsulation layer TFE and a second protective layer PRL2 formed on the first protective layer PRL1.

[0153] The first protective layer PRL1 can prevent or reduce impurity penetration and acts as a buffer between the thin-film encapsulation layer TFE and the second protective layer PRL2 to prevent external impacts. The first protective layer PRL1 may include a transparent insulating material (e.g., formed of a transparent insulating material). For example, the first protective layer PRL1 may include (e.g., is) molybdenum oxide (MoO3) or silicon oxide (SiO2). x Therefore, even though the first protective layer PRL1 is located on the thin-film encapsulation layer TFE in the final structure of the display panel DP, light emitted from the display element layer DPL can still be transmitted, and thus the first protective layer PRL1 can not affect (e.g., substantially not affect) the transmittance of the display panel DP. In an embodiment, the first protective layer PRL1 can be formed as follows: Or even a thinner thickness, but not limited to that.

[0154] The second protective layer PRL2 can be located at the top edge of the display panel DP. For example, the second protective layer PRL2 can be the top layer of the display panel DP. When the thin-film encapsulation layer TFE is positioned facing downwards, the second protective layer PRL2 can be positioned at the bottom edge of the display panel DP. The second protective layer PRL2 can include a thin, low-resistance conductive material (e.g., it can be formed of a thin, low-resistance conductive material). For example, the second protective layer PRL2 can include (e.g., is) a material with a resistance of less than 10. 6 The aluminum (Al) has a resistive property of Ω (ohms). Furthermore, in embodiments, the second protective layer PRL2 can be formed (e.g., with...) to The thickness can prevent, reduce or block static electricity that may occur at the bottom of the display panel DP.

[0155] Reference Figure 8E To form the second line RL on the second surface BS2 of the base layer BSL, the base layer BSL is positioned such that the first surface BS1 faces downwards and the second surface BS2 faces upwards by rotating (e.g., turning, flipping, etc.) the base layer BSL vertically (e.g., inverting). For example, a partially manufactured display panel can be inverted so that the direction from the protective layer PRL to the base layer BSL is on the third direction DR3. Therefore, the thin-film encapsulation layer TFE can be positioned facing downwards, and the first protective layer PRL1 and the second protective layer PRL2 can be positioned below the thin-film encapsulation layer TFE. The thin-film encapsulation layer TFE may not be directly exposed to the outside and can be protected by the protective layer PRL. For example, the first protective layer PRL1 can absorb external impacts, and the second protective layer PRL2 can prevent or reduce the occurrence of static electricity, thereby preventing static electricity from interacting with the outside.

[0156] The second surface protective film PTF2 is removed from the second surface BS2 of the base layer BSL, and a second line RL is formed on the second surface BS2 of the base layer BSL. The second line RL may include a second gate line GL_R, a second data line DL_R, and a second drive voltage line VDD_R. In a cross-sectional view, the second line RL may be configured (e.g., along the third direction DR3) to overlap with the first line FL, and may be electrically and / or physically connected (e.g., connected) to the first line FL through the conductive material CM of the base via BSH.

[0157] A second line RL is formed, and a lower guard layer BPRL is formed to cover the second surface BS2 of the base layer BSL and the second line RL. Furthermore, the lower guard layer BPRL is etched to expose a portion of the second gate line GL_R, the second data line DL_R, and the second drive voltage line VDD_R.

[0158] Subsequently, the connection film COF can be coupled (e.g., attached) to the exposed portion of the second line RL. Gate drivers, data drivers, power drivers, etc., can be mounted on the connection film COF, and the second gate line GL_R, the second data line DL_R, and the second drive voltage line VDD_R of the second line RL can be coupled (e.g., connected) to the gate driver, the data driver, and the power driver, respectively.

[0159] In the back-side process of forming a second line RL and a lower protective layer BPRL and a connecting (e.g., attaching) connecting film COF on the second surface BS2 of the base layer BSL, the display panel DP according to the embodiment can protect the thin film encapsulation layer TFE through the protective layer PRL.

[0160] Therefore, in the process of forming a second line RL on the second surface BS2 of the base layer BSL and forming a lower protective layer BPRL on the second line RL, the thin film encapsulation layer TFE of the display panel DP can be protected from external damage.

[0161] In the display device according to the comparative example, an organic protective film can be bonded (e.g., attached) to the upper surface of the thin-film encapsulation layer to protect the thin-film encapsulation layer. On the other hand, the display device according to embodiments of the present disclosure can be formed with molybdenum oxide (MoO3) or silicon oxide (SiO2), which are cheaper than organic protective films. x ), aluminum (Al) film, etc., and therefore, the cost of manufacturing display devices can be reduced.

[0162] Reference Figure 8F A second line RL and a lower protective layer BPRL can be formed on the second surface BS2 of the base layer BSL, and the base layer BSL can be rotated (e.g., rotated, flipped, etc.) again. For example, the display panel can be partially inverted again (e.g., a second time) so that the direction from the base layer BSL to the protective layer PRL is in the third direction DR3. Therefore, the base layer BSL can be positioned such that the first surface BS1 of the base layer BSL faces the upper surface and the second surface BS2 faces the lower surface.

[0163] Subsequently, the second protective layer PRL2 can be etched using a stripping process with a stripping agent. Therefore, the second protective layer PRL2 is removed and not retained in the display panel DP, while a portion of the first protective layer PRL1 remains.

[0164] Reference Figure 9 , as reference Figure 8F The time required for the etching process used to remove the second protective layer can be determined from the description.

[0165] Figure 9The etching rate of the second protective layer according to the deposition voltage in the etching process of the display device is shown according to an embodiment.

[0166] In this embodiment, the second protective layer PRL2 is formed of aluminum (Al), and Figure 9 Experimental results are shown when the second protective layer PRL2 is aluminum (Al). However, the etching rate can vary depending on the material forming the second protective layer PRL2, and therefore the etching rate is not limited to this.

[0167] Furthermore, in the embodiments, when an alkaline etching solution (e.g., deionized water (DIW)) is added and a deposition voltage is applied, the etching rate of the second protective layer PRL2 can be checked based on the deposition voltage and the concentration of the etching solution.

[0168] At the first, second, and third voltages, the etching rate was observed when the concentration of the etching solution (e.g., DIW) was 97 wt% and 99 wt%, respectively. The etching rate could increase when the concentration of the etching solution was low (e.g., deionized).

[0169] For example, when the concentration of the etching solution is 97 wt%, and the etching rate of the second protective layer PRL2 under the first voltage is greater than... Even when a second voltage approximately twice as high as the first voltage is applied, the etching rate of the second protective layer PRL2 can still be less than [a certain value]. Furthermore, when a third voltage, approximately twice as high as the second voltage, is applied, the etching rate of the second protective layer PRL2 can be less than [a certain value]. Or smaller (or less than when the etching solution is 99 wt%) On average, the etching rate of the second protective layer PRL2 can be... Therefore, when the thickness of the second protective layer PRL2 is 30 to The second protective layer PRL2 can be removed by performing an etching process of approximately 60 seconds. In the etching process used to remove the second protective layer PRL2, because a stripping agent that does not damage the display panel DP is used, the display panel DP can be left unaffected (e.g., substantially unaffected).

[0170] See below for reference. Figure 10 According to Figures 5 to 7 The transmittance of the first protective layer is checked in the display device of the embodiment shown.

[0171] Figure 10 The transmittance of a first protective layer in a display device according to an embodiment is shown according to wavelength.

[0172] Reference Figure 10When the wavelength is 400 nm or greater, it can be known that the first protective layer PRL1 exhibits a transmittance of approximately 90% or greater. Therefore, even if the first protective layer PRL1 is located in the area described above... Figures 5 to 7 High transmittance can also be observed on the TFE thin-film encapsulation layer of the display panel DP. When the first protective layer PRL1 is formed of molybdenum oxide (MoO3), Figure 10 The transmittance shown is an experimental example. According to the implementation, because the first protective layer PRL1 may include (e.g., be) a material with high transmittance, the first protective layer PRL1 may not affect (e.g., substantially not affect) the transmittance of the display panel DP.

[0173] Although this disclosure has been described with reference to the embodiments disclosed above, those skilled in the art and those with common knowledge in the art will understand that different and appropriate modifications and changes can be made to this disclosure without departing from the spirit and technical field of this disclosure as described in the appended claims and their equivalents.

[0174] Therefore, the technical scope of this disclosure should not be limited to what is described in the detailed description of the specification, but should be defined by the claims and their equivalents.

Claims

1. A method for manufacturing a display device, the method comprising: Prepare a base layer with a defined base hole region, and irradiate the base hole region with a laser to form a base hole; The conductive material is filled into the foundation hole formed by irradiation with the laser; A first surface protective film is attached to the first surface of the base layer, and a second surface protective film is attached to the second surface of the base layer; Remove the first surface protective film, and sequentially form a circuit element layer including a first line, a display element layer, and a thin film encapsulation layer on the first surface of the base layer; A first protective layer and a second protective layer are formed on the thin film encapsulation layer, wherein the second protective layer is formed of a conductive material; The base layer is inverted and rotated to remove the second surface protective film, and a second line is formed on the second surface of the base layer; as well as The base layer is inverted and rotated, and the second protective layer is removed.

2. The method according to claim 1, wherein, The first protective layer is formed of an insulating material including molybdenum oxide or silicon oxide.

3. The method according to claim 1, wherein, The second protective layer is formed of a conductive material including aluminum.

4. The method according to claim 1, wherein, The second protective layer is formed to have a thickness of 30 Å to 100 Å.

5. The method according to claim 1, wherein, The second line overlaps with the first line and is formed to be electrically connected to the first line and the conductive material filling the base hole.

6. The method according to claim 1, further comprising: Form a lower protective layer covering the second line; as well as The lower protective layer is etched to expose a portion of the second line.

7. The method according to claim 6, further comprising: Connect the connecting membrane to the exposed portion of the second line.

8. The method according to claim 1, further comprising: A light-emitting element, including an organic light-emitting diode or an inorganic light-emitting diode, is formed in the display element layer.

9. The method according to claim 1, further comprising: A light conversion layer is formed between the display element layer and the thin film encapsulation layer.

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