Pixel and display device including the pixel

Abstract

A pixel and a display device including the pixel are disclosed. The pixel includes: a pixel circuit connected to a gate line and a data line; and a light-emitting diode having a first electrode connected to the pixel circuit, wherein the pixel circuit may include: a driving thin-film transistor connected to the first electrode of the light-emitting diode; a first capacitor formed horizontally between the gate and source of the driving thin-film transistor; and a second capacitor formed vertically between the gate of the driving thin-film transistor and the first electrode of the light-emitting diode.

Description

Technical Field

[0001] This disclosure relates to pixels and display devices including such pixels. Background Technology

[0002] With the development of the information age, the demand for display devices for displaying images has increased in various forms. Therefore, various types of display devices have recently been used, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and organic light-emitting diode (OLED) display devices.

[0003] In such a display device, the organic light-emitting display device is a self-luminous display device that uses an organic light-emitting diode (OLED) that injects holes from the anode and electrons from the cathode into the light-emitting layer, and emits light when the excitons generated by the combination of injected holes and electrons change its state from the excited state to the ground state.

[0004] Organic light-emitting display devices can be classified into top-emitting, bottom-emitting, and dual-emitting types according to the direction of light emission, and can be classified into passive matrix type and active matrix type according to the driving method.

[0005] Unlike liquid crystal displays (LCDs), organic light-emitting diode (OLEDs) displays do not require a separate light source, allowing them to be manufactured in a lightweight and thin form. Furthermore, OLEDs are driven by low voltage, which is advantageous considering power consumption. Moreover, OLEDs exhibit excellent color reproduction, high response speed, wide viewing angle, and high contrast ratio (CR). Therefore, OLEDs have been investigated as a next-generation display device.

[0006] Organic light-emitting display devices include storage capacitors to maintain a certain current during light emission. These storage capacitors are provided per pixel and occupy a certain area, thus reducing the aperture ratio. With the trend towards higher resolution display devices, aperture ratio has recently become an important issue. The current density of the light-emitting diodes (LEDs) can be reduced by increasing the aperture ratio, thereby increasing the LED's lifespan. Due to the increased adaptability of high-resolution display devices, it is necessary to realize organic light-emitting display devices with high aperture ratios.

[0007] The above-mentioned background technology is owned by the inventor of this disclosure and is the technical information obtained by designing this disclosure or by the process of designing this disclosure, but it cannot be regarded as known technology disclosed to the public before this disclosure was made public. Summary of the Invention

[0008] This disclosure was made in consideration of the above-mentioned problems, and the purpose of this disclosure is to provide a pixel and a display device including the pixel, wherein the aperture ratio can be improved and the structure can be simplified.

[0009] In addition to the purposes of this disclosure as stated above, those skilled in the art will clearly understand other purposes and features of this disclosure from the following description.

[0010] According to one aspect of this disclosure, the above and other objectives can be achieved by providing a pixel comprising: a pixel circuit connected to a gate line and a data line; and a light-emitting diode having a first electrode connected to the pixel circuit, wherein the pixel circuit may include: a driving thin-film transistor connected to the first electrode of the light-emitting diode; a first capacitor formed in a horizontal direction between the gate and source of the driving thin-film transistor; and a second capacitor formed in a vertical direction between the gate of the driving thin-film transistor and the first electrode of the light-emitting diode.

[0011] According to another aspect of this disclosure, the above and other objectives can be achieved by providing a display device that includes the aforementioned pixels.

[0012] According to other aspects of this disclosure, the above and other objectives can be achieved by providing a display device comprising a plurality of sub-pixels having an opening region defined by the intersection of a gate line and a data line, wherein each of the plurality of sub-pixels may include a first circuit region disposed on a first side of the opening region, a second circuit region disposed on a second side of the opening region, and a capacitor overlapping the opening region and formed between the first circuit region and the second circuit region.

[0013] In the pixel and display device including the pixel according to this disclosure, the driving thin-film transistor can be disposed above the light-emitting region of each sub-pixel, and the storage capacitor can be embodied in the light-emitting region, thereby increasing the aperture ratio and simplifying the structure. As a result, display performance can be improved by increasing brightness based on the increased aperture ratio, and the lifespan of the light-emitting diode can be increased.

[0014] In addition to the effects of this disclosure as described above, those skilled in the art will clearly understand other purposes and features of this disclosure from the following description. Attached Figure Description

[0015] The above and other objects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This is a schematic block diagram illustrating a display device according to various embodiments of the present disclosure;

[0017] Figure 2 It is shown Figure 1 A schematic circuit driving view of the sub-pixels of the display device;

[0018] Figure 3 It is shown Figure 1 The equivalent circuit diagram of an example of a sub-pixel of the display device shown;

[0019] Figure 4 This is a schematic plan view showing a unit pixel of a display device according to various embodiments of the present disclosure;

[0020] Figure 5 This is a plan view showing a unit pixel of a display device according to various embodiments of the present disclosure;

[0021] Figure 6 It is along Figure 5 A cross-sectional view taken from line I-I' in the diagram;

[0022] Figure 7 From Figure 5 A cross-sectional view taken from line II-II' in the diagram;

[0023] Figure 8 It is along Figure 5 A cross-sectional view taken from line III-III' in the diagram;

[0024] Figure 9 It is shown Figure 5 The equivalent circuit diagram of the storage capacitor of the sub-pixel of part A;

[0025] Figure 10 yes Figure 5 A magnified view of part B;

[0026] Figure 11 It is along Figure 10 A cross-sectional view taken from line IV-IV' in the diagram;

[0027] Figures 12 to 16 It is shown Figure 5 A planar view of a single-layer structure representing a portion of a unit pixel;

[0028] Figure 17 This is a plan view showing a unit pixel of a display device according to various embodiments of the present disclosure;

[0029] Figure 18 It is along Figure 17 A cross-sectional view taken from line V-V' in the diagram;

[0030] Figure 19 It is along Figure 17 The cross-sectional view taken by line VI-VI' in the middle; and

[0031] Figure 20 It is along Figure 17 The cross-sectional view taken from line VII-VII' in the diagram. Detailed Implementation

[0032] The advantages and features of this disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the exemplary embodiments described. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0033] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. The same reference numerals denote the same elements throughout the specification. In the following description, detailed descriptions that would unnecessarily obscure the focus of this disclosure will be omitted where such descriptions would unnecessarily obscure the main points.

[0034] Where “including,” “having,” and “contains” are used as described in this specification, an additional part may be added, unless “only” is used. Unless otherwise indicated, singular terms may include plural forms.

[0035] When interpreting components, even without an explicit description, the components are interpreted as including a range of error.

[0036] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "near," one or more parts may be arranged between two other parts unless "only" or "directly" is used.

[0037] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “only” or “directly” is used.

[0038] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0039] The terms “first horizontal axis direction”, “second horizontal axis direction” and “vertical axis direction” should not be interpreted solely based on the geometric relationship that the directions are perpendicular to each other, but may refer to directions with a wider directional range within the scope of which the components of this disclosure can be functionally operated.

[0040] The term "at least one" should be understood as any and all combinations including one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of two or more of the first, second, and third items, as well as all items derived from the first, second, or third item.

[0041] Features of the various embodiments of this disclosure may be linked or combined with each other in part or in whole, and, as will be fully understood by those skilled in the art, may interoperate differently with each other and be technically driven. Embodiments of this disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

[0042] In the following, preferred embodiments of the display device according to the present disclosure will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Since the scale of each element shown in the drawings differs from the actual scale for ease of description, the present disclosure is not limited to the scales shown.

[0043] Figure 1 This is a schematic block diagram illustrating a display device according to various embodiments of the present disclosure. Figure 2 It is shown Figure 1 A schematic circuit driving view of the sub-pixels of the display device. Figure 3 It is shown Figure 1 The equivalent circuit diagram of an example of a sub-pixel of the display device shown.

[0044] Reference Figures 1 to 3 The display device 100 according to various embodiments of the present disclosure may include a display panel 110, an image processor 120, a timing controller 130, a data driver 140, and a scan driver 150.

[0045] Display panel 110 can display an image in response to data signals DATA and scan signals provided from data driver 140 and scan driver 150, respectively. Display panel 110 may include sub-pixels SP for displaying the image.

[0046] Depending on the specific structure, subpixels can be formed as top-emitting, bottom-emitting, or dual-emitting types. A subpixel SP can include red, green, and blue subpixels, or it can include red, blue, white, and green subpixels. Depending on its light-emitting characteristics, a subpixel SP can have one or more different light-emitting regions.

[0047] The image processor 120 can output a data enable signal DE together with a data signal DATA provided from an external source. In addition to the data enable signal DE, the image processor 120 can also output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, but for the sake of description, these signals will be omitted and not shown.

[0048] The image processor 120 can provide data signals DATA and drive signals to the timing controller 130. The drive signals include a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing controller 130 can output a data timing control signal DDC for controlling the operating timing of the data driver 140 and a gating timing control signal GDC for controlling the operating timing of the scan driver 150 based on the drive signals.

[0049] Data driver 140 can sample and latch the data signal DATA provided by timing controller 130 in response to the data timing control signal DDC provided by timing controller 130, convert the latched data signal into a gamma reference voltage, and output the converted gamma reference voltage. Data driver 140 can output the data signal DATA through data lines DL1 to DLn. Data driver 140 can be implemented as an integrated circuit (IC).

[0050] The scan driver 150 can output a scan signal in response to a gating timing control signal GDC provided from the timing controller 130. The scan driver 150 can output the scan signal via gating lines GL1 to GLm. The scan driver 150 can be implemented as an IC (integrated circuit) or as a GIP (gate-in-panel) type display panel 110.

[0051] like Figure 2 As shown, a sub-pixel SP constituting a unit pixel may include a switching thin-film transistor SW, a driving thin-film transistor DR, a storage capacitor Cst, a compensation circuit CC, and a light-emitting diode EL.

[0052] In response to a scan signal provided via the first gate line GL1, the switching thin-film transistor SW can perform a switching operation to store a data signal provided via the first data line DL1 as a data voltage in the storage capacitor Cst. The driving thin-film transistor DR can operate to cause a drive current to flow between the first power line EVDD (e.g., a high-potential voltage) and the second power line EVSS (e.g., a low-potential voltage) according to the data voltage stored in the storage capacitor Cst. The light-emitting diode EL can operate to emit light according to the drive current generated by the driving thin-film transistor DR.

[0053] A compensation circuit CC is a circuit added within a sub-pixel to compensate for the threshold voltage driving the thin-film transistor DR. The compensation circuit CC may include one or more thin-film transistors. Depending on the compensation method, the compensation circuit CC can have various configurations, and examples will be described below.

[0054] like Figure 3 As shown, the compensation circuit CC may include a sensing thin-film transistor ST and a sensing line VREF.

[0055] A sensing thin-film transistor (ST) can be connected between the drain of a driving thin-film transistor (DR) and the anode of a light-emitting diode (EL) (hereinafter referred to as a sensing node). The sensing TFT ST can be operated to provide an initialization voltage (or sensing voltage) transmitted through the sensing line VREF to the sensing node of the driving thin-film transistor DR, or to sense the voltage or current of the sensing node of the driving thin-film transistor DR or the sensing line VREF.

[0056] The first electrode (e.g., the source) of the switching thin-film transistor SW can be connected to the first data line DL1, and the second electrode (e.g., the drain) of the switching thin-film transistor SW can be connected to the gate of the driving thin-film transistor DR.

[0057] The first electrode (e.g., the source) of the driving thin-film transistor DR can be connected to the first power line EVDD, and the second electrode (e.g., the drain) of the driving thin-film transistor DR can be connected to the anode of the light-emitting diode EL.

[0058] The storage capacitor Cst may include a first electrode connected to the gate of a driving thin-film transistor DR and a second electrode connected to the anode of a light-emitting diode EL. In display devices according to various embodiments of the present disclosure, the storage capacitor Cst may include a first electrode pattern DTG connected to the gate of the driving thin-film transistor DR and a second electrode pattern DTS connected to the source of the driving thin-film transistor DR. The first electrode pattern DTG and the second electrode pattern DTS may be formed by conductiveizing the active layer. Furthermore, according to various variations of the first electrode pattern DTG and the second electrode pattern DTS, the storage capacitor Cst may include a first capacitor formed in a horizontal direction and a second capacitor formed in a vertical direction. For example, each of the first electrode pattern DTG and the second electrode pattern DTS may include a finger pattern structure, wherein the first electrode pattern and the second electrode pattern are arranged parallel to each other on the same plane. The horizontal capacitor may be formed by structures spaced apart from each other in the horizontal direction. The storage capacitor Cst will be described in more detail later.

[0059] The anode of the light-emitting diode (EL) can be connected to the second electrode that drives the thin-film transistor (DR), and the cathode of the EL can be connected to the second power supply line (EVSS). For example, the EL can be an organic light-emitting diode (OLED).

[0060] The first electrode (e.g., the source) of the sensing thin-film transistor ST can be connected to the sensing line VREF, and the second electrode (e.g., the drain) of the sensing thin-film transistor ST can be connected to the anode of the light-emitting diode EL, which serves as the sensing node, and the second electrode of the driving thin-film transistor DR.

[0061] Depending on the compensation algorithm (or the configuration of the compensation circuit), the operating time of the sensing thin-film transistor ST can be similar to, the same as, or different from the operating time of the switching thin-film transistor SW. For example, the gate of the switching thin-film transistor SW can be connected to a first gate line GL1, and the gate of the sensing thin-film transistor ST can be connected to a second gate line GL2. In this case, a scan signal Scan can be transmitted to the first gate line GL1, and a sensing signal Sense can be transmitted to the second gate line GL2. In another example, the first gate line GL1 connected to the gate of the switching thin-film transistor SW and the second gate line GL2 connected to the gate of the sensing thin-film transistor ST can be connected to each other.

[0062] The sensing line VREF can be connected to the data driver 140. In this case, the data driver 140 can sense the sensing nodes of sub-pixels in real time, at the non-display period of the image or at N frame periods (N is an integer of 1 or greater), and can generate the sensing results. Simultaneously, the switching thin-film transistor SW and the sensing thin-film transistor ST can be turned on at the same time. In this case, the sensing operation via the sensing line VREF and the data output operation for outputting data signals can be separated (identified) from each other using a time-division multiplexing method of the data driver 140.

[0063] Furthermore, the compensation target based on the sensing result can be a digital data signal, an analog data signal, or a gamma signal. The compensation circuit used to generate a compensation signal (or compensation voltage) based on the sensing result can be implemented as internal circuitry of the data driver 140, internal circuitry of the timing controller 130, or a separate circuit.

[0064] In addition, Figure 3 In the example, although a sub-pixel with a 3T (transistor) 1C (capacitor) structure including a switching thin-film transistor SW, a driving thin-film transistor DR, a storage capacitor Cst, a light-emitting diode EL, and a sensing thin-film transistor ST has been described as an example, each sub-pixel can have a 3T2C, 4T2C, 5T1C, 6T2C, etc. structure when a compensation circuit CC is added to each sub-pixel.

[0065] Figure 4 This is a schematic plan view showing a unit pixel of a display device according to various embodiments of the present disclosure. Figure 4 Briefly illustrated by Figure 3 A unit pixel is composed of sub-pixels.

[0066] Reference Figure 4 According to various embodiments of the present disclosure, a unit pixel of the display device may include a first sub-pixel R, a second sub-pixel B, a third sub-pixel W, and a fourth sub-pixel G, including a red sub-pixel R, a blue sub-pixel B, a white sub-pixel W, and a green sub-pixel G. However, the present disclosure is not limited to... Figure 4 This example illustrates that a unit pixel can consist of a first subpixel R, a second subpixel G, and a third subpixel B, comprising a red subpixel R, a green subpixel G, and a blue subpixel B. Furthermore, various modifications can be made to the arrangement of at least three or four subpixels included in a unit pixel. In the following description, the 3T1C subpixel will be described as an example.

[0067] Each of the first sub-pixel R, the second sub-pixel B, the third sub-pixel W, and the fourth sub-pixel G may include an opening region LE where the light-emitting region is located, and a first circuit region C1 and a second circuit region C2 respectively disposed on both sides (i.e., the upper and lower sides of the figure) of the opening region (or light-emitting region) LE. That is, in the display device according to various embodiments of the present disclosure, the first circuit region C1 and the second circuit region C2 of each of the sub-pixels R, B, W, and G may be separated from each other based on the opening region LE.

[0068] In the display device according to various embodiments of the present disclosure, the driving thin-film transistor DR included in the first sub-pixel R, the second sub-pixel B, the third sub-pixel W, and the fourth sub-pixel G can be respectively disposed in the first circuit regions RC1, BC1, WC1, and GC1, and the switching thin-film transistor SW and the sensing thin-film transistor ST can be respectively disposed in the second circuit regions RC2, BC2, WC2, and GC2, and the storage capacitor Cst can overlap with the opening regions RLE, BLE, WLE, and GLE respectively, and be disposed between the first circuit regions RC1, BC1, WC1, and GC1 and the second circuit regions RC2, BC2, WC2, and GC2.

[0069] Since the display device according to various embodiments of the present disclosure includes a first circuit region C1 and a second circuit region C2 above and below the aperture region LE of the sub-pixels R, B, W and G, sub-pixels R, B, W and G in different rows adjacent to each other can be arranged in a mirror shape to share the common line between them, thereby achieving the effect of increasing the aperture ratio.

[0070] Figure 5 This is a plan view showing a unit pixel of a display device according to various embodiments of the present disclosure. Figure 5 Showing more details Figure 4 The unit pixel of a display device.

[0071] Reference Figure 5 The display device according to various embodiments of the present disclosure may include a first sub-pixel R, a second sub-pixel B, a third sub-pixel W, and a fourth sub-pixel G constituting a unit pixel.

[0072] Each sub-pixel R, B, W, and G can be defined by the intersection between the gate line GL and the data line DL, and can include a light-emitting diode PXL, a driving thin-film transistor DR, a sensing thin-film transistor ST, a switching thin-film transistor ST, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0073] The first electrode ANO and the first storage capacitor Cst1 of the light-emitting diode PXL can be disposed in the opening region (or the light-emitting region).

[0074] The driving thin-film transistor DR can be disposed in the first circuit region, which is disposed on one side of the opening region (e.g., the upper side of the opening region), and the sensing thin-film transistor ST, the switching thin-film transistor SW, and the second storage capacitor Cst2 can be disposed in the second circuit region, which is disposed on the other side of the opening region (e.g., the lower side of the opening region).

[0075] Each sub-pixel R, B, W, and G may include an opening region (or light-emitting region) provided with a first storage capacitor Cst1, a color filter CF, and a light-emitting diode PXL; a first circuit region provided on one side of the opening region (e.g., the upper side of the opening region) including a driving thin-film transistor DR; and a second circuit region provided on the other side of the opening region (e.g., the lower side of the opening region) including a sensing thin-film transistor ST, a switching thin-film transistor SW, and a second storage capacitor Cst2.

[0076] By using power lines EVDD as boundaries, the four sub-pixels constituting a unit pixel—first sub-pixel R, second sub-pixel B, third sub-pixel W, and fourth sub-pixel G—can be separated from their adjacent unit pixels. For example, power lines EVDD can be positioned to the left of the first sub-pixel R and to the right of the fourth sub-pixel G, respectively, arranged along a column direction (e.g., vertically). A horizontal power line EVDD_H, extending in the horizontal direction and electrically connected to the power lines EVDD on the left and right, can be included between the power lines EVDD. The power lines EVDD can be connected via the horizontal power line EVDD_H to the driving thin-film transistor DR disposed in the first circuit region of the first sub-pixel R, second sub-pixel B, third sub-pixel W, and fourth sub-pixel G.

[0077] Data lines DL can be arranged parallel to each other between the first sub-pixel R and the second sub-pixel B, and between the third sub-pixel W and the fourth sub-pixel G, which are arranged along the column direction. The data lines can provide data signals to the switching thin-film transistors SW located in the second circuit regions of sub-pixels R, B, W, and G.

[0078] The reference line VREF can be configured to extend along the column direction between the second sub-pixel B and the third sub-pixel W. The reference line VREF can include a horizontal reference line VREF_H extending to the left and right in the horizontal direction. The reference line VREF can be connected via the horizontal reference line VREF_H to the sensing thin-film transistor ST disposed in the second circuit region of the first sub-pixel R, the second sub-pixel B, the third sub-pixel W, and the fourth sub-pixel G.

[0079] Figure 6 It is along Figure 5 The cross-sectional view taken from line I-I' in the diagram. Figure 7 From Figure 5 The cross-sectional view taken from line II-II' in the diagram. Figure 8 It is along Figure 5 The cross-sectional view taken from line III-III' in the diagram. Figure 9 It is shown Figure 5 The figures show the equivalent circuit diagram of the storage capacitor Cst for a sub-pixel of portion A. These figures are intended to specifically illustrate the storage capacitor Cst in a display device according to various embodiments of the present disclosure.

[0080] Reference Figures 6 to 9 Combination Figure 5 This describes the cross-sectional structure of the storage capacitor Cst in a display device according to various embodiments of the present disclosure.

[0081] like Figure 6 As shown, the buffer layer BUF, active layer ACT, interlayer dielectric film ILD, color filter CF, outer coating OC, and light-emitting diode PXL can be set in the opening regions of each sub-pixel R, B, W, and G.

[0082] The buffer layer BUF can be formed on the entire surface of the substrate SUB, and the active layer ACT on the buffer layer BUF can be connected to either the gate or source of the driving thin-film transistor DR. For example, in Figure 6 In this configuration, the active layer ACT can be a first electrode pattern DTG that is conductive by being connected to the gate of the driving thin-film transistor DR. Alternatively, the active layer ACT can be a second electrode pattern DTS that is conductive by being connected to the source of the driving thin-film transistor DR.

[0083] Interlayer dielectric film (ILD), color filter (CF), outer coating (OC), and light-emitting diode (PXL) can be formed on the active layer (ACT).

[0084] The first electrode pattern DTG, formed by conductiveizing the active layer ACT and the first electrode ANO of the light-emitting diode PXL, can be separated from each other by inserting an interlayer dielectric film ILD, a color filter CF, and an outer coating OC, thereby forming a vertical capacitor Cst_V1 in the vertical direction. Optionally, the vertical capacitor Cst_V1 can be formed in the vertical direction between the second electrode pattern DTS formed by conductiveizing the active layer ACT and the first electrode ANO of the light-emitting diode PXL.

[0085] like Figure 7 As shown, in the opening regions of each sub-pixel R, B, W, and G, the buffer layer BUF, the active layer ACT, the interlayer dielectric film ILD, the color filter CF, the outer coating OC, and the light-emitting diode PXL can be disposed on the substrate SUB.

[0086] The buffer layer BUF can be formed on the entire surface of the substrate SUB, and the active layer ACT on the buffer layer BUF can be connected to either the gate or source of the driving thin-film transistor DR. For example, in Figure 7 In this structure, the active layer ACT can be a finger-patterned structure, wherein each of a plurality of first electrode patterns DTGs, which are conductive by being connected to the gate of a driving thin-film transistor DR, and each of a plurality of second electrode patterns DTSs, which are conductive by being connected to the source of the driving thin-film transistor DR, are arranged parallel to each other on the same plane. The width h1 of each of the plurality of first electrode patterns DTGs and second electrode patterns DTS can be smaller than the width h2 between the first electrode patterns DTGs and the second electrode patterns DTS.

[0087] Multiple first electrode patterns DTG and multiple second electrode patterns DTS formed by the conductor formation of the active layer ACT can be alternately arranged, thereby forming a horizontal capacitor Cst_H between the first electrode patterns and the second electrode patterns in the horizontal direction.

[0088] Reference Figure 6 and Figure 7 A first storage capacitor Cst1 can be formed in the opening region of each of the sub-pixels R, B, W, and G, the first storage capacitor Cst1 comprising... Figure 6 The vertical capacitor Cst_V1 shown is Figure 7 The horizontal capacitor Cst_H is shown in the figure. For example, based on the red sub-pixel R, the first storage capacitor Cst1 of the opening region can be a capacitor composed of the vertical capacitor Cst_V1 and the horizontal capacitor Cst_H combined with each other.

[0089] like Figure 8 As shown, in the second circuit region of each sub-pixel R, B, W and G, the light-shielding layer LS, the buffer layer BUF, the active layer ACT, the interlayer dielectric film ILD and the source / drain electrode SD can be disposed on the substrate SUB.

[0090] The light-shielding layer LS can be disposed on the substrate SUB to overlap with the active layer ACT and the source / drain electrode SD. The active layer ACT on the buffer layer BUF can be connected to either the gate or the source of the driving thin-film transistor DR. For example, in Figure 8 In this configuration, the active layer ACT can be a first electrode pattern DTG that is conductive by being connected to the gate of the driving thin-film transistor DR. Alternatively, the active layer ACT can be a second electrode pattern DTS that is conductive by being connected to the source of the driving thin-film transistor DR.

[0091] The interlayer dielectric film (ILD) and source / drain electrodes (SDs) can be formed on the active layer (ACT). That is, the light-shielding layer (LS) can be placed below the active layer (ACT) by inserting a buffer layer (BUF), and the source / drain electrodes (SDs) can be placed above the active layer (ACT) by inserting an interlayer dielectric film (ILD).

[0092] In the first electrode pattern DTG formed by making the active layer ACT conductive, the dual vertical capacitor Cst_V2 is separated from the light-shielding layer LS by inserting a buffer layer BUF and from the source / drain electrode SD by inserting an interlayer dielectric film ILD. The dual vertical capacitor Cst_V2 can be formed in a direction vertical to the light-shielding layer LS located below it and the source / drain electrode SD located above it.

[0093] Reference Figure 9 In the display device according to various embodiments of the present disclosure, the storage capacitor Cst may overlap with the opening regions of sub-pixels R and B, and be formed between the driving thin-film transistor DR in the first circuit region and the sensing thin-film transistor ST in the second circuit region. For example, based on the red sub-pixel R, a capacitor consisting of dual vertical capacitors Cst_V2 in the non-opening region (or the second circuit region), a vertical storage capacitor Cst_V1 corresponding to the first storage capacitor Cst1 in the opening region, and a horizontal capacitor Cst_H can be combined to form the storage capacitor Cst.

[0094] Figure 10 yes Figure 5 A magnified view of part B. Figure 11 It is along Figure 10 The cross-sectional view taken from line IV-IV' in the diagram.

[0095] Combination Figure 5 Reference Figure 10 and Figure 11 In the display device according to various embodiments of the present disclosure, the active layer ACT may be connected to the source of the driving thin film transistor DR and may extend to overlap with at least a portion of the horizontal power line EVDD_H.

[0096] like Figure 10 As shown, a portion of the active layer ACT can overlap with the gate GAT of the driving thin-film transistor DR, and extend from the gate GAT to overlap with the horizontal power line EVDD_H, thereby forming a portion of the active layer ACT that extends to a position where the power line EVDD and the horizontal power line EVDD_H are adjacent to each other.

[0097] like Figure 11 As shown, the light-shielding layer LS, buffer layer BUF, active layer ACT, gate GAT, interlayer dielectric film ILD, and source / drain electrode SD can be disposed on the substrate SUB.

[0098] The light-shielding layer LS can be disposed on the substrate SUB to overlap with the active layer ACT and the source / drain electrode SD, and can directly contact the source / drain electrode SD by inserting the active layer ACT into the contact area EVDD_CNT.

[0099] In the display device according to various embodiments of the present disclosure, since a contact region EVDD_CNT that directly contacts the light-shielding layer LS, the active layer ACT, and the source / drain electrode SD can be formed in the power line EVDD, the contact hole for making the driving thin-film transistor DR contact the source / drain electrode SD can be removed from the opening region, thereby increasing the aperture ratio. Furthermore, the line resistance load of the horizontal power line EVDD_H can be reduced by using the dual lines of the active layer ACT and the source / drain electrode SD.

[0100] Figures 12 to 16 It is shown Figure 5 The diagram shows a planar view of a single-layer structure representing a portion of a unit pixel.

[0101] Combination Figure 5 Reference Figures 12 to 16 The sub-pixels constituting a unit pixel in a display device according to various embodiments of the present disclosure will be described in more detail.

[0102] like Figure 12 As shown, power lines EVDD, two sets of data lines DL, and a reference line VREF can be formed on a substrate. The power lines EVDD are arranged parallel to each other along a first direction (e.g., from left to right) and extend in a second direction (e.g., a vertical direction) intersecting the first direction. The two sets of data lines DL are arranged adjacent to each other, parallel to the power lines EVDD, between the power lines EVDD, and the reference line is arranged parallel to the data lines DL, between the data lines DL. The power lines EVDD, data lines DL, and reference line VREF can be formed by a light-shielding layer LS.

[0103] A light-shielding pattern Cst2_LS can be set to correspond to the sensing thin-film transistor ST and the switching thin-film transistor SW formed in the second circuit region of the first sub-pixel R, the second sub-pixel B, the third sub-pixel W and the fourth sub-pixel G, and to form the second storage capacitor Cst2.

[0104] Buffer layers (BUF) can be set to form a buffer layer. Figure 12 The substrate of the device shown is covered with a buffer layer (BUF). The buffer layer (BUF) can be used to protect the thin-film transistor formed by subsequent processes from impurities such as alkali ions leaking from the light-shielding layer (LS) or the substrate. The buffer layer (BUF) can be a multilayer of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of SiOx and SiNx.

[0105] like Figure 13 As shown, the active layer ACT can be set on the buffer layer BUF.

[0106] The active layer ACT may include an active layer DR_ACT of driving thin-film transistors DR disposed in the first circuit regions RC1, BC1, WC1, and GC1 of each sub-pixel R, B, W, and G; an active layer ST_ACT of sensing thin-film transistors ST disposed in the second circuit regions RC2, BC2, WC2, and GC2; and an active layer SW_ACT of switching thin-film transistors SW. Furthermore, the active layer ACT may include an active layer constituting a first electrode pattern DTG and a second electrode pattern DTS, which are disposed in the opening regions of each sub-pixel R, B, W, and G. In the active layer ACT, the portion connected to the gate of the driving thin-film transistor DR in the first circuit region, the portion constituting the first electrode pattern DTG in the opening region, and the portion constituting the switching thin-film transistor SW in the second circuit region can be formed integrally. Furthermore, in the active layer ACT, the portion connected to the source of the driving thin-film transistor DR in the first circuit region, the portion constituting the second electrode pattern DTS in the opening region, and the portion constituting the sensing thin-film transistor ST in the second circuit region can be formed integrally.

[0107] Each of the first electrode pattern DTG and the second electrode pattern DTS in the active layer ACT in the opening region can be formed as a first common pattern, a second common pattern, and a plurality of first and second electrode patterns that are commonly connected to the first common pattern and the second common pattern and are arranged in parallel as a finger pattern structure.

[0108] like Figure 14 As shown, the gate DR_GAT for constituting the driving thin-film transistor DR can be formed in the first circuit region of the first sub-pixel R, the second sub-pixel B, the third sub-pixel W, and the fourth sub-pixel G, and the gate ST_GAT for constituting the sensing thin-film transistor ST and the gate SW_GAT for constituting the switching thin-film transistor SW can be disposed in the second circuit region. The gate ST_GAT of the sensing thin-film transistor ST and the gate SW_GAT of the switching thin-film transistor SW can be formed as a single unit.

[0109] Interlayer dielectric film (ILD) can be set in the formation of Figure 14 The substrate of the device shown is covered with a layer of interlayer dielectric film (ILD). The interlayer dielectric film (ILD) can be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer of SiOx and SiNx.

[0110] like Figure 15As shown, the power line EVDD, the horizontal power line EVDD_H, the horizontal reference line VREF_H, and the gate line GL can be formed on the interlayer dielectric film ILD. Furthermore, the source / drain electrodes SD of the driving thin-film transistor DR formed in the first circuit region of the first sub-pixel R, the second sub-pixel B, the third sub-pixel W, and the fourth sub-pixel G, and the source / drain electrodes SD of the sensing thin-film transistor ST and the switching thin-film transistor SW formed in the second circuit region can also be formed.

[0111] Figure 15 The components shown can be formed from the same material and can be multilayered from any of the group consisting of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or alloys thereof. For example, the components can be made from a Cu / MoTi bilayer.

[0112] In addition, the passivation film PAS can be configured to cover Figure 15 All components are shown. The passivation film PAS is an insulating film used to protect the components underneath, and can be a multilayer of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of SiOx and SiNx.

[0113] Red, blue, white, and green color filters (CFs) can be positioned on the passivation film PAS to correspond to the opening regions of the individual sub-pixels R, B, W, and G. The color filters (CFs) can emit red, blue, white, and green light by passing through white light emitted from the light-emitting diode PXL.

[0114] An outer coating OC can be applied to the color filter CF to cover it. The outer coating OC can be a planarization film that reduces the step difference of the underlying structure.

[0115] like Figure 16 As shown, the light-emitting diode (LED) PXL can be disposed on the outer coating OC to correspond to the opening regions of each sub-pixel R, B, W, and G. The LED PXL may include a first electrode (e.g., anode ANO), a light-emitting layer, and a second electrode (e.g., cathode). For example, the LED PXL may be an organic light-emitting diode (OLED).

[0116] Figure 17 This is a plan view showing a unit pixel of a display device according to various embodiments of the present disclosure. Figure 18 It is along Figure 17 The cross-sectional view taken from line V-V' in the diagram. Figure 19 It is along Figure 17 The cross-sectional view taken from line VI-VI' in the diagram. Figure 20 It is along Figure 17 The cross-sectional view taken from line VII-VII' in the diagram. Figure 17 In, with Figure 5Compared to the unit pixel of a display device, the number of masks can be reduced, and Figure 17 The number of masks in Figure 5 The structure of the active layer in the opening region was modified. Therefore, in the following description, the structure of the active layer in the opening region was modified. Figure 5 The components of the display device are described in a modified manner, and components related to the display device are omitted. Figure 5 Repeated descriptions of the same other elements.

[0117] Reference Figures 17 to 20 In the display devices according to various embodiments of this disclosure, the source / drain electrodes are omitted and replaced with gate electrodes. Therefore, the processes for forming the source / drain electrodes and the masking processes for forming the contact holes for the source / drain electrodes can be reduced.

[0118] like Figure 17 As shown, the horizontal power line EVDD_H, which extends horizontally between the power lines EVDD and is electrically connected to the power lines EVDD on the left and right sides, can be formed as the active layer ACT. The horizontal reference line VREF_H, which is connected to the reference line VREF, can be formed as the gate.

[0119] like Figure 18 As shown, the buffer layer BUF, active layer ACT, interlayer dielectric film ILD, color filter CF, outer coating OC, and light-emitting diode PXL can be set in the opening regions of each sub-pixel R, B, W, and G.

[0120] The buffer layer BUF can be formed on the entire surface of the substrate SUB, and the active layer ACT on the buffer layer BUF can be connected to either the gate or source of the driving thin-film transistor DR. For example, in Figure 18 In this configuration, the active layer ACT can be a first electrode pattern DTG that is conductive by being connected to the gate of the driving thin-film transistor DR. Alternatively, the active layer ACT can be a second electrode pattern DTS that is conductive by being connected to the source of the driving thin-film transistor DR.

[0121] Interlayer dielectric film (ILD), color filter (CF), outer coating (OC), and light-emitting diode (PXL) can be formed on the active layer (ACT).

[0122] The first electrode pattern DTG, formed by conductiveizing the active layer ACT and the first electrode ANO of the light-emitting diode PXL, can be separated from each other by inserting an interlayer dielectric film ILD, a color filter CF, and an outer coating OC, thereby forming a vertical capacitor Cst_V1 in the vertical direction. Optionally, the vertical capacitor Cst_V1 can be formed in the vertical direction between the second electrode pattern DTS formed by conductiveizing the active layer ACT and the first electrode ANO of the light-emitting diode PXL.

[0123] Right now, Figure 18 The vertical capacitor Cst_V1 shown can be substantially the same as Figure 6 The vertical capacitor Cst_V1 shown is the same.

[0124] like Figure 19 As shown, the buffer layer BUF, active layer ACT, interlayer dielectric film ILD, color filter CF, outer coating OC, and light-emitting diode PXL can be set in the opening regions of each sub-pixel R, B, W, and G.

[0125] The buffer layer BUF can be formed on the entire surface of the substrate SUB, and the active layer ACT on the buffer layer BUF can be connected to either the gate or source of the driving thin-film transistor DR. For example, in Figure 19 In this structure, the active layer ACT can have a structure in which a first electrode pattern DTG, which is conductive by being connected to the gate of the driving thin film transistor DR, and a second electrode pattern DTS, which is conductive by being connected to the source of the driving thin film transistor DR, are spaced parallel to each other on the same plane.

[0126] A horizontal capacitor Cst_H can be formed horizontally between the first electrode pattern DTG and the second electrode pattern DTS formed by the conductive layer ACT. For example, the first electrode pattern DTG can be formed with a wider area than the second electrode pattern DTS. That is, in order to make the first electrode pattern DTG and the second electrode pattern DTS form a horizontal capacitor Cst_H formed at a single interval, the vertical capacitor CST_V1 between the conductive first electrode pattern DTG and the first electrode ANO of the light-emitting diode PXL can be increased by increasing the area of ​​the first electrode pattern DTG. Meanwhile, although... Figure 19 The diagram shows that the area of ​​the first electrode pattern DTG is wider than the area of ​​the second electrode pattern DTS. The second electrode pattern DTS can also be formed with an area wider than the first electrode pattern DTG. In this case, the vertical capacitor CST_V1 between the conductive second electrode pattern DTS and the first electrode ANO of the light-emitting diode PXL can be increased by increasing the area of ​​the second electrode pattern DTS.

[0127] like Figure 20 As shown, in the second circuit region of each sub-pixel R, B, W, and G, a light-shielding layer LS, a buffer layer BUF, an active layer ACT, an interlayer dielectric film ILD, and a light-emitting diode PXL can be disposed on the substrate SUB. That is, with Figure 8 Unlike the double vertical capacitors in the non-opening region shown, in Figure 20 In this configuration, the source / drain SD can be omitted, and the LED PXL can be configured to extend into the region where the source / drain SD is omitted.

[0128] The light-shielding layer LS can be disposed on the substrate SUB to overlap with the active layer ACT and the light-emitting diode PXL. The active layer ACT on the buffer layer BUF can be connected to either the gate or source of the driving thin-film transistor DR. For example, in Figure 20 In this configuration, the active layer ACT can be a first electrode pattern DTG that is conductive by being connected to the gate of the driving thin-film transistor DR. Alternatively, the active layer ACT can be a second electrode pattern DTS that is conductive by being connected to the source of the driving thin-film transistor DR.

[0129] The interlayer dielectric film (ILD) and the light-emitting diode (PXL) can be formed on the active layer (ACT). That is, the light-shielding layer (LS) can be placed below the active layer (ACT) by inserting a buffer layer (BUF), and the light-emitting diode (PXL) can be placed above the active layer (ACT) by inserting an interlayer dielectric film (ILD).

[0130] In the first electrode pattern DTG formed by making the active layer ACT conductive, separated from the light-shielding layer LS by inserting a buffer layer BUF and separated from the light-emitting diode PXL by inserting an interlayer dielectric film ILD, a dual vertical capacitor Cst_V2 can be formed in the vertical direction to each of the light-shielding layer LS below it and the light-emitting diode PXL above it.

[0131] The pixels and display devices including the pixels according to various embodiments of the present disclosure can be described as follows.

[0132] A pixel according to various embodiments of the present disclosure may include: a pixel circuit connected to a gate line and a data line; and a light-emitting diode having a first electrode connected to the pixel circuit, wherein the pixel circuit may include: a driving thin-film transistor connected to the first electrode of the light-emitting diode; a first capacitor formed in a horizontal direction between the gate and source of the driving thin-film transistor; and a second capacitor formed in a vertical direction between the gate of the driving thin-film transistor and the first electrode of the light-emitting diode.

[0133] In a pixel according to various embodiments of the present disclosure, a first capacitor may include a plurality of first electrode patterns connected to the gate of a driving thin-film transistor, and a plurality of second electrode patterns connected to the source of the driving thin-film transistor and disposed between the plurality of first electrode patterns.

[0134] In pixels according to various embodiments of the present disclosure, the gate and source of the driving thin-film transistor can form an active layer, and a plurality of first electrode patterns and a plurality of second electrode patterns can be made of the same material as the active layer.

[0135] In pixels according to various embodiments of the present disclosure, each of the plurality of first electrode patterns and the plurality of second electrode patterns may be a finger pattern structure.

[0136] In pixels according to various embodiments of the present disclosure, a plurality of first electrode patterns and a plurality of second electrode patterns may be arranged in parallel on the same plane.

[0137] In the pixels of various embodiments according to the present disclosure, the pixel may further include: a first common pattern that is commonly connected to one side of each of the plurality of first electrode patterns and connected to either the gate or the source of the driving thin-film transistor; and a second common pattern that is configured to be parallel to the first common pattern and connected to the other of the gate or the source of the driving thin-film transistor, and commonly connected to one side of each of the plurality of second electrode patterns, wherein the plurality of first electrode patterns and the plurality of second electrode patterns may be alternately disposed between the first common pattern and the second common pattern.

[0138] In a pixel according to various embodiments of the present disclosure, the first capacitor may include: a first common electrode pattern connected to the gate of the driving thin-film transistor; and a second common electrode pattern configured to be parallel to the first common electrode pattern and connected to the source of the driving thin-film transistor.

[0139] In pixels according to various embodiments of the present disclosure, the second capacitor may be formed between the first common electrode pattern and the first electrode of the light-emitting diode.

[0140] In the pixels of various embodiments according to this disclosure, the pixel may further include an opening region overlapping the light-emitting diode and a circuit region overlapping the pixel circuit, wherein each of the first capacitor and the second capacitor may be disposed in the opening region.

[0141] In pixels according to various embodiments of the present disclosure, the circuit region may include a first circuit region disposed on a first side of the opening region and a second circuit region disposed on a second side of the opening region.

[0142] In the pixels according to various embodiments of the present disclosure, the pixel circuit may further include a switching circuit connected to a gate line and a data line, wherein the driving thin-film transistor may be disposed in the first circuit region and the switching circuit may be disposed in the second circuit region.

[0143] In the pixels of various embodiments of the present disclosure, the pixels may further include a reference line to which a reference voltage is provided, wherein the switching circuit may include a first switching thin-film transistor connected to a gating line and a data line and the gate of a driving thin-film transistor, and a second switching thin-film transistor connected to the gating line, the reference line and the source of the driving thin-film transistor.

[0144] A display device according to various embodiments of the present disclosure may include a plurality of sub-pixels having an opening region defined by the intersection of a gate line and a data line, wherein each of the plurality of sub-pixels may include a first circuit region disposed on a first side of the opening region, a second circuit region disposed on a second side of the opening region, and a capacitor overlapping the opening region and formed between the first circuit region and the second circuit region.

[0145] A display device according to various embodiments of the present disclosure may include: a light-emitting diode disposed in the opening region and having a first electrode; a driving thin-film transistor disposed in the first circuit region and connected to the first electrode of the light-emitting diode; and a switching circuit disposed in the second circuit region and connected to the gate line and the data line, wherein the capacitor may include: a first capacitor formed in a horizontal direction between the gate and source of the driving thin-film transistor; and a second capacitor formed in a vertical direction between the gate electrode and the source of the driving thin-film transistor.

[0146] In the display device according to various embodiments of the present disclosure, the first capacitor may include a plurality of first electrode patterns connected to the gate of a driving thin film transistor, and a plurality of second electrode patterns connected to the source of the driving thin film transistor and disposed between the plurality of first electrode patterns.

[0147] In the display device according to various embodiments of the present disclosure, the gate and source of the driving thin-film transistor can form an active layer, and a plurality of first electrode patterns and a plurality of second electrode patterns can be made of the same material as the active layer.

[0148] In the display device according to various embodiments of the present disclosure, each of the plurality of first electrode patterns and each of the plurality of second electrode patterns may be disposed in parallel on the same plane as the finger pattern structure.

[0149] The display device according to various embodiments of the present disclosure may further include: a first common pattern, which is commonly connected to one side of each of the plurality of first electrode patterns and connected to either the gate or the source of the driving thin-film transistor; and a second common pattern, which is configured to be parallel to the first common pattern and connected to the other of the gate or the source of the driving thin-film transistor, and is commonly connected to one side of each of the plurality of second electrode patterns, wherein the plurality of first electrode patterns and the plurality of second electrode patterns may be alternately disposed between the first common pattern and the second common pattern.

[0150] In a display device according to various embodiments of the present disclosure, the first capacitor may include: a first common electrode pattern connected to the gate of the driving thin-film transistor; and a second common electrode pattern configured to be parallel to the first common electrode pattern and connected to the source of the driving thin-film transistor.

[0151] It will be apparent to those skilled in the art that the disclosure described above is not limited to the embodiments and drawings described herein, and that various substitutions, modifications, and variations can be made to the disclosure without departing from its spirit or scope. Therefore, the scope of this disclosure is defined by the appended claims, and all variations or modifications intended to be derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of this invention.

Claims

1. A pixel comprising: A pixel circuit that is connected to the gating line and the data line; as well as A light-emitting diode having a first electrode connected to the pixel circuit. The pixel circuit includes: A driving thin-film transistor is connected to the first electrode of the light-emitting diode; A first capacitor is formed horizontally between the gate and source of the driving thin-film transistor; and A second capacitor is formed vertically between the gate of the driving thin-film transistor and the first electrode of the light-emitting diode. The first capacitor includes: A plurality of first electrode patterns connected to the gate of the driving thin-film transistor; and A plurality of second electrode patterns are connected to the source of the driving thin-film transistor and disposed between the plurality of first electrode patterns.

2. The pixel of claim 1, wherein, The gate and source of the driving thin-film transistor constitute an active layer, and the plurality of first electrode patterns and the plurality of second electrode patterns are made of the same material as the active layer.

3. The pixel of claim 2, wherein, Each of the plurality of first electrode patterns and the plurality of second electrode patterns is a finger-shaped pattern structure.

4. The pixel of claim 3, wherein, The plurality of first electrode patterns and the plurality of second electrode patterns are arranged in parallel on the same plane.

5. The pixel according to claim 4, wherein the pixel further comprises: A first common pattern, which is commonly connected to one side of each of the plurality of first electrode patterns and to either the gate or the source of the driving thin-film transistor; as well as A second common pattern is configured to be parallel to the first common pattern and connected to another of the gate and source of the driving thin-film transistor, and together connected to one side of each of the plurality of second electrode patterns. The plurality of first electrode patterns and the plurality of second electrode patterns are alternately arranged between the first common pattern and the second common pattern.

6. The pixel of claim 1, wherein, The first capacitor includes: A first common electrode pattern, which is connected to the gate of the driving thin-film transistor; and The second common electrode pattern is configured to be parallel to the first common electrode pattern and connected to the source of the driving thin-film transistor.

7. The pixel of claim 6, wherein, The second capacitor is formed between the first common electrode pattern and the first electrode of the light-emitting diode.

8. The pixel according to claim 1, wherein the pixel further comprises: The opening region overlaps with the light-emitting diode; as well as The circuit region overlaps with the pixel circuit. Each of the first capacitor and the second capacitor is disposed in the opening region.

9. The pixel of claim 8, wherein, The circuit region includes: A first circuit region is disposed on a first side of the opening region; and A second circuit region is disposed on the second side of the opening region.

10. The pixel of claim 9, wherein, The pixel circuit further includes a switching circuit connected to the gate line and the data line, wherein the driving thin-film transistor is disposed in the first circuit region and the switching circuit is disposed in the second circuit region.

11. The pixel of claim 10, further comprising a reference line to which a reference voltage is provided, wherein The switching circuit includes: A first switching thin-film transistor is connected to the gate line, the data line, and the gate of the driving thin-film transistor; and A second switching thin-film transistor is connected to the gate line, the reference line, and the source of the driving thin-film transistor.

12. A display device comprising a plurality of sub-pixels having an opening region defined by the intersection of a gate line and a data line. wherein Each of the plurality of sub-pixels includes: A first circuit region is disposed on a first side of the opening region; A second circuit region is disposed on the second side of the opening region; A capacitor, which overlaps with the opening region and is formed between the first circuit region and the second circuit region; and A driving thin-film transistor is disposed in the first circuit region. The capacitor includes: A first capacitor is formed horizontally between the gate and source of the driving thin-film transistor; and A second capacitor is formed vertically between the gate and source of the driving thin-film transistor. The first capacitor includes: A plurality of first electrode patterns connected to the gate of the driving thin-film transistor; and A plurality of second electrode patterns are connected to the source of the driving thin-film transistor and disposed between the plurality of first electrode patterns.

13. The display device according to claim 12, further comprising: A light-emitting diode (LED) is disposed in the opening region, and the LED has a first electrode, wherein the driving thin-film transistor is connected to the first electrode of the LED; and A switching circuit is disposed in the second circuit area and connected to the gating line and the data line.

14. The display device of claim 12, wherein, The gate and source of the driving thin-film transistor constitute an active layer, and the plurality of first electrode patterns and the plurality of second electrode patterns are made of the same material as the active layer.

15. The display device of claim 14, wherein, Each of the plurality of first electrode patterns and each of the plurality of second electrode patterns are arranged in parallel on the same plane as the finger pattern structure.

16. The display device according to claim 15, further comprising: A first common pattern, which is commonly connected to one side of each of the plurality of first electrode patterns and to either the gate or the source of the driving thin-film transistor; as well as A second common pattern is configured to be parallel to the first common pattern and connected to another of the gate and source of the driving thin-film transistor, and together connected to one side of each of the plurality of second electrode patterns. The plurality of first electrode patterns and the plurality of second electrode patterns are alternately arranged between the first common pattern and the second common pattern.

17. The display device of claim 13, wherein, The first capacitor includes: A first common electrode pattern, which is connected to the gate of the driving thin-film transistor; and The second common electrode pattern is configured to be parallel to the first common electrode pattern and connected to the source of the driving thin-film transistor.

18. The display device of claim 12, wherein, Subpixels in adjacent rows are set in a mirror shape and share common lines between adjacent subpixels in adjacent rows.

19. A pixel comprising: Opening area; A first circuit region is disposed on a first side of the opening region; A second circuit region is disposed on the second side of the opening region; A capacitor, which overlaps with the opening region and is formed between the first circuit region and the second circuit region; as well as A driving thin-film transistor is disposed in the first circuit region. The capacitor includes: A first capacitor is formed horizontally between the gate and source of the driving thin-film transistor; and A second capacitor is formed vertically between the gate and source of the driving thin-film transistor. The first capacitor includes: A plurality of first electrode patterns connected to the gate of the driving thin-film transistor; and A plurality of second electrode patterns are connected to the source of the driving thin-film transistor and disposed between the plurality of first electrode patterns.

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