Semiconductor device and transistor

Abstract

In a semiconductor device including an oxide semiconductor film, a semiconductor device including a transistor with excellent electric characteristics is provided. A semiconductor device including a transistor is provided. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film over and in contact with the first oxide semiconductor film. The source electrode and the drain electrode each include a first conductive film and a second conductive film over and in contact with the first conductive film. The first conductive film contains titanium and the second conductive film contains copper, and an end portion of the second conductive film includes a region containing a compound including copper.

Description

[0001] This application is a divisional application of the Chinese patent application entitled "Semiconductor device and display device including the semiconductor device", which was filed after the international application PCT international application with international application number PCT / IB2017 / 050230 and international application date of January 17, 2017 entered the Chinese phase and has national application number 201780006127.6. Technical Field

[0002] One aspect of the present invention relates to a semiconductor device comprising an oxide semiconductor film and a display device comprising the semiconductor device.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical field of one aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods for driving these devices, or methods for manufacturing these devices.

[0004] Note that the term "semiconductor device" in this specification refers to all devices that can operate by utilizing the properties of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, and storage devices are also types of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices sometimes include semiconductor devices. Background Technology

[0005] The technique of constructing transistors (also known as thin-film transistors (TFTs) or field-effect transistors (FETs)) using semiconductor films formed on a substrate has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image processing devices (display devices). Silicon-based semiconductor materials are widely known as suitable semiconductor films for transistors. However, oxide semiconductors are also attracting attention as alternative materials.

[0006] For example, techniques for manufacturing transistors using In-Ga-Zn type oxides as oxide semiconductors have been disclosed (e.g., see Patent Document 1).

[0007] Furthermore, while aluminum was previously the most commonly used material for wiring or signal lines, the use of copper (Cu) is now being actively developed to further reduce resistance. However, copper (Cu) has the following disadvantages: it has poor adhesion to the film used as a substrate; and it can diffuse into the semiconductor film of the transistor, easily degrading the transistor's characteristics.

[0008] In addition, Cu-Mn alloys have been disclosed as ohmic electrode materials formed on indium-containing oxide semiconductor films (for example, see Patent Document 2).

[0009] [Preliminary Technology Documents]

[0010] [Patent Literature]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2007-96055

[0012] [Patent Document 2] International Publication No. 2012 / 002573 Summary of the Invention

[0013] The technical problem that the invention aims to solve

[0014] In the structure described in Patent Document 2, after depositing a Cu-Mn alloy film on an oxide semiconductor film, the Cu-Mn alloy film is heat-treated to form a Mn oxide at the interface between the oxide semiconductor film and the Cu-Mn alloy film. This Mn oxide is formed by the diffusion of Mn from the Cu-Mn alloy film into the oxide semiconductor film and its preferential bonding with oxygen constituting the oxide semiconductor film. Regions in the oxide semiconductor film reduced by Mn become oxygen vacancies, increasing carrier concentration and resulting in high conductivity. Furthermore, by diffusing Mn into the oxide semiconductor film, the Cu-Mn alloy becomes pure Cu, yielding an ohmic electrode with low resistance.

[0015] However, the above structure does not take into account the effect of Cu diffusing from the ohmic electrode after its formation. For example, by forming an electrode comprising a Cu-Mn alloy film on an oxide semiconductor film and then performing a heat treatment, Mn oxide is formed at the interface between the oxide semiconductor film and the Cu-Mn alloy film. When this Mn oxide is formed, even if Cu that might diffuse from the Cu-Mn alloy film in contact with the oxide semiconductor film can be suppressed, Cu will still adhere to the surface of the oxide semiconductor film from the side surface of the Cu-Mn alloy film and the side surface or surface of the pure Cu film obtained by detaching Mn from the Cu-Mn alloy film.

[0016] In transistors using oxide semiconductor films, such as those using a bottom gate structure, a portion of the surface of the oxide semiconductor film is located on the so-called back channel side. When Cu is attached to this back channel side, there is a problem of degradation of the transistor's electrical characteristics (e.g., on-state current, field-effect mobility, frequency characteristics, etc.) or degradation of transistor characteristics during gate BT stress testing, one of the reliability tests of transistors.

[0017] In view of the above problems, one objective of the present invention is to provide a novel semiconductor device that uses a copper-containing conductive film in a transistor using an oxide semiconductor film. Another objective of the present invention is to provide a semiconductor device comprising a transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, frequency characteristics, etc.) using a copper-containing conductive film in a transistor using an oxide semiconductor film. A further objective of the present invention is to provide a semiconductor device comprising a transistor in which variations in electrical characteristics of the copper-containing conductive film are suppressed. A further objective of the present invention is to provide a semiconductor device comprising a highly reliable transistor using a copper-containing conductive film in a transistor using an oxide semiconductor film. A further objective of the present invention is to provide a semiconductor device that uses a copper-containing conductive film in a transistor using an oxide semiconductor film while suppressing manufacturing costs. A further objective of the present invention is to provide a semiconductor device that uses a copper-containing conductive film in a transistor using an oxide semiconductor film and achieves high productivity. A further objective of the present invention is to provide a novel semiconductor device. Additionally, a further objective of the present invention is to provide a novel method for manufacturing a semiconductor device.

[0018] Note that the description of the above objectives does not preclude the existence of other objectives. One embodiment of the present invention does not necessarily require achieving all of the above objectives. Furthermore, objectives other than those described above can be identified and extracted from the specification, etc.

[0019] means of solving technical problems

[0020] One aspect of the present invention is a semiconductor device comprising: a transistor, wherein the transistor includes: a gate electrode; a first insulating film on the gate electrode; an oxide semiconductor film including a region sandwiching the first insulating film overlapping the gate electrode; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; and a second insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode, wherein both the source electrode and the drain electrode comprise copper, and both the ends of the source electrode and the ends of the drain electrode include regions comprising copper and silicon.

[0021] Another aspect of the present invention is a semiconductor device comprising: a transistor, wherein the transistor includes: a gate electrode; a first insulating film on the gate electrode; an oxide semiconductor film including a region sandwiching the first insulating film overlapping the gate electrode; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; and a second insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode, wherein both the source electrode and the drain electrode comprise copper, and both the ends of the source electrode and the ends of the drain electrode include regions having a compound comprising copper and silicon.

[0022] In the above structures, preferably, the ends of the source electrode and the drain electrode both include areas that contact the second insulating film.

[0023] Another aspect of the present invention is a semiconductor device comprising: a transistor, wherein the transistor includes: a gate electrode; a first insulating film on the gate electrode; an oxide semiconductor film including a region sandwiching the first insulating film overlapping the gate electrode; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; and a second insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode, wherein both the source electrode and the drain electrode include a first conductive film, a second conductive film on and in contact with the first conductive film, and a third conductive film on and in contact with the second conductive film, the second conductive film comprising copper, the first conductive film and the third conductive film comprising a material that inhibits the diffusion of copper, and the end of the second conductive film including a region comprising copper and silicon.

[0024] Another aspect of the present invention is a semiconductor device comprising: a transistor, wherein the transistor includes: a gate electrode; a first insulating film on the gate electrode; an oxide semiconductor film including a region sandwiching the first insulating film overlapping the gate electrode; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; and a second insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode, wherein both the source electrode and the drain electrode include a first conductive film, a second conductive film on and in contact with the first conductive film, and a third conductive film on and in contact with the second conductive film, the second conductive film comprising copper, the first conductive film and the third conductive film comprising a material for inhibiting the diffusion of copper, and the end of the second conductive film including a region having a compound comprising copper and silicon.

[0025] In each of the above structures, the end of the second conductive film preferably includes a region that contacts the second insulating film.

[0026] In the above structures, the first conductive film and the third conductive film preferably comprise at least one of titanium, tungsten, tantalum, and molybdenum. Furthermore, it is preferred that the first conductive film and the third conductive film comprise an oxide, and that the oxide comprises at least one of In and Zn.

[0027] In the above structures, the oxide semiconductor film preferably contains In, Zn, and M (M represents Al, Ga, Y, or Sn). Furthermore, it is preferred that the oxide semiconductor film includes crystalline portions, and that the crystalline portions have c-axis orientation.

[0028] Another aspect of the present invention is a display device, comprising: a semiconductor device of the above-described embodiments; and a display element. Furthermore, another aspect of the present invention is a display module, comprising: a display device of the above-described embodiments; and a touch sensor. Another aspect of the present invention is an electronic device, comprising: a semiconductor device of the above-described embodiments, a display module of the above-described embodiments, or a display module of the above-described embodiments; and at least one of operation keys and a battery.

[0029] Invention Effects

[0030] According to one aspect of the present invention, a novel semiconductor device is provided that uses a copper-containing conductive film in a transistor using an oxide semiconductor film. According to one aspect of the present invention, a semiconductor device is provided that includes a transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, frequency characteristics, etc.) using a copper-containing conductive film in a transistor using an oxide semiconductor film. According to one aspect of the present invention, a semiconductor device is provided that suppresses variations in the electrical characteristics of a transistor using a copper-containing conductive film in a transistor using an oxide semiconductor film. One aspect of the present invention provides a semiconductor device that includes a highly reliable transistor using a copper-containing conductive film in a transistor using an oxide semiconductor film. According to one aspect of the present invention, a semiconductor device is provided that uses a copper-containing conductive film in a transistor using an oxide semiconductor film and suppresses manufacturing costs. According to one aspect of the present invention, a semiconductor device is provided that uses a copper-containing conductive film in a transistor using an oxide semiconductor film and has high productivity. According to one aspect of the present invention, a novel semiconductor device is provided. Furthermore, according to one aspect of the present invention, a novel method for manufacturing a semiconductor device is provided.

[0031] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Furthermore, effects other than those described above can be identified and extracted from the description, drawings, claims, etc. Attached Figure Description

[0032] [Figure 1] shows a top view and cross-sectional view of one embodiment of a semiconductor device.

[0033] [Figure 2] shows a top view and cross-sectional view of one embodiment of a semiconductor device.

[0034] [Figure 3] shows a cross-sectional view of one type of semiconductor device.

[0035] [Figure 4] shows a top view and cross-sectional view of one type of semiconductor device.

[0036] [Figure 5] shows a cross-sectional view of one type of semiconductor device.

[0037] [Figure 6] shows a top view and cross-sectional view of one embodiment of a semiconductor device.

[0038] [Figure 7] shows a cross-sectional view of one type of semiconductor device.

[0039] [Figure 8] shows a cross-sectional view of one type of semiconductor device.

[0040] [Figure 9] shows a cross-sectional view of one type of semiconductor device.

[0041] [Figure 10] shows a cross-sectional view of one type of semiconductor device.

[0042] [Figure 11] shows a cross-sectional view of one type of semiconductor device.

[0043] [Figure 12] shows a top view and cross-sectional view of one embodiment of a semiconductor device.

[0044] [Figure 13] shows a top view and cross-sectional view of one embodiment of a semiconductor device.

[0045] [Figure 14] shows a cross-sectional view of an example of the manufacturing process of a semiconductor device.

[0046] [Figure 15] shows a cross-sectional view of an example of a semiconductor device manufacturing process.

[0047] [Figure 16] shows a cross-sectional view of an example of a semiconductor device manufacturing process.

[0048] [Figure 17] shows a cross-sectional view of an example of a semiconductor device manufacturing process.

[0049] [Figure 18] shows a cross-sectional view of an example of a semiconductor device manufacturing process.

[0050] [Figure 19] shows a cross-sectional view of an example of a semiconductor device manufacturing process.

[0051] [Figure 20] shows a cross-sectional view of an example of a semiconductor device manufacturing process.

[0052] [Figure 21] is a graph illustrating the range of the atomic number ratio of an oxide semiconductor according to one aspect of the present invention.

[0053] [ Figure 22 [Diagram illustrating the crystallization of InMZnO4]

[0054] [Figure 23] Band diagram of the stacked structure of oxide semiconductor.

[0055] [Figure 24] shows the structure analysis of CAAC-OS and single-crystal oxide semiconductor using XRD and the selected area electron diffraction pattern of CAAC-OS.

[0056] [Figure 25] Cross-sectional TEM image and planar TEM image of CAAC-OS and their analysis images.

[0057] [Figure 26] shows the electron diffraction pattern of nc-OS and a cross-sectional TEM image of nc-OS.

[0058] [Figure 27] Cross-sectional TEM image of a-like OS.

[0059] [ Figure 28 The diagram shows the changes in the crystallization region of In-Ga-Zn oxide due to electron irradiation.

[0060] [ Figure 29 This shows a top view of one mode of display device.

[0061] [ Figure 30 This shows a cross-sectional view of one configuration of the display device.

[0062] [ Figure 31 This shows a cross-sectional view of one configuration of the display device.

[0063] [ Figure 32 This shows a cross-sectional view of one configuration of the display device.

[0064] [ Figure 33 This shows a cross-sectional view of one configuration of the display device.

[0065] [ Figure 34 This shows a cross-sectional view of one configuration of the display device.

[0066] [ Figure 35 This shows a cross-sectional view of one configuration of the display device.

[0067] [Figure 36] Illustrate the block diagram and circuit diagram of the display device.

[0068] [Figure 37] A circuit diagram and timing diagram illustrating one aspect of the present invention.

[0069] [Figure 38] A diagram and circuit diagram illustrating one aspect of the present invention.

[0070] [Figure 39] A circuit diagram and timing diagram illustrating one aspect of the present invention.

[0071] [Figure 40] A circuit diagram and timing diagram illustrating one aspect of the present invention.

[0072] [Figure 41] illustrates a block diagram, circuit diagram, and waveform diagram of one aspect of the present invention.

[0073] [Figure 42] A circuit diagram and timing diagram illustrating one aspect of the present invention.

[0074] [Figure 43] is a circuit diagram illustrating one aspect of the present invention.

[0075] [Figure 44] is a circuit diagram illustrating one aspect of the present invention.

[0076] [ Figure 45 [Illustration of the diagram for the display module.]

[0077] [Figure 46] A diagram illustrating an electronic device.

[0078] [Figure 47] A diagram illustrating an electronic device.

[0079] [Figure 48] Illustrative perspective view of the display device.

[0080] [Figure 49] A cross-sectional view and circuit diagram illustrating the structure of a semiconductor device according to one aspect of the present invention.

[0081] [ Figure 50 [A block diagram illustrating the structure of a CPU according to one aspect of the present invention.]

[0082] [ Figure 51 [A circuit diagram illustrating the structure of a storage element according to one aspect of the present invention.]

[0083] [Figure 52] shows a circuit diagram of an example imaging device.

[0084] [Figure 53] shows a structural example of an imaging device.

[0085] [Figure 54] A diagram illustrating a STEM photograph of a sample according to an embodiment.

[0086] [ Figure 55 [Graph showing XPS analysis results of samples according to the embodiment.]

[0087] [Figure 56] A graph illustrating the XPS analysis results of the sample according to the embodiment.

[0088] [Figure 57] Id-Vg characteristics of the transistor according to the embodiment.

[0089] [Figure 58] Id-Vg characteristics of the transistor according to the embodiment.

[0090] [Figure 59] A diagram illustrating a STEM photograph of a sample according to an embodiment.

[0091] [ Figure 60 [A graph illustrating the EDX analysis results of the sample according to the embodiment.] Detailed Implementation

[0092] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and its methods and details can be varied in various forms without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0093] Furthermore, for ease of understanding, the positions, sizes, and extents of various structures shown in the accompanying drawings, etc., do not necessarily represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings, etc.

[0094] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are used for convenience, but they do not always indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. Additionally, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify an embodiment of the present invention.

[0095] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate configuration, referring to the accompanying drawings to illustrate the positional relationships of the constituent elements. Furthermore, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in this specification and may be replaced as appropriate.

[0096] Note that in this specification and the like, when the structure of the invention is described using the accompanying drawings, symbols representing the same parts are sometimes used in common in different drawings.

[0097] Note that in this specification, for example, when the conductivity is sufficiently low, it may sometimes possess the characteristics of an "insulator" even when referred to as a "semiconductor." Furthermore, the boundary between "semiconductor" and "insulator" is unclear, and therefore sometimes cannot be precisely distinguished. Therefore, sometimes "semiconductor" as described in this specification may be replaced with "insulator." Similarly, sometimes "insulator" as described in this specification may be replaced with "semiconductor." Or, sometimes "insulator" as described in this specification may be replaced with "semi-insulator."

[0098] Furthermore, in this specification, for example, when the conductivity is sufficiently high, it may sometimes possess the characteristics of a "conductor" even when referred to as a "semiconductor." Moreover, the boundary between "semiconductor" and "conductor" is unclear, and therefore sometimes cannot be precisely distinguished. Therefore, sometimes "semiconductor" as described in this specification may be replaced with "conductor." Similarly, sometimes "conductor" as described in this specification may be replaced with "semiconductor."

[0099] In this specification and the like, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. Note that in this specification and the like, the channel region refers to the region through which current primarily flows.

[0100] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0101] Note that channel length, for example, refers to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor, or between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region forming the channel. Furthermore, the channel length in a transistor is not necessarily the same value in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length refers to any value, maximum value, minimum value, or average value in the region forming the channel.

[0102] The channel width, for example, refers to the length of the overlapping region between the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode, or the portion of the region forming the channel where the source and drain electrodes face each other. Furthermore, in a transistor, the channel width is not necessarily the same value in all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value in the region forming the channel.

[0103] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0104] Voltage generally refers to the potential difference between a certain potential and a standard potential (e.g., ground potential (GND) or source potential). Therefore, voltage can be referred to as potential.

[0105] Furthermore, in this specification, "silicon oxynitride film" refers to a film in which the oxygen content is greater than the nitrogen content, preferably a film having the following concentration ranges: oxygen concentration of 55 atomic% or more and 65 atomic% or less, nitrogen concentration of 1 atomic% or more and 20 atomic% or less, silicon concentration of 25 atomic% or more and 35 atomic% or less, and hydrogen concentration of 0.1 atomic% or more and 10 atomic% or less. In this specification, "silicon oxynitride film" refers to a film in which the nitrogen content is greater than the oxygen content, preferably a film having the following concentration ranges: nitrogen concentration of 55 atomic% or more and 65 atomic% or less, oxygen concentration of 1 atomic% or more and 20 atomic% or less, silicon concentration of 25 atomic% or more and 35 atomic% or less, and hydrogen concentration of 0.1 atomic% or more and 10 atomic% or less.

[0106] Additionally, in this specification and other materials, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Furthermore, "insulating film" may sometimes be replaced with "insulating layer."

[0107] In this specification, "parallel" refers to a state where the angle formed by two straight lines is between -10° and 10°. Therefore, it also includes states where the angle is between -5° and 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is between -30° and 30°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is between 80° and 100°. Therefore, it also includes states where the angle is between 85° and 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is between 60° and 120°.

[0108] Furthermore, in this specification and other documents, the hexagonal crystal system includes the trigonal crystal system and the rhombohedral crystal system.

[0109] (Implementation Method 1)

[0110] In this embodiment, a semiconductor device and a method for manufacturing a semiconductor device according to one aspect of the present invention will be described below with reference to FIGS. 1 to 20.

[0111] <1-1. Example 1 of the structure of a semiconductor device>

[0112] Figure 1A This is a top view of a transistor 100 in a semiconductor device according to one embodiment of the present invention. Furthermore, Figure 1B Equivalent to along Figure 1A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 1C Equivalent to along Figure 1A The cross-sectional view shown is cut between the dotted-dashed lines Y1 and Y2. Note that... Figure 1A For clarity, some of the constituent elements of transistor 100 (substrate 102 and insulating film, etc.) are omitted from the illustration.

[0113] Sometimes Figure 1A The direction of the dotted line X1-X2 in the diagram is called the channel length direction of transistor 100, and the direction of the dotted line Y1-Y2 is called the channel width direction of transistor 100.

[0114] The transistor 100 includes: a conductive film 104 on a substrate 102 serving as a gate electrode; an insulating film 106 on the substrate 102 and the conductive film 104; an insulating film 107 on the insulating film 106; an oxide semiconductor film 108 on the insulating film 107; conductive films 112a and 112b electrically connected to the oxide semiconductor film 108 and serving as a pair of electrodes; insulating films 114 and 116 on the oxide semiconductor film 108 and the conductive films 112a and 112b; and an insulating film 118 on the insulating film 116.

[0115] The oxide semiconductor film 108 preferably contains indium (In), zinc (Zn), M (M represents aluminum (Al), gallium (Ga), yttrium (Y) or tin (Sn)).

[0116] In transistor 100, insulating films 106 and 107 are used as gate insulating films of transistor 100. In addition, in transistor 100, one of the conductive films 112a and 112b, which are used as a pair of electrodes, is used as a source electrode and the other is used as a drain electrode.

[0117] The conductive film 112a includes a conductive film 112a_1, a conductive film 112a_2 on and in contact with the conductive film 112a_1, and a conductive film 112a_3 on and in contact with the conductive film 112a_2. The conductive film 112b includes a conductive film 112b_1, a conductive film 112b_2 on and in contact with the conductive film 112b_1, and a conductive film 112b_3 on and in contact with the conductive film 112b_2. The conductive film 112a_2 includes regions 112a_2a and 112a_2b. Furthermore, the conductive film 112b_2 includes regions 112b_2a and 112b_2b.

[0118] Both conductive films 112a_2 and 112b_2 contain copper, and regions 112a_2b and 112b_2b both contain copper and silicon. Conductive films 112a_1, 112a_3, 112b_1, and 112b_3 all contain materials that inhibit copper diffusion. Furthermore, region 112a_2b is located at the end of conductive film 112a_2 and includes a region in contact with insulating film 114. Region 112b_2b is located at the end of conductive film 112b_2 and includes a region in contact with insulating film 114. Additionally, the end of conductive film 112a_1 includes a region located outside the end of conductive film 112a_2, and the end of conductive film 112b_1 includes a region located outside the end of conductive film 112b_2. Conductive film 112a_3 covers the top surface of conductive film 112a_2, and conductive film 112b_3 covers the top surface of conductive film 112b_2. Therefore, conductive film 112a_2a has a structure covered by conductive film 112a_1, region 112a_2b, and conductive film 112a_3, and conductive film 112b_2a has a structure covered by conductive film 112b_1, region 112b_2b, and conductive film 112b_3.

[0119] Regions 112a_2b and 112b_2b preferably form copper silicides. Because of the copper-silicon bonding, copper silicides are more stable than copper and have the function of inhibiting copper diffusion to the outside. Furthermore, when the insulating film 114 contains silicon, the presence of copper and silicon in regions 112a_2b and 112b_2b improves the adhesion between the conductive films 112a_2 and 112b_2 and the insulating film 114.

[0120] Regions 112a_2b and 112b_2b can also contain copper, silicon, and nitrogen, and can also form copper silicide nitrides. The presence of copper silicide nitrides in regions 112a_2b and 112b_2b can suppress the diffusion of copper to the outside.

[0121] By having conductive films 112a and 112b respectively containing copper, the resistance of conductive films 112a and 112b can be reduced. Furthermore, by having the above-described structure, the diffusion of copper to the exterior of conductive films 112a and 112b can be suppressed, particularly the diffusion of copper to the oxide semiconductor film 108. Therefore, a semiconductor device including a transistor with excellent electrical characteristics can be provided.

[0122] <1-2. Example 2 of the structure of a semiconductor device>

[0123] Next, refer to Figures 2 to 11 to explain the relationship with... Figure 1A , Figure 1B as well as Figure 1C Different structural examples of transistor 100 are shown. Furthermore, in Figures 2 through 11 below, the same shading lines are sometimes used to represent parts having the same function as transistor 100, without the addition of specific reference numerals.

[0124] Figure 2A This is a top view of a transistor 100A, a semiconductor device according to one embodiment of the present invention. Figure 2B Equivalent to along Figure 2A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 2C Equivalent to along Figure 2A The cross-sectional view shown is cut between the dotted and dashed lines Y1 and Y2.

[0125] Transistor 100A includes a conductive film 104 on substrate 102 serving as a first gate electrode, an insulating film 106 on substrate 102 and conductive film 104, an insulating film 107 on insulating film 106, an oxide semiconductor film 108 on insulating film 107, conductive films 112a and 112b electrically connected to oxide semiconductor film 108 and serving as a pair of electrodes, insulating films 114 and 116 on oxide semiconductor film 108 and conductive films 112a and 112b, an opening 152c disposed on insulating film 116 and disposed in insulating films 114 and 116, and one of conductive films 112a and 112b (in Figure 2B The conductive film 120a is electrically connected to the conductive film 112b, the conductive film 120b is disposed on the insulating film 116 and used as the second gate electrode, and the insulating film 118 is on the insulating film 116 and the conductive films 120a and 120b.

[0126] In transistor 100A, insulating films 106 and 107 function as first gate insulating films of transistor 100A, insulating films 114 and 116 function as second gate insulating films of transistor 100A, and insulating film 118 functions as a protective insulating film of transistor 100A. Furthermore, in this specification and the like, insulating films 106 and 107 are sometimes referred to as first gate insulating films, and insulating films 114 and 116 are sometimes referred to as second gate insulating films. Additionally, in transistor 100A, one of the conductive films 112a and 112b, which are used as a pair of electrodes, is used as a source electrode, and the other is used as a drain electrode. Furthermore, conductive film 120a functions as a pixel electrode in a display device.

[0127] S-channel structure

[0128] In the transistor 100A shown in Figure 2, the oxide semiconductor film 108 is sandwiched between the conductive film 104 and the conductive film 120b, separated by a first gate insulating film and a second gate insulating film. The length and width of the channel of the conductive film 104 are longer than those of the oxide semiconductor film 108. Similarly, the length and width of the channel of the conductive film 120b are also longer than those of the oxide semiconductor film 108. Therefore, the oxide semiconductor film 108 is entirely covered by the conductive film 104 and the conductive film 120b, separated by the first and second gate insulating films.

[0129] In other words, in the channel width direction of transistor 100A, conductive film 104 and conductive film 120b surround oxide semiconductor film 108 through first gate insulating film and second gate insulating film.

[0130] By employing the above structure, the electric field of conductive film 104 and conductive film 120b is used to surround the oxide semiconductor film 108 included in transistor 100A. As shown in transistor 100A, the device structure of a transistor in which the electric field of conductive film 104 and conductive film 120b surrounds the oxide semiconductor film in which the channel region is formed can be called a surrounded channel (S-channel) structure.

[0131] Because transistor 100A has an s-channel structure, the conductive films 104 and 120b can be used to effectively apply an electric field to the oxide semiconductor film 108 to induce a channel. This improves the current-driving capability of transistor 100A, resulting in high on-state current characteristics. Furthermore, the increased on-state current allows for miniaturization of transistor 100A. Additionally, the structure of transistor 100A, where the oxide semiconductor film 108 is surrounded by the conductive films 104 and 120b, enhances its mechanical strength.

[0132] By adopting the above structure, since the area through which charge carriers flow in the oxide semiconductor film 108 is a relatively large range within the oxide semiconductor film 108, namely, both the first gate insulating film side and the second gate insulating film side of the oxide semiconductor film 108, the amount of charge carrier mobility in the transistor 100A is increased. As a result, while the on-state current of the transistor 100A increases, the field-effect mobility also increases; specifically, the field-effect mobility becomes 10 cm⁻¹. 2 / V·s or higher. Furthermore, the field-effect mobility here is an indicator of the current-driving force in the saturation region of the transistor, i.e., the apparent field-effect mobility, rather than an approximation of the mobility as a physical property of the oxide semiconductor film.

[0133] like Figure 3A and Figure 3B In the transistor 100B shown, conductive films 120a and 120b can also be disposed on the insulating film 118. In this case, at the opening 152c provided in the insulating films 114, 116, and 118, conductive film 120a is electrically connected to one of conductive films 112a and 112b. Note that the top view of transistor 100B is different from... Figure 2A The transistor shown is the same as the 100A. Figure 3A Equivalent to along Figure 2A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 3B Equivalent to along Figure 2A The diagram shows a cross-sectional view cut off between the dotted and dashed lines Y1 and Y2. Furthermore, the other structures of transistor 100B are the same as those of transistor 100A; refer to the structure of transistor 100A for details.

[0134] like Figure 3C The transistor 100C shown may include, in the conductive films 112a and 112b, a region in which the end of conductive film 112a_1 coincides with the end of conductive film 112a_2, and a region in which the end of conductive film 112b_1 coincides with the end of conductive film 112b_2.

[0135] like Figure 4A , Figure 4B and Figure 4C In the transistor 100D shown, the conductive film 120b, which serves as the second gate electrode, is connected to the conductive film 104, which serves as the first gate electrode, through openings 152a and 152b provided in the first gate insulating film (insulating films 106, 107) and the second gate insulating film (insulating films 114, 116). Furthermore, Figure 4A This is a top view of a transistor 100D of a semiconductor device according to one embodiment of the present invention. Furthermore, Figure 4B Equivalent to along Figure 4A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 4C Equivalent to along Figure 4A The diagram shows a cross-sectional view cut off between the dotted and dashed lines Y1 and Y2. Furthermore, the other structures of transistor 100D are the same as those of transistor 100A, and the structure of transistor 100A can be referenced.

[0136] In transistor 100D, since conductive film 104 and conductive film 120b are connected at openings 152a and 152b provided in the first gate insulating film and the second gate insulating film, conductive film 120b is positioned opposite to oxide semiconductor film 108 on the side of the channel width direction, separated by the first gate insulating film and the second gate insulating film. Furthermore, conductive film 104 and conductive film 120b are supplied with the same potential. Therefore, the oxide semiconductor film 108 included in transistor 100D is effectively surrounded by the electric field of conductive film 104 and conductive film 120b. Alternatively, only one of openings 152a and 152b may be provided.

[0137] like Figure 5A and Figure 5B In the transistor 100E shown, conductive films 120a and 120b can also be disposed on the insulating film 118. In this case, in the opening 152c provided in the insulating films 114, 116, and 118, conductive film 120a is electrically connected to one of conductive films 112a and 112b. In the openings 152a and 152b provided in the insulating films 106, 107, 114, 116, and 118, conductive film 120b, used as a second gate electrode, is electrically connected to conductive film 104, used as a first gate electrode. Note that the top view of transistor 100E is different from... Figure 4A The transistor 100D shown is the same. Figure 5A Equivalent to along Figure 4A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 5B Equivalent to along Figure 4A The diagram shows a cross-sectional view cut off between the dotted and dashed lines Y1 and Y2. Furthermore, the other structures of transistor 100E are the same as those of transistor 100D, so the structure of transistor 100D can be referenced.

[0138] like Figure 6A , Figure 6B , Figure 6C The transistor 100F shown may also have the following structure: the conductive film 120b, which serves as the second gate electrode, is connected to the conductive film 104, which serves as the first gate electrode, via the conductive film 112c, which serves as the connecting electrode. Furthermore, Figure 6A This is a top view of a transistor 100F of a semiconductor device according to one embodiment of the present invention. Furthermore, Figure 6B Equivalent to along Figure 6A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 6C Equivalent to along Figure 6A The cross-sectional view shown is cut between the dotted and dashed lines Y1 and Y2.

[0139] Figure 6A , Figure 6B , Figure 6CThe transistor 100F shown differs from the transistor 100A in that it includes a conductive film 112c disposed on the insulating film 107 and electrically connected to the conductive film 104 through an opening 151 disposed in the first gate insulating film (insulating films 106, 107); and a conductive film 120b disposed on the insulating film 116 and electrically connected to the conductive film 112c through an opening 152d disposed in the second gate insulating film (insulating films 114, 116).

[0140] In transistor 100F, conductive film 104 and conductive film 120b are electrically connected via conductive film 112c. One side of oxide semiconductor film 108 in the channel width direction is opposite to conductive film 112c, separated by a first gate insulating film and a second gate insulating film. Furthermore, conductive film 104 and conductive film 120b are supplied with the same potential. Therefore, the electric field of conductive film 104 and conductive film 120b effectively surrounds the oxide semiconductor film 108 included in transistor 100F.

[0141] On the other hand, for example, transistors 100A and 100B, in a structure in which the conductive film 104 and the conductive film 120b are not connected, can supply different potentials to the conductive film 104 and the conductive film 120b respectively.

[0142] The length of the conductive film 120b in the channel length direction and the length in the channel width direction may or may not necessarily be longer than the length of the oxide semiconductor film 108 in the channel length direction and the length in the channel width direction.

[0143] The conductive film 112c can be formed in the same process as the conductive films 112a and 112b. In this case, the conductive film 112c includes a conductive film 112c_1, a conductive film 112c_2 on and in contact with the conductive film 112c_1, and a conductive film 112c_3 on and in contact with the conductive film 112c_2. Furthermore, the conductive film 112c_2 includes regions 112c_2a and 112c_2b.

[0144] Conductive film 112c_2 contains copper, region 112c_2b contains copper and silicon, and both conductive films 112c_1 and 112c_3 contain materials that inhibit copper diffusion. Furthermore, region 112c_2b is located at the end of conductive film 112c_2 and includes a region in contact with insulating film 114. Additionally, the end of conductive film 112c_1 includes a region located outside the end of conductive film 112c_2. Furthermore, conductive film 112c_3 covers the top surface of conductive film 112c_2. Therefore, conductive film 112c_2a has a structure covering conductive film 112c_1, region 112c_2b, and conductive film 112c_3.

[0145] Region 112c_2b can be formed using the same materials and processes as regions 112a_2b and 112b_2b.

[0146] By adopting the above structure, the resistance of the conductive film 112c can be reduced. In addition, the diffusion of copper elements to the outside of the conductive film 112c, especially to the oxide semiconductor film 108, can be suppressed.

[0147] Note that since the other structures of transistor 100F are the same as those of transistor 100A, the structure of transistor 100A can be referenced.

[0148] <1-3. Example 3 of the structure of a semiconductor device>

[0149] Figure 7A , Figure 7B This is a cross-sectional view of a transistor 100G in a semiconductor device according to one embodiment of the present invention, and a top view of the transistor 100G. Figure 1A The transistor 100 shown is the same. Figure 7A Equivalent to along Figure 1A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 7B Equivalent to Figure 1A The cross-sectional view shown is cut between the dotted and dashed lines Y1 and Y2.

[0150] The difference between transistor 100G and transistor 100 lies in that the oxide semiconductor film 108 includes an oxide semiconductor film 108a on one side of the conductive film 104, an oxide semiconductor film 108b on the oxide semiconductor film 108a, and an oxide semiconductor film 108c on the oxide semiconductor film 108b. That is, the oxide semiconductor film 108 has a three-layer structure. The other structures are the same as those of transistor 100 and perform the same function. The following describes the structure that differs from transistor 100.

[0151] The oxide semiconductor films 108a, 108b and 108c all contain In, Zn and M (M is Al, Ga, Y or Sn).

[0152] For example, oxide semiconductor film 108b preferably includes regions where the number of In atoms is greater than the number of M atoms. Additionally, oxide semiconductor films 108a and 108c preferably include regions where the number of In atoms is less than that of oxide semiconductor film 108b.

[0153] By including regions in the oxide semiconductor film 108b where the ratio of In atoms is greater than the ratio of M atoms, the field-effect mobility of the transistor 100G can be improved. Specifically, the field-effect mobility of the transistor 100G can exceed 10 cm⁻¹. 2 / Vs, preferably, the field-effect mobility of the 100G transistor can exceed 30cm.2 / Vs.

[0154] For example, by using the aforementioned high field-effect mobility transistors as gate drivers for generating gate signals (in particular, demultiplexers connected to the output terminals of shift registers included in the gate driver), semiconductor devices or display devices with narrow bezel widths (also known as narrow bezels) can be provided.

[0155] On the other hand, when the oxide semiconductor film 108b includes a region where the atomic ratio of In is greater than the atomic ratio of M, the electrical characteristics of the transistor 100G are prone to change under light irradiation. However, in a semiconductor device according to one aspect of the present invention, an oxide semiconductor film 108c is formed on the oxide semiconductor film 108b. The oxide semiconductor film 108c includes a region where the atomic ratio of In is less than that of the oxide semiconductor film 108b, so its Eg is greater than that of the oxide semiconductor film 108b. Therefore, the tolerance of the oxide semiconductor film 108 employing the stacked structure of oxide semiconductor film 108b and oxide semiconductor film 108c to optical negative bias stress testing can be improved.

[0156] Furthermore, impurities such as hydrogen or moisture, particularly in the channel region of the oxide semiconductor film 108b, affect transistor characteristics and thus become a problem. Therefore, fewer impurities such as hydrogen or moisture in the channel region of the oxide semiconductor film 108b are preferred. Additionally, oxygen defects formed in the channel region of the oxide semiconductor film 108b affect transistor characteristics and thus become a problem. For example, when oxygen defects are formed in the channel region of the oxide semiconductor film 108b, these oxygen defects bond with hydrogen and become a source of charge carriers. When a source of charge carriers is generated in the channel region of the oxide semiconductor film 108b, changes occur in the electrical characteristics of the transistor 100G, including the oxide semiconductor film 108b; typically, a threshold voltage drift occurs. Therefore, fewer oxygen defects in the channel region of the oxide semiconductor film 108b are preferred.

[0157] Therefore, in one aspect of the invention, the insulating film in contact with the oxide semiconductor film 108, specifically, the insulating films 114, 116 formed above the oxide semiconductor film 108, contain excess oxygen. By moving oxygen or excess oxygen from the insulating films 114, 116 to the oxide semiconductor film 108, oxygen defects in the oxide semiconductor film can be reduced.

[0158] like Figure 8A and Figure 8B The transistor 100H shown can also have the following structure: the oxide semiconductor film 108 has a two-layer structure of oxide semiconductor film 108b and oxide semiconductor film 108c. Furthermore, the top view of transistor 100H is similar to... Figure 1A The transistor 100 shown is the same. Figure 8A Equivalent to along Figure 1A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 8B Equivalent to along Figure 1A The diagram shows a cross-sectional view cut off between the dotted lines Y1 and Y2. Furthermore, the other structures of transistor 100H are the same as those of transistor 100G, so the structure of transistor 100G can be referenced.

[0159] like Figure 9A and Figure 9B The transistor 100J shown may also have the following structure: including a conductive film 120b used as a second gate electrode, and an oxide semiconductor film 108 including oxide semiconductor film 108b and oxide semiconductor film 108c. Furthermore, the top view of transistor 100J is similar to... Figure 2A The transistor shown is the same as the 100A. Figure 9A Equivalent to along Figure 2A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 9B Equivalent to along Figure 2A The diagram shows a cross-sectional view cut off between the dotted and dashed lines Y1 and Y2. Furthermore, the other structures of transistor 100J are the same as those of transistor 100A, so the structure of transistor 100A can be referenced.

[0160] like Figure 9C The transistor 100K shown may include, in the conductive films 112a and 112b, a region in which the end of conductive film 112a_1 coincides with the end of conductive film 112a_2, and a region in which the end of conductive film 112b_1 coincides with the end of conductive film 112b_2.

[0161] like Figure 10A and Figure 10B The conductive films 120a and 120b of the transistor 100L shown can also be disposed on the insulating film 118. Furthermore, as... Figure 10C The transistor 100M shown may include, in the conductive films 112a and 112b, a region in which the end of conductive film 112a_1 coincides with the end of conductive film 112a_2, and a region in which the end of conductive film 112b_1 coincides with the end of conductive film 112b_2.

[0162] Transistors such as 100J, 100K, 100L, and 100M, by having an s-channel structure, allow the carriers in the oxide semiconductor film 108 to flow over a wider area of ​​the film, specifically the side of the first gate insulating film and the side of the second gate insulating film. Therefore, the carrier mobility in these transistors is increased. As a result, the on-state current of the transistor increases, and the field-effect mobility also increases.

[0163] The accompanying drawings illustrate that the oxide semiconductor film 108 included in transistor 100 has a thinner thickness in the region exposed from conductive films 112a, 112b, i.e., a portion of the oxide semiconductor film has a recess. Note that one aspect of the invention is not limited to this, and the oxide semiconductor film in the region exposed from conductive films 112a, 112b may not be thin, and may not have a recess. Figure 11A and Figure 11B Here is an example of this situation. Figure 11A and Figure 11B This is a cross-sectional view showing an example of a semiconductor device. Additionally, Figure 11A and Figure 11B This is a cross-sectional view of the oxide semiconductor film 108 of the aforementioned transistor 100, excluding the recessed portion of the transistor 100.

[0164] <1-4. Example 4 of the structure of a semiconductor device>

[0165] Figure 12A This is a top view of the 100P transistor. Figure 12B Equivalent to along Figure 12A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 12C Equivalent to along Figure 12A The cross-sectional view shown is cut between the dotted and dashed lines Y1 and Y2.

[0166] The transistor 100P shown in Figure 12 includes a conductive film 104 on a substrate 102, an insulating film 106 on the substrate 102 and the conductive film 104, an insulating film 107 on the insulating film 106, an oxide semiconductor film 108 on the insulating film 107, an insulating film 114 on the oxide semiconductor film 108, an insulating film 116 on the insulating film 114, a conductive film 112a electrically connected to the oxide semiconductor film 108 through an opening 151a provided in the insulating film 114 and the insulating film 116, and a conductive film 112b electrically connected to the oxide semiconductor film 108 through an opening 151b provided in the insulating film 114 and the insulating film 116. More specifically, an insulating film 118 is provided on the conductive films 112a and 112b and the insulating film 116 of the transistor 100P.

[0167] In transistor 100P, insulating films 106 and 107 function as gate insulating films of transistor 100P, insulating films 114 and 116 function as protective insulating films of oxide semiconductor film 108, and insulating film 118 functions as a protective insulating film of transistor 100P. Furthermore, in transistor 100P, conductive film 104 functions as a gate electrode, conductive film 112a functions as a source electrode, and conductive film 112b functions as a drain electrode.

[0168] The transistor 100 shown in Figure 1 adopts a channel-etched structure, while Figure 12A , Figure 12B and Figure 12C The transistor 100P shown employs a channel-protected structure. Channel-protected transistors can also be used in a semiconductor device according to one embodiment of the present invention. Furthermore, the other structures of transistor 100P are the same as those of transistor 100, so the structure of transistor 100 can be referred to.

[0169] Figure 13A This is a top view of transistor 100Q. Figure 13B Equivalent to along Figure 13A The cross-sectional view shown is cut between the dotted and dashed lines X1 and X2. Figure 13C Equivalent to along Figure 13A The cross-sectional view shown is cut between the dotted and dashed lines Y1 and Y2.

[0170] Figure 13 shows the transistor 100Q and its relationship with Figure 12A , Figure 12B and Figure 12C The difference between transistor 100P and transistor 100Q lies in the shape of insulating films 114 and 116. Specifically, the insulating films 114 and 116 of transistor 100Q are formed as islands in the channel region of oxide semiconductor film 108. Other structures are the same as those of transistor 100P.

[0171] The transistor according to this embodiment can be freely combined with the structures described above.

[0172] <1-5. Components of a Semiconductor Device>

[0173] The constituent elements of the semiconductor device according to this embodiment will be described in detail below.

[0174] Substrate

[0175] While there are no particular restrictions on the material of the substrate 102, it must at least possess heat resistance capable of withstanding subsequent heat treatments. For example, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., can be used as the substrate 102. In addition, single-crystal semiconductor substrates or polycrystalline semiconductor substrates made of silicon or silicon carbide, compound semiconductor substrates made of silicon-germanium, SOI (Silicon on Insulator) substrates, etc., can also be used, and the aforementioned substrates on which semiconductor elements are disposed can also be used as the substrate 102.

[0176] When a glass substrate is used as substrate 102, large-area display devices can be manufactured by using large-area substrates such as the sixth generation (1500mm×1850mm), the seventh generation (1870mm×2200mm), the eighth generation (2200mm×2400mm), the ninth generation (2400mm×2800mm), and the tenth generation (2950mm×3400mm).

[0177] A flexible substrate can also be used as substrate 102, and transistor 100 can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between substrate 102 and transistor 100. The release layer can be used when a part or all of a semiconductor device is fabricated on the release layer, and then it is separated from substrate 102 and transferred to another substrate. In this case, transistor 100 can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0178] Conductive films

[0179] The conductive film 104 used as the first gate electrode, the conductive film 112a used as the source electrode, the conductive film 112b used as the drain electrode, the conductive film 112c used as the connection electrode, the conductive film 120b used as the second gate electrode, and the conductive film 120a used as the pixel electrode can be formed using metal elements selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co), alloys composed of the above metal elements, or alloys combining the above metal elements.

[0180] Cu is preferably used in conductive films 104, 112a, 112b, 112c, 120a, and 120b. Alternatively, Cu-X alloy films (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be used. By using Cu-X alloy films, processing can be performed via a wet etching process, thereby reducing manufacturing costs.

[0181] Cu or the aforementioned Cu-X alloy film can be applied to conductive films 112a_2 (including conductive film 112a), 112b_2 (including conductive film 112b), and 112c_2 (including conductive film 112c). Cu-Mn alloy film is particularly preferred as the Cu-X alloy film. Note that one aspect of the invention is not limited thereto, and conductive films 112a_2, 112b_2, and 112c_2 may contain at least copper.

[0182] Regions 112a_2b, 112b_2b, and 112c_2b preferably contain Cu and Si, and more preferably copper silicides. The presence of copper silicide nitrides in regions 112a_2b, 112b_2b, and 112c_2b helps suppress copper diffusion to the outside. The copper silicides are formed, for example, by reacting with silane gas after the formation of a Cu film or a Cu-containing alloy film. Alternatively, copper silicide nitrides containing Cu, Si, and N can be formed by reacting with, for example, a nitrogen-containing plasma after the reaction with silane gas. Furthermore, when the surface of copper or a copper-containing alloy is covered with an oxide film, a reduction treatment using hydrogen or ammonia to remove the oxide film is preferably performed before the above reactions.

[0183] The conductive films 112a_1 and 112a_3 included in conductive film 112a, the conductive films 112b_1 and 112b_3 included in conductive film 112b_, and the conductive films 112c_1 and 112c_3 included in conductive film 112c preferably contain one or more of the aforementioned metallic elements selected from titanium, tungsten, tantalum, and molybdenum. When the conductive films 112a_1, 112a_3, 112b_1, 112b_3, 112c_1, and 112c_3 contain one or more of the elements selected from titanium, tungsten, tantalum, and molybdenum, the diffusion of copper contained in the conductive films 112a_2, 112b_2, and 112c_2 to the outside can be suppressed. That is, the conductive films 112a_1, 112a_3, 112b_1, 112b_3, 112c_1, and 112c_3 have the function of acting as a so-called barrier metal.

[0184] As conductive films 112a_1, 112a_3, 112b_1, 112b_3, 112c_1, and 112c_3, a so-called tantalum nitride film containing nitrogen and tantalum is preferably used. This tantalum nitride film is conductive and has high barrier properties against copper or hydrogen. Furthermore, because little hydrogen is released from the tantalum nitride film itself, it is most suitable as a conductive film in contact with the oxide semiconductor film 108.

[0185] Alternatively, oxide conductors such as oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, and oxides containing indium, gallium and zinc can be used as conductive films 104, 112a_1, 112a_3, 112b_1, 112b_3, 112c_1 and 112c_3. Because conductive films 112a_1, 112a_3, 112b_1, 112b_3, 112c_1 and 112c_3 have oxides containing at least one of In and Zn, the diffusion of copper contained in conductive films 112a_2, 112b_2 and 112c_2 to the outside can be suppressed.

[0186] In particular, the aforementioned oxide conductor is preferably used as the conductive film 120a. Furthermore, it is preferable that the conductive film 120a and the oxide semiconductor film 108 (oxide semiconductor film 108b and oxide semiconductor film 108c) contain the same metal element. By employing this structure, manufacturing costs can be suppressed.

[0187] Here, oxide conductors are explained. In this specification, oxide conductors may also be referred to as OC (Oxide Conductor). As an oxide conductor, for example, an oxygen defect is formed in an oxide semiconductor, and hydrogen is added to this oxygen defect to form a donor level near the conduction band. As a result, the conductivity of the oxide semiconductor increases, and it becomes conductive. The conductive oxide semiconductor can be called an oxide conductor. Generally, oxide semiconductors have a large band gap and are therefore transparent to visible light. On the other hand, an oxide conductor is an oxide semiconductor with a donor level near the conduction band. Therefore, in an oxide conductor, the effect of absorption by the donor level is small, and it has approximately the same transparency to visible light as an oxide semiconductor.

[0188] Insulating film used as the first gate insulating film

[0189] The insulating films 106 and 107, which serve as the first gate insulating film of the transistor 100, can each be made of one or more insulating layers selected from silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, and neodymium oxide, formed by plasma-enhanced chemical vapor deposition (PECVD), sputtering, or the like. Note that a single-layer insulating film or three or more insulating layers selected from the above materials can also be used instead of a stacked structure of insulating films 106 and 107.

[0190] The insulating film 106 functions as a barrier film that inhibits oxygen permeation. For example, when excess oxygen is supplied to the insulating films 107, 114, 116 and / or the oxide semiconductor film 108, the insulating film 106 can inhibit oxygen permeation.

[0191] The insulating film 107 that contacts the oxide semiconductor film 108, which is used as the channel region of the transistor 100, is preferably an oxide insulating film, and more preferably includes a region containing oxygen in excess of its stoichiometric composition (oxygen excess region). In other words, the insulating film 107 is an insulating film capable of releasing oxygen. To provide an oxygen excess region in the insulating film 107, the insulating film 107 can be formed, for example, in an oxygen atmosphere. Alternatively, the formed insulating film 107 can be heated in an oxygen atmosphere.

[0192] Furthermore, when hafnium oxide is used as the insulating film 107, the following effects occur: Hafnium oxide has a higher relative permittivity than silicon oxide or silicon oxynitride. Therefore, the thickness of the insulating film 107 can be greater than when silicon oxide is used, thereby reducing leakage current caused by tunneling current. In other words, a transistor with low off-state current can be realized. Moreover, hafnium oxide with a crystalline structure has a higher relative permittivity than hafnium oxide with an amorphous structure. Therefore, hafnium oxide with a crystalline structure is preferred for forming a transistor with low off-state current. Examples of crystalline structures include monoclinic or cubic crystal systems. Note that one aspect of the invention is not limited to this.

[0193] Note that in this embodiment, a silicon nitride film is formed as insulating film 106, and a silicon oxide film is formed as insulating film 107. Compared to a silicon oxide film, a silicon nitride film has a higher relative permittivity and requires a larger thickness to obtain an electrostatic capacitance equal to that of a silicon oxide film. Therefore, by including a silicon nitride film in the gate insulating film of the transistor 100, the thickness of the insulating film can be increased. Thus, electrostatic discharge damage to the transistor 100 can be suppressed by inhibiting the decrease in the dielectric withstand voltage and increasing the dielectric withstand voltage.

[0194] Oxide Semiconductor Films

[0195] The above-mentioned material can be used as the oxide semiconductor film 108.

[0196] When the oxide semiconductor film 108b is an In-M-Zn oxide, the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide preferably satisfies In > M. Examples of such atomic ratios for the metal elements in the sputtering target include In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, and In:M:Zn = 4:2:4.1.

[0197] Furthermore, when the oxide semiconductor films 108a and 108c are In-M-Zn oxides, the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide preferably satisfies In ≤ M. Examples of such atomic ratios for the metal elements in the sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, and In:M:Zn = 1:3:6.

[0198] Furthermore, when the oxide semiconductor films 108 (108a, 108b, and 108c) are all In-M-Zn oxides, a sputtering target containing polycrystalline In-M-Zn oxide is preferably used. By using a target containing polycrystalline In-M-Zn oxide, crystalline oxide semiconductor films 108a, 108b, and 108c can be easily formed. Note that the atomic ratios of the formed oxide semiconductor films 108a, 108b, and 108c vary within ±40% of the atomic ratio of the metal elements contained in the aforementioned sputtering target. For example, when a sputtering target with an atomic ratio of In:Ga:Zn = 4:2:4.1 is used as the sputtering target for oxide semiconductor film 108b, the atomic ratio of the formed oxide semiconductor film 108b is sometimes around In:Ga:Zn = 4:2:3.

[0199] The bandgap of the oxide semiconductor film 108 is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Thus, by using an oxide semiconductor with a wider bandgap, the off-state current of the transistor 100 can be reduced. Particularly preferred is that an oxide semiconductor film with a bandgap of 2 eV or more, preferably 2 eV or more and 3.0 eV or less, is used as oxide semiconductor film 108b, and oxide semiconductor films with bandgap of 2.5 eV or more and 3.5 eV or less are used as oxide semiconductor films 108a and 108c. Furthermore, it is preferable that the bandgap of oxide semiconductor films 108a and 108c is larger than the bandgap of oxide semiconductor film 108b.

[0200] Furthermore, the thicknesses of the oxide semiconductor films 108a, 108b and 108c are 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0201] Furthermore, oxide semiconductor films with low carrier densities are used as oxide semiconductor films 108a and 108c. For example, the carrier density of oxide semiconductor films 108a and 108c is 1 × 10⁻⁶. 17 cm -3 The following is preferred: 1×10 15 cm -3Hereinafter, 1×10 is more preferred. 13 cm -3 Hereinafter, 1×10 is further preferred. 11 cm -3 the following.

[0202] This invention is not limited thereto; materials with appropriate compositions can be used according to the desired semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Furthermore, it is preferable to appropriately set the carrier density, impurity concentration, defect density, ratio of metal to oxygen atoms, interatomic distance, density, etc., of the oxide semiconductor film 108 to obtain the desired semiconductor characteristics of the transistor.

[0203] Using an oxide semiconductor film with low impurity concentration and low defect state density as the oxide semiconductor film 108 allows for the fabrication of transistors with superior electrical characteristics, making it preferable. Here, the state of low impurity concentration and low defect state density (few oxygen defects) is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic." Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have fewer carrier generation sources, the carrier density can be reduced. Therefore, transistors with a channel region formed in this oxide semiconductor film rarely exhibit negative threshold voltage characteristics (also known as always-on characteristics). Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect state density, they are likely to have a low trapped state density. The off-state current of high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films is significantly small, even with a channel width of 1 × 10⁻⁶. 6 A device with a channel length L of 10 μm and a diameter of μm can also achieve the following characteristics: when the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V, the off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10⁻⁶. -13 Below A.

[0204] Therefore, transistors with channel regions formed in oxide semiconductor films of high intrinsic purity or substantially high intrinsic purity can be transistors with small variations in electrical characteristics and high reliability. Furthermore, the charge trapped in the trap levels of the oxide semiconductor film requires a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, transistors with channel regions formed in oxide semiconductor films with high trap state density sometimes exhibit unstable electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals.

[0205] Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to form water, while oxygen defects are formed in the lattice (or the portion where oxygen desorption occurs) where oxygen desorption takes place. When hydrogen enters this oxygen defect, electrons are sometimes generated as charge carriers. Additionally, sometimes electrons are generated as charge carriers because a portion of the hydrogen bonds with oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductor films containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the oxide semiconductor film 108. Specifically, the hydrogen concentration in the oxide semiconductor film 108, as measured by SIMS analysis, is 2 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is 5×10 18 atoms / cm 3 The following is preferred: 1×10 18 atoms / cm 3 The following is more preferably 5×10 17 atoms / cm 3 Hereinafter, 1×10 is further preferred. 16 atoms / cm 3 the following.

[0206] Furthermore, the oxide semiconductor film 108b preferably includes a region with a hydrogen concentration lower than that of the oxide semiconductor film 108c. By including a region with a hydrogen concentration lower than that of the oxide semiconductor film 108c in the oxide semiconductor film 108b, a highly reliable semiconductor device can be provided.

[0207] Furthermore, when the oxide semiconductor film 108b contains silicon or carbon, one of the Group 14 elements, oxygen defects increase in the oxide semiconductor film 108b, leading to n-type formation. Therefore, the concentration of silicon or carbon in the oxide semiconductor film 108b, and the concentration of silicon or carbon near the interface with the oxide semiconductor film 108b (measured using SIMS analysis), is 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0208] Furthermore, in the oxide semiconductor film 108b, the concentration of alkali metals or alkaline earth metals, as measured by SIMS analysis, is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm3 The following applies. When alkali metals and alkaline earth metals bond with oxide semiconductors, charge carriers are sometimes generated, which increases the off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor film 108b.

[0209] When nitrogen is present in the oxide semiconductor film 108b, electrons are generated as charge carriers, increasing the charge carrier density and causing the oxide semiconductor film 108b to become n-type. As a result, transistors using nitrogen-containing oxide semiconductor films tend to have always-on characteristics. Therefore, it is preferable to minimize the nitrogen content in the oxide semiconductor film as much as possible; for example, a nitrogen concentration measured by SIMS analysis is preferably 5 × 10⁻⁶. 18 atoms / cm 3 the following.

[0210] The oxide semiconductor films 108b and 108c can each have non-single-crystal structures. Non-single-crystal structures include, for example, CAAC-OS (C-axis Aligned Crystalline Oxide Semiconductor), polycrystalline structures, microcrystalline structures, or amorphous structures (described later). Among non-single-crystal structures, amorphous structures have the highest defect level density, while CAAC-OS has the lowest.

[0211] Insulating film used as the second gate insulating film

[0212] Insulating films 114 and 116 are used as the second gate insulating films of transistor 100. Furthermore, insulating films 114 and 116 function to supply oxygen to oxide semiconductor film 108. That is, insulating films 114 and 116 contain oxygen. Additionally, insulating film 114 is an insulating film that allows oxygen to permeate. Note that insulating film 114 also serves as a film to mitigate damage to oxide semiconductor film 108 during the subsequent formation of insulating film 116.

[0213] As the insulating film 114, silicon oxide, silicon oxynitride, etc., with a thickness of 5 nm or more and 150 nm or less can be used, preferably 5 nm or more and 50 nm or less.

[0214] Furthermore, the amount of defects in the insulating film 114 is preferably low; typically, the spin density of the signal originating from the dangling bonds in silicon at g = 2.001, as measured by ESR, is preferably 3 × 10⁻⁶. 17 spins / cm 3 The reason is that if the defect density of the insulating film 114 is high, oxygen will bond with the defect, thereby reducing the amount of oxygen permeating into the insulating film 114.

[0215] In the insulating film 114, sometimes oxygen entering from the outside does not completely migrate to the outside of the insulating film 114, but a portion of it remains in the insulating film 114. Additionally, sometimes, while oxygen enters the insulating film 114, oxygen contained within the insulating film 114 migrates to the outside of the insulating film 114, resulting in oxygen movement within the insulating film 114. When forming an oxide insulating film 114 that allows oxygen to permeate, oxygen detached from the insulating film 116 disposed on the insulating film 114 can migrate through the insulating film 114 to the oxide semiconductor film 108.

[0216] Furthermore, the insulating film 114 can be formed using an oxide insulating film that is low in density of states due to oxide nitride. Note that this density of states due to oxide nitride can sometimes occur between the energy of the valence band top (Ev_os) and the energy of the conduction band bottom (Ec_os) of the oxide semiconductor film. As the aforementioned oxide insulating film, silicon oxynitride films or aluminum oxynitride films with low oxide nitride release can be used, etc.

[0217] Furthermore, in thermal desorption spectroscopy analysis, silicon oxynitride films with low nitrogen oxide release are those with higher ammonia release than nitrogen oxide release, typically with an ammonia release of 1 × 10⁻⁶. 18 pcs / cm 3 Above and 5×10 19 pcs / cm 3 Note that the ammonia release amount is the amount released during heat treatment at a membrane surface temperature of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower.

[0218] Nitrogen oxides (NO) x A nitrogen oxide (x) greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2, typically NO2 or NO, forms an energy level in the insulating film 114, etc. This energy level is located in the band gap of the oxide semiconductor film 108. Therefore, when nitrogen oxides diffuse to the interface between the insulating film 114 and the oxide semiconductor film 108, electrons are sometimes trapped on the insulating film 114 side of this energy level. As a result, the trapped electrons remain near the interface between the insulating film 114 and the oxide semiconductor film 108, thereby causing the threshold voltage of the transistor to drift in the positive direction.

[0219] Furthermore, during heat treatment, nitrogen oxides react with ammonia and oxygen. During heat treatment, the nitrogen oxides contained in insulating film 114 react with the ammonia contained in insulating film 116, thereby reducing the amount of nitrogen oxides contained in insulating film 114. Therefore, electrons are less likely to be trapped at the interface between insulating film 114 and oxide semiconductor film 108.

[0220] By using the aforementioned oxide insulating film as insulating film 114, the threshold voltage drift of the transistor can be reduced, thereby reducing the variation in the electrical characteristics of the transistor.

[0221] Due to the heat treatment in transistor manufacturing processes, typically above 300°C and below 350°C, the spectrum obtained by ESR measurement of the insulating film 114 at below 100K shows a first signal with a g value of 2.037 to 2.039, a second signal with a g value of 2.001 to 2.003, and a third signal with a g value of 1.964 to 1.966. In X-band ESR measurements, the split width between the first and second signals, and between the second and third signals, is approximately 5 mT. Furthermore, the sum of the spin densities of the first signal (g value 2.037 to 2.039), the second signal (g value 2.001 to 2.003), and the third signal (g value 1.964 to 1.966) is less than 1 × 10⁻⁶. 18 spins / cm 3 Typically 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 .

[0222] In ESR spectra below 100 K, the sum of the spin densities of the first signal (g=2.037 to 2.039), the second signal (g=2.001 to 2.003), and the third signal (g=1.964 to 1.966) corresponds to the spin density originating from nitrogen oxides (NO). x The signal is defined as x being greater than 0 and less than 2, preferably greater than 1 and less than 2. Typical examples of nitrogen oxides include nitric oxide and nitrogen dioxide. That is, the lower the sum of the spin densities of the first signal with a g value of 2.037 to 2.039, the second signal with a g value of 2.001 to 2.003, and the third signal with a g value of 1.964 to 1.966, the lower the nitrogen oxide content in the oxide insulating film.

[0223] In addition, the nitrogen concentration of the oxide insulating film measured using SIMS was 6 × 10⁻⁶. 20 atoms / cm 3 the following.

[0224] By forming the above-mentioned oxide insulating film using PECVD with silane and nitrous oxide at a substrate temperature of 220°C or higher and 350°C or lower, a dense and hard film can be formed.

[0225] Insulating film 116 is formed using an oxide insulating film whose oxygen content exceeds its stoichiometric composition. The oxide insulating film containing more oxygen than its stoichiometric composition experiences partial oxygen loss due to heating. TDS analysis shows that the amount of oxygen lost from the oxide insulating film with the excess oxygen content, converted to oxygen atoms, is 1.0 × 10⁻⁶. 19 atoms / cm 3 The preferred value is 3.0 × 10⁴. 20 atoms / cm 3 That's all. Note that the surface temperature of the membrane during the TDS analysis is preferably 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower.

[0226] The insulating film 116 can be made of silicon oxide, silicon oxynitride, etc., with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less.

[0227] Furthermore, the amount of defects in the insulating film 116 is preferably low; typically, the spin density of the signal originating from the dangling bonds in silicon at g = 2.001, as measured by ESR, is preferably below 1.5 × 10⁻⁶. 18 spins / cm 3 More preferably 1×10 18 spins / cm 3 Therefore, since the insulating film 116 is farther away from the oxide semiconductor film 108 than the insulating film 114, the defect density of the insulating film 116 can also be higher than that of the insulating film 114.

[0228] Furthermore, since insulating films 114 and 116 can be made of the same type of material, the interface between insulating film 114 and insulating film 116 is sometimes not clearly identifiable. Therefore, in this embodiment, the interface between insulating film 114 and insulating film 116 is shown as a dashed line. Note that although a two-layer structure of insulating film 114 and insulating film 116 is described in this embodiment, it is not limited to this; for example, a single-layer structure of insulating film 114 or a stacked structure of three or more layers may also be used.

[0229] Insulating film used as a protective insulating film

[0230] Insulating film 118 is used as a protective insulating film for transistor 100.

[0231] The insulating film 118 contains one or both of hydrogen and nitrogen. Additionally, the insulating film 118 contains nitrogen and silicon. Furthermore, the insulating film 118 has the function of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the insulating film 118, it is possible to prevent oxygen from diffusing from the oxide semiconductor film 108 to the outside, and it is also possible to prevent the oxygen contained in the insulating films 114 and 116 from diffusing to the outside, and it is also possible to prevent hydrogen, water, etc., from entering the oxide semiconductor film 108 from the outside.

[0232] As the insulating film 118, a nitride insulating film can be used, for example. Examples of such nitride insulating films include silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride.

[0233] While the various films described above, such as conductive films, insulating films, and oxide semiconductor films, can be formed using sputtering or PECVD methods, they can also be formed using other methods, such as thermal CVD (Chemical Vapor Deposition). Examples of thermal CVD methods include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD (Atomic Layer Deposition).

[0234] Since thermal CVD is a film formation method that does not use plasma, it has the advantage of not producing defects caused by plasma damage.

[0235] Film formation using thermal CVD can be performed as follows: source gas and oxidant are simultaneously supplied to the processing chamber, and the pressure in the processing chamber is set to atmospheric pressure or reduced pressure, so that they react near the substrate or on the substrate and are deposited on the substrate.

[0236] Alternatively, film formation using the ALD method can be performed as follows: the pressure inside the processing chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the processing chamber sequentially, and the gas is introduced repeatedly in this order.

[0237] Various films, such as conductive films, insulating films, oxide semiconductor films, and metal oxide films, as described in the above embodiments, can be formed using thermal CVD methods such as MOCVD and ALD. For example, when forming an In-Ga-ZnO film, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. Dimethylzinc has the chemical formula Zn(CH3)2. However, not limited to the above combinations, triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc.

[0238] For example, when forming a hafnium oxide film using an ALD film-forming apparatus, two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, tetramethylammonium hafnium (TDMAH), etc.); and ozone (O3) as an oxidant. Furthermore, the chemical formula of tetramethylammonium hafnium is Hf[N(CH3)2]4. Other materials include tetra(ethylmethylammonium)hafnium.

[0239] For example, when forming an alumina film using an ALD film-forming apparatus, two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA)); and H2O as an oxidant. Furthermore, the chemical formula of trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylammonium)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptadecyl)one.

[0240] For example, when forming a silicon oxide film using an ALD film-forming apparatus, hexachlorosilane is attached to the surface to be film-forming, removing the chlorine contained in the attached material, and supplying free radicals of oxidizing gases (O2, nitrous oxide) to react with the attached material.

[0241] For example, when forming a tungsten film using an ALD (Alternating Discharge) film-forming apparatus, WF6 gas and B2H6 gas are introduced sequentially and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are used to form the final tungsten film. Note that SiH4 gas can also be used instead of B2H6 gas.

[0242] For example, when forming an oxide semiconductor film such as an In-Ga-ZnO film using an ALD film-forming apparatus, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly to form an In-O layer, then Ga(CH3)3 gas and O3 gas are used to form a GaO layer, and finally Zn(CH3)2 gas and O3 gas are used to form a ZnO layer. Note that the order of these layers is not limited to the example above. Furthermore, these gases can also be used to form mixed compound layers such as In-Ga-O layers, In-Zn-O layers, Ga-Zn-O layers, etc. Note that although H2O gas obtained by bubbling with an inert gas such as Ar can be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. Additionally, In(C2H5)3 gas can be used instead of In(CH3)3 gas. Additionally, Ga(C2H5)3 gas can be used instead of Ga(CH3)3 gas. Additionally, Zn(CH3)2 gas can also be used.

[0243] <1-6. Transistor Manufacturing Methods 1>

[0244] Hereinafter, a method for manufacturing a transistor 100J of a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 14 to 17. FIG. 14 to 17 are cross-sectional views illustrating the method for manufacturing the semiconductor device. Figure 14A , Figure 14C , Figure 14E , Figure 15A , Figure 15C , Figure 15E , Figure 16A , Figure 16C , Figure 16E , Figure 17A , Figure 17C , Figure 17E This is a cross-sectional view along the length of the channel, shown in X1-X2. Figure 14B , Figure 14D , Figure 14F , Figure 15B , Figure 15D , Figure 15F , Figure 16B , Figure 16D , Figure 16F , Figure 17B , Figure 17D , Figure 17F This is a cross-sectional view along the width of the channel, shown in Y1-Y2.

[0245] Formation process of the first gate electrode and the first gate insulating film

[0246] First, a conductive film is formed on the substrate 102. This conductive film is then processed through photolithography and etching processes to form a conductive film 104, which serves as the first gate electrode. Next, insulating films 106 and 107, which serve as the first gate insulating film, are formed on the conductive film 104. Figure 14A and Figure 14B ).

[0247] In this embodiment, a glass substrate is used as the substrate 102, and a titanium film with a thickness of 10 nm, a copper film with a thickness of 100 nm, and a tantalum nitride film with a thickness of 50 nm are formed by sputtering as the conductive film 104 used as the first gate electrode.

[0248] As insulating film 106, a silicon nitride film with a thickness of 400 nm is formed by PECVD, and as insulating film 107, a silicon oxynitride film with a thickness of 15 nm is formed by PECVD. Insulating film 106 can be a stacked structure of silicon nitride films. Specifically, insulating film 106 can be a three-layer stacked structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. This three-layer structure can be formed, for example, as shown below.

[0249] A first silicon nitride film with a thickness of 50 nm can be formed under the following conditions: for example, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 100 sccm are supplied as source gases to the reaction chamber of the PECVD apparatus, the pressure in the reaction chamber is controlled at 100 Pa, and 2000 W of power is supplied using a 27.12 MHz high-frequency power supply.

[0250] A second silicon nitride film with a thickness of 300 nm can be formed under the following conditions: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 2000 sccm are supplied as source gases to the reaction chamber of the PECVD device; the pressure in the reaction chamber is controlled at 100 Pa; and a 2000 W power supply is provided using a 27.12 MHz high-frequency power supply.

[0251] A third silicon nitride film with a thickness of 50 nm can be formed under the following conditions: silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm are supplied as source gases to the reaction chamber of the PECVD device, the pressure in the reaction chamber is controlled at 100 Pa, and a 2000 W power supply is provided using a 27.12 MHz high-frequency power supply.

[0252] Alternatively, the substrate temperature during the formation of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be set to 350°C or below.

[0253] By employing a three-layer structure of silicon nitride film as insulating film 106, and for example, using a conductive film containing copper (Cu) as conductive film 104, the following effects can be achieved.

[0254] The first silicon nitride film can suppress the diffusion of copper (Cu) from the conductive film 104. The second silicon nitride film has the function of releasing hydrogen, which can improve the withstand voltage of the insulating film used as the gate insulating film. The third silicon nitride film is a film with low hydrogen release and can suppress the diffusion of hydrogen released from the second silicon nitride film.

[0255] To improve the interfacial properties between the insulating film 107 and the subsequently formed oxide semiconductor film 108 (more specifically, oxide semiconductor film 108b), it is preferable to use an oxygen-containing insulating film as the insulating film 107. Oxygen can be added to the insulating film 107 after its formation. The oxygen added to the insulating film 107 can be oxygen radicals, oxygen atoms, oxygen ions, oxygen molecular ions, etc. Methods of adding oxygen include ion doping, ion implantation, plasma treatment, etc.

[0256] The Formation Process of Oxide Semiconductor Films

[0257] Next, oxide semiconductor films 108b and 108c are formed on the insulating film 107 (see reference). Figure 14C , Figure 14D ).

[0258] Figure 14C and Figure 14D This is a cross-sectional schematic diagram of the film-forming apparatus during the formation of an oxide semiconductor film that will later become an oxide semiconductor film 108 on an insulating film 107. Figure 14C and Figure 14D The following are schematically shown: a sputtering apparatus as a film forming device; a target 191 disposed in the sputtering apparatus; and plasma 192 generated below the target 191.

[0259] First, during the formation of the oxide semiconductor film, plasma discharge is performed in an atmosphere containing a first oxygen gas. At this time, oxygen is added to the insulating film 107, which becomes the oxide semiconductor film to be formed. In addition to the first oxygen gas, the atmosphere during the formation of the oxide semiconductor film may also contain an inert gas (e.g., helium, argon, xenon, etc.).

[0260] The first oxygen gas need to be included in the film-forming gas when forming the oxide semiconductor film. In the total film-forming gas when forming the oxide semiconductor film, the proportion of the first oxygen gas is greater than 0% and less than 100%, preferably more than 10% and less than 100%, and more preferably more than 30% and less than 100%.

[0261] In addition, Figure 14C and Figure 14D In the diagram, dashed arrows schematically represent oxygen or excess oxygen added to the insulating film 107.

[0262] The substrate temperature for forming the oxide semiconductor film 108b can be the same as or different from the substrate temperature for forming the oxide semiconductor film 108c. However, it is preferred to make the substrate temperature for forming the oxide semiconductor film 108b the same as the substrate temperature for forming the oxide semiconductor film 108c to reduce manufacturing costs.

[0263] For example, the substrate temperature for forming the oxide semiconductor film 108 is above room temperature and below 340°C, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C, and even more preferably above 100°C and below 200°C. By forming the oxide semiconductor film 108 while heating, the crystallinity of the oxide semiconductor film 108 can be improved. On the other hand, when a large glass substrate (e.g., sixth to tenth generation) is used as the substrate 102, the substrate 102 may deform (strain or warp) if the substrate temperature for forming the oxide semiconductor film 108 is above 150°C and below 340°C. Therefore, when using a large glass substrate, by setting the substrate temperature for forming the oxide semiconductor film 108 to above 100°C and below 150°C, deformation of the glass substrate can be suppressed.

[0264] In addition, it is also necessary to ensure the high purity of the sputtering gas. For example, the oxygen or argon gas used as the sputtering gas should be a high-purity gas with a dew point of -40°C or below, preferably -80°C or below, more preferably -100°C or below, and even more preferably -120°C or below, thereby preventing moisture and other substances from mixing into the oxide semiconductor film as much as possible.

[0265] Furthermore, when forming oxide semiconductor films by sputtering, it is preferable to use an adsorption-type vacuum pump, such as a cryogenic pump, to perform high-vacuum evacuation (evacuating to 5 × 10⁻⁶) of the processing chamber of the sputtering apparatus. -7 Pa to 1×10 -4 (Approximately Pa) to remove as much water and other substances as possible, which are impurities for oxide semiconductor films. Alternatively, a combination of a turbomolecular pump and a cold trap is preferred to prevent gases, especially those containing carbon or hydrogen, from flowing back from the extraction system into the processing chamber.

[0266] After forming the oxide semiconductor film that will later become oxide semiconductor film 108b, the oxide semiconductor film that will later become oxide semiconductor film 108c is then formed. Note that during the formation of these oxide semiconductor films, plasma discharge can be performed in an atmosphere containing a second oxygen gas.

[0267] The proportion of the first oxygen gas in forming the oxide semiconductor film that will later become oxide semiconductor film 108b can be the same as or different from the proportion of the second oxygen gas in forming the oxide semiconductor film that will later become oxide semiconductor film 108c.

[0268] In this embodiment, an oxide semiconductor film, which will later become an oxide semiconductor film 108b, is formed by sputtering using an In-Ga-Zn metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). Then, in a vacuum, an oxide semiconductor film, which will later become an oxide semiconductor film 108c, is continuously formed by sputtering using an In-Ga-Zn metal oxide target (In:Ga:Zn = 1:1:1.2 [atomic ratio]). The substrate temperature during the formation of these oxide semiconductor films is set to 170°C. As the film-forming gas for the oxide semiconductor film that will later become the oxide semiconductor film 108b, an oxygen gas with a flow rate of 15 sccm and an argon gas with a flow rate of 35 sccm are used. Furthermore, as the film-forming gas for the oxide semiconductor film that will later become the oxide semiconductor film 108c, an oxygen gas with a flow rate of 25 sccm and an argon gas with a flow rate of 25 sccm are used.

[0269] Next, by processing the formed oxide semiconductor film into the desired shape, island-shaped oxide semiconductor films 108b and 108c are formed (see reference). Figure 14E and Figure 14F Furthermore, in this embodiment, the oxide semiconductor film 108 is composed of oxide semiconductor film 108b and oxide semiconductor film 108c (see reference). Figure 14E and Figure 14F ).

[0270] Furthermore, it is preferable to perform a heat treatment (hereinafter referred to as the first heat treatment) after forming the oxide semiconductor film 108. By performing the first heat treatment, the amount of hydrogen, water, etc. contained in the oxide semiconductor film 108 can be reduced. In addition, the heat treatment aimed at reducing hydrogen, water, etc. can also be performed before the oxide semiconductor film 108 is processed into an island shape. Note that the first heat treatment is one of the high-purity treatments for the oxide semiconductor film.

[0271] The temperature of the first heat treatment can be, for example, above 150°C and below the strain point of the substrate, preferably above 200°C and below 450°C, more preferably above 250°C and below 350°C.

[0272] Furthermore, the first heat treatment can be performed using an electric furnace, a rapid thermal anneal (RTA) device, or the like. By using an RTA device, heat treatment can be performed at a temperature above the strain point of the substrate for a short period of time. This shortens the heating time. The first heat treatment can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a rare gas (argon, helium, etc.). The aforementioned nitrogen, oxygen, ultra-dry air, or rare gas preferably does not contain hydrogen, water, etc. Furthermore, after heat treatment in a nitrogen or rare gas atmosphere, heating can also be performed in an oxygen or ultra-dry air atmosphere. As a result, oxygen can be supplied to the oxide semiconductor film while simultaneously removing hydrogen, water, etc., from the oxide semiconductor film. Consequently, oxygen defects in the oxide semiconductor film can be reduced.

[0273] Formation process of source and drain electrodes

[0274] Next, a conductive film 112, which will later become the source and drain electrodes, is formed on the insulating film 107 and the oxide semiconductor film 108 by sputtering (see reference). Figure 15A and Figure 15B ).

[0275] In this embodiment, conductive films 112_1, 112_2, and 112_3 are stacked as conductive films 112. A stacked film is formed by sequentially stacking a 50 nm thick tungsten film as conductive film 112_1, a 200 nm thick copper film as conductive film 112_2, and a 5 nm thick tungsten film as conductive film 112_3 using a sputtering method. Furthermore, in this embodiment, conductive films 112_1 and 112_3 are formed using the same material, but this is not a limitation. For example, a stacked film consisting of a 50 nm thick tungsten film as conductive film 112_1, a 200 nm thick copper film as conductive film 112_2, and a 50 nm thick titanium film as conductive film 112_3 can also be used. Additionally, a three-layer stacked structure of conductive film 112 is used here, but this is not a limitation. For example, a two-layer or four-layer stacked structure can also be used as conductive film 112.

[0276] Next, masks 141a and 141b are formed on the desired areas of the conductive film 112_3. Then, the conductive films 112_2 and 112_3 are processed using masks 141a and 141b to form island-shaped conductive films 112a_2, 112b_2, 112a_3, and 112b_3 separated from each other (see reference). Figure 15C and Figure 15D ).

[0277] In this embodiment, a wet etching apparatus is used to process the conductive films 112_2 and 112_3. Note that the processing method for the conductive film 112 is not limited to this; for example, a dry etching apparatus can also be used. Furthermore, compared to processing the conductive film 112 using a dry etching apparatus, processing the conductive film 112 using a wet etching apparatus can reduce manufacturing costs.

[0278] Next, by siliconizing the ends of the conductive films 112a_2 and 112b_2, regions 112a_2a and 112b_2a containing copper and regions 112a_2b and 112b_2b containing copper silicide are formed.

[0279] Figure 15E and Figure 15F This is a cross-sectional schematic diagram of the inside of the plasma device during the siliconization of the ends of conductive films 112a_2 and 112b_2. Figure 15E and Figure 15F The image schematically illustrates a PECVD apparatus used as a plasma device and plasma 195 generated inside the PECVD apparatus.

[0280] An oxide film easily forms on the copper surface exposed at the ends of conductive films 112a_2 and 112b_2. Therefore, as a pretreatment for silicide formation of copper, plasma discharge is performed in an atmosphere with a reducing gas (e.g., hydrogen, ammonia, etc.) to remove the oxide film covering the copper surface. This reduces the oxide film covering the copper surface, exposing copper at the ends of conductive films 112a_2 and 112b_2. Furthermore, the reduction method used to remove this oxide film is not limited to plasma treatment. For example, reduction can also be performed by exposing the copper surface to an atmosphere containing a reducing gas (e.g., hydrogen, ammonia, etc.) and then heating it. Furthermore, the substrate temperature during the plasma treatment and heating treatment is preferably 300°C or higher, more preferably 350°C or higher. In this embodiment, the substrate temperature for removing the oxide film covering the copper surface is set to 350°C.

[0281] Next, by exposing the copper surface to an atmosphere containing silane gas and reacting the copper with the silane gas, copper silicides containing copper and silicon are formed at the ends of conductive films 112a_2 and 112b_2, forming regions 112a_2b and 112b_2b. Furthermore, regions in conductive films 112a_2 and 112b_2 where no copper silicide is formed are referred to as regions 112a_2a and 112b_2a. The substrate temperature for forming the copper silicide is preferably 200°C or higher and 400°C or lower, more preferably 220°C or higher and 350°C or lower. In this embodiment, the substrate temperature for forming the copper silicide is 220°C, and silane gas with a flow rate of 300 sccm and nitrogen gas with a flow rate of 500 sccm are used.

[0282] When the substrate temperature for removing the oxide film from the copper surface is equal to the substrate temperature for forming the copper silicide, oxide film removal and copper silicide formation can be performed in the same apparatus or the same processing chamber, which is preferred. In this case, the substrate temperature for forming the copper silicide is preferably 350°C.

[0283] As the gas used to form copper silicide, any gas containing at least silicon may be used. The percentage of silicon-containing gas in the overall gas mixture for forming copper silicide is greater than 0% and less than 100%, preferably more than 10% and less than 100%, and more preferably more than 30% and less than 100%.

[0284] exist Figure 15E and Figure 15F In the diagram, dashed arrows schematically represent silicon or silane added to conductive films 112a_2 and 112b_2.

[0285] After forming the copper silicide, plasma discharge can be performed in a nitrogen-containing atmosphere to form copper silicide nitrides containing copper, silicon, and nitrogen in the conductive films 112a_2 and 112b_2. Alternatively, copper silicide nitrides containing copper, silicon, and nitrogen can be formed in the conductive films 112a_2 and 112b_2 by exposing the substrate to a nitrogen-containing atmosphere and performing a heat treatment.

[0286] Next, masks 142a and 142b are formed on a portion of conductive film 112_1 and on desired areas of conductive films 112a_2, 112b_2, 112a_3, and 112b_3. Then, conductive film 112_1 is processed using masks 142a and 142b to form island-shaped conductive films 112a_1 and 112b_1 separated from each other. Through the above processes, a conductive film 112a including conductive film 112a_1, conductive film 112a_2 including region 112a_2a and region 112a_2b, and conductive film 112_3 are formed; and a conductive film 112b including conductive film 112b_1, conductive film 112b_2 including region 112b_2a and region 112b_2b, and conductive film 112b_3 are formed (see reference). Figure 16A and Figure 16B ).

[0287] In this embodiment, the conductive film 112_1 is processed using a dry etching apparatus. However, the processing method for the conductive film 112_1 is not limited to this; for example, a wet etching apparatus can also be used. Note that compared to processing the conductive film 112_1 using a wet etching apparatus, processing the conductive film 112_1 using a dry etching apparatus can form finer patterns.

[0288] Furthermore, the surface (back channel side) of the oxide semiconductor film 108 (more specifically, the oxide semiconductor film 108b) can be washed after the conductive films 112a and 112b are formed. Examples of such washing methods include washing with a chemical solution such as phosphoric acid. By washing with a chemical solution such as phosphoric acid, impurities (e.g., elements contained in the conductive films 112a and 112b) adhering to the surface of the oxide semiconductor film 108b can be removed. Note that this washing is not always necessary and may be omitted depending on the circumstances.

[0289] In addition, in one or both of the forming processes of conductive films 112a and 112b and the washing processes described above, the area of ​​oxide semiconductor film 108 exposed from conductive films 112a and 112b may sometimes become thinner.

[0290] Formation process of the second gate insulating film

[0291] Next, insulating films 114 and 116 are formed on oxide semiconductor film 108, conductive films 112a and 112b (see reference). Figure 16C and Figure 16D ).

[0292] Preferably, after forming the insulating film 114, the insulating film 116 is continuously formed without exposure to the atmosphere. After forming the insulating film 114, the insulating film 116 is continuously formed by adjusting one or more of the source gas flow rate, pressure, high-frequency power, and substrate temperature without exposure to the atmosphere. This reduces the concentration of atmospheric impurities at the interface between the insulating films 114 and 116, and allows oxygen contained in the insulating films 114 and 116 to move into the oxide semiconductor film 108, thereby reducing the amount of oxygen defects in the oxide semiconductor film 108.

[0293] For example, silicon oxynitride film can be formed as insulating film 114 by PECVD. In this case, a silicon-containing deposition gas and an oxidizing gas are preferably used as the source gas. Typical examples of silicon-containing deposition gases include silane, disilane, propane, and fluorinated silane. Oxidizing gases include nitrous oxide and nitrogen dioxide. Furthermore, an insulating film 114 containing nitrogen and with low defect content can be formed by PECVD under the following conditions: the flow rate of the oxidizing gas is greater than 20 times and less than 100 times, preferably more than 40 times and less than 80 times, the flow rate of the deposition gas; and the pressure in the processing chamber is less than 100 Pa, preferably less than 50 Pa.

[0294] In this embodiment, as the insulating film 114, a silicon oxynitride film is formed using PECVD under the following conditions: the temperature of the substrate 102 is maintained at 220°C; silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as the source gases; the pressure inside the processing chamber is 20 Pa; and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz and 100 W (power density of 1.6 × 10⁻⁶). -2 W / cm 2 ).

[0295] As the insulating film 116, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate temperature in the processing chamber of the PECVD apparatus, which has been vacuum-evacuated, is maintained at 180°C or higher and 350°C or lower; a source gas is introduced into the processing chamber and the pressure inside the processing chamber is set to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower; and 0.17 W / cm² is supplied to the electrode provided in the processing chamber. 2 Above and 0.5W / cm 2 The following is more preferably 0.25 W / cm 2 Above and 0.35W / cm 2 The following are high-frequency power values.

[0296] As the film-forming conditions for the insulating film 116, a high-frequency power with the aforementioned power density is supplied to the reaction chamber at the aforementioned pressure. This improves the decomposition efficiency of the source gas in the plasma, increases oxygen free radicals, and promotes the oxidation of the source gas, causing the oxygen content in the insulating film 116 to exceed its stoichiometric composition. On the other hand, in the film formed at the aforementioned substrate temperature, since the bonding force between silicon and oxygen is weak, a portion of the oxygen in the film is removed through subsequent heat treatment processes. As a result, an oxide insulating film with an oxygen content exceeding its stoichiometric composition and a portion of its oxygen removed due to heating can be formed.

[0297] In the process of forming the insulating film 116, the insulating film 114 is used as a protective film for the oxide semiconductor film 108. Therefore, the insulating film 116 can be formed using high-frequency power with high power density while minimizing damage to the oxide semiconductor film 108.

[0298] Furthermore, as a film-forming condition for the insulating film 116, the amount of defects in the insulating film 116 can be reduced by increasing the flow rate of the silicon-containing deposition gas relative to the oxidizing gas. Typically, an oxide insulating film with a low amount of defects can be formed, wherein the spin density of the signal originating from silicon dangling bonds and appearing at g = 2.001, as measured by ESR, is less than 6 × 10⁻⁶. 17 spins / cm 3 Preferably 3×10 17spins / cm 3 The following is more preferably 1.5 × 10 17 spins / cm 3 The result is that the reliability of transistor 100 can be improved.

[0299] Preferably, a heat treatment (hereinafter referred to as a second heat treatment) is performed after the insulating films 114 and 116 are formed. The second heat treatment can reduce the amount of nitrogen oxides contained in the insulating films 114 and 116. Alternatively, the second heat treatment can move a portion of the oxygen contained in the insulating films 114 and 116 into the oxide semiconductor film 108 to reduce the amount of oxygen defects in the oxide semiconductor film 108.

[0300] The temperature for the second heat treatment is typically set below 400°C, preferably below 375°C, and more preferably above 150°C and below 350°C. The second heat treatment can be carried out in an atmosphere of nitrogen, oxygen, ultra-dry air (containing less than 20 ppm of water, preferably less than 1 ppm, and more preferably less than 10 ppb of water), or a rare gas (argon, helium, etc.). Preferably, the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, or the like. This heat treatment can be carried out using an electric furnace, an RTA device, or the like.

[0301] Next, a mask is formed on the insulating film 116 using a photolithography process, forming an opening 152c in the desired area of ​​the insulating films 114 and 116. Furthermore, the opening 152c is formed such that it reaches the conductive film 112b (see reference). Figure 16E and Figure 16F ).

[0302] Formation process of the second gate electrode

[0303] Next, conductive films 120a and 120b are formed on the insulating film 116 in a manner that covers the opening 152c (see reference). Figure 17A , Figure 17B , Figure 17C , Figure 17D ).

[0304] Figure 17A and Figure 17B This is a cross-sectional schematic diagram of the film-forming apparatus when forming conductive films 120a and 120b on the insulating film 116. Figure 17A and Figure 17B The following are schematically shown: a sputtering apparatus as a film forming device; a target 193 disposed in the sputtering apparatus; and plasma 194 formed below the target 193.

[0305] First, during the formation of conductive films 120a and 120b, plasma discharge is performed in an atmosphere containing a third oxygen gas. At this time, oxygen is added to the insulating film 116 on which the conductive films 120a and 120b are formed. During the formation of conductive films 120a and 120b, this atmosphere may contain an inert gas (e.g., helium, argon, xenon, etc.) in addition to the third oxygen gas. For example, it is preferable to use argon gas and the third oxygen gas, with the flow rate of the third oxygen gas being greater than that of argon gas. By making the flow rate of the third oxygen gas greater than that of argon gas, oxygen can be appropriately added to the insulating film 116. For example, as the formation conditions for conductive films 120a and 120b, the proportion of a fourth oxygen gas in the overall film-forming gas can be 50% or more and 100% or less, preferably 80% or more and 100% or less.

[0306] exist Figure 17A and Figure 17B In the diagram, dashed arrows schematically represent oxygen or excess oxygen added to the insulating film 116.

[0307] The substrate temperature for forming conductive films 120a and 120b is above room temperature and below 340°C, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C, and even more preferably above 100°C and below 200°C. By forming conductive films 120a and 120b simultaneously with heating, the crystallinity of conductive films 120a and 120b can be improved. On the other hand, when a large glass substrate (e.g., sixth to tenth generation) is used as substrate 102, if the substrate temperature for forming conductive films 120a and 120b is above 150°C and below 340°C, substrate 102 may deform (strain or warp). Therefore, when using a large glass substrate, by setting the substrate temperature for forming conductive films 120a and 120b to above 100°C and below 150°C, deformation of the glass substrate can be suppressed.

[0308] In this embodiment, conductive films 120a and 120b are formed by sputtering using an In-Ga-Zn metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The substrate temperature for forming the conductive films 120a and 120b is set to 170°C. An oxygen gas with a flow rate of 100 sccm is used as the film-forming gas for forming the conductive films 120a and 120b.

[0309] As conductive films 120a and 120b, for example, the oxide semiconductor films described above (e.g., In:Ga:Zn = 1:1:1 [atomic ratio], In:Ga:Zn = 1:3:2 [atomic ratio], In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 1:3:6 [atomic ratio], In:Ga:Zn = 3:1:2 [atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], In:Ga:Zn = 5:1:6 [atomic ratio], etc.) can be used.

[0310] Although this embodiment shows a method for adding oxygen to the insulating film 116 during the formation of conductive films 120a and 120b, it is not limited thereto. For example, oxygen may also be added to the insulating film 116 after the formation of conductive films 120a and 120b.

[0311] As a method for adding oxygen to the insulating film 116, for example, an ITSO film with a thickness of 5 nm can be formed using an oxide (also known as ITSO) target containing indium, tin, and silicon (In2O3:SnO2:SiO2 = 85:10:5 [wt%]) as an oxide conductive film.

[0312] At this point, it is preferable that the thickness of the oxide conductive film is 1 nm or more and 20 nm or less, or 2 nm or more and 10 nm or less, so that oxygen can be appropriately permeated while oxygen release is suppressed. Then, oxygen is added to the insulating film 116 through the oxide conductive film. Examples of methods for adding oxygen include ion doping, ion implantation, and plasma treatment. When adding oxygen, it can be effectively added to the insulating film 116 by applying a bias voltage to the substrate side. When applying the bias voltage, for example, using an ashing device, the power density of the bias voltage applied to the substrate side of the ashing device can be set to 1 W / cm². 2 Above and 5W / cm 2 Furthermore, by setting the substrate temperature at which oxygen is added to be above room temperature and below 300°C, preferably above 100°C and below 250°C, oxygen can be added to the insulating film 116 efficiently.

[0313] Next, by processing the formed conductive film into the desired shape, island-shaped conductive film 120a and island-shaped conductive film 120b are formed (see reference). Figure 17C and Figure 17D ).

[0314] The process of forming the protective insulating film

[0315] Next, an insulating film 118 is formed on the insulating film 116 and the conductive films 120a and 120b (see reference). Figure 17E and Figure 17F ).

[0316] The insulating film 118 contains one or both of hydrogen and nitrogen. Silicon nitride film is preferably used as the insulating film 118, for example. The insulating film 118 can be formed, for example, by sputtering or PECVD. For example, when forming the insulating film 118 by PECVD, the substrate temperature is kept below 400°C, preferably below 375°C, and more preferably above 180°C and below 350°C. By setting the substrate temperature during the formation of the insulating film 118 to the above range, a dense film can be formed, which is preferred. Furthermore, by setting the substrate temperature during the formation of the insulating film 118 to the above range, oxygen or excess oxygen in the insulating films 114 and 116 can be moved to the oxide semiconductor film 108.

[0317] Alternatively, a heat treatment identical to the first or second heat treatment described above (hereinafter referred to as the third heat treatment) can be performed after the formation of the insulating film 118. Thus, by adding oxygen to the insulating film 116 during the formation of the insulating film 118, and then performing a heat treatment at a temperature below 400°C, preferably below 375°C, and more preferably above 180°C and below 350°C, oxygen or excess oxygen in the insulating film 116 can be moved to the oxide semiconductor film 108 (especially the oxide semiconductor film 108b), thereby filling oxygen defects in the oxide semiconductor film 108.

[0318] Furthermore, an insulating film 106 is disposed below the insulating film 107, and an insulating film 118 is disposed above the insulating films 114 and 116. By using a material with low oxygen permeability, such as silicon nitride, to form the insulating films 106 and 118, the oxygen contained in the insulating films 107, 114, and 116 can be sealed on one side of the oxide semiconductor film 108, so oxygen can be effectively moved to the oxide semiconductor film 108.

[0319] In addition, the insulating film 118 contains one or both of hydrogen and nitrogen. Therefore, by forming the insulating film 118, the conductive films 120a and 120b in contact with the insulating film 118 are added with one or both of hydrogen and nitrogen, thereby increasing their carrier density and enabling them to be used as oxide conductive films.

[0320] When a silicon nitride film is formed as an insulating film 118 using PECVD, a silicon-containing deposition gas, nitrogen, and ammonia are preferably used as the source gas. By using ammonia in a quantity less than nitrogen, active species are generated through ammonia dissociation in the plasma. These active species break the bonds between silicon and hydrogen, as well as the triple bonds between nitrogen and silicon, contained in the silicon-containing deposition gas. As a result, silicon-nitrogen bonding is promoted, and a dense silicon nitride film with fewer silicon-hydrogen bonds and fewer defects can be formed. On the other hand, when the amount of ammonia is greater than the amount of nitrogen, the decomposition of the silicon-containing deposition gas and nitrogen does not progress, and silicon-hydrogen bonds remain, resulting in the formation of a silicon nitride film with increased defects and a less dense structure. Therefore, the nitrogen flow rate ratio relative to ammonia in the source gas is set to 5 times or more and 50 times or less, preferably 10 times or more and 50 times or less.

[0321] In this embodiment, as the insulating film 118, a silicon nitride film with a thickness of 100 nm is formed using a PECVD apparatus and silane, nitrogen, and ammonia as source gases. The flow rate of silane is 50 sccm, the flow rate of nitrogen is 5000 sccm, and the flow rate of ammonia is 100 sccm. The pressure of the processing chamber is set to 100 Pa, the substrate temperature is set to 350°C, and a high-frequency power of 1000 W is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power supply. The PECVD apparatus has an electrode area of ​​6000 cm². 2 The parallel plate PECVD device, and the power supplied is converted to power density per unit area as 1.7 × 10⁻⁶. -1 W / cm 2 .

[0322] Through the above processes, it is possible to manufacture Figure 9A and Figure 9B The transistor shown is 100J.

[0323] Throughout the manufacturing process of transistor 100J, by keeping the substrate temperature below 400°C, preferably below 375°C, and more preferably above 180°C and below 350°C, substrate deformation (strain or warping) can be suppressed even when using a large-area substrate, which is therefore preferred. In the manufacturing process of transistor 100J, as a process of increasing the substrate temperature, typically, the substrate temperature during the formation of insulating films 106 and 107 (below 400°C, preferably above 250°C and below 350°C), the substrate temperature during the formation of oxide semiconductor film 108 (above room temperature and below 340°C, preferably above 100°C and below 200°C, more preferably above 100°C and below 150°C), the substrate temperature during the formation of insulating films 116 and 118 (below 400°C, preferably below 375°C, more preferably above 180°C and below 350°C), and the temperature of the first or second heat treatment after adding oxygen (below 400°C, preferably below 375°C, more preferably above 180°C and below 350°C) are applied to the substrate.

[0324] <1-7. Transistor Manufacturing Method 2>

[0325] Next, a method for manufacturing a transistor 100M of a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 18 to 20. FIG. 18 to 20 are cross-sectional views illustrating the method for manufacturing the semiconductor device. Figure 18A , Figure 18C , Figure 18E , Figure 19A , Figure 19C , Figure 20A It is the length direction of the channel shown in X1-X2. Figure 18B , Figure 18D , Figure 18F , Figure 19B , Figure 19D , Figure 20B This is a cross-sectional view along the width of the channel, shown in Y1-Y2.

[0326] The methods for forming conductive film 104, insulating film 106, 107, oxide semiconductor film 108, conductive film 112_1, conductive film 112a_2 (regions 112a_2a, 112a_2b), conductive film 112b_2 (regions 112b_2a, 112b_2b), conductive film 112a_3, and conductive film 112b_3 are the same as the method for forming transistor 100J described above, so please refer to Figures 14 and 15.

[0327] In this embodiment, the conductive film 112 is a stacked film consisting of a tungsten film with a thickness of 50 nm as conductive film 112_1, a copper film with a thickness of 200 nm as conductive film 112_2, and a titanium film with a thickness of 50 nm as conductive film 112_3, which are stacked in sequence.

[0328] Next, by using conductive films 112a_2, 112b_2, and 112_3 as masks, conductive film 112_1 is processed to form island-shaped conductive films 112a_1 and 112b_1 that are separated from each other. Through this process, conductive film 112a, comprising conductive film 112a_1, conductive film 112a_2 (regions 112a_2a and 112a_2b), and conductive film 112a_3, and conductive film 112b, comprising conductive film 112b_1, conductive film 112b_2 (regions 112b_2a and 112b_2b), and conductive film 112b_3, are formed (see reference). Figure 18A and Figure 18B ).

[0329] The conductive films 112a and 112b can be formed using the same method as transistor 100J.

[0330] Next, insulating films 114, 116 and 118 (see reference) are formed on the oxide semiconductor film 108 and the conductive films 112a, 112b. Figure 18C , Figure 18D , Figure 18E , Figure 18F The same method as that used for forming the insulating films 114, 116, and 118 can be used as for forming the transistor 100J.

[0331] Alternatively, a heat treatment identical to the first or second heat treatment described above (hereinafter referred to as the third heat treatment) can be performed after the formation of the insulating film 118. Thus, by adding oxygen to the insulating film 116 during the formation of the insulating film 118, and then performing a heat treatment at a temperature below 400°C, preferably below 375°C, and more preferably above 180°C and below 350°C, oxygen or excess oxygen in the insulating film 116 can be moved to the oxide semiconductor film 108 (especially the oxide semiconductor film 108b), thereby filling oxygen defects in the oxide semiconductor film 108.

[0332] Here, the migration of oxygen into the oxide semiconductor film 108 will be explained with reference to FIG20. FIG20 is a model diagram showing the migration of oxygen into the oxide semiconductor film 108 due to the substrate temperature during the formation of the insulating film 118 (typically below 375°C) or a second heat treatment after the formation of the insulating film 118 (typically below 375°C). Note that in FIG20, the dashed arrows represent oxygen (oxygen radicals, oxygen atoms, or oxygen molecules) that migrate into the oxide semiconductor film 108.

[0333] When oxygen moves from the insulating film (here, insulating film 107 and insulating film 114) close to the oxide semiconductor film 108 shown in FIG. 20, oxygen defects are filled. In particular, in a semiconductor device according to one aspect of the present invention, when the oxide semiconductor film 108b is formed by sputtering, the insulating film 107 contains excess oxygen regions because oxygen is added to the insulating film 107 using an oxygen gas. Furthermore, when the oxide conductive film is formed by sputtering, the insulating film 116 has excess oxygen regions because oxygen is added to the insulating film 116 using an oxygen gas. Therefore, since the oxide semiconductor film 108 is sandwiched between these insulating films containing excess oxygen regions, oxygen defects are effectively filled.

[0334] Next, a mask is formed on the insulating film 118 using a photolithography process, forming openings 152c in desired areas of the insulating films 114, 116, and 118. Furthermore, the openings 152c are formed such that they reach the conductive film 112b (see reference). Figure 19A and Figure 19B ).

[0335] Next, conductive films 120a and 120b are formed on the insulating film 116 in a manner that covers the opening 152c (see reference). Figure 19C and Figure 19D The conductive films 120a and 120b can be formed using the same method as transistor 100J.

[0336] Through the above processes, it is possible to manufacture Figure 10C The transistor shown is 100M.

[0337] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0338] (Implementation Method 2)

[0339] In this embodiment, refer to Figures 21 to 22. Figure 28 The composition and structure of the oxide semiconductor, which can be used in one aspect of the present invention, will be described.

[0340] 2-1. Composition of oxide semiconductors

[0341] First, let's explain the composition of oxide semiconductors.

[0342] The oxide semiconductor preferably contains at least indium or zinc. Particularly preferred are indium and zinc. Additionally, it is preferable to also contain aluminum, gallium, yttrium, or tin. Furthermore, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0343] Consider the case where an oxide semiconductor contains indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of these elements can sometimes be combined as element M.

[0344] First, refer to Figure 21A , Figure 21B and Figure 21C The preferred atomic ratio range of indium, element M, and zinc contained in an oxide semiconductor according to one embodiment of the present invention is explained. Note that the atomic ratio of oxygen is not shown in FIG. 21. The atomic ratios of indium, element M, and zinc contained in the oxide semiconductor are referred to as [In], [M], and [Zn], respectively.

[0345] exist Figure 21A , Figure 21B and Figure 21C In the diagram, the dashed lines represent the atomic ratios of [In]:[M]:[Zn] = (1+α):(1-α):1 (-1≤α≤1), [In]:[M]:[Zn] = (1+α):(1-α):2, [In]:[M]:[Zn] = (1+α):(1-α):3, [In]:[M]:[Zn] = (1+α):(1-α):4, and [In]:[M]:[Zn] = (1+α):(1-α):5.

[0346] The dotted-dash lines represent the atomic ratios of [In]:[M]:[Zn] = 1:1:β (β≥0), [In]:[M]:[Zn] = 1:2:β, [In]:[M]:[Zn] = 1:3:β, [In]:[M]:[Zn] = 1:4:β, [In]:[M]:[Zn] = 2:1:β, and [In]:[M]:[Zn] = 5:1:β.

[0347] Furthermore, the double-dotted line represents the atomic ratio of [In]:[M]:[Zn] = (1+γ):2:(1-γ) (-1≤γ≤1). Additionally, oxide semiconductors with an atomic ratio of [In]:[M]:[Zn] = 0:2:1 or values ​​close to that shown in Figure 21 tend to have spinel-type crystal structures.

[0348] Figure 21A and Figure 21B An example is shown of a preferred atomic ratio range of indium, element M, and zinc contained in an oxide semiconductor according to one aspect of the present invention.

[0349] As an example Figure 22 The crystal structure of InMZnO4 with [In]:[M]:[Zn] = 1:1:1 is shown. Figure 22 This is the crystal structure of InMZnO4 when viewed from a direction parallel to the b-axis. Figure 22 The metallic elements in the layer containing M, Zn, and oxygen (hereinafter, the (M, Zn) layer) shown represent either element M or zinc. At this point, the proportions of element M and zinc are equal. Element M and zinc can substitute for each other, and their arrangement is irregular.

[0350] InMZnO4 has a layered crystalline structure (also known as a layered structure), such as Figure 22 As shown, the ratio of the layer containing indium and oxygen (hereinafter referred to as the In layer) to the (M, Zn) layer containing elements M, zinc, and oxygen is 1:2.

[0351] Indium and element M can be interchanged. Therefore, element M in a (M, Zn) layer can be replaced by indium, and the layer can be represented as an (In, M, Zn) layer. In this case, there is a layered structure with an In layer : (In, M, Zn) layer ratio of 1:2.

[0352] Oxide semiconductors with an atomic ratio of [In]:[M]:[Zn] = 1:1:2 have a layered structure with an In layer:(M,Zn) layer ratio of 1:3. That is, as [Zn] increases relative to [In] and [M], the proportion of the (M,Zn) layer relative to the In layer increases when the oxide semiconductor is crystallized.

[0353] Note that in oxide semiconductors, when the In:(M,Zn) layer ratio is 1: a non-integer, there are sometimes multiple layered structures where the In:(M,Zn) layer ratio is 1: an integer. For example, in the case of [In]:[M]:[Zn] = 1:1:1.5, there are sometimes layered structures where the In:(M,Zn) layer ratio is 1:2 and the In:(M,Zn) layer ratio is 1:3 mixed together.

[0354] For example, when forming oxide semiconductors using a sputtering apparatus, a film is formed with an atomic ratio different from that of the target. In particular, depending on the substrate temperature during film formation, sometimes the [Zn] of the film is less than that of the target.

[0355] In oxide semiconductors, multiple phases sometimes coexist (e.g., two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn] = 0:2:1, spinel-type and layered-type crystalline structures tend to coexist. When the atomic ratio is close to [In]:[M]:[Zn] = 1:0:0, ferromanganese-type and layered-type crystalline structures tend to coexist. When multiple phases coexist in oxide semiconductors, grain boundaries (also called grain boundaries) sometimes form between different crystalline structures.

[0356] Increasing the indium content can improve the carrier mobility (electron mobility) of oxide semiconductors. This is because, in oxide semiconductors containing indium, element M, and zinc, the s orbitals of heavy metals primarily facilitate carrier conduction. By increasing the indium content, the overlapping region of s orbitals becomes larger, thus the carrier mobility of oxide semiconductors with high indium content is higher than that of oxide semiconductors with low indium content.

[0357] On the other hand, when the indium and zinc content of oxide semiconductors decreases, the carrier mobility decreases. Therefore, the atomic ratio of [In]:[M]:[Zn] = 0:1:0 and the atomic ratio of its vicinity (e.g., Figure 21C In region C), the insulation becomes higher.

[0358] Therefore, the oxide semiconductor of one aspect of the present invention preferably has Figure 21A The ratio of the number of atoms in region A indicates that the oxide semiconductor is likely to have a layered structure with high carrier mobility and few grain boundaries.

[0359] Figure 21B Region B in the diagram shows [In]:[M]:[Zn] = 4:2:3 to 4.1 and its vicinity. Vicinity values ​​include, for example, an atomic ratio of [In]:[M]:[Zn] = 5:3:4. Oxide semiconductors with atomic ratios represented by region B are particularly excellent oxide semiconductors with high crystallinity and high carrier mobility.

[0360] Note that the conditions for forming a layered structure in oxide semiconductors are not solely determined by the atomic ratio. The formation of a layered structure is difficult to differentiate based on the atomic ratio. On the other hand, even with the same atomic ratio, the presence of a layered structure can vary depending on the formation conditions. Therefore, the illustrated region represents the atomic ratio when an oxide semiconductor exhibits a layered structure, and the boundary between regions A and C is not strictly defined.

[0361] 2-2. Using oxide semiconductors in transistor structures

[0362] Next, we will explain the application of the aforementioned oxide semiconductor in transistors.

[0363] By using the aforementioned oxide semiconductors in transistors, carrier scattering at grain boundaries can be reduced, thus enabling the realization of transistors with high field-effect mobility. Furthermore, transistors with high reliability can be achieved.

[0364] Furthermore, oxide semiconductors with low carrier density are preferably used in transistors. For example, the carrier density of the oxide semiconductor is set to be less than 8 × 10⁻⁶. 11 / cm 3 Preferably less than 1×10 11 / cm 3 More preferably, less than 1×10 10 / cm 3 And 1×10 -9 / cm 3 above.

[0365] Furthermore, because there are fewer carrier generation sources in high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors, the carrier density can be reduced. In addition, the defect state density is low in high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors, so their trap state density is sometimes also reduced.

[0366] Furthermore, the charge trapped in the trap levels of oxide semiconductors takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical characteristics of transistors forming channel regions in oxide semiconductors with high trap state densities are sometimes unstable.

[0367] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0368] Here, we will explain the effects of various impurities in oxide semiconductors.

[0369] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor, and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration measured by secondary ion mass spectrometry (SIMS)) are set to 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0370] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states can sometimes form, resulting in charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to have always-on characteristics. Consequently, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor, as measured by SIMS, should be 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0371] When oxide semiconductors contain nitrogen, electrons are generated as charge carriers, and the carrier density increases, making the oxide semiconductor more prone to n-type characteristics. As a result, transistors using nitrogen-containing oxide semiconductors tend to exhibit normally-on characteristics. Therefore, it is preferable to minimize the nitrogen content in the oxide semiconductor as much as possible; for example, the nitrogen concentration in the oxide semiconductor measured by SIMS analysis should be less than 5 × 10⁻⁶. 19 atoms / cm 3 Preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0372] Hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using oxide semiconductors containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the oxide semiconductor. Specifically, the hydrogen concentration in the oxide semiconductor, as measured by SIMS, should be less than 1 × 10⁻⁶.20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 .

[0373] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of transistors, stable electrical characteristics can be imparted.

[0374] <2-3. Stacked Structure of Oxide Semiconductors>

[0375] Next, the cases where the oxide semiconductor adopts a two-layer or three-layer structure will be explained. Referring to FIG23, the energy band diagrams of the insulators in contact with the stacked structures of oxide semiconductors S1, S2, and S3, and the energy band diagrams of the insulators in contact with the stacked structures of oxide semiconductors S2 and S3 will be explained.

[0376] Figure 23A This is an example of a band structure along the thickness direction of a stacked structure including insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2. Additionally, Figure 23B This is an example of an energy band diagram along the thickness direction of a stacked structure comprising insulator I1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2. Note that, for ease of understanding, the energy band diagram shows the energy level (Ec) at the conduction band bottom of insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2.

[0377] Preferably, the conduction band bottom of oxide semiconductors S1 and S3 is closer to the vacuum level than that of oxide semiconductor S2. Typically, the energy difference between the conduction band bottom of oxide semiconductor S2 and that of oxide semiconductors S1 and S3 is 0.15 eV or more, 0.5 eV or more and 2 eV or less, or 1 eV or less. That is, compared to oxide semiconductors S1 and S3, oxide semiconductor S2 has a larger electron affinity, and the difference between the electron affinity of oxide semiconductors S1 and S3 and that of oxide semiconductor S2 is 0.15 eV or more, 0.5 eV or more and 2 eV or less, or 1 eV or less.

[0378] like Figure 23A and Figure 23BAs shown, in oxide semiconductors S1, S2, and S3, the energy levels at the bottom of the conduction band change gradually. In other words, the above situation can also be expressed as the energy levels at the bottom of the conduction band changing continuously or continuously converging. To achieve this band pattern, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide semiconductors S1 and S2 or between oxide semiconductors S2 and S3.

[0379] Specifically, by including a common element (main component) other than oxygen in oxide semiconductors S1 and S2, and oxide semiconductors S2 and S3, a mixed layer with low defect state density can be formed. For example, when oxide semiconductor S2 is In-Ga-Zn oxide, In-Ga-Zn oxide semiconductor, Ga-Zn oxide semiconductor, gallium oxide, etc. are preferably used as oxide semiconductors S1 and S3.

[0380] At this point, oxide semiconductor S2 becomes the main pathway for charge carriers. Because the defect state density at the interfaces between oxide semiconductors S1 and S2, and between oxide semiconductors S2 and S3, can be reduced, the effect of interface scattering on charge carrier conduction is small, thus resulting in a large on-state current.

[0381] When an electron is trapped in the trap level, the trapped electron behaves like a fixed charge, causing the threshold voltage of the transistor to drift in the positive direction. By setting oxide semiconductors S1 and S3, the trap level can be moved away from oxide semiconductor S2. By adopting this structure, the threshold voltage of the transistor can be prevented from drifting in the positive direction.

[0382] Oxide semiconductors S1 and S3 are made of materials with conductivity sufficiently lower than that of oxide semiconductor S2. In this case, oxide semiconductor S2, the interface between oxide semiconductor S2 and oxide semiconductor S1, and the interface between oxide semiconductor S2 and oxide semiconductor S3 are primarily used as channel regions. For example, oxide semiconductors S1 and S3 can be made of materials with conductivity sufficiently lower than that of oxide semiconductor S2. Figure 21C In oxide semiconductors, the ratio of the number of atoms is represented by C, indicating the region with high insulation. Note that... Figure 21C The region C shown represents the ratio of the number of atoms in the range [In]:[M]:[Zn] = 0:1:0 or a value close to that.

[0383] In particular, when an oxide semiconductor having an atomic ratio represented by region A is used as oxide semiconductor S2, oxide semiconductors with [M] / [In] of 1 or more, preferably 2 or more, are preferably used as oxide semiconductors S1 and S3. Furthermore, as oxide semiconductor S3, an oxide semiconductor with [M] / ([Zn]+[In]) of 1 or more, which provides sufficiently high insulation, is preferably used.

[0384] <2-4. Structure of Oxide Semiconductors>

[0385] The structure of oxide semiconductors will be described below.

[0386] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0387] From another perspective, oxide semiconductors are divided into amorphous oxide semiconductors and crystalline oxide semiconductors. Crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS, among others.

[0388] Generally speaking, amorphous structures have the following characteristics: they are isotropic but not inhomogeneous; they are in a metastable state and the atomic configuration is not fixed; bond angles are not fixed; they have short-range order but not long-range order; etc.

[0389] That is, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Furthermore, an oxide semiconductor that does not possess isotropy (e.g., has a periodic structure in a small region) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic but is an unstable structure with voids. In this instability, a-like OS is physically close to amorphous oxide semiconductors.

[0390] CAAC-OS

[0391] First, let's explain CAAC-OS.

[0392] CAAC-OS is one of the oxide semiconductors that contains multiple c-axis oriented crystalline regions (also known as particles).

[0393] This section describes the analysis of CAAC-OS using X-ray diffraction (XRD). For example, when analyzing the structure of CAAC-OS containing InGaZnO4 crystals classified as space group R-3m using the out-of-plane method, such as… Figure 24A As shown, a peak appears near a diffraction angle (2θ) of 31°. Since this peak originates from the (009) plane of the InGaZnO4 crystal, it confirms that the crystals in CAAC-OS have a c-axis orientation, and the c-axis is oriented approximately perpendicular to the plane (also called the formed plane) or top surface of the CAAC-OS film. Note that, in addition to the peak near 2θ 31°, a peak sometimes also appears near 2θ 36°. The peak near 2θ 36° is due to the crystal structure classified as space group Fd-3m. Therefore, it is preferable that this peak does not appear in CAAC-OS.

[0394] On the other hand, when analyzing the structure of CAAC-OS using the in-plane method, where X-rays are incident on the sample from a direction parallel to the formed surface, a peak appears near 2θ at 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. Furthermore, even when the 2θ is fixed at around 56° and the sample is rotated about the normal vector of the sample surface (φ axis) for analysis (φ scan), the peak remains the same. Figure 24B As shown, no clear peak was observed. On the other hand, when performing a φ scan on single-crystal InGaZnO4 with 2θ fixed at around 56°, as... Figure 24C As shown, six peaks originating from the crystal plane equivalent to (110) were observed. Therefore, structural analysis using XRD confirmed that the orientations of the a-axis and b-axis in CAAC-OS are irregular.

[0395] Next, the analysis of CAAC-OS using electron diffraction will be explained. For example, when an electron beam with a diameter of 300 nm is incident on CAAC-OS containing InGaZnO4 crystals in a direction parallel to the formed surface of CAAC-OS, it is possible to observe... Figure 24D The diffraction pattern shown is also known as a selected area electron diffraction pattern. This diffraction pattern contains spots originating from the (009) plane of InGaZnO4 crystallization. Therefore, electron diffraction also shows that the particles contained in CAAC-OS have a c-axis orientation, and the c-axis is oriented approximately perpendicular to the formed surface or top surface. On the other hand, Figure 24E The diffraction pattern is shown when an electron beam with a diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample plane. From Figure 24EA ring-shaped diffraction pattern was observed. Therefore, electron diffraction using an electron beam with a diameter of 300 nm also showed that the a-axis and b-axis of the particles contained in CAAC-OS are not oriented. It can be considered that... Figure 24E The first ring in the crystal originates from the (010) and (100) planes of InGaZnO4 crystals. Furthermore, it can be considered that... Figure 24E The second ring in the middle is caused by (110) surface, etc.

[0396] Furthermore, in the composite analysis image of the bright-field image and diffraction pattern of CAAC-OS obtained by observation using transmission electron microscopy (TEM) (also known as a high-resolution TEM image), multiple particles can be observed. However, even in high-resolution TEM images, clear boundaries between particles, i.e., grain boundaries, are sometimes not observed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility caused by grain boundaries is not easily observed.

[0397] Figure 25A This shows a high-resolution TEM image of a cross-section of the CAAC-OS as viewed from a direction approximately parallel to the sample plane. The observation of the high-resolution TEM image was performed using the Spherical Aberration Corrector (SAC) function. High-resolution TEM images acquired using the SAC function are specifically referred to as Cs-corrected high-resolution TEM images. For example, Cs-corrected high-resolution TEM images can be observed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by NJE Ltd.

[0398] from Figure 25A It can be confirmed that the metal atoms are arranged in a layered structure within the particles. Furthermore, the size of each particle is known to be greater than 1 nm or 3 nm. Therefore, these particles can also be referred to as nanocrystals (nc). Alternatively, CAAC-OS can be called an oxide semiconductor with CANC (C-Axis Aligned nanocrystals). The particles reflect the unevenness of the formed surface or top surface of the CAAC-OS film and are parallel to the formed surface or top surface of the CAAC-OS.

[0399] in addition, Figure 25B and Figure 25C This shows a Cs-corrected high-resolution TEM image of the CAAC-OS plane, obtained from a direction approximately perpendicular to the sample surface. Figure 25D and Figure 25E Through the Figure 25B and Figure 25CThe image obtained after image processing. The image processing method is explained below. First, by... Figure 25B A Fast Fourier Transform (FFT) was performed to obtain the FFT image. Then, the image was processed to retain the area 2.8 nm from the origin. -1 Up to 5.0nm -1 The image is masked in a range-bound manner. Next, the masked FFT image is subjected to an Inverse Fast Fourier Transform (IFFT) to obtain the processed image. This obtained image is called the FFT-filtered image. The FFT-filtered image is the image from which the periodic components are extracted from a Cs-corrected high-resolution TEM image, revealing the lattice arrangement.

[0400] exist Figure 25D In the diagram, dashed lines indicate the areas where the crystal lattice arrangement is disrupted. The region surrounded by the dashed lines represents a particle. Furthermore, the dashed lines show the connections between particles. The dashed lines are hexagonal, indicating that the particles are hexagonal. Note that the shape of the particles is not limited to regular hexagons; many are not.

[0401] exist Figure 25E In the diagram, dashed lines indicate the regions between areas with consistent lattice arrangement and those with consistent lattice arrangement. Clear grain boundaries cannot be identified near the dotted lines. When lattice points surrounding the dotted lines are connected, distorted hexagons, pentagons, and / or heptagons can be formed. That is, it can be seen that grain boundary formation can be suppressed by distorting the lattice arrangement. This may be because CAAC-OS can tolerate distortions caused by factors such as low atomic density in the ab-plane direction or changes in interatomic bonding distance due to metal element substitution.

[0402] As shown above, CAAC-OS exhibits c-axis orientation, with multiple particles (nanocrysts) linked along the ab-plane direction, resulting in a distorted crystal structure. Therefore, CAAC-OS can also be referred to as CAA crystal (c-axis-aligned ab-plane-anchored crystal).

[0403] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors can sometimes be reduced due to the introduction of impurities or the formation of defects. Therefore, it can be said that CAAC-OS is an oxide semiconductor with few impurities or defects (such as oxygen defects).

[0404] Furthermore, impurities refer to elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. For example, elements like silicon, which have a stronger bonding force with oxygen than the metal elements constituting the oxide semiconductor, can strip oxygen from the oxide semiconductor, thereby disrupting the atomic arrangement and leading to decreased crystallinity. Additionally, heavy metals such as iron or nickel, argon, and carbon dioxide have large atomic radii (or molecular radii), which can also disrupt the atomic arrangement of oxide semiconductors, resulting in decreased crystallinity.

[0405] nc-OS

[0406] Next, nc-OS will be explained.

[0407] This section describes the analysis of nc-OS using an XRD apparatus. For example, when analyzing the structure of nc-OS using the out-of-plane method, no peaks indicating orientation appear. In other words, the crystals of nc-OS do not exhibit orientation.

[0408] Additionally, for example, when an nc-OS sheet containing InGaZnO4 crystals is thinned and an electron beam with a diameter of 50 nm is incident on a region with a thickness of 34 nm in a direction parallel to the surface to be formed, the following observations are made: Figure 26A The ring-shaped diffraction pattern shown is a nanobeam electron diffraction pattern. Additionally, Figure 26B This shows the diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a diameter of 1 nm is incident on the same sample. From Figure 26B Multiple spots were observed within the annular region. Therefore, no order was observed in nc-OS with an incident electron beam diameter of 50 nm, but order was confirmed with an incident electron beam diameter of 1 nm.

[0409] Furthermore, when an electron beam with a diameter of 1 nm is incident on a region with a thickness of less than 10 nm, such as Figure 26C As shown, sometimes the spots are observed to be configured as quasi-hexagonal electron diffraction patterns. This indicates that nc-OS contains highly ordered regions, i.e., crystalline structures, within a thickness range of less than 10 nm. Note that because the crystals are oriented in various directions, there are also regions where regular electron diffraction patterns are not observed.

[0410] Figure 26DCs-corrected high-resolution TEM images of nc-OS sections viewed from a direction approximately parallel to the formed surface are shown. In the high-resolution TEM images of nc-OS, there are regions where crystalline regions are observed, as indicated by the auxiliary lines, and regions where crystalline regions are not clearly observed. The crystalline regions contained in nc-OS have a size of 1 nm or more and 10 nm or less, especially mostly 1 nm or more and 3 nm or less. Note that oxide semiconductors with crystalline regions larger than 10 nm but less than 100 nm are sometimes referred to as microcrystalline oxide semiconductors. For example, grain boundaries are sometimes not clearly observed in high-resolution TEM images of nc-OS. Note that the origin of nanocrystals may be the same as that of particles in CAAC-OS. Therefore, the crystalline regions of nc-OS are sometimes referred to as particles below.

[0411] Thus, in nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, especially above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different particles in nc-OS. Therefore, no orientation is observed in the overall film. Consequently, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0412] In addition, since there is no regularity in the crystallization orientation between particles (nanocrystals), nc-OS can also be called an oxide semiconductor containing RANC (Random Aligned nanocrystals) or an oxide semiconductor containing NANC (Non-Aligned nanocrystals).

[0413] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, the defect state density of nc-OS is lower than that of a-like OS or amorphous oxide semiconductors. However, no regularity in crystal orientation is observed between different particles in nc-OS. Therefore, the defect state density of nc-OS is higher than that of CAAC-OS.

[0414] a-like OS

[0415] a-like OS is an oxide semiconductor with a structure between nc-OS and amorphous oxide semiconductor.

[0416] Figure 27 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, Figure 27A A high-resolution cross-sectional TEM image of the a-like OS at the onset of electron irradiation is shown. Figure 27B The irradiation level is shown as 4.3 10. 8 e - / nm 2 electrons (e - High-resolution cross-sectional TEM images of a-like OS following this. Figure 27A and Figure 27B It is observed that a-like OS exhibits strip-shaped bright regions extending in the longitudinal direction from the onset of electron irradiation. Furthermore, the shape of these bright regions changes after electron irradiation. These bright regions are estimated to be voids or low-density areas.

[0417] Because a-like OS contains voids, its structure is unstable. To demonstrate that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, the structural changes caused by electron irradiation are shown below.

[0418] As samples, a-like OS, nc-OS, and CAAC-OS were prepared. Each sample was an In-Ga-Zn oxide.

[0419] First, high-resolution cross-sectional TEM images of each sample were obtained. The high-resolution cross-sectional TEM images show that each sample has a crystalline structure.

[0420] It is known that the unit lattice of InGaZnO4 crystals has a structure consisting of nine layers—three In-O layers and six Ga-Zn-O layers—stacked in a layered manner along the c-axis. The spacing between these closely spaced layers is almost equal to the lattice surface spacing (also known as the d-value) of the (009) plane, which is determined to be 0.29 nm by crystal structure analysis. Therefore, the portion with lattice fringe spacing greater than 0.28 nm and less than 0.30 nm can be considered as the InGaZnO4 crystalline region. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0421] Figure 28 Examples are shown where the average size of the crystalline regions (at locations 22 to 30) of each sample was investigated. Note that the crystalline region size corresponds to the length of the lattice fringes described above. Figure 28 It can be seen that in a-like OS, the crystalline region gradually increases based on the cumulative irradiation of electrons obtained from TEM images, etc. From Figure 28 It can be seen that, in the initial observation using TEM, the crystal portion (also known as the initial crystal nucleus) with a size of about 1.2 nm is affected by electrons (e - The cumulative radiation dose was 4.2 × 10⁻⁶. 8 e - / nm 2The growth rate reached approximately 1.9 nm. On the other hand, it was found that the cumulative electron irradiation dose for both nc-OS and CAAC-OS from the start of electron irradiation to the present was 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, the size of the crystallized portion remained unchanged. Figure 28 It was found that, regardless of the cumulative electron irradiation, the crystal size of nc-OS and CAAC-OS was approximately 1.3 nm and 1.8 nm, respectively. Furthermore, electron beam irradiation and TEM observations were performed using a Hitachi H-9000NAR transmission electron microscope. The electron beam irradiation conditions were an accelerating voltage of 300 kV and a current density of 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s); the diameter of the irradiated area is 230nm.

[0422] Thus, electron irradiation can sometimes induce the growth of crystalline regions in a-like OS. On the other hand, electron irradiation almost never induces the growth of crystalline regions in nc-OS and CAAC-OS. In other words, a-like OS has an unstable structure compared to CAAC-OS and nc-OS.

[0423] Furthermore, because a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is more than 78.6% and less than 92.3% of that of a single crystal with the same composition. The densities of nc-OS and CAAC-OS are more than 92.3% and less than 100% of those of a single crystal with the same composition. Note that it is difficult to form oxide semiconductors with densities lower than 78% of the density of a single crystal.

[0424] For example, in oxide semiconductors satisfying the In:Ga:Zn ratio of 1:1:1 [atomic number ratio], the density of a single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm³. 3 Therefore, for example, in an oxide semiconductor satisfying the In:Ga:Zn ratio of 1:1:1 [atomic number ratio], the density of a-like OS is 5.0 g / cm³. 3 Above and below 5.9 g / cm 3 Additionally, for example, in oxide semiconductors satisfying the In:Ga:Zn ratio of 1:1:1 [atomic number ratio], the densities of nc-OS and CAAC-OS are 5.9 g / cm³. 3 Above and below 6.3 g / cm 3 .

[0425] Note that when no single crystals with identical compositions exist, the density of a single crystal with the desired composition can be estimated by combining different single crystals in arbitrary proportions. The density of a single crystal with the desired composition can then be estimated using a weighted average based on the proportions of the different single crystal combinations. It is preferable to minimize the number of different types of single crystals used in the density estimation.

[0426] As described above, oxide semiconductors have various structures and properties. Note that oxide semiconductors can be, for example, stacked films of two or more types, including amorphous oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0427] <2-5. Carrier Density of Oxide Semiconductors>

[0428] The carrier density of oxide semiconductors will be explained below.

[0429] Factors that affect the carrier density of oxide semiconductors include oxygen vacancies (Vo) or impurities in oxide semiconductors.

[0430] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen bonds to these vacancies (this state can also be called VoH), thus increasing the defect state density. Alternatively, when the number of impurities in the oxide semiconductor increases, the defect state density also increases due to the increase in impurities. Therefore, the carrier density of an oxide semiconductor can be controlled by controlling the defect state density.

[0431] The following describes transistors that use oxide semiconductors in the channel region.

[0432] When aiming to suppress negative drift of the threshold voltage of a transistor or reduce the off-state current of a transistor, it is preferable to reduce the carrier density of the oxide semiconductor. To reduce the carrier density of the oxide semiconductor, the impurity concentration in the oxide semiconductor can be reduced to decrease the defect state density. In this specification, a state with low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". The carrier density of a high-purity intrinsic oxide semiconductor is less than 8 × 10⁻⁶. 15 cm -3 Preferably less than 1×10 11 cm -3 More preferably, less than 1×10 10 cm -3 And it is 1×10 -9 cm -3 That's all.

[0433] On the other hand, when the goal is to increase the on-state current of the transistor or improve its field-effect mobility, it is preferable to increase the carrier density of the oxide semiconductor. To increase the carrier density of the oxide semiconductor, it is sufficient to slightly increase the impurity concentration or the defect state density. Alternatively, it is preferable to narrow the band gap of the oxide semiconductor. For example, within the range of conduction / cutoff ratios that yield the Id-Vg characteristics of the transistor, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher defect state density can be considered substantially intrinsic. Furthermore, an oxide semiconductor with a high electron affinity and a small band gap, resulting in increased thermally excited electron (carrier) density, can be considered substantially intrinsic. Additionally, when using an oxide semiconductor with a higher electron affinity, the threshold voltage of the transistor is lower.

[0434] The aforementioned oxide semiconductor with increased carrier density is slightly n-type. Therefore, the oxide semiconductor with increased carrier density can also be called "Slightly-n".

[0435] The carrier density of an intrinsic oxide semiconductor is preferably 1 × 10⁻⁶. 5 cm -3 Above and below 1×10 18 cm -3 Further preferred is 1×10 7 cm -3 Above and 1×10 17 cm -3 Hereinafter, 1×10 is further preferred. 9 cm -3 Above and 5×10 16 cm -3 Hereinafter, 1×10 is further preferred. 10 cm -3 Above and 1×10 16 cm -3 Hereinafter, 1×10 is further preferred. 11 cm -3 Above and 1×10 15 cm -3 the following.

[0436] The structure shown in this embodiment can be used in appropriate combinations with the structures shown in other embodiments or examples.

[0437] (Implementation Method 3)

[0438] In this embodiment, using Figures 29 to 35 The description includes an example of a transistor display device illustrated in the preceding embodiments.

[0439] Figure 29This is a top view showing an example of a display device. Figure 29 The display device 700 shown includes: a pixel portion 702 disposed on a first substrate 701; a source driving circuit portion 704 and a gate driving circuit portion 706 disposed on the first substrate 701; a sealant 712 disposed around the pixel portion 702, the source driving circuit portion 704, and the gate driving circuit portion 706; and a second substrate 705 disposed opposite to the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealant 712. That is, the pixel portion 702, the source driving circuit portion 704, and the gate driving circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Note that although in Figure 29 Although not shown in the figure, a display element is disposed between the first substrate 701 and the second substrate 705.

[0440] Furthermore, in the display device 700, an FPC terminal 708 (Flexible Printed Circuit) is provided in an area on the first substrate 701 not surrounded by the sealant 712. This FPC terminal 708 is electrically connected to the pixel unit 702, the source drive circuit unit 704, and the gate drive circuit unit 706, respectively. The FPC terminal 708 is connected to an FPC 716, and various signals are supplied to the pixel unit 702, the source drive circuit unit 704, and the gate drive circuit unit 706 via the FPC 716. Each of the pixel unit 702, the source drive circuit unit 704, the gate drive circuit unit 706, and the FPC terminal 708 is connected to a signal line 710. Various signals supplied by the FPC 716 are supplied to the pixel unit 702, the source drive circuit unit 704, the gate drive circuit unit 706, and the FPC terminal 708 via the signal lines 710.

[0441] Alternatively, multiple gate drive circuit sections 706 may be provided in the display device 700. Furthermore, while an example is shown where the source drive circuit section 704 and the gate drive circuit section 706 are formed on the same first substrate 701 as the pixel section 702, the display device 700 is not limited to this structure. For example, only the gate drive circuit section 706 may be formed on the first substrate 701, or only the source drive circuit section 704 may be formed on the first substrate 701. In this case, a structure in which a substrate on which the source drive circuit or gate drive circuit is formed (e.g., a drive circuit substrate formed from a single-crystal semiconductor film or a polycrystalline semiconductor film) is formed may also be used on the first substrate 701. Furthermore, there are no particular limitations on the connection method for the separately formed drive circuit substrate, and methods such as COG (Chip On Glass) and wire bonding can be used.

[0442] In addition, the pixel section 702, the source driving circuit section 704, and the gate driving circuit section 706 included in the display device 700 include a plurality of transistors, and the transistors of a semiconductor device according to one aspect of the present invention can be applied.

[0443] Furthermore, the display device 700 may include various components. Examples of such components include electroluminescent (EL) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (transistors that emit light according to current), electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, electrowetting elements, plasma display panels (PDPs), MEMS (microelectromechanical systems), displays (such as grating light valves (GLVs), digital micromirror devices (DMDs), digital micro shutter (DMS) elements, interferometric modulation (IMOD) elements, piezoelectric ceramic displays, etc.).

[0444] Furthermore, examples of display devices using EL elements include EL displays. Examples of display devices using electron emission elements include field emission displays (FEDs) or surface-conduction electron-emitter displays (SEDs). Examples of display devices using liquid crystal elements include liquid crystal displays (LCDs) (transmissive LCDs, semi-transmissive LCDs, reflective LCDs, intuitive LCDs, projected LCDs). Examples of display devices using electronic ink elements or electrophoretic elements include electronic paper. Note that when implementing semi-transmissive or reflective liquid crystal displays, part or all of the pixel electrodes function as reflective electrodes. For example, part or all of the pixel electrodes may contain aluminum, silver, etc. Furthermore, storage circuits such as SRAM can be placed under the reflective electrodes. This further reduces power consumption.

[0445] The display method of the display device 700 can be progressive scan or interlaced scan. Furthermore, the color elements controlled within pixels during color display are not limited to the three colors RGB (R for red, G for green, and B for blue). For example, it can be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, in a PenTile arrangement, a color element can be composed of two colors from RGB, and different two colors can be selected depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta can be added to RGB. Additionally, the display area size of each color element's pixel can be different. However, the disclosed invention is not limited to color display devices, but can also be applied to monochrome display devices.

[0446] In addition, to enable full-color display by using white light (W) for backlighting (organic EL elements, inorganic EL elements, LEDs, fluorescent lamps, etc.), a color layer (also called a filter) can be used. As a color layer, red (R), green (G), blue (B), yellow (Y), etc., can be appropriately combined. By using a color layer, color reproduction can be further improved compared to not using a color layer. At this time, it is also possible to set up areas including the color layer and areas not including the color layer, and directly use the white light from the areas not including the color layer for display. By partially setting up areas not including the color layer, during bright display, the brightness reduction caused by the color layer can sometimes be reduced, resulting in a power consumption reduction of about 20% to 30%. However, when using self-emissive elements such as organic or inorganic EL elements for full-color display, R, G, B, Y, and W can be emitted from elements having each luminous color. By using self-emissive elements, power consumption can sometimes be further reduced compared to using a color layer.

[0447] In addition, as a method of colorization, besides the method of converting a portion of the light emitted from the aforementioned white light into red, green, and blue through a color filter (color filter method), other methods can be used, such as using red, green, and blue light emitted separately (three-color method) and converting a portion of the light emitted from blue light into red or green (color conversion method or quantum dot method).

[0448] In this embodiment, using Figure 30 and Figure 32 Explain the structure of liquid crystal elements and EL elements used as display elements. Figure 30 It is along Figure 29 The cross-sectional view of the dotted-dash line QR shown illustrates the structure of a liquid crystal element used as a display element. Additionally, Figure 32 It is along Figure 29The cross-sectional view of the dotted-dash line QR shown is an EL element used as a display element.

[0449] Below, firstly, it is explained Figure 30 and Figure 32 The common parts are explained, followed by the different parts.

[0450] <3-1. Explanation of common parts of display devices>

[0451] Figure 30 and Figure 32 The display device 700 shown includes: a lead-in wiring section 711; a pixel section 702; a source drive circuit section 704; and an FPC terminal section 708. The lead-in wiring section 711 includes signal lines 710. The pixel section 702 includes a transistor 750 and a capacitor 790. The source drive circuit section 704 includes a transistor 752.

[0452] Transistors 750 and 752 have the same structure as transistor 100 described above. Transistors 750 and 752 may also have structures using other transistors as shown in the above embodiments.

[0453] The transistor used in this embodiment comprises a high-purity oxide semiconductor film in which the formation of oxygen defects is suppressed. This transistor can reduce off-state current. Therefore, the hold time of electrical signals such as image signals can be extended, and the write interval can also be extended in the powered-on state. Therefore, the refresh frequency can be reduced, thereby achieving the effect of suppressing power consumption.

[0454] Furthermore, the transistors used in this embodiment exhibit high field-effect mobility, enabling high-speed driving. For example, by using such high-speed driving transistors in a liquid crystal display device, both the switching transistors for the pixel section and the driving transistors for the driving circuit section can be formed on the same substrate. In other words, since a separate semiconductor device formed from silicon wafers or the like is not required for the driving circuit, the number of components in the semiconductor device can be reduced. Additionally, high-quality images can be provided in the pixel section by using high-speed driving transistors.

[0455] The capacitor 790 includes: a lower electrode formed by processing a conductive film identical to the conductive film used as the first gate electrode in the transistor 750; and an upper electrode formed by processing a conductive film identical to the conductive film used as the source and drain electrodes in the transistor 750. Furthermore, an insulating film formed by forming an insulating film identical to the insulating film used as the first gate insulating film in the transistor 750 is disposed between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film serving as a dielectric film is sandwiched between a pair of electrodes.

[0456] In addition, Figure 30 and Figure 32 In this process, a planarization insulating film 770 is provided on transistors 750, 752 and capacitor 790.

[0457] As the planarization insulating film 770, heat-resistant organic materials such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, and epoxy resin can be used. The planarization insulating film 770 can be formed by laminating multiple insulating films formed from these materials. Alternatively, a structure without the planarization insulating film 770 can also be used.

[0458] exist Figure 30 and Figure 32 The diagram shows a structure where the transistors 750 included in the pixel section 702 and the transistors 752 included in the source drive circuit section 704 use the same transistor structure, but this is not a limitation. For example, the pixel section 702 and the source drive circuit section 704 may use different transistors. Specifically, examples include a structure where the pixel section 702 uses an interleaved transistor and the source drive circuit section 704 uses an anti-interleaved transistor as shown in Embodiment 1, or a structure where the pixel section 702 uses an anti-interleaved transistor as shown in Embodiment 1 and the source drive circuit section 704 uses an interleaved transistor, etc. Furthermore, the source drive circuit section 704 may be replaced with a gate drive circuit section.

[0459] The signal line 710 and the conductive film used as the source and drain electrodes of transistors 750 and 752 are formed in the same process. For example, when the signal line 710 is formed using a material containing copper, the signal delay due to wiring resistance is less, thus enabling large-screen display.

[0460] Additionally, the FPC terminal portion 708 includes a connecting electrode 760, an anisotropic conductive film 780, and an FPC 716. The connecting electrode 760 and the conductive film used as the source and drain electrodes of transistors 750 and 752 are formed in the same process. Furthermore, the connecting electrode 760 and the terminals included in the FPC 716 are electrically connected through the anisotropic conductive film 780.

[0461] Alternatively, glass substrates can be used as the first substrate 701 and the second substrate 705. Alternatively, flexible substrates can be used as the first substrate 701 and the second substrate 705. Examples of such flexible substrates include plastic substrates.

[0462] Furthermore, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching the insulating film, used to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Alternatively, a spherical spacer may also be used as the structure 778.

[0463] Additionally, on one side of the second substrate 705, there is a light-shielding film 738 used as a black matrix, a coloring film 736 used as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the coloring film 736.

[0464] <3-2. Structural Examples of Display Devices Using Liquid Crystal Elements>

[0465] Figure 30 The display device 700 shown includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is disposed on one side of the second substrate 705 and serves as a counter electrode. Figure 30 The display device 700 shown can change the orientation state of the liquid crystal layer 776 by applying a voltage between the conductive film 772 and the conductive film 774, thereby controlling the transmission and non-transmission of light to display images.

[0466] The conductive film 772 is electrically connected to the conductive film of the transistor 750, which serves as both the source and drain electrodes. The conductive film 772 is formed on the planarized insulating film 770 and serves as a pixel electrode, i.e., an electrode of the display element. Furthermore, the conductive film 772 serves as a reflective electrode. Figure 30 The display device 700 shown is a so-called reflective color liquid crystal display device in which external light is reflected by a conductive film 772 and displayed through a color film 736.

[0467] As the conductive film 772, a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used. For example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used as the conductive film that is transparent to visible light. For example, a material containing aluminum or silver is preferably used as the conductive film that is reflective to visible light. In this embodiment, a conductive film that is reflective to visible light is used as the conductive film 772.

[0468] also, Figure 30 The diagram illustrates a structure in which the conductive film 772 is connected to a conductive film used as the drain electrode of the transistor 750, but is not limited thereto. For example, as... Figure 31As shown, a structure can also be adopted in which the conductive film 772 is electrically connected to the conductive film used as the drain electrode of the transistor 750 via the conductive film 777 used as the connecting electrode. Furthermore, since the conductive film 777 is formed by processing the same conductive film used as the second gate electrode of the transistor 750, the conductive film 777 can be formed without adding any manufacturing steps.

[0469] also, Figure 30 The display device 700 shown is a reflective color liquid crystal display device, but it is not limited to this. For example, a conductive film that is transparent to visible light can be used as the conductive film 772, thereby realizing a transmissive color liquid crystal display device. In addition, a so-called transmissive color liquid crystal display device that combines a reflective color liquid crystal display device and a transmissive color liquid crystal display device can be realized.

[0470] Here, Figure 33 An example of a transmissive color liquid crystal display device is shown. Figure 33 It is along Figure 29 The diagram shows a cross-sectional view of the dotted-dash line QR, and also illustrates the structure of a liquid crystal element used as a display element. Furthermore, Figure 33 The display device 700 shown is an example of a structure that uses a horizontal electric field method (e.g., FFS (Fringe Field Switching) mode) as the driving method for liquid crystal elements. Figure 33 In the structure shown, an insulating film 773 is disposed on the conductive film 772, which is used as a pixel electrode, and a conductive film 774 is disposed on the insulating film 773. At this time, the conductive film 774 functions as a common electrode, and the orientation state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773.

[0471] Note that, although in Figure 30 and Figure 33 Although not shown in the diagram, alignment films can also be provided on one or both of the conductive films 772 and 774 on the side that contacts the liquid crystal layer 776. Furthermore, although in Figure 30 and Figure 33 Although not illustrated, optical components (optical substrates) such as polarizing components, phase difference components, and anti-reflection components can be appropriately incorporated. For example, circular polarization utilizing polarizing and phase difference substrates can also be used. Furthermore, backlighting, sidelighting, etc., can also be used as light sources.

[0472] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, high-molecular-weight dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals can be used. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, and homogeneous phases, depending on the conditions.

[0473] Furthermore, when using a lateral electric field, liquid crystals exhibiting a blue phase can be used without an alignment film. The blue phase is a type of liquid crystal phase that appears just before the cholesteric liquid crystal transitions to a homogeneous phase when the temperature is raised. Because the blue phase only appears within a narrow temperature range, a liquid crystal composition containing several wt% or more chiral reagents is used in the liquid crystal layer to broaden the temperature range. Since liquid crystal compositions containing both the blue phase liquid crystal and the chiral reagent have a fast response speed and are optically isotropic, alignment processing is not required. Additionally, since no alignment film is needed, friction processing is eliminated, preventing electrostatic damage caused by friction processing and reducing defects and breakage in the manufacturing process of the liquid crystal display device. Furthermore, the blue phase liquid crystal material exhibits low viewing angle dependence.

[0474] In addition, when liquid crystal elements are used as display elements, the following modes can be used: TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS mode, ASM (Axially Symmetricaligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, and AFLC (Anti-Ferroelectric Liquid Crystal) mode.

[0475] Alternatively, normally black liquid crystal display devices can be used, such as transmissive liquid crystal display devices employing vertical alignment (VA) mode. Several examples of vertical alignment modes include MVA (Multi-Domain Vertical Alignment), PVA (Patterned Vertical Alignment), and ASV (Advanced Super View).

[0476] <3-3. Display devices using light-emitting elements>

[0477] Figure 32 The display device 700 shown includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788. Figure 32 The display device 700 shown can display images by emitting light from the EL layer 786 included in the light-emitting element 782. Furthermore, the EL layer 786 contains inorganic compounds such as organic compounds or quantum dots.

[0478] Examples of materials that can be used in organic compounds include fluorescent or phosphorescent materials. Furthermore, examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell quantum dot materials, and core-type quantum dot materials. Additionally, materials containing elements from Groups 12 and 16, 13 and 15, or 14 and 16 can also be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used.

[0479] exist Figure 32 In the display device 700 shown, an insulating film 730 is provided on the planarized insulating film 770 and the conductive film 772. The insulating film 730 covers a portion of the conductive film 772. The light-emitting element 782 adopts a top-emitting structure. Therefore, the conductive film 788 is transparent and allows light emitted by the EL layer 786 to pass through. Note that although a top-emitting structure is illustrated in this embodiment, it is not limited to this. For example, a bottom-emitting structure that emits light to one side of the conductive film 772 or a double-sided emitting structure that emits light to both one side of the conductive film 772 and one side of the conductive film 788 can also be applied.

[0480] Additionally, a coloring film 736 is provided at the position overlapping with the light-emitting element 782, and a light-shielding film 738 is provided at the position overlapping with the insulating film 730, in the winding wiring portion 711, and in the source drive circuit portion 704. The coloring film 736 and the light-shielding film 738 are covered by the insulating film 734. A sealing film 732 fills the space between the light-emitting element 782 and the insulating film 734. Note that although an example is shown... Figure 32 The display device 700 shown has a structure in which a color film 736 is provided, but it is not limited to this. For example, when the EL layer 786 is formed by separate coating, a structure in which the color film 736 is not provided may also be used.

[0481] <3-4. Examples of structures for setting up input / output devices in a display device>

[0482] Alternatively, it can also be done in Figure 32 and Figure 33The display device 700 shown is equipped with an input / output device. Examples of such an input / output device include a touch panel.

[0483] Figure 34 and Figure 35 Showing the Figure 32 and Figure 33 The display device 700 shown has a structure with a touch panel 791.

[0484] Figure 34 Is Figure 32 The diagram shows a cross-sectional view of the structure in which a touch panel 791 is provided in the display device 700. Figure 35 Is Figure 33 The diagram shows a cross-sectional view of the structure in which a touch panel 791 is provided in the display device 700.

[0485] First, the following explanation Figure 34 and Figure 35 The touch panel 791 shown.

[0486] Figure 34 and Figure 35 The touch panel 791 shown is a so-called In-Cell type touch panel disposed between the substrate 705 and the color film 736. The touch panel 791 can be formed on one side of the substrate 705 before the light-shielding film 738 and the color film 736 are formed.

[0487] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, when a detection object such as a finger or a stylus approaches, the change in mutual capacitance between the electrode 793 and the electrode 794 can be detected.

[0488] In addition, Figure 34 and Figure 35 The intersection of electrodes 793 and 794 is shown above the transistor 750. Electrode 796 is electrically connected to the two electrodes 793 that clamp electrode 794 through an opening provided in the insulating film 795. Furthermore, in Figure 34 and Figure 35 The diagram shows a structure in which the area where the electrode 796 is provided is located in the pixel section 702, but it is not limited to this. For example, it can also be formed in the source drive circuit section 704.

[0489] Electrodes 793 and 794 are disposed in the area overlapping with the light-shielding film 738. Furthermore, as... Figure 34 As shown, electrode 793 is preferably arranged in a manner that does not overlap with light-emitting element 782. Furthermore, as... Figure 35As shown, electrode 793 is preferably arranged in a manner that does not overlap with liquid crystal element 775. In other words, electrode 793 has an opening in the area where it overlaps with light-emitting element 782 and liquid crystal element 775. That is, electrode 793 has a grid shape. By adopting this structure, electrode 793 can have a structure that does not block the light emitted by light-emitting element 782. Alternatively, electrode 793 can also have a structure that does not block the light transmitted through liquid crystal element 775. Therefore, since the brightness reduction caused by the arrangement of touch panel 791 is minimal, a display device with high visibility and reduced power consumption can be realized. Furthermore, electrode 794 can also have the same structure.

[0490] Since electrodes 793 and 794 do not overlap with the light-emitting element 782, electrodes 793 and 794 can be made of a metal material with low transmittance of visible light. Alternatively, since electrodes 793 and 794 do not overlap with the liquid crystal element 775, electrodes 793 and 794 can be made of a metal material with low transmittance of visible light.

[0491] Therefore, compared with electrodes using oxide materials with high visible light transmittance, the resistance of electrodes 793 and 794 can be reduced, thereby improving the sensor sensitivity of the touch panel.

[0492] For example, conductive nanowires can also be used for electrodes 793, 794, and 796. The average diameter of these nanowires can be 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 5 nm or more and 25 nm or less. Furthermore, metal nanowires such as Ag nanowires, Cu nanowires, and Al nanowires, or carbon nanotubes, can be used as the aforementioned nanowires. For example, when Ag nanowires are used as any one or all of electrodes 793, 794, and 796, a visible light transmittance of 89% or more and a sheet resistance of 40 Ω / square or more and 100 Ω / square or less can be achieved.

[0493] Although Figure 34 and Figure 35 The structure of an In-Cell type touch panel is shown, but it is not limited to this. For example, a so-called On-Cell type touch panel formed on the display device 700 or a so-called Out-Cell type touch panel attached to the display device 700 may also be used.

[0494] Thus, a display device according to one aspect of the present invention can be used in combination with various types of touch panels.

[0495] The structure shown in this embodiment can be implemented by appropriately combining it with the structures shown in other embodiments.

[0496] (Implementation Method 4)

[0497] In this embodiment, a display device including a semiconductor device according to one aspect of the present invention will be described with reference to FIG36.

[0498] <4. Circuit Structure of Display Device>

[0499] Figure 36A The display device shown includes: a region having pixels with display elements (hereinafter referred to as pixel section 502); a circuit section (hereinafter referred to as driving circuit section 504) disposed outside the pixel section 502 and having circuitry for driving the pixels; a circuitry having the function of a protection element (hereinafter referred to as protection circuitry 506); and a terminal section 507. Alternatively, the protection circuitry 506 may not be provided.

[0500] Part or all of the drive circuit section 504 is preferably formed on the same substrate as the pixel section 502. This reduces the number of components and terminals. When part or all of the drive circuit section 504 is not formed on the same substrate as the pixel section 502, part or all of the drive circuit section 504 can be mounted by COG or TAB (Tape Automated Bonding).

[0501] The pixel unit 502 includes a circuit (hereinafter referred to as pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driving circuit unit 504 includes a circuit (hereinafter referred to as gate driver 504a) for outputting a signal (scan signal) for selecting a pixel and a circuit (hereinafter referred to as source driver 504b) for supplying a signal (data signal) for driving the display elements in the pixel.

[0502] The gate driver 504a includes a shift register, etc. The gate driver 504a receives signals for driving the shift register via terminal 507 and outputs signals. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has the function of controlling the potential of the wiring supplied with scan signals (hereinafter referred to as scan lines GL_1 to GL_X). Alternatively, multiple gate drivers 504a can be provided, and each of the multiple gate drivers 504a can individually control scan lines GL_1 to GL_X. Alternatively, the gate driver 504a can have the function of supplying an initialization signal. However, it is not limited to this; the gate driver 504a can also supply other signals.

[0503] The source driver 504b includes a shift register, etc. The source driver 504b receives signals for driving the shift register and signals from which data signals (image signals) are derived via terminal section 507. The source driver 504b has the function of generating data signals to be written to the pixel circuit 501 based on the image signals. Furthermore, the source driver 504b has the function of controlling the output of the data signals according to pulse signals generated by inputs such as start pulse signals and clock signals. Additionally, the source driver 504b has the function of controlling the potential of the wiring to which the data signals are supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b can supply an initialization signal. However, it is not limited to this; the source driver 504b can supply other signals.

[0504] The source driver 504b can be configured using, for example, multiple analog switches. By sequentially turning on multiple analog switches, the source driver 504b can output a signal obtained by time-dividing an image signal as a data signal. Alternatively, the source driver 504b can also be configured using a shift register or the like.

[0505] Pulse signals and data signals are input to each of the plurality of pixel circuits 501 via one of the plurality of scan lines GL supplied with scan signals and one of the plurality of data lines DL supplied with data signals, respectively. Furthermore, gate driver 504a controls the writing and holding of data signals in each of the plurality of pixel circuits 501. For example, a pulse signal is input from gate driver 504a to the pixel circuit 501 in the m-th row and n-th column via scan line GL_m (m is a natural number less than or equal to X), and a data signal is input from source driver 504b to the pixel circuit 501 in the m-th row and n-th column via data line DL_n (n is a natural number less than or equal to Y) according to the potential of scan line GL_m.

[0506] Figure 36A The protection circuit 506 shown is connected, for example, to the scan line GL, which is the wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 may be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 may be connected to the wiring between the source driver 504b and the terminal portion 507. Furthermore, the terminal portion 507 refers to the portion provided with terminals for inputting power, control signals, and image signals to the display device from external circuitry.

[0507] The protection circuit 506 is a circuit that makes the wiring connected to it conductive with other wiring when a potential outside a certain range is supplied to the wiring connected to it.

[0508] like Figure 36A As shown, by providing a protection circuit 506 to the pixel section 502 and the driving circuit section 504, the display device's tolerance to overcurrent caused by ESD (Electro Static Discharge) and the like can be improved. However, the structure of the protection circuit 506 is not limited to this. For example, a structure in which the gate driver 504a is connected to the protection circuit 506 or a structure in which the source driver 504b is connected to the protection circuit 506 may also be used. Alternatively, a structure in which the terminal section 507 is connected to the protection circuit 506 may also be used.

[0509] In addition, although Figure 36A The diagram shows an example of a drive circuit section 504 formed by a gate driver 504a and a source driver 504b, but it is not limited to this structure. For example, only the gate driver 504a may be formed and a separately prepared substrate for forming the active drive circuit may be mounted (e.g., a drive circuit substrate formed of a single-crystal semiconductor film or a polycrystalline semiconductor film).

[0510] in addition, Figure 36A The multiple pixel circuits 501 shown can, for example, employ... Figure 36B The structure shown.

[0511] Figure 36B The pixel circuit 501 shown includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor shown in the previous embodiment can be used for transistor 550.

[0512] The potential of one of the pairs of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written. Furthermore, a common potential can be supplied to one of the pairs of electrodes of the liquid crystal element 570 in each of the plurality of pixel circuits 501. Additionally, different potentials can be supplied to one of the pairs of electrodes of the liquid crystal element 570 in each row of pixel circuits 501.

[0513] For example, the driving method for a display device including the liquid crystal element 570 can also use the following modes: TN mode; STN mode; VA mode; ASM (Axially Symmetric Aligned Micro-cell) mode; OCB (Optically Compensated Birefringence) mode; FLC (Ferroelectric Liquid Crystal) mode; AFLC (Anti-Ferroelectric Liquid Crystal) mode; MVA mode; PVA (Patterned Vertical Alignment) mode; IPS mode; FFS mode; or TBA (Transverse Bend Alignment) mode, etc. In addition to the above driving methods, other driving methods for the display device include ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and guest-host mode, etc. However, it is not limited to this; various liquid crystal elements and their driving methods can be used.

[0514] In the pixel circuit 501 at row m and column n, one of the source and drain electrodes of transistor 550 is electrically connected to the data line DL_n, and the other of the source and drain electrodes is electrically connected to the other electrode of a pair of electrodes in the liquid crystal element 570. The gate electrode of transistor 550 is electrically connected to the scan line GL_m. Transistor 550 has the function of controlling the writing of data signals.

[0515] One electrode of the pair of electrodes of capacitor 560 is electrically connected to the wiring supplied with the potential (hereinafter referred to as the potential supply line VL), and the other electrode is electrically connected to the other electrode of the pair of electrodes of liquid crystal element 570. Furthermore, the potential of the potential supply line VL is appropriately set according to the specifications of pixel circuit 501. Capacitor 560 functions as a storage capacitor for storing written data.

[0516] For example, in including Figure 36B In the display device shown by pixel circuit 501, through Figure 36A The gate driver 504a shown sequentially selects the pixel circuits 501 of each row and turns on the transistors 550 to write data signals.

[0517] When transistor 550 is turned off, the pixel circuit 501, on which data is being written, remains in a held state. By performing the above steps row by row, an image can be displayed.

[0518] Figure 36A The multiple pixel circuits 501 shown can, for example, employ... Figure 36C The structure shown.

[0519] Figure 36C The pixel circuit 501 shown includes transistors 552 and 554, capacitor 562, and light-emitting element 572. The transistors shown in the previous embodiments can be used in one or both of transistors 552 and 554.

[0520] One of the source and drain electrodes of transistor 552 is electrically connected to the wiring for which a data signal is supplied (hereinafter referred to as signal line DL_n). Furthermore, the gate electrode of transistor 552 is electrically connected to the wiring for which a gate signal is supplied (hereinafter referred to as scan line GL_m).

[0521] Transistor 552 has the function of controlling the writing of data signals.

[0522] One of the electrodes of capacitor 562 is electrically connected to the wiring supplied with potential (hereinafter referred to as potential supply line VL_a), and the other electrode is electrically connected to the other of the source and drain electrodes of transistor 552.

[0523] Capacitor 562 has the function of a storage capacitor for storing the data that has been written.

[0524] One of the source and drain electrodes of transistor 554 is electrically connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the other of the source and drain electrodes of transistor 552.

[0525] One of the anode and cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source and drain electrodes of the transistor 554.

[0526] As the light-emitting element 572, for example, an organic electroluminescent element (also known as an organic EL element) can be used. Note that the light-emitting element 572 is not limited to this, and an inorganic EL element made of inorganic materials can also be used.

[0527] In addition, one of the potential supply lines VL_a and VL_b is supplied with a high power supply potential VDD, and the other is supplied with a low power supply potential VSS.

[0528] For example, in including Figure 36C In the display device with pixel circuit 501, through Figure 36A The gate driver 504a shown sequentially selects the pixel circuits 501 of each row and turns on the transistors 552 to write the data signal.

[0529] When transistor 552 is turned off, the pixel circuit 501, on which data is being written, remains in a held state. Furthermore, the amount of current flowing between the source and drain electrodes of transistor 554 is controlled according to the potential of the written data signal, and the light-emitting element 572 emits light with a brightness corresponding to the amount of current flowing through it. By performing the above steps line by line, an image can be displayed.

[0530] The structure shown in this embodiment can be implemented by appropriately combining it with the structures shown in other embodiments.

[0531] (Implementation Method 5)

[0532] In this embodiment, examples of the transistor circuit structure described in the above embodiments will be described with reference to FIGS. 37 to 40.

[0533] Note that in this embodiment, the oxide semiconductor transistor described in the above embodiment will be referred to as an OS transistor.

[0534] <5. Example of an inverter circuit structure>

[0535] Figure 37A This diagram shows an inverter applicable to shift registers and buffers included in a drive circuit. Inverter 800 outputs a signal whose logic is inverted at input terminal IN to output terminal OUT. Inverter 800 includes multiple OS transistors. Signal S BG It is a signal that can switch the electrical characteristics of the OS transistor.

[0536] Figure 37B This is an example of an inverter 800. Inverter 800 includes OS transistors 810 and 820. Inverter 800 can use only n-channel transistors, so it can be manufactured at a lower cost compared to inverters manufactured using CMOS (Complementary Metal Oxide Semiconductor).

[0537] Alternatively, the inverter 800, including the OS transistor, can also be placed on the CMOS circuit composed of Si transistors. Because the inverter 800 can be configured to overlap with the CMOS circuit, the increase in circuit area caused by adding the inverter 800 can be suppressed.

[0538] OS transistors 810 and 820 include a first gate used as a front gate, a second gate used as a back gate, a first terminal used as one of the source and drain, and a second terminal used as the other of the source and drain.

[0539] The first gate of OS transistor 810 is connected to the second terminal of OS transistor 810. The second gate of OS transistor 810 is connected to the supply signal S. BG The wiring connections are as follows: The first terminal of the OS transistor 810 is connected to the supply voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.

[0540] The first gate of OS transistor 820 is connected to the input terminal IN. The second gate of OS transistor 820 is connected to the input terminal IN. The first terminal of OS transistor 820 is connected to the output terminal OUT. The second terminal of OS transistor 820 is connected to the wiring for the supply voltage VSS.

[0541] Figure 37C This is a timing diagram used to illustrate the operation of inverter 800. Figure 37C The timing diagram shows the signal waveforms at the input terminal IN, the output terminal OUT, and the signal S. BG The signal waveform and the change in the threshold voltage of the OS transistor 810.

[0542] By signal S BG The threshold voltage of the OS transistor 810 can be controlled by applying a second gate to the OS transistor 810.

[0543] Signal S BG It has a voltage V used to shift the threshold voltage in the negative direction. BG_A And the voltage V used to shift the threshold voltage in the positive direction BG_B By applying a voltage V to the second gate BG_A This can cause the threshold voltage of the OS transistor 810 to drift negatively, becoming the threshold voltage V. TH_A Additionally, by applying a voltage V to the second gate... BG_B This can cause the threshold voltage of the OS transistor 810 to drift in the positive direction, thus becoming the threshold voltage V. TH_B .

[0544] To make the above explanation visual, Figure 38A The Id-Vg curve shows one of the electrical characteristics of a transistor.

[0545] By increasing the voltage of the second gate to voltage V BG_A The curves showing the electrical characteristics of the aforementioned OS transistor 810 can be plotted to... Figure 38AThe curve drift is represented by the dashed line 840. Additionally, by reducing the voltage of the second gate to voltage V... BG_B The curves showing the electrical characteristics of the aforementioned OS transistor 810 can be plotted to... Figure 38A The curve drift, represented by the solid line 841, is shown in the figure. This is achieved by using signal S... BG Switch to voltage V BG_A or voltage V BG_B ,like Figure 38A As shown, the threshold voltage of the OS transistor 810 can be shifted in the positive or negative direction.

[0546] The threshold voltage V is obtained by shifting the threshold voltage in the positive direction. TH_B This can put the OS transistor 810 in a state where current does not easily flow. Figure 38B Visually represent the current state.

[0547] like Figure 38B As shown, the current I flowing through the OS transistor 810 can be... B Extremely small. Therefore, when the signal applied to the input terminal IN is high and the OS transistor 820 is turned on, the voltage at the output terminal OUT can be drastically reduced.

[0548] like Figure 38B As shown, the OS transistor 810 can be placed in a state where current does not easily flow, so it can... Figure 37C The timing diagram shown causes a sharp change in the signal waveform 831 at the output terminal. Because the current flowing between the wiring for the supply voltage VDD and the wiring for the supply voltage VSS can be reduced, it can operate with low power consumption.

[0549] Additionally, the threshold voltage V is obtained by shifting the threshold voltage in the negative direction. TH_A This allows the OS transistor 810 to be in a state where current can flow easily. Figure 38C Visually represent the current state. For example... Figure 38C As shown, the current I flowing at this time can be... A Set to be at least greater than current I B The value of . Therefore, when the signal applied to the input terminal IN is low and the OS transistor 820 is in the off state (OFF), the voltage at the output terminal OUT can be increased sharply. For example Figure 38C As shown, the OS transistor 810 can be placed in a state where current can easily flow, so it can... Figure 37C The timing diagram shown causes a sharp change in the signal waveform 832 at the output terminal.

[0550] Note that signal S BGThe control of the threshold voltage of OS transistor 810 is preferably performed before switching the state of OS transistor 820, i.e., before times T1 and T2. For example, as Figure 37C As shown, preferably, the threshold voltage of the OS transistor 810 is changed from the threshold voltage V before the moment T1 when the signal applied to the input terminal IN is switched to a high level. TH_A Switch to threshold voltage V TH_B Additionally, such as Figure 37C As shown, preferably, the threshold voltage of the OS transistor 810 is reduced from the threshold voltage V before the moment T2 when the signal applied to the input terminal IN is switched to a low level. TH_B Switch to threshold voltage V TH_A .

[0551] Note that, although Figure 37C The timing diagram shows the switching signal S based on the signal applied to the input terminal IN. BG While the structure is correct, other structures can also be used. For example, a structure can be used that maintains the second gate of the floating OS transistor 810 at a voltage used to control the threshold voltage. Figure 39A An example of a circuit structure that can implement this structure is shown.

[0552] exist Figure 39A In addition to Figure 37B In addition to the circuit structure shown, an OS transistor 850 is also included. The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to the supply voltage V. BG_B (or voltage V) BG_A The wiring connection of the OS transistor 850. The first gate of the OS transistor 850 is connected to the supply signal S. F The wiring connection. The second gate of the OS transistor 850 is connected to the supply voltage V. BG_B (or voltage V) BG_A Wiring connections.

[0553] Reference Figure 39B The timing diagram Figure 39A The work will be explained.

[0554] Before the signal applied to the input terminal IN is switched to a high level at time T3, the threshold voltage used to control the OS transistor 810 is applied to the second gate of the OS transistor 810. The signal S... F The OS transistor 850 is set to high level and turned on, affecting node N. BG Apply a voltage V to control the threshold voltage. BG_B .

[0555] At node N BG Become voltage V BG_BNext, the OS transistor 850 is turned off. Because the off-state current of the OS transistor 850 is extremely small, keeping it off maintains the stability of node N. BG The maintained threshold voltage V BG_B Therefore, a voltage V is applied to the second gate of the OS transistor 850. BG_B The number of operations is reduced, so the rewrite voltage V can be reduced. BG_B The required power consumption.

[0556] Note that, although in Figure 37B and Figure 39A The circuit structure shown depicts a configuration where a voltage is applied to the second gate of the OS transistor 810 via external control; however, other configurations are also possible. For example, a configuration could be used where a voltage is generated based on a signal applied to the input terminal IN to control a threshold voltage, which is then applied to the second gate of the OS transistor 810. Figure 40A An example of a circuit structure that can implement this structure is shown.

[0557] Figure 40A Shown in Figure 37B The circuit structure shown includes a CMOS inverter 860 between the input terminal IN and the second gate of the OS transistor 810. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.

[0558] Reference Figure 40B The timing diagram Figure 40A The work will be explained. Figure 40B The timing diagram shows the signal waveforms at the input terminal IN, the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the change in the threshold voltage of the OS transistor 810.

[0559] The output waveform IN_B, which is the logical inversion of the signal applied to the input terminal IN, can be used as a signal to control the threshold voltage of the OS transistor 810. Therefore, as... Figures 38A to 38C As explained, the threshold voltage of the OS transistor 810 can be controlled. For example, in Figure 40B At time T4, the signal applied to the input terminal IN is high, and the OS transistor 820 is turned on. At this time, the output waveform IN_B is low. Therefore, the OS transistor 810 can be placed in a state where current does not flow easily, thus drastically reducing the voltage rise at the output terminal OUT.

[0560] In addition, Figure 40BAt time T5, the signal applied to the input terminal IN is low, and the OS transistor 820 is off. At this time, the output waveform IN_B is high. Therefore, the OS transistor 810 can be placed in a state where current can easily flow, thus drastically increasing the voltage at the output terminal OUT.

[0561] As described above, in this embodiment, the voltage of the back gate of the inverter, including the OS transistor, is switched according to the logic of the signal at the input terminal IN. By employing this structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor according to the signal applied to the input terminal IN, the voltage at the output terminal OUT can be drastically changed. Furthermore, the through current between the power supply wirings can be reduced. Therefore, low power consumption can be achieved.

[0562] The structure shown in this embodiment can be implemented by appropriately combining it with the structures shown in other embodiments.

[0563] (Implementation Method 6)

[0564] In this embodiment, an example of a semiconductor device will be described with reference to FIGS. 41 to 44: a semiconductor device in which an oxide semiconductor transistor (OS transistor) described in the above embodiment is used in multiple circuits.

[0565] <6. Examples of Circuit Structures for Semiconductor Devices>

[0566] Figure 41A This is a block diagram of a semiconductor device 900. The semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generation circuit 903, a circuit 904, a voltage generation circuit 905, and a circuit 906.

[0567] The power supply circuit 901 generates the reference voltage V. ORG The circuit. Voltage V ORG It can also be multiple voltages, instead of just a single voltage. Voltage V ORG The voltage V can be generated based on a voltage V0 supplied externally from the semiconductor device 900. The semiconductor device 900 can generate the voltage V based on a single power supply voltage supplied externally. ORG Therefore, the semiconductor device 900 can operate without multiple power supply voltages supplied from the outside.

[0568] Circuits 902, 904, and 906 are circuits that operate using different power supply voltages. For example, the power supply voltage of circuit 902 is based on voltage V. ORG and voltage V SS (V ORG >V SSThe voltage applied to the circuit. Additionally, for example, the power supply voltage of circuit 904 is based on voltage V. POG and voltage V SS (V POG >V ORG The voltage applied to the circuit. Additionally, for example, the power supply voltage of circuit 906 is based on voltage V. ORG Voltage V NEG (V ORG >V SS >V NEG The voltage applied. Furthermore, when the voltage V... SS Setting the voltage to the same level as ground (GND) can reduce the variety of voltages generated by the power supply circuit 901.

[0569] The voltage generating circuit 903 generates voltage V. POG The circuit. The voltage generation circuit 903 can be based on the voltage V supplied from the power supply circuit 901. ORG Generated voltage V POG Therefore, the semiconductor device 900, including circuit 904, can operate based on a single power supply voltage supplied from an external source.

[0570] The voltage generating circuit 905 generates voltage V. NEG The circuit. The voltage generation circuit 905 can be based on the voltage V supplied from the power supply circuit 901. ORG Generated voltage V NEG Therefore, the semiconductor device 900, including circuit 906, can operate based on a single power supply voltage supplied from an external source.

[0571] Figure 41B It shows the voltage V POG An example of a working 904 circuit. Figure 41C An example of the signal waveform used to make circuit 904 work is shown.

[0572] Figure 41B Transistor 911 is shown. The signal supplied to the gate of transistor 911 is, for example, based on voltage V. POG and voltage V SS This signal is generated. The voltage V is used to turn on transistor 911. POG And the voltage V is used to make transistor 911 non-conducting. SS .like Figure 41C As shown, voltage V POG Specific voltage V ORG This allows transistor 911 to operate more reliably, ensuring the source (S) and drain (D) are in a conducting state. Consequently, circuit 904 can reduce erroneous operation.

[0573] Figure 41D It shows the voltage V NEG An example of a working circuit 906. Figure 41E An example of the signal waveform used to make circuit 906 work is shown.

[0574] Figure 41D A transistor 912 including a back gate is shown. The signal supplied to the gate of transistor 912 is, for example, based on a voltage V. ORG and voltage V SS This signal is generated. The voltage V is what causes transistor 911 to operate in the on state. ORG And the voltage V is used to make transistor 911 non-conducting. SS Additionally, the voltage supplied to the back gate of transistor 912 is based on voltage V. NEG Generate. For example... Figure 41E As shown, voltage V NEG Specific voltage V SS (GND) is low. Therefore, the threshold voltage of transistor 912 can be controlled to drift in the positive direction. This allows transistor 912 to be more reliably de-conducted, resulting in a smaller current flowing between the source (S) and drain (D). As a result, circuit 906 can achieve reduced malfunctions and lower power consumption.

[0575] In addition, the voltage V can be NEG It can be applied directly to the back gate of transistor 912. Alternatively, it can be based on voltage V. ORG and voltage V NEG A signal is generated and supplied to the gate of transistor 912 and then supplied to the back gate of transistor 912.

[0576] Figure 42A and Figure 42B Show Figure 41D and Figure 41E Examples of variations.

[0577] exist Figure 42A The circuit diagram shows a transistor 922 between voltage generation circuit 905 and circuit 906, whose conduction state can be controlled by control circuit 921. Transistor 922 is an n-channel OS transistor. The control signal S output by control circuit 921 is... BG This is a signal used to control the conduction state of transistor 922. Additionally, transistors 912A and 912B included in circuit 906 are the same OS transistors as transistor 922.

[0578] exist Figure 42B The timing diagram shows the control signal S. BG and node N BGThe potential change at node N BG This indicates the potential state of the back gate of transistors 912A and 912B. When the control signal S... BG When the voltage level is high, transistor 922 becomes active, and node N... BG Become voltage V NEG Then, when the control signal S... BG When it is low, node N BG It becomes electrically floating. Transistor 922 is an OS transistor, therefore its off-state current is small. Thus, even at node N... BG Even in a floating state, the supplied voltage V can be maintained. NEG .

[0579] Figure 43A An example of a circuit structure applicable to the voltage generation circuit 903 described above is shown. Figure 43A The voltage generation circuit 903 shown is a five-stage charge pump, including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is supplied directly or via the inverter INV to capacitors C1 to C5. When the supply voltage of the inverter INV is based on voltage V... ORG and voltage V SS When the applied voltage is applied, it can be boosted to voltage V due to the clock signal CLK. ORG Five times the positive voltage V POG Additionally, the forward voltage of diodes D1 through D5 is 0V. Furthermore, by changing the number of stages in the charge pump, the desired voltage V can be obtained. POG .

[0580] Figure 43B An example of a circuit structure applicable to the voltage generation circuit 905 described above is shown. Figure 43B The voltage generation circuit 905 shown is a four-stage charge pump, including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is supplied directly or via the inverter INV to capacitors C1 to C5. When the supply voltage of the inverter INV is based on voltage V... ORG and voltage V SS When the applied voltage is applied, the voltage V can be obtained from ground potential (i.e., voltage V) due to the clock signal CLK. SS Step down to voltage V ORG The voltage V is four times the negative voltage. NEG Additionally, the forward voltage of diodes D1 through D5 is 0V. Furthermore, by changing the number of stages in the charge pump, the desired voltage V can be obtained. NEG .

[0581] Note that the circuit structure of the voltage generating circuit 903 described above is not limited to... Figure 43A The circuit diagram shown has the following structure. Figures 44A to 44C A modified example of the voltage generation circuit 903 is shown. Figures 44A to 44C In the voltage generating circuits 903A to 903C shown, variations of the voltage generating circuit 903 can be realized by changing the voltage supplied to each wiring or by changing the configuration of the components.

[0582] Figure 44A The voltage generation circuit 903A shown includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1. A clock signal CLK is supplied directly to the gates of transistors M1 to M10, or via the inverter INV1. The voltage V is boosted due to the clock signal CLK. ORG The voltage V is four times the positive voltage. POG Furthermore, by changing the number of stages, the desired voltage V can be obtained. POG .exist Figure 44A In the voltage generation circuit 903A shown, by using OS transistors as transistors M1 to M10, the off-state current can be kept small, and leakage of charge held in capacitors C11 to C14 can be suppressed. Therefore, voltage V can be generated efficiently. ORG Boost to voltage V POG .

[0583] Figure 44B The voltage generation circuit 903B shown includes transistors M11 to M14, capacitors C15 and C16, and inverter INV2. A clock signal CLK is supplied directly to the gates of transistors M11 to M14, or via inverter INV2. The clock signal CLK can be used to boost the voltage to V. ORG The voltage V is twice the positive voltage. POG .exist Figure 44B In the voltage generation circuit 903B shown, by using OS transistors as transistors M11 to M14, the off-state current can be kept small, and leakage of charge held in capacitors C15 and C16 can be suppressed. Therefore, voltage V can be generated efficiently. ORG Boost to voltage V POG .

[0584] in addition, Figure 44C The voltage generation circuit 903C shown includes an inductor Ind1, a transistor M15, a diode D6, and a capacitor C17. The conduction state of transistor M15 is controlled by a control signal EN. Due to the control signal EN, a voltage V can be generated. ORG Boost voltage V POGBecause Figure 44C The voltage generation circuit 903C shown uses an inductor Ind1 to boost the voltage, so it can boost the voltage with high conversion efficiency.

[0585] As described above, in the structure of this embodiment, the voltage required for the circuits included in the semiconductor device can be generated inside the semiconductor device. Therefore, the number of power supply voltages supplied from outside the semiconductor device can be reduced.

[0586] The structures shown in this embodiment can be appropriately combined with the structures shown in other embodiments.

[0587] (Implementation Method 7)

[0588] In this embodiment, refer to Figure 45 Figures 4 to 48 illustrate a display module and an electronic device that include a semiconductor device according to one aspect of the present invention.

[0589] <7-1. Display Module>

[0590] Figure 45 The display module 7000 shown includes a touch panel 7004 connected to FPC 7003, a display panel 7006 connected to FPC 7005, a backlight 7007, a frame 7009, a printed circuit board 7010, and a battery 7011, located between the upper cover 7001 and the lower cover 7002.

[0591] For example, a semiconductor device according to one aspect of the present invention can be used in a display panel 7006.

[0592] The upper cover 7001 and the lower cover 7002 can be appropriately changed in shape or size according to the size of the touch panel 7004 and the display panel 7006.

[0593] The touch panel 7004 can be a resistive or capacitive touch panel, and can be formed to overlap with the display panel 7006. Alternatively, the opposing substrate (sealing substrate) of the display panel 7006 can also function as a touch panel. Furthermore, an optical touch panel can be formed by placing a light sensor within each pixel of the display panel 7006.

[0594] The backlight 7007 has a light source 7008. Note that, although in Figure 45 The illustration shows a structure in which a light source 7008 is arranged on a backlight 7007, but it is not limited to this. For example, the light source 7008 can be arranged at the end of the backlight 7007 and a light diffuser plate can be used. When using a self-emissive light-emitting element such as an organic EL element, or when using a reflective panel, a structure in which the backlight 7007 is not provided can be adopted.

[0595] In addition to protecting the display panel 7006, the frame 7009 also serves as electromagnetic shielding to block electromagnetic waves generated by the operation of the printed circuit board 7010. Furthermore, the frame 7009 can also function as a heat sink.

[0596] The printed circuit board 7010 includes a power supply circuit and a signal processing circuit for outputting video and clock signals. The power supply to the power supply circuit can be either an external commercial power supply or a power supply using a separately provided battery 7011. When using a commercial power supply, the battery 7011 can be omitted.

[0597] In addition, components such as polarizers, phase difference plates, and prism sheets can also be installed in the display module 7000.

[0598] <7-2. Electronic Devices 1>

[0599] also, Figures 46A to 46E Examples of electronic devices are shown.

[0600] Figure 46A This is an exterior view of the camera 8000 equipped with a viewfinder 8100.

[0601] The camera 8000 includes a frame 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. In addition, the camera 8000 is equipped with a detachable lens 8006.

[0602] Here, the camera 8000 has a structure that allows the lens 8006 to be detached from the frame 8001 and exchanged, and the lens 8006 and the frame can also be formed as one piece.

[0603] The camera 8000 can take an image by pressing the shutter button 8004. Alternatively, the display unit 8002 is used as a touch panel, and images can also be taken by touching the display unit 8002.

[0604] The camera 8000's frame 8001 includes an insert with electrodes, which can be connected to the viewfinder 8100 and to a flash unit, etc.

[0605] The viewfinder 8100 includes a frame 8101, a display 8102, and buttons 8103, etc.

[0606] The housing 8101 includes an inserter that fits into the camera 8000, allowing the viewfinder 8100 to be mounted onto the camera 8000. Additionally, the inserter includes electrodes that can display images received from the camera 8000 via these electrodes onto the display unit 8102.

[0607] Button 8103 is used as a power button. By using button 8103, the display unit 8102 can be switched between displaying and not displaying.

[0608] One aspect of the display device of the present invention can be applied to the display unit 8002 of a camera 8000 and the display unit 8102 of a viewfinder 8100.

[0609] In addition, Figure 46A In this case, the camera 8000 and the viewfinder 8100 are separate and detachable electronic devices, but a viewfinder with a display device can also be built into the frame 8001 of the camera 8000.

[0610] also, Figure 46B This is a diagram showing the appearance of the head-mounted display 8200.

[0611] The head-mounted display 8200 includes a mounting section 8201, a lens 8202, a main body 8203, a display section 8204, and a cable 8205. Additionally, a battery 8206 is built into the mounting section 8201.

[0612] Power is supplied from battery 8206 to main body 8203 via cable 8205. Main body 8203 includes a wireless receiver and can display image information, such as received image data, on display unit 8204. In addition, by using a camera installed in main body 8203 to capture the user's eyeball and eyelid movements, and calculating the coordinates of the user's viewpoint based on this information, the user's viewpoint can be used as an input method.

[0613] Alternatively, multiple electrodes can be provided at the user-contacted location of the mounting section 8201. The main body 8203 may also have the function of identifying the user's gaze point by detecting the current flowing through the electrodes according to the user's eye movements. Furthermore, the main body 8203 may have the function of monitoring the user's pulse by detecting the current flowing through the electrodes. The mounting section 8201 may have various sensors such as temperature sensors, pressure sensors, and acceleration sensors, and may also have the function of displaying the user's biometric information on the display section 8204. In addition, the main body 8203 may also detect the user's head movements, and synchronously change the image displayed on the display section 8204 in sync with the user's head movements.

[0614] A display device to which one aspect of the present invention can be applied to the display unit 8204.

[0615] Figure 46C , Figure 46D and Figure 46EThis is a diagram showing the appearance of a head-mounted display 8300. The head-mounted display 8300 includes a frame 8301, a display unit 8302, a strap-shaped fixing tool 8304, and a pair of lenses 8305.

[0616] Users can see the display on the display unit 8302 through the lens 8305. Preferably, the display unit 8302 is configured in a curved shape. By configuring the display unit 8302 in a curved shape, users can experience a high degree of realism.

[0617] The display device according to one aspect of the present invention can be applied to the display unit 8302. Because the display device including the semiconductor device according to one aspect of the present invention has extremely high resolution, even if... Figure 46E Using the 8305 lens to magnify the image in that way allows for a more realistic image to be displayed without the user seeing the pixels.

[0618] <7-3. Electronic Devices 2>

[0619] then, Figures 47A to 47G Showing with Figures 46A to 46E Examples of different electronic devices are shown.

[0620] Figures 47A to 47G The electronic device shown includes a frame 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (which has the function of measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0621] Figures 47A to 47G The electronic device shown has various functions. For example, it may have the following functions: displaying various information (still images, moving images, text images, etc.) on a display panel; a touch panel; displaying calendars, dates, or times; controlling processing using various software (programs); wireless communication; connecting to various computer networks using wireless communication; sending or receiving various data using wireless communication; reading programs or data stored in a storage medium and displaying them on the display panel; etc. Note that... Figures 47A to 47G The electronic device shown may have functions not limited to those described above, but may possess a variety of functions. Furthermore, although in Figures 47A to 47GAlthough not illustrated, the electronic device may include multiple display units. Furthermore, a camera or similar device may be incorporated into the electronic device to provide the following functions: the ability to capture still images; the ability to capture moving images; the ability to store captured images in a storage medium (external storage medium or storage medium built into the camera); the ability to display captured images on a display unit; and so on.

[0622] The following is a detailed explanation. Figures 47A to 47G The electronic device shown.

[0623] Figure 47A This is a perspective view showing the television device 9100. A large display unit 9001, for example, 50 inches or more or 100 inches or more, can be assembled into the television device 9100.

[0624] Figure 47B This is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 has one or more functions, such as a telephone, an electronic notebook, and an information reading device. Specifically, it can be used as a smartphone. Furthermore, the portable information terminal 9101 may be equipped with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Additionally, the portable information terminal 9101 can display text and image information on multiple surfaces. For example, three operation buttons 9050 (also called operation icons or simply icons) can be displayed on one surface of the display unit 9001. Additionally, information 9051, represented by a dashed rectangle, can be displayed on another surface of the display unit 9001. Furthermore, examples of information 9051 include displays indicating received messages from emails, SNS (Social Networking Services), or telephone calls; the title of the email or SNS message; the sender's name; the date; the time; battery level; and antenna reception strength. Alternatively, operation buttons 9050 can be displayed instead of information 9051 in the same location where information 9051 is displayed.

[0625] Figure 47CThis is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, the user of the portable information terminal 9102 can check its display (in this case, information 9053) while the portable information terminal 9102 is placed in an upper pocket. Specifically, the phone number or name of the caller is displayed in a position that allows the user to view this information from above the portable information terminal 9102. The user can check this display without taking the portable information terminal 9102 out of their pocket, thereby determining whether to answer the call.

[0626] Figure 47D This is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as mobile phone use, email, article reading and editing, music playback, internet communication, and computer games. Furthermore, the display surface of the display unit 9001 is curved, allowing for display on the curved surface. Additionally, the portable information terminal 9200 can perform short-range wireless communication according to communication standards. For example, hands-free calling can be performed by communicating with a headset capable of wireless communication. Furthermore, the portable information terminal 9200 includes a connection terminal 9006, allowing direct data exchange with other information terminals via a connector. Charging can also be performed via the connection terminal 9006. Moreover, charging can also be performed wirelessly without using the connection terminal 9006.

[0627] Figure 47E , Figure 47F and Figure 47G This is a perspective view showing the foldable portable information terminal 9201. Additionally, Figure 47E This is a 3D view of the 9201 portable information terminal in its unfolded state. Figure 47F This is a 3D diagram of the portable information terminal 9201 in the intermediate state between its unfolded and folded states. Figure 47G This is a perspective view of the portable information terminal 9201 in its folded state. The portable information terminal 9201 offers good portability in its folded state and excellent visibility in its unfolded state due to its large, seamlessly integrated display area. The display unit 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. By bending two frames 9000 together via the hinges 9055, the portable information terminal 9201 can be reversibly changed from its unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0628] Figure 48A and Figure 48B It is a perspective view of a display device that includes multiple display panels. Figure 48A It is a 3D image of multiple display panels being rolled up. Figure 48B It is a 3D view of multiple display panels unfolded.

[0629] Figure 48A and Figure 48B The display device 9500 shown includes multiple display panels 9501, a shaft portion 9511, and a bearing portion 9512. Each of the multiple display panels 9501 includes a display area 9502 and a light-transmitting area 9503.

[0630] Multiple display panels 9501 are flexible. Adjacent display panels 9501 are arranged with a portion overlapping each other. For example, the light-transmitting areas 9503 of two adjacent display panels 9501 can overlap. By using multiple display panels 9501, a display device with a large screen can be realized. Furthermore, the display panels 9501 can be rolled up depending on the application, thus enabling a highly versatile display device.

[0631] Figure 48A and Figure 48B The illustration shows a case where the display areas 9502 of adjacent display panels 9501 are separated from each other, but it is not limited to this. For example, a continuous display area 9502 can also be achieved by overlapping the display areas 9502 of adjacent display panels 9501 without gaps.

[0632] The electronic device shown in this embodiment is characterized by having a display section for displaying certain information. Note that the semiconductor device of one aspect of the present invention can also be applied to electronic devices that do not include a display section.

[0633] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0634] (Implementation Method 8)

[0635] In this embodiment, refer to Figures 49 to 49. Figure 51 A semiconductor device (memory device) and a CPU including the semiconductor device (memory device) will be described. This semiconductor device (memory device) can retain its stored contents even without a power supply and has no limit on the number of write cycles. The CPU described in this embodiment can, for example, be used in the electronic device described in the above embodiments.

[0636] <8-1. Storage Device>

[0637] Figure 49 illustrates an example of a semiconductor device (memory device) that can retain its stored contents even without a power supply and has no limit on the number of write cycles. Furthermore, Figure 49B Represented by circuit diagram Figure 49A The image.

[0638] exist Figure 49A and Figure 49B The semiconductor device shown includes: a transistor 3200 using a first semiconductor material; a transistor 3300 using a second semiconductor material; and a capacitor 3400.

[0639] The first and second semiconductor materials are preferably materials with different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.), and the second semiconductor material can be an oxide semiconductor. Transistors using single-crystal silicon, etc., which are materials other than oxide semiconductors, are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors have low off-state currents.

[0640] Transistor 3300 is a transistor whose channel is formed in a semiconductor layer including oxide semiconductor. Because transistor 3300 has a small off-state current, stored content can be retained for a long time by using this transistor. In other words, because a semiconductor memory device that does not require refresh operation or has an extremely low refresh frequency can be formed, power consumption can be significantly reduced.

[0641] exist Figure 49B In this configuration, the first wiring 3101 is electrically connected to the source electrode of transistor 3200, and the second wiring 3102 is electrically connected to the drain electrode of transistor 3200. Furthermore, the third wiring 3103 is electrically connected to one of the source and drain electrodes of transistor 3300, and the fourth wiring 3104 is electrically connected to the gate electrode of transistor 3300. Additionally, the other of the gate electrode of transistor 3200 and the other of the source and drain electrodes of transistor 3300 are electrically connected to one electrode of capacitor 3400, and the fifth wiring 3105 is electrically connected to the other electrode of capacitor 3400.

[0642] exist Figure 49A In the semiconductor device shown, by effectively utilizing the feature that can maintain the potential of the gate electrode of transistor 3200, information can be written, held, and read out as shown below.

[0643] The writing and retention of information are explained. First, the potential of the fourth wiring 3104 is set to the potential that turns on transistor 3300, thus turning on transistor 3300. Consequently, the potential of the third wiring 3103 is applied to the gate electrode of transistor 3200 and capacitor 3400. In other words, a predetermined charge is applied to the gate of transistor 3200 (writing). Here, either a charge with two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. Then, by setting the potential of the fourth wiring 3104 to the potential that turns off transistor 3300, transistor 3300 is turned off, and the charge applied to the gate of transistor 3200 is retained (retention).

[0644] Because the off-state current of transistor 3300 is extremely small, the gate charge of transistor 3200 is maintained for a long time.

[0645] Next, the information readout will be explained. When a predetermined potential (constant potential) is applied to the fifth wiring 3105 while a predetermined potential (readout potential) is applied to the first wiring 3101, the second wiring 3102 has a different potential depending on the amount of charge held in the gate of the transistor 3200. This is because, generally speaking, when the transistor 3200 is an n-channel transistor, the apparent threshold voltage V when a high-level charge is applied to the gate electrode of the transistor 3200 is... th_H The apparent threshold voltage V is lower than the voltage V that appears when a low-level charge is applied to the gate electrode of transistor 3200. th_L Here, the apparent threshold voltage refers to the potential of the fifth wiring 3105 required to make transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3105 to V... th_L With V th_H The potential V0 between these values ​​can be used to identify the charge applied to the gate of transistor 3200. For example, when a high-level charge is supplied during writing, if the potential of the fifth wiring 3105 is V0 (>V0), then the potential can be determined. th_H When transistor 3200 is supplied with a low-level charge, even if the potential of the fifth wiring 3105 is V0 (< V), transistor 3200 becomes "conducting". th_L Transistor 3200 remains in the "off state". Therefore, the held information can be read by identifying the potential of the second wiring 3102.

[0646] Figure 49C The semiconductor device shown is Figure 49A The difference is that transistor 3200 is not included. In this case, information writing and retention can still be performed using the same methods as described above.

[0647] Next, regarding Figure 49C The reading of information from the semiconductor device shown will be explained. When transistor 3300 is in the ON state, the floating third wiring 3103 and capacitor 3400 are turned on, and charge is redistributed between the third wiring 3103 and capacitor 3400. As a result, the potential of the third wiring 3103 changes. The amount of change in the potential of the third wiring 3103 varies depending on the potential of one of the electrodes of capacitor 3400 (or the charge accumulated in capacitor 3400).

[0648] For example, if the potential of one of the electrodes of capacitor 3400 is V, the capacitance of capacitor 3400 is C, the capacitive component of the third wiring 3103 is CB, and the potential of the third wiring 3103 before charge redistribution is VB0, then the potential of bit line BL after charge redistribution is (CB×VB0+C×V) / (CB+C). Therefore, assuming that the potential of one of the electrodes of capacitor 3400 is in two states, namely V1 and V0 (V1>V0), it can be known that the potential of bit line BL at the holding potential V1 (=(CB×VB0+C×V1) / (CB+C)) is higher than the potential of bit line BL at the holding potential V0 (=(CB×VB0+C×V0) / (CB+C)).

[0649] Information can be read by comparing the potential of the third wiring 3103 with the specified potential.

[0650] In this case, the transistor using the first semiconductor material can be used in a drive circuit to drive the memory cell, and the transistor using the second semiconductor material can be stacked as transistor 3300 on the drive circuit.

[0651] In the semiconductor device shown in this embodiment, by using transistors whose channel formation region comprises oxide semiconductors with extremely low off-state current, stored content can be retained for an extremely long time. In other words, because refresh operations are not required, or the refresh frequency can be made extremely low, power consumption can be significantly reduced. Furthermore, stored content can be retained for a long time even without a power supply (note that a fixed potential is preferred).

[0652] Furthermore, in the semiconductor device shown in this embodiment, information writing does not require high voltage, and there is no problem of component degradation. Since, for example, it is not necessary to inject or extract electrons from the floating gate as in conventional non-volatile memories, problems such as degradation of the gate insulating film do not occur. In other words, in the semiconductor device according to this embodiment, there is no limitation on the number of rewrites, a limitation inherent in conventional non-volatile memories, thus greatly improving reliability. Moreover, information is written based on the transistor's on or off state, making high-speed operation easily achievable.

[0653] The aforementioned storage devices can be applied to, for example, CPUs (Central Processing Units), LSIs such as DSPs (Digital Signal Processors), custom LSIs, PLDs (Programmable Logic Devices), and RF-IDs (Radio Frequency Identification).

[0654] <8-2. CPU>

[0655] The following describes the CPU, which includes the aforementioned storage device.

[0656] Figure 50 This is a block diagram illustrating an example of the structure of a CPU including the aforementioned storage device.

[0657] Figure 50 The CPU shown has the following components on substrate 2190: ALU 2191 (ALU: Arithmetic Logic Unit), ALU controller 2192, instruction decoder 2193, interrupt controller 2194, timing controller 2195, register 2196, register controller 2197, bus interface 2198 (Bus I / F), rewritable ROM 2199, and ROM interface 2189 (ROM I / F). The substrate 2190 can be a semiconductor substrate, SOI substrate, glass substrate, etc. The ROM 2199 and ROM interface 2189 can also be located on different chips. Of course, Figure 50 The CPU shown is merely a simplified example; actual CPUs have various architectures depending on their application. For instance, they can also include... Figure 50 The CPU or arithmetic circuit shown is the core structure, with multiple such cores configured to operate simultaneously. Furthermore, the number of bits that can be processed in the CPU's internal arithmetic circuitry or data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0658] Instructions input to the CPU via bus interface 2198 are input to instruction decoder 2193 and decoded before being input to ALU controller 2192, interrupt controller 2194, register controller 2197, and timing controller 2195.

[0659] The ALU controller 2192, interrupt controller 2194, register controller 2197, and timing controller 2195 perform various controls based on the decoded instructions. Specifically, the ALU controller 2192 generates signals to control the operation of the ALU 2191. Furthermore, the interrupt controller 2194, while executing the CPU's program, determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority or mask state. The register controller 2197 generates the address of register 2196 and reads or writes register 2196 according to the CPU's state.

[0660] In addition, timing controller 2195 generates signals to control the operating timing of ALU 2191, ALU controller 2192, instruction decoder 2193, interrupt controller 2194, and register controller 2197. For example, timing controller 2195 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the various circuits mentioned above.

[0661] exist Figure 50 The CPU shown has a storage device in register 2196.

[0662] exist Figure 50 In the CPU shown, the register controller 2197 selects the holding operation in register 2196 based on instructions from ALU 2191. In other words, the register controller 2197 selects whether data is held by flip-flops or by capacitors within the storage device of register 2196. When flip-flops are selected, power supply voltage is supplied to the storage device in register 2196. When capacitors are selected, the data is overwritten, and power supply voltage to the storage device in register 2196 can be stopped.

[0663] Figure 51This is an example of a circuit diagram that can be used as a storage element in register 2196. Storage element 2200 includes circuitry 2201 (which loses stored data when power is off), circuitry 2202 (which does not lose stored data when power is off), switches 2203 and 2204, logic element 2206, capacitor 2207, and circuitry 2220 with selection functionality. Circuitry 2202 includes capacitor 2208, transistor 2209, and transistor 2210. Additionally, storage element 2200 may include other elements such as diodes, resistors, or inductors as needed.

[0664] Here, circuit 2202 can use the aforementioned storage device. When the power supply voltage to storage element 2200 is stopped, a ground potential (0V) or a potential that turns off transistor 2209 continues to be input to the gate of transistor 2209 in circuit 2202. For example, the gate of transistor 2209 is grounded through a load such as a resistor.

[0665] This example illustrates a transistor 2213 with a conductivity type (e.g., n-channel) as switch 2203, and a transistor 2214 with the opposite conductivity type (e.g., p-channel) as switch 2204. Here, the first terminal of switch 2203 corresponds to one of the source and drain terminals of transistor 2213, and the second terminal of switch 2203 corresponds to the other of the source and drain terminals of transistor 2213. The on / off state (i.e., the turn-on or turn-off state of transistor 2213) between the first and second terminals of switch 2203 is selected by a control signal RD input to the gate of transistor 2213. Similarly, the first terminal of switch 2204 corresponds to one of the source and drain terminals of transistor 2214, and the second terminal of switch 2204 corresponds to the other of the source and drain terminals of transistor 2214. The on / off state (i.e., the turn-on or turn-off state of transistor 2214) between the first and second terminals of switch 2204 is selected by a control signal RD input to the gate of transistor 2214.

[0666] One of the source and drain electrodes of transistor 2209 is electrically connected to one of the pairs of electrodes of capacitor 2208 and the gate of transistor 2210. This connection is referred to here as node M2. One of the source and drain electrodes of transistor 2210 is electrically connected to a wiring capable of supplying a low power supply potential (e.g., GND), while the other is electrically connected to the first terminal of switch 2203 (one of the source and drain electrodes of transistor 2213). The second terminal of switch 2203 (the other of the source and drain electrodes of transistor 2213) is electrically connected to the first terminal of switch 2204 (one of the source and drain electrodes of transistor 2214). The second terminal of switch 2204 (the other of the source and drain electrodes of transistor 2214) is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of switch 2203 (the other of the source and drain electrodes of transistor 2213), the first terminal of switch 2204 (one of the source and drain electrodes of transistor 2214), the input terminal of logic element 2206, and one of the pairs of electrodes of capacitor 2207 are electrically connected to each other. Here, the connection portion is referred to as node M1. The other input of one of the pairs of electrodes of capacitor 2207 can be fixed at a potential. For example, a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) can be input. The other input of the pair of electrodes of capacitor 2207 is electrically connected to a wiring capable of supplying a low power supply potential (e.g., a GND line). The other input of the other of the pairs of electrodes of capacitor 2208 can be fixed at a potential. For example, a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) can be input. The other input of the pair of electrodes of capacitor 2208 is electrically connected to a wiring capable of supplying a low power supply potential (e.g., a GND line).

[0667] When actively utilizing the parasitic capacitance of transistors or wiring, capacitors 2207 and 2208 may not be required.

[0668] The control signal WE is input to the first gate (first gate electrode) of transistor 2209. The conduction or non-conducting state between the first and second terminals of switches 2203 and 2204 is selected by a control signal RD, which is different from the control signal WE. When the first and second terminals of one switch are in a conduction state, the first and second terminals of the other switch are in a non-conducting state.

[0669] A signal corresponding to the data held in circuit 2201 is input to another of the source and drain terminals of transistor 2209. Figure 51This illustrates an example where a signal output from circuit 2201 is input to the other of the source and drain of transistor 2209. Logic element 2206 inverts the logic value of the signal output from the second terminal of switch 2203 (the other of the source and drain of transistor 2213) to create an inverted signal, which is then input to circuit 2201 via circuit 2220.

[0670] In addition, although Figure 51 The diagram illustrates an example where a signal output from the second terminal of switch 2203 (the other of the source and drain of transistor 2213) is input to circuit 2201 via logic element 2206 and circuit 2220, but is not limited to this. Alternatively, the signal output from the second terminal of switch 2203 (the other of the source and drain of transistor 2213) can be input to circuit 2201 without inverting its logic value. For example, when there is a node in circuit 2201 containing a signal that inverts the logic value of a signal input from an input terminal, the signal output from the second terminal of switch 2203 (the other of the source and drain of transistor 2213) can be input to that node.

[0671] exist Figure 51 In the transistors shown for the storage element 2200, transistors other than transistor 2209 can be transistors whose channels are formed in a layer of semiconductor other than oxide semiconductor or in substrate 2190. For example, transistors whose channels are formed in a silicon layer or silicon substrate can be used. Alternatively, all transistors for the storage element 2200 can also be transistors whose channels are formed in an oxide semiconductor film. Alternatively, the storage element 2200 may also include transistors other than transistor 2209 whose channels are formed in an oxide semiconductor film, and the remaining transistors can be transistors whose channels are formed in a layer of semiconductor other than oxide semiconductor or in substrate 2190.

[0672] Figure 51 The circuit 2201 shown can be, for example, a flip-flop. Alternatively, the logic element 2206 can be, for example, an inverter or a clock inverter.

[0673] In the semiconductor device shown in this embodiment, when no power supply voltage is supplied to the storage element 2200, the data stored in the circuit 2201 can be retained by the capacitor 2208 provided in the circuit 2202.

[0674] Furthermore, the off-state current of the transistor whose channel is formed in an oxide semiconductor film is extremely small. For example, the off-state current of the transistor whose channel is formed in an oxide semiconductor film is much lower than that of the transistor whose channel is formed in crystalline silicon. Therefore, by using the transistor 2209 whose channel is formed in an oxide semiconductor film, the signal held by the capacitor 2208 can be maintained for a long period of time, even when no power supply voltage is supplied to the storage element 2200. Therefore, the storage element 2200 can retain its stored contents (data) even when the power supply voltage is stopped.

[0675] In addition, since the storage element is characterized by pre-charging operation by setting switches 2203 and 2204, it can shorten the time from when the power supply voltage is restarted until the circuit 2201 retains the original data again.

[0676] Furthermore, in circuit 2202, the signal held by capacitor 2208 is input to the gate of transistor 2210. Therefore, after the power supply voltage to the storage element 2200 is resumed, the signal held by capacitor 2208 can be converted into the state of transistor 2210 (on or off state) and read out from circuit 2202. Thus, even if there are some changes in the potential corresponding to the signal held in capacitor 2208, the original signal can be read accurately.

[0677] By using this storage element 2200 in storage devices such as registers or cache memories in the processor, data in the storage device can be prevented from being lost due to a interruption of the power supply voltage. Furthermore, the storage device can be restored to its state before the power supply was interrupted within a short period after the power supply voltage is resumed. Therefore, power can be interrupted for a short time in the entire processor or one or more logic circuits constituting the processor, thereby suppressing power consumption.

[0678] Note that although this embodiment describes an example of using the storage element 2200 in a CPU, the storage element 2200 can also be applied to LSIs such as DSPs (Digital Signal Processors), custom LSIs, PLDs (Programmable Logic Devices), and RF-IDs (Radio Frequency Identification).

[0679] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0680] (Implementation Method 9)

[0681] In this embodiment, an imaging apparatus using a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 52 and 53.

[0682] Figures 52A to 52C An example of the circuit structure of an imaging device is shown.

[0683] <9. Imaging Device>

[0684] include Figure 52A The imaging device 610 shown includes a photoelectric conversion element 601, a transistor 602, a transistor 604, and a capacitor 606. One of the source and drain of transistor 602 is electrically connected to the photoelectric conversion element 601. The other of the source and drain of transistor 602 is electrically connected to the gate of transistor 604 through node 607 (charge storage section).

[0685] Transistor 602 is preferably an OS transistor. In an OS transistor, its off-state current can be minimized, thus allowing for a smaller capacitor 606. Alternatively, as... Figure 52B As shown, capacitor 606 can be omitted. Furthermore, by using an OS transistor as transistor 602, the potential of node 607 is less susceptible to fluctuations. Thus, an imaging device less affected by noise can be realized.

[0686] For example, the transistor shown in the above embodiment can be used as transistor 602. Alternatively, an OS transistor can be used as transistor 604.

[0687] As the photoelectric conversion element 601, a diode element with a pn junction or pin junction formed in a silicon substrate can be used, or a pin junction diode element using an amorphous silicon film or microcrystalline silicon film can also be used. Alternatively, a transistor connected to a diode can also be used. Furthermore, silicon, germanium, selenium, etc., can be used to form a variable resistor utilizing photoelectric effects.

[0688] Photoelectric conversion elements can also be formed using materials that can absorb radiation and generate electric charge. Materials capable of absorbing radiation and generating electric charge include lead iodide, mercuric iodide, gallium arsenide, CdTe, or CdZn.

[0689] include Figure 52C The imaging device 610 of the circuit shown uses a photodiode as a photoelectric conversion element 601. Figure 52CThe imaging device 610 shown includes a photoelectric conversion element 601, transistors 602, 603, 604, and 605, and a capacitor 606. One of the source and drain terminals of transistor 602 is electrically connected to the cathode of photoelectric conversion element 601, and the other is electrically connected to node 607. The anode of photoelectric conversion element 601 is electrically connected to wiring 611. One of the source and drain terminals of transistor 603 is electrically connected to node 607, and the other is electrically connected to wiring 608. The gate of transistor 604 is electrically connected to node 607, one of its source and drain terminals is electrically connected to wiring 609, and the other is electrically connected to one of the source and drain terminals of transistor 605. The other is electrically connected to wiring 608. One electrode of capacitor 606 is electrically connected to node 607, and the other electrode is electrically connected to wiring 611.

[0690] Transistor 602 can be used as a transfer transistor. A transfer signal TX is supplied to the gate of transistor 602. Transistor 603 can be used as a reset transistor. A reset signal RST is supplied to the gate of transistor 603. Transistor 604 can be used as an amplification transistor. Transistor 605 can be used as a selection transistor. A selection signal SEL is supplied to the gate of transistor 605. VDD is supplied to wiring 608, and VSS is supplied to wiring 611.

[0691] Next, the explanation includes Figure 52C The imaging device 610 shown operates as follows: First, transistor 603 is turned on to supply VDD to node 607 (reset operation). Then, transistor 603 is turned off, and VDD is maintained in node 607. Next, transistor 602 is turned on, causing a potential change in node 607 corresponding to the amount of light received by photoelectric conversion element 601 (accumulation operation). Then, transistor 602 is turned off, maintaining the potential of node 607. Next, transistor 605 is turned on, outputting a potential corresponding to the potential of node 607 from wiring 609 (selection operation). By detecting the potential of wiring 609, the amount of light received by photoelectric conversion element 601 can be determined.

[0692] Transistors 602 and 603 are preferably OS transistors. As mentioned above, the off-state current of an OS transistor can be minimized, thus allowing for a smaller capacitor 606. Alternatively, capacitor 606 can be omitted. Furthermore, by using OS transistors as transistors 602 and 603, the potential of node 607 is less susceptible to fluctuations. Consequently, an imaging device less affected by noise can be realized.

[0693] By including Figures 52A to 52CThe imaging device 610 of any of the circuits shown is configured in a matrix shape, which can realize a high-resolution imaging device.

[0694] For example, when the imaging device 610 is configured as a 1920×1080 matrix, an imaging device capable of imaging at a resolution of so-called Full HD (also known as "2K resolution," "2K1K," or "2K," etc.) can be realized. Furthermore, for example, when the imaging device 610 is configured as a 4096×2160 matrix, an imaging device capable of imaging at a resolution of so-called Ultra HD (also known as "4K resolution," "4K2K," or "4K," etc.) can be realized. Additionally, for example, when the imaging device 610 is configured as an 8192×4320 matrix, an imaging device capable of imaging at a resolution of so-called Ultra HD (also known as "8K resolution," "8K4K," or "8K," etc.) can be realized. By increasing the number of display elements, an imaging device capable of imaging at a resolution of 16K or 32K can also be realized.

[0695] Figure 53A and Figure 53B An example of the structure of an imaging device 610 using the aforementioned transistor is shown. Figure 53A and Figure 53B This is a cross-sectional view of the imaging device 610.

[0696] Figure 53A The imaging device 610 shown uses an n-type semiconductor as the substrate 641. Furthermore, a p-type semiconductor 1221 for a photoelectric conversion element 601 is disposed in the substrate 641. Additionally, a portion of the substrate 641 serves as an n-type semiconductor 1223 for the photoelectric conversion element 601.

[0697] Transistor 604 is disposed on substrate 641. Transistor 604 can be used as an n-channel transistor. Additionally, a p-type semiconductor well 1220 is disposed in a portion of substrate 641. Well 1220 can be disposed using the same method as when forming p-type semiconductor 1221. Furthermore, well 1220 and p-type semiconductor 1221 can be formed simultaneously.

[0698] exist Figure 53B In the imaging apparatus 610 shown, transistors 604 and 605 are formed on a substrate 641. Transistor 604 can be used as an n-channel transistor. Transistor 605 can be used as a p-channel transistor.

[0699] exist Figure 53B In the imaging device 610 shown, a photoelectric conversion element 601 is disposed on the substrate 641.

[0700] exist Figure 53BIn the photoelectric conversion element 601 shown, a photoelectric conversion layer 681 is included between an electrode 686 formed of a metal material or the like and a light-transmitting conductive layer 682. Figure 53B This diagram illustrates the use of selenium-based materials in the photoelectric conversion layer 681. The photoelectric conversion element 601 using selenium-based materials exhibits high external quantum efficiency for visible light. This photoelectric conversion element can be a highly sensitive sensor with a large electron amplification relative to the incident light due to avalanche breakdown. Furthermore, due to the high light absorption coefficient of selenium-based materials, it is easy to form the photoelectric conversion layer 681 in a relatively thin manner.

[0701] As a selenium-based material, amorphous selenium or crystalline selenium can be used. For example, crystalline selenium can be obtained by heat treatment after the formation of amorphous selenium. Furthermore, by making the crystal grain size of crystalline selenium smaller than the pixel pitch, the characteristic deviation of each pixel can be reduced. In addition, compared with amorphous selenium, crystalline selenium has higher spectral sensitivity and light absorption coefficient for visible light.

[0702] Note that although the attached figure shows the photoelectric conversion layer 681 as a single layer, it is also possible to use a structure in which gallium oxide or cerium oxide is provided as a hole blocking layer on the light-receiving side of the selenium-based material, and nickel oxide or antimony sulfide is provided as an electron blocking layer on the electrode 686 side.

[0703] The photoelectric conversion layer 681 can be a layer containing a compound (CIS) of copper, indium, and selenium. Alternatively, it can be a layer containing a compound (CIGS) of copper, indium, gallium, and selenium. By using CIS and CIGS, similar to the case of using a single layer of selenium, a photoelectric conversion element capable of utilizing the avalanche breakdown phenomenon can be formed.

[0704] In addition, CIS and CIGS are p-type semiconductors. In order to form a bond, cadmium sulfide or zinc sulfide of n-type semiconductors can also be placed in contact with p-type semiconductors.

[0705] To induce avalanche breakdown, a higher voltage (e.g., above 10V) is preferably applied to the photoelectric conversion element. Since OS transistors have a higher drain breakdown voltage than Si transistors, it is easier to apply a higher voltage to the photoelectric conversion element. Therefore, by combining OS transistors with high drain breakdown voltages with photoelectric conversion elements using selenium-based materials in the photoelectric conversion layer, a highly sensitive and reliable imaging device can be realized.

[0706] The light-transmitting conductive layer 682 can be, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, tin oxide containing fluorine, tin oxide containing antimony, or graphene. Furthermore, the light-transmitting conductive layer 682 is not limited to a single layer, but can also be a stack of different films.

[0707] As the photoelectric conversion element 601, a pin junction diode element using materials such as amorphous silicon film or microcrystalline silicon film can also be used. This photodiode includes an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer stacked sequentially. The i-type semiconductor layer is preferably made of amorphous silicon. The p-type and n-type semiconductor layers can be made of amorphous silicon or microcrystalline silicon containing dopants that impart each conductivity type. Photodiodes whose photoelectric conversion layer includes amorphous silicon have higher sensitivity in the visible light wavelength region and can easily detect weak visible light.

[0708] The pn junction diode element and the pin junction diode element are preferably arranged with the p-type semiconductor layer as the light-receiving surface. By using the p-type semiconductor layer as the light-receiving surface, the output current of the photoelectric conversion element 601 can be increased.

[0709] The photoelectric conversion element 601 formed using the above-mentioned selenium-based materials or amorphous silicon can be manufactured using general semiconductor manufacturing processes such as film formation, photolithography, and etching.

[0710] This embodiment can be implemented by appropriately combining it with the structures described in other embodiments, etc.

[0711] [Example 1]

[0712] In this embodiment, a sample comprising a conductive film capable of being used in one aspect of the present invention was fabricated, and the cross-sectional shape of the sample was observed using a scanning transmission electron microscope (STEM). Furthermore, XPS (X-ray photoelectron spectroscopy) analysis was performed on the sample.

[0713] <Sample Manufacturing>

[0714] As sample A1, tantalum nitride with a thickness of 35 nm and copper with a thickness of 200 nm were sequentially formed on a 720 mm × 600 mm glass substrate using a sputtering device.

[0715] As sample A2, tantalum nitride with a thickness of 35 nm and copper with a thickness of 200 nm were sequentially formed on a 720 mm × 600 mm glass substrate using a sputtering apparatus. Next, silicide formation was performed on the copper surface. In the silicide formation process, firstly, to remove the oxide film formed on the copper surface, plasma discharge was performed using a PECVD apparatus in an atmosphere containing ammonia. Then, silane gas was introduced into the PECVD apparatus, exposing the copper surface to the silane gas to form copper silicide. Furthermore, the substrate temperature for removing the oxide film on the copper surface was 350 °C. Furthermore, the substrate temperature for forming the copper silicide was 220 °C, using silane gas at a flow rate of 300 sccm and nitrogen gas at a flow rate of 500 sccm.

[0716] <Cross-Section Observation>

[0717] The cross-sectional shapes of the above-prepared Sample A1 and Sample A2 were observed using STEM. Figure 54A is a cross-sectional STEM photograph of Sample A1, Figure 54B is a cross-sectional STEM photograph of Sample A2.

[0718] It was confirmed from Figure 54A and Figure 54B the cross-sectional STEM photographs that a film different from copper (a copper silicide layer) is formed on the outermost surface of the film in Sample A2.

[0719] <XPS Analysis>

[0720] Subsequently, XPS analysis was performed on the surface of Sample A2. Table 1 shows the composition obtained by XPS. In addition, the detection depth of surface XPS is about 5 nm.

[0721] [Table 1]

[0722] Composition (atomic%) 24.1 37.6 18.2 11.3 8.8

[0723] Copper and silicon were detected on the surface of Sample A2, and the ratio of silicon to copper (Si / Cu) was 0.47.

[0724] Subsequently, Figure 55 shows the XPS analysis results in the depth direction of Sample A2. Figure 55 shows the distribution of copper (Cu), silicon (Si), tantalum (Ta), oxygen (O) and nitrogen (N) in the depth direction from the film surface of Sample A2 to the glass substrate.

[0725] As shown in Figure 55 , copper (Cu) and silicon (Si) are detected near the surface of the film.

[0726] Subsequently, Figure 56A and Figure 56B respectively show the Cu2p spectra obtained from the XPS analysis in the depth direction of Sample A2 3 / 2 and the Si2p spectrum. In addition, the horizontal axis represents Binding Energy.

[0727] In Figure 56A , the peak in the range of 931 eV or more and 934 eV or less is derived from Cu-Si bonds. Furthermore, in Figure 56B , the peak in the range of 98 eV or more and 100 eV or less is derived from metal-Si bonds.

[0728] As described above, it was confirmed that copper silicide having bonding between Cu and Si is formed on the surface of the film in Sample A2.

[0729] The structure shown in this embodiment can be implemented by appropriately combining it with the structures shown in other embodiments or examples.

[0730] [Example 2]

[0731] In this embodiment, a transistor of one aspect of the present invention is manufactured and its electrical characteristics are evaluated.

[0732] As a transistor used for evaluating electrical characteristics, it is manufactured as equivalent to... Figure 10A and Figure 10B Samples B1 and B2 of transistor 100L are shown. Furthermore, sample B1 is a transistor according to one embodiment of the present invention, and sample B2 is a transistor used for comparison.

[0733] Transistor 100L includes a conductive film 104 on substrate 102 serving as a gate electrode; insulating films 106 and 107 on substrate 102 and conductive film 104 serving as a first gate insulating film; an oxide semiconductor film 108 on insulating film 107; a conductive film 112a serving as a source electrode electrically connected to oxide semiconductor film 108; a conductive film 112b serving as a drain electrode electrically connected to oxide semiconductor film 108; insulating films 114 and 116 on oxide semiconductor film 108 and conductive films 112a and 112b serving as a second gate insulating film; an insulating film 118 on insulating film 116 serving as a protective insulating film; and a 120b on insulating film 118 serving as a second gate electrode. Furthermore, oxide semiconductor film 108 includes oxide semiconductor films 108b and 108c.

[0734] The conductive film 112a includes conductive films 112a_1, 112a_2, and 112a_3, and the conductive film 112b includes conductive films 112b_1, 112b_2, and 112b_3. Furthermore, the conductive film 112a_2 includes a region 112a_2b at its end that contacts the insulating film 114, and the conductive film 112b_2 includes a region 112b_2b at its end that contacts the insulating film 114.

[0735] <Transistor Manufacturing Methods>

[0736] Next, a method for manufacturing transistors corresponding to samples B1 and B2 will be described. Furthermore, the method for manufacturing transistors can be referred to Embodiment 1.

[0737] Manufacturing of Sample B1

[0738] A conductive film 104 is formed on a substrate 102. A glass substrate is used as the substrate 102. Furthermore, the conductive film 104 is formed by sequentially stacking a titanium film with a thickness of 10 nm, a copper film with a thickness of 100 nm, and a tantalum nitride film with a thickness of 50 nm using a sputtering apparatus.

[0739] Next, insulating films 106 and 107 are formed on substrate 102 and conductive film 104. As insulating film 106, a silicon nitride film with a thickness of 400 nm is formed using a PECVD apparatus. Furthermore, as insulating film 107, a silicon oxynitride film with a thickness of 15 nm is formed using a PECVD apparatus.

[0740] Next, an oxide semiconductor film 108 is formed on the insulating film 107.

[0741] In-Ga-Zn oxide (also known as IGZO) is used as the oxide semiconductor film 108. The oxide semiconductor film 108b, included in the oxide semiconductor film 108, is an IGZO film with a thickness of 10 nm formed using a sputtering apparatus. The film formation conditions for the IGZO film are as follows: the substrate temperature is set to 170°C; the oxygen gas ratio in the total flow rate of argon and oxygen gas is set to 30% and introduced into the processing chamber; the pressure is set to 0.2 Pa; and 1500 W of AC power is supplied to the metal oxide sputtering target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). Next, an IGZO film with a thickness of 20 nm is formed as the oxide semiconductor film 108c using a sputtering apparatus. Furthermore, the IGZO film formation conditions were as follows: the substrate temperature was set to 170°C; the oxygen gas ratio in the total flow rate of argon and oxygen gas was set to 50% and introduced into the processing chamber; the pressure was set to 0.2 Pa; and 500 W of AC power was supplied to the metal oxide sputtering target (In:Ga:Zn = 1:1:1.2 [atomic number ratio]). Additionally, after forming the oxide semiconductor film 108, a heat treatment was performed at 350°C for 1 hour.

[0742] Next, conductive films, which will later become conductive films 112a and 112b, are formed on insulating film 107 and oxide semiconductor film 108. As these conductive films, a 50 nm thick tungsten film, a 200 nm thick copper film, and a 5 nm thick tungsten film are continuously formed in a vacuum using a sputtering apparatus. Next, a photoresist mask is formed on these conductive films, and desired areas of the 5 nm thick tungsten film and the 200 nm thick copper film are etched. After removing the photoresist mask, the exposed copper surface is subjected to silicide treatment. In the silicide treatment conditions, firstly, to remove the oxide film formed on the copper surface, plasma discharge is performed using a PECVD apparatus in an atmosphere containing ammonia gas. Next, silane gas is introduced into the PECVD apparatus, exposing the copper surface to the silane gas to form copper silicide. Furthermore, the substrate temperature during the removal of the oxide film from the copper surface is 350°C. Furthermore, the substrate temperature for forming the copper silicide was 220°C, and silane gas with a flow rate of 300 sccm and nitrogen gas with a flow rate of 500 sccm were used. Next, a photoresist mask was formed on the conductive film treated with the silicide, and the desired area of ​​the 50 nm thick tungsten film was etched to form conductive films 112a and 112b. After forming the conductive films 112a and 112b, the photoresist mask was removed.

[0743] Next, an aqueous solution of phosphoric acid (an aqueous solution prepared by diluting an 85% aqueous solution of phosphoric acid 100 times with pure water) is applied to the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b to remove a portion of the surface of the oxide semiconductor film 108 exposed from the conductive films 112a and 112b.

[0744] Next, insulating films 114 and 116 are formed on insulating film 107, oxide semiconductor film 108, and conductive films 112a and 112b. Silicon oxynitride film with a thickness of 40 nm is formed as insulating film 114 using a PECVD apparatus. Silicon oxynitride film with a thickness of 400 nm is formed as insulating film 116 using a PECVD apparatus. Note that insulating films 114 and 116 are formed continuously in a vacuum using a PECVD apparatus.

[0745] The deposition conditions for insulating film 114 are as follows: substrate temperature 220°C; introduction of silane gas at a flow rate of 50 sccm and nitrous oxide gas at a flow rate of 2000 sccm into the processing chamber; pressure 20 Pa; and supply of 100 W RF power to the parallel plate electrodes disposed within the PECVD apparatus. The deposition conditions for insulating film 116 are as follows: substrate temperature 220°C; introduction of silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm into the processing chamber; pressure 200 Pa; and supply of 1500 W RF power to the parallel plate electrodes disposed within the PECVD apparatus.

[0746] Next, it was heat-treated at 300°C for 1 hour in a nitrogen-containing atmosphere.

[0747] Next, an insulating film 118 is formed on the insulating film 116. As the insulating film 118, a silicon nitride film with a thickness of 100 nm is formed using a PECVD apparatus. The film formation conditions for the insulating film 118 are as follows: the substrate temperature is set to 220°C; silane gas at a flow rate of 50 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm are introduced into the processing chamber; the pressure is set to 100 Pa; and 1000 W of RF power is supplied between the parallel plate electrodes disposed within the PECVD apparatus.

[0748] Next, an ITSO film with a thickness of 100 nm was formed on the insulating film 118 as a conductive film using a sputtering apparatus. The film formation conditions for this ITSO film were as follows: the substrate temperature was room temperature; argon gas at a flow rate of 72 sccm and oxygen gas at a flow rate of 5 sccm were introdu...

Claims

1. A semiconductor device, comprising: transistor, The transistor includes: Gate electrode; The first insulating film on the gate electrode; The oxide semiconductor film includes the region where the first insulating film overlaps with the gate electrode; The source electrode is electrically connected to the oxide semiconductor film; The drain electrode electrically connected to the oxide semiconductor film; and The second insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film on and in contact with the first oxide semiconductor film. The thickness of the second oxide semiconductor film is greater than the thickness of the first oxide semiconductor film. Both the source electrode and the drain electrode include a first conductive film and a second conductive film on and in contact with the first conductive film. The first conductive film has an end portion located further outward than the end portion of the second conductive film. The first conductive film contains titanium. The second conductive film contains copper. Furthermore, the end of the second conductive film includes a region having copper and silicon.

2. A semiconductor device, comprising: transistor, The transistor includes: Gate electrode; The first insulating film on the gate electrode; The second insulating film on the gate electrode; The oxide semiconductor film includes the region where the first insulating film and the second insulating film overlap with the gate electrode; The source electrode is electrically connected to the oxide semiconductor film; The drain electrode electrically connected to the oxide semiconductor film; and The third insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film on and in contact with the first oxide semiconductor film. The thickness of the second oxide semiconductor film is greater than the thickness of the first oxide semiconductor film. Both the source electrode and the drain electrode include a first conductive film and a second conductive film on and in contact with the first conductive film. The first conductive film has an end portion located further outward than the end portion of the second conductive film. The first conductive film contains titanium. The second conductive film contains copper. Furthermore, the end of the second conductive film includes a region having copper and silicon.

3. A semiconductor device, comprising: transistor, The transistor includes: Gate electrode; The first insulating film on the gate electrode; The oxide semiconductor film includes the region where the first insulating film overlaps with the gate electrode; The source electrode is electrically connected to the oxide semiconductor film; The drain electrode electrically connected to the oxide semiconductor film; and The second insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film on and in contact with the first oxide semiconductor film. The thickness of the second oxide semiconductor film is greater than the thickness of the first oxide semiconductor film. Both the source electrode and the drain electrode include a first conductive film and a second conductive film on and in contact with the first conductive film. The first conductive film has an end portion located further outward than the end portion of the second conductive film. The first conductive film contains at least one of titanium, tungsten, tantalum, and molybdenum. The second conductive film contains copper. Furthermore, the end of the second conductive film includes a region having copper and silicon.

4. A semiconductor device, comprising: transistor, The transistor includes: Gate electrode; The first insulating film on the gate electrode; The second insulating film on the gate electrode; The oxide semiconductor film includes the region where the first insulating film and the second insulating film overlap with the gate electrode; The source electrode is electrically connected to the oxide semiconductor film; The drain electrode is electrically connected to the oxide semiconductor film; The third insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode; The fourth insulating film on the third insulating film; and A first conductor is electrically connected to one of the source electrode and the drain electrode through an opening in the third and fourth insulating films. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film on and in contact with the first oxide semiconductor film. The thickness of the second oxide semiconductor film is greater than the thickness of the first oxide semiconductor film. Both the source electrode and the drain electrode include a first conductive film and a second conductive film on and in contact with the first conductive film. The first conductive film has an end portion located further outward than the end portion of the second conductive film. The source electrode is in contact with the sides of the first oxide semiconductor film and the second oxide semiconductor film. The first conductive film contains titanium. The second conductive film contains copper. Furthermore, the end of the second conductive film includes a region having copper and silicon.

5. A semiconductor device, comprising: Channel-etched transistors, The channel-etched transistor includes: Gate electrode on substrate; The first insulating film on the gate electrode; The oxide semiconductor film includes the region where the first insulating film overlaps with the gate electrode; The source electrode is electrically connected to the oxide semiconductor film; The drain electrode electrically connected to the oxide semiconductor film; and The second insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film on and in contact with the first oxide semiconductor film. The thickness of the second oxide semiconductor film is greater than the thickness of the first oxide semiconductor film. Both the source electrode and the drain electrode include a first conductive film and a second conductive film on and in contact with the first conductive film. The first conductive film has an end portion located further outward than the end portion of the second conductive film. The first conductive film contains titanium. Furthermore, the second conductive film contains copper.

6. A semiconductor device, comprising: Channel-etched transistors, The channel-etched transistor includes: Gate electrode on substrate; The first insulating film on the gate electrode; The second insulating film on the gate electrode; The oxide semiconductor film includes the region where the first insulating film and the second insulating film overlap with the gate electrode; The source electrode is electrically connected to the oxide semiconductor film; The drain electrode electrically connected to the oxide semiconductor film; and The third insulating film on the oxide semiconductor film, on the source electrode, and on the drain electrode. The fourth insulating film on the third insulating film; and A first conductor is electrically connected to one of the source electrode and the drain electrode through an opening in the third and fourth insulating films. The oxide semiconductor film includes a first oxide semiconductor film and a second oxide semiconductor film on and in contact with the first oxide semiconductor film. The thickness of the second oxide semiconductor film is greater than the thickness of the first oxide semiconductor film. Both the source electrode and the drain electrode include a first conductive film and a second conductive film on and in contact with the first conductive film. The first conductive film has an end portion located further outward than the end portion of the second conductive film. The source electrode is in contact with the sides of the first oxide semiconductor film and the second oxide semiconductor film. The first conductive film contains titanium. Furthermore, the second conductive film contains copper.

7. The semiconductor device according to any one of claims 1 to 6, Both the first oxide semiconductor film and the second oxide semiconductor film contain In, Zn, and M. The M is Al, Ga, Y, or Sn.

Images