Integrated circuit and power supply circuit

Abstract

The present application provides an integrated circuit capable of safely driving a power transistor even when a power supply voltage is high. The integrated circuit includes an inductor to which a rectified voltage corresponding to an alternating voltage is applied, and a power transistor to control an inductor current flowing through the inductor, the integrated circuit drives the power transistor of a power supply circuit that generates an output voltage of a target level in accordance with the alternating voltage, the integrated circuit includes a first terminal to which a power supply voltage generated in accordance with a change in the inductor current and used to operate the integrated circuit is applied, a second terminal to which a control electrode of the power transistor is connected, a first drive circuit to drive the power transistor via the second terminal to turn on the power transistor during a first period, and a second drive circuit to drive the power transistor via the second terminal to turn on the power transistor during a second period including at least a part of the first period, and the second drive circuit has a smaller drive capability than the first drive circuit.

Description

Technical Field

[0001] This invention relates to integrated circuits and power supply circuits. Background Technology

[0002] There exists an integrated circuit that drives a power transistor to control the inductor current flowing through the transformer of an AC-DC converter. (For example, Patent Document 1) Existing technical documents Patent documents

[0003] Patent Document 1: US Patent No. 7,554,367 Summary of the Invention The technical problem that the invention aims to solve

[0004] However, among the aforementioned integrated circuits, there are those that operate using a power supply voltage generated by the voltage produced according to changes in inductor current. Furthermore, for example, when the power transistor is an NMOS transistor, the power supply voltage is used as the gate voltage when the power transistor is turned on. However, the power supply voltage sometimes increases as it deviates from the rated gate voltage of the power transistor. In this case, a power transistor with a higher rated gate voltage is required, but this increases the cost.

[0005] Furthermore, high-voltage transistors are needed to withstand the increase in power supply voltage. However, high-voltage transistors are not prepared in standard manufacturing processes. Therefore, special manufacturing processes are required to produce integrated circuits, increasing the manufacturing cost.

[0006] The present invention was made in view of the aforementioned existing problems, and its object is to provide an integrated circuit that can safely drive power transistors even under high power supply voltage conditions. Technical solutions adopted to solve technical problems

[0007] The integrated circuit according to the present invention for solving the above-mentioned technical problems is as follows: An integrated circuit includes an inductor to which a rectified voltage corresponding to an AC voltage is applied and a power transistor for controlling the inductor current flowing through the inductor. The integrated circuit drives the power transistor of a power supply circuit that generates an output voltage of a target level according to the AC voltage. The integrated circuit includes a first terminal to which a power supply voltage generated according to a change in the inductor current and used to operate the integrated circuit is applied; a second terminal to which a control electrode of the power transistor is connected; a first driving circuit that drives the power transistor via the second terminal during a first period to turn it on; and a second driving circuit that drives the power transistor via the second terminal during a second period including at least a portion of the first period to turn it on, and the driving capability of the second driving circuit is smaller than that of the first driving circuit.

[0008] The power supply circuit according to the present invention for solving the above-mentioned technical problems is as follows: a power supply circuit that generates a DC voltage based on an AC voltage, comprising: an inductor to which a rectified voltage corresponding to the AC voltage is applied; a power transistor that controls the inductor current flowing through the inductor; and an integrated circuit for driving the power transistor, the integrated circuit comprising: a first terminal to which a power supply voltage generated according to a change in the inductor current and causing the integrated circuit to operate is applied; a second terminal to which a control electrode of the power transistor is connected; a first driving circuit that drives the power transistor via the second terminal during a first period to turn on the power transistor; and a second driving circuit that drives the power transistor via the second terminal during a second period including at least a portion of the first period to turn on the power transistor, and the driving capability of the second driving circuit is smaller than that of the first driving circuit. Invention Effects

[0009] An integrated circuit can be provided that can safely drive power transistors even under high power supply voltage conditions. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating an example of an AC-DC converter 10. Figure 2 This is a diagram showing an example of a switch control IC22. Figure 3 This is a diagram illustrating an example of the operation of the AC-DC converter 10 during continuous operation. Figure 4 is a diagram illustrating an example of the operation of the AC-DC converter 10 in discontinuous mode. Figure 5 is a diagram illustrating an example of the drive circuit 60. Figure 6 is a diagram illustrating an example of the first drive circuit 71. Figure 7 is a diagram illustrating the logic levels of control signals D0 to D3 output by the adjustment circuit 81 in various states. Figure 8 is a diagram illustrating an example of the second drive circuit 72. Figure 9 is a diagram illustrating an example of the operation of the switch control IC 22 when the voltage Vdr is lower than the lower limit level. Figure 10 is a diagram illustrating an example of the operation of the switch control IC 22 when the voltage Vdr is set to be equal to or higher than the lower limit level. Figure 11 is a diagram illustrating an example of the operation of the switch control IC 22 when the voltage Vdr is higher than the upper limit level. Figure 12 is a diagram illustrating an example of the operation of the switch control IC 22 when the voltage Vdr is set to be equal to or lower than the upper limit level. Figure 13 is a diagram illustrating an example of the operation of the switch control IC 22 when the signal en is at "L" level. Detailed Description of Embodiments

[0011] Based on the description of the present specification and the accompanying drawings, at least the following matters become clear.

[0012] =====Present Embodiment===== <<<Outline of AC-DC Converter 10>> Figure 1 is a diagram illustrating an example of the configuration of the AC-DC converter 10, which is an embodiment of the present invention. The AC-DC converter 10 is a flyback-type power supply circuit that generates an output voltage Vout of a target level based on an AC voltage Vac from a commercial power supply.

[0013] The AC-DC converter 10 is configured to include a full-wave rectifier circuit 20, capacitors 21, 31, 33, 41, a switch control IC 22, a power transistor 23, a transformer 24, resistors 25, 27, 28, diodes 26, 30, 40, a phototransistor 32, a constant voltage circuit 42, and a light emitting diode 43.

[0014] The full-wave rectifier circuit 20 performs full-wave rectification on the input AC voltage Vac and outputs it, while the capacitor 21 filters the output from the full-wave rectifier circuit 20 to generate the voltage Vrec.

[0015] The switch control IC22 is an integrated circuit that controls the switching of the power transistor 23 so that the output voltage Vout level becomes the target level.

[0016] The switch control IC 22 drives the power transistor 23 based on the current flowing in the primary coil L1 of the transformer 24 and the output voltage Vout. Additionally, in this embodiment, resistors 25 and 27 and diode 26 are connected between the terminal OUT of the switch control IC 22 and the gate electrode of the power transistor 23.

[0017] However, the terminal OUT and the power transistor 23 can also be directly connected. Here, resistors 25 and 27 and diode 26 are components that control the slope of the rising or falling edge of the gate voltage of the power transistor 23.

[0018] In this embodiment, "connection" includes direct connection and indirect connection via circuit elements. Details of the switch control IC22 will be described later.

[0019] The power transistor 23 is, for example, an NMOS transistor used to control the power of the load 11 of the AC-DC converter 10. Alternatively, in this embodiment, the power transistor 23 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited to this. The power transistor 23 can be any other switching element, such as a bipolar transistor, as long as it is a transistor capable of controlling power.

[0020] Resistor 28 is a resistor disposed between the source electrode of power transistor 23 and ground, used to detect the current flowing through the primary coil L1 of transformer 24 and power transistor 23. Additionally, resistor 28 generates a voltage Vcs, which represents the current value flowing through the primary coil L1.

[0021] Transformer 24 includes a primary coil L1, a secondary coil L2, and an auxiliary coil L3, with the primary coil L1 and auxiliary coil L3 insulated from the secondary coil L2. In transformer 24, voltages are generated across each of the secondary coil L2 and the auxiliary coil L3 according to the voltage change across the primary coil L1.

[0022] In this embodiment, a voltage Vrec is applied to one end of the primary coil L1, and the other end is connected to the drain electrode of the power transistor 23. Therefore, when the power transistor 23 is driven, a voltage is generated across each of the secondary coil L2 and the auxiliary coil L3.

[0023] Additionally, diode 30 rectifies the current from the auxiliary coil L3 of transformer 24 and supplies it to capacitor 31. Therefore, when the power transistor 23 is driven, capacitor 31 is charged by the current from diode 30.

[0024] In addition, although details are omitted, the switch control IC22 is started based on voltage Vrec, and after starting, it operates based on voltage Vcc (hereinafter referred to as power supply voltage Vcc) charged to capacitor 31.

[0025] Diode 40 rectifies the current from the secondary coil L2 of transformer 24 and supplies it to capacitor 41. Capacitor 41 is charged by the current from diode 40, thus generating an output voltage Vout between the terminals of capacitor 41. Furthermore, in this embodiment, the number of turns and polarity of the primary coil L1 and the secondary coil L2 are determined such that the output voltage Vout increases when the power transistor 23 is on for a longer period.

[0026] The constant voltage circuit 42 is a circuit that generates a constant DC voltage, for example, by using a shunt regulator.

[0027] The light-emitting diode 43 is a device that emits light with an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 42, and together with the phototransistor 32 described later, forms an optical coupler. In this embodiment, when the level of the output voltage Vout increases, the intensity of the light from the light-emitting diode 43 increases.

[0028] The phototransistor 32 receives light from the light-emitting diode 43, and the greater the intensity of the light, the greater the sink current I1 flows through it.

[0029] Capacitor 33 is a component used to stabilize the voltage Vfb generated at terminal FB of switch control IC22 when sink current I1 flows through it.

[0030] In addition, the primary coil L1 is equivalent to an "inductor", and the voltage Vrec is equivalent to a "rectified voltage".

[0031] <<<Structure of Switch Control IC22>>> Figure 2 This diagram illustrates an example of a switch control IC 22. The switch control IC 22 is an integrated circuit that controls the drive of the power transistor 23 and has terminals VCC, FB, CS, and OUT. For simplicity, the GND terminal is omitted.

[0032] Terminal VCC is the terminal to which the power supply voltage Vcc is applied. This power supply voltage Vcc is generated by the current from coil L3 according to the change in the inductor current flowing through coil L1.

[0033] Terminal FB is the terminal that generates voltage Vfb corresponding to the sink current I1 of phototransistor 32.

[0034] Terminal CS is a terminal to which voltage Vcs is applied, generated by the inductor current IL flowing through resistor 28 when power transistor 23 is turned on.

[0035] Terminal OUT is the terminal that outputs the voltage Vdr of the power transistor 23, and is connected to the gate electrode of the power transistor 23 via resistors 25 and 27 and diode 26.

[0036] In addition, the switch control IC22 is configured to include voltage divider circuits 50, 58, and 61, comparators 51 and 59, internal power supply 52, resistor 53, enable circuit 54, PWM oscillator 55, single trigger circuit 56, SR trigger 57, and drive circuit 60.

[0037] The voltage divider circuit 50 is a circuit that divides the power supply voltage Vcc to, for example, 1 / 10 to generate a voltage Vcc_div.

[0038] Comparator 51 is a circuit that compares the voltage Vcc_div with the reference voltage VREF0 and outputs a reset signal rst. Here, the reference voltage VREF0 is used to determine whether the power supply voltage Vcc has risen to the operating voltage of the switch control IC22. That is, when the reset signal rst goes high (hereinafter referred to as "H" level), the switch control IC22 starts to operate.

[0039] Specifically, when comparator 51 outputs a signal rst at the "H" level, the various circuits of switch control IC22 operate, and when comparator 51 outputs a signal rst at the low level (hereinafter referred to as "L" level), the various circuits of switch control IC22 are reset.

[0040] The internal power supply 52 is a circuit that generates the internal voltage Vdd based on the power supply voltage Vcc. Additionally, the back voltage Vdd is supplied to the control circuit 70 and the second drive circuit 72, which will be described later. Furthermore, the voltage Vfb generated at terminal FB is generated by the sink current I1 of the phototransistor 32 flowing through the resistor 53 connected between the internal voltage Vdd and terminal FB.

[0041] Furthermore, when the output voltage Vout becomes higher than the target level, the light-emitting diode 43 emits stronger light, and the sink current I1 of the phototransistor 32 increases. As a result, the current flowing through the resistor 53 increases, and therefore, the voltage Vfb decreases. Conversely, when the output voltage Vout becomes lower than the target level, the current flowing through the resistor 53 decreases, and the voltage Vfb increases.

[0042] The enable circuit 54 generates a signal en that controls the operation of the drive circuit 60, which will be described later, based on the voltage Vcc_div when the signal IN falls. Furthermore, the enable circuit 54 is configured to include a comparator 62, an inverter 63, a D flip-flop 64, and transmission gates 65 and 66.

[0043] Comparator 62 is a circuit that compares the voltage Vcc_div with the reference voltage ref. Furthermore, the reference circuit ref is either the reference voltage VREF1 or VREF2 selected based on the signal en.

[0044] Inverter 63 is a component that inverts the signal IN (described later) and outputs it as the clock for D flip-flop 64.

[0045] The D flip-flop 64 acquires the output of comparator 62 on the rising edge of the clock and outputs it as the Q output. Additionally, the Q output of the D flip-flop 64 becomes the signal en.

[0046] Transmission gates 65 and 66 are circuits used to output either reference voltage VREF1 or VREF2 as reference voltage ref based on the signal en. Specifically, when the signal en is at the "L" level, the output reference voltage VREF1 is used as reference voltage ref, and when the signal en is at the "H" level, the output reference voltage VREF2 is used as reference voltage ref.

[0047] Therefore, after the voltage Vcc_div is higher than the reference voltage VREF1 and the signal en is at the "H" level, if the voltage Vcc_div at the falling edge of the signal IN is lower than the reference voltage VREF2, the enable circuit 54 outputs the signal en at the "L" level.

[0048] On the other hand, after the voltage Vcc_div is lower than the reference voltage VREF2 and the signal en is at the "L" level, if the voltage Vcc_div at the falling edge of the signal IN exceeds the reference voltage VREF1, then the enable circuit 54 outputs the signal en at the "H" level. Otherwise, the enable circuit 54 maintains the signal en at the same logic level as before.

[0049] The PWM oscillator 55 is a circuit that outputs a signal Vpwm, which is a PWM waveform with a switching frequency corresponding to the voltage Vfb.

[0050] The single trigger circuit 56 is a circuit that generates a single trigger pulse Vs at the rising edge of the signal Vpwm.

[0051] In the SR flip-flop 57, a single trigger pulse Vs is input to the set input terminal, a reset signal Vr is input to the reset input terminal, and a signal IN is generated. Therefore, when the single trigger pulse Vs changes to the "H" level, the SR flip-flop 57 generates the "H" level signal IN, and when the reset signal Vr changes to the "H" level, the SR flip-flop 57 generates the "L" level signal IN.

[0052] Voltage divider circuit 58 is a circuit that divides the voltage Vfb generated in terminal FB to generate voltage Vfb_div.

[0053] Comparator 59 is a circuit that compares the voltage Vcs from terminal CS with the voltage Vfb_div and generates a reset signal Vr. Specifically, when the voltage Vcs is lower than the voltage Vfb_div, comparator 59 outputs a reset signal Vr at the "L" level, and when the voltage Vcs is higher than the voltage Vfb_div, comparator 59 outputs a reset signal Vr at the "H" level.

[0054] When the reset signal rst changes to the "H" level, the drive circuit 60 operates and outputs the voltage Vdr to drive the power transistor 23 according to the signal IN.

[0055] Specifically, when the signal en is at the "H" level, the drive circuit 60 clamps the voltage Vdr to the specified level and outputs it according to the "H" level signal IN. When the signal en is at the "L" level, the drive circuit 60 outputs the voltage Vdr at the voltage level of the power supply voltage Vcc according to the "H" level signal IN.

[0056] On the other hand, when the signal IN is at the "L" level, the drive circuit 60 outputs a ground-level voltage Vdr. Further details about the drive circuit 60 will be provided later.

[0057] Voltage divider circuit 61 is a circuit that divides voltage Vdr to, for example, 1 / 10 to generate voltage Vdr_div. Furthermore, voltage divider circuit 61 outputs voltage Vdr_div to control circuit 70 and second drive circuit 72, which will be described later.

[0058] Furthermore, the switching control circuit 22 operates to cause the AC-DC converter 10 to output a target level output voltage Vout. The following explains how the switching frequency of the power transistor 23 varies proportionally to the voltage Vfb corresponding to the output voltage Vout.

[0059] First, when the output voltage Vout exceeds the target level, the voltage Vfb drops, and the PWM oscillator 55 outputs a signal Vpwm with a lower switching frequency. As a result, the switch control IC 22 turns on the power transistor 23 for a shorter period, and the AC-DC converter 10 reduces the output voltage Vout to the target level.

[0060] Next, when the output voltage Vout is below the target level, the voltage Vfb rises, and the PWM oscillator 55 outputs a signal Vpwm with a higher switching frequency. As a result, the switch control IC 22 turns on the power transistor 23 for a longer period, and the AC-DC converter 10 raises the output voltage Vout to the target level.

[0061] In addition, terminal VCC is equivalent to "first terminal", terminal OUT is equivalent to "second terminal", and comparator 62 is equivalent to "second decision circuit".

[0062] The following describes the operation of the switch control circuit 22 when the AC-DC converter 10 operates continuously or discontinuously.

[0063] <<<Operation of AC-DC Converter 10 during Continuous Operation>>> Figure 3 This diagram illustrates the operation of the switch control IC22 when it continuously operates the AC-DC converter 10. The period from time t0 to t2 is designated as the Nth period, the period from time t2 to t4 as the (N+1)th period, and the period from time t4 to t6 as the (N+2)th period. The Nth period will be explained first.

[0064] At time t0, the PWM oscillator 55 outputs a signal Vpwm with a switching frequency corresponding to the voltage Vfb. The single trigger circuit 56 outputs a single trigger pulse, i.e., signal Vs, at the rising edge of the signal Vpwm, which is at the "H" level.

[0065] When a single trigger pulse (signal Vs) of level "H" is input, the SR flip-flop 57 outputs a signal IN of level "H". This causes the drive circuit 60 to raise the voltage level of signal Vdr and turn on the power transistor 23.

[0066] When the voltage level of signal Vdr rises and power transistor 23 is turned on, the inductor current IL1 flowing through the primary side coil L1 increases with a positive offset due to the continuous operation of AC-DC converter 10. Therefore, the voltage Vcs generated by the inductor current IL1 flowing through resistor 28 increases with the same positive offset as the inductor current IL1.

[0067] On the other hand, since the secondary coil L2 is electromagnetically coupled with opposite polarity and the diode 40 is cut off, when the power transistor 23 is turned on, the inductor current IL2 flowing through the secondary coil L2 does not flow, and the energy is stored in the transformer 24.

[0068] When the voltage Vcs exceeds the voltage Vfb_div at time t1, comparator 59 outputs a signal Vr at the "H" level. Therefore, SR flip-flop 57 outputs a signal IN at the "L" level, driving circuit 60 to reduce the voltage level of signal Vdr and turn off power transistor 23.

[0069] When the voltage level of signal Vdr decreases and power transistor 23 is turned off, the inductor current IL1 decreases sharply. Therefore, the energy stored in transformer 24 is output from the secondary winding L2 via diode 40. At this time, the inductor current IL2 flows while decreasing proportionally. Furthermore, at the instant of time t2, the inductor current IL2 has not yet become 0, and when power transistor 23 turns on and the inductor current IL1 begins to flow, the inductor current IL2 becomes 0.

[0070] Furthermore, the operation from time t0 to t2 is repeated from time t2 to t6. Therefore, during continuous operation, the AC-DC converter 10 operates while the inductor current IL1 remains constant at zero when the power transistor 23 is turned on. During continuous operation, either the inductor current IL1 or the inductor current IL2 is flowing at any instant from time t0 to time t6.

[0071] <<<Operation of AC-DC Converter 10 during Discontinuous Operation>>> Figure 4 This diagram illustrates the operation of the switch control IC 22 when it causes the AC-DC converter 10 to operate discontinuously. The period from time t10 to t12 is designated as the Nth period, the period from time t12 to t14 as the (N+1)th period, and the period from time t14 to t16 as the (N+2)th period. The Nth period will be explained first.

[0072] At time t0, the PWM oscillator 55 outputs a signal Vpwm with a switching frequency corresponding to the voltage Vfb. The single trigger circuit 56 outputs a single trigger pulse, i.e., signal Vs, at the rising edge of the signal Vpwm, which is at the "H" level.

[0073] When a single trigger pulse (signal Vs) of level "H" is input, the SR flip-flop 57 outputs a signal IN of level "H". Therefore, the drive circuit 60 raises the voltage level of signal Vdr and turns on the power transistor 23.

[0074] When the voltage level of signal Vdr rises and power transistor 23 is turned on, the inductor current IL1 flowing through the primary winding L1 does not increase with a positive offset due to the discontinuous operation of AC-DC converter 10. That is, when AC-DC converter 10 operates discontinuously, the inductor current IL1 increases from a non-current state (i.e., zero). Therefore, the voltage Vcs generated by the inductor current IL1 flowing through resistor 28 also increases with a positive offset, just like the inductor current IL1. That is, the voltage Vcs also increases from zero.

[0075] On the other hand, since the secondary coil L2 is electromagnetically coupled with opposite polarity and the diode 40 is cut off, when the power transistor 23 is turned on, the inductor current IL2 flowing through the secondary coil L2 does not flow, and the energy is stored in the transformer 24.

[0076] When the voltage Vcs exceeds the voltage Vfb_div at time t11, comparator 59 outputs a signal Vr at the "H" level. Therefore, SR flip-flop 57 outputs a signal IN at the "L" level, driving circuit 60 to reduce the voltage level of signal Vdr and turn off power transistor 23.

[0077] When the voltage level of signal Vdr decreases and power transistor 23 is turned off, the inductor current IL1 decreases sharply. Therefore, the energy stored in transformer 24 is output from the secondary winding L2 via diode 40. Additionally, when power transistor 23 turns on again at time t12 as it did at time t10, the AC-DC converter 10 operates discontinuously, and therefore, the inductor current IL2 does not flow. The inductor current IL2 is generated at time t11, then decreases proportionally, and becomes zero at some point between time t11 and time t12.

[0078] Furthermore, from time t12 to t17, the operation from time t10 to t12 is repeated. Therefore, during discontinuous operation, when power transistor 23 is turned on, AC-DC converter 10 operates to make inductor current IL1 zero. During discontinuous operation, there are periods, such as from time t11 to time t12, from time t13 to time t14, and from time t15 to time t16, during which neither inductor current IL1 nor inductor current IL2 flows.

[0079] <<<Structure of Drive Circuit 60>>> Figure 5 This is a diagram showing an example of a drive circuit 60. The drive circuit 60 is configured to include a control circuit 70, a first drive circuit 71, and a second drive circuit 72.

[0080] The control circuit 70 is a circuit used to determine the period during which the first drive circuit 71 drives the power transistor 23. Furthermore, the control circuit 70 outputs signals D0 to D3, thereby controlling the first drive circuit 71.

[0081] The first drive circuit 71 is a voltage drive circuit that drives the power transistor 23 based on the signal D0 from the control circuit 70.

[0082] The second drive circuit 72 is a current drive circuit that supplies current to or draws current from the terminal OUT of the switch control IC 22 based on the voltage Vdr_div and the signals en and IN, thereby driving the power transistor 23 with current. Furthermore, the control circuit 70, the first drive circuit 71, and the second drive circuit 72 will be described in detail later.

[0083] <<<Structure of Control Circuit 70>>> Furthermore, the control circuit 70 is configured to include a determination circuit 80 and an adjustment circuit 81, and outputs signals D0 to D3 based on the voltage Vdr_div, the signal IN, and the reset signal rst.

[0084] Furthermore, the control circuit 70 outputs signal D0 based on voltage Vdr_div and controls the first drive circuit 71 so that voltage Vdr falls within the specified range described later.

[0085] The determination circuit 80 is a circuit that determines whether the voltage Vdr is within a specified range (i.e., whether the voltage Vdr_div is between the reference voltage VREF2 (e.g., 1.4V) and the reference voltage VREF3 (e.g., 1.5V)).

[0086] Specifically, if the voltage Vdr_div continuously exceeds the reference voltage VREF3 during the three rising edges of the clock signal trd output by timer 92 (described later), then the determination circuit 80 outputs the "L" level signal Sup and the "H" level signal Sdown to the adjustment circuit 81 (described later). Furthermore, if the voltage Vdr_div continuously falls below the reference voltage VREF2 during the three rising edges of the clock signal trd output by timer 92, then the determination circuit 80 outputs the "H" level signal Sup and the "L" level signal Sdown to the adjustment circuit 81. In all other cases, the determination circuit 80 outputs the "L" level signals Sup and Sdown.

[0087] The determination circuit 80 is configured to include comparators 90 and 91, timer 92, and logic circuit 93, and controls the signal generated by the adjustment circuit 81 described later.

[0088] Comparator 90 is used to determine whether the voltage Vdr_div is higher than the reference voltage VREF2, and comparator 91 is used to determine whether the voltage Vdr_div is higher than the reference voltage VREF3.

[0089] Timer 92 is a circuit that outputs a clock signal trd to activate the determination circuit 80. When the signal IN changes to an "H" level, timer 92 outputs an "H" level clock signal trd after a predetermined time ta, and when the signal IN changes to an "L" level, timer 92 outputs an "L" level clock signal trd. Furthermore, the predetermined time ta is shorter than the period during which the signal IN is at an "H" level.

[0090] Logic circuit 93 maintains the outputs of comparators 90 and 91 on the rising edge of the clock signal trd from timer 92. When the voltage Vdr_div is continuously lower than the reference voltage VREF2 during the three rising edges of the clock signal trd, logic circuit 93 outputs the "H" level signal Sup and the "L" level signal Sdown. Conversely, when the voltage Vdr_div is continuously higher than the reference voltage VREF3 during the three rising edges of the clock signal trd, logic circuit 93 outputs the "L" level signal Sup and the "H" level signal Sdown. Furthermore, if the voltage Vdr_div is discontinuously lower than the reference voltage VREF2 or higher than the reference voltage VREF3 during the three rising edges of the clock signal trd, logic circuit 93 outputs the "L" level signals Sup and Sdown.

[0091] In addition, the adjustment circuit 81 outputs signals D0 to D3 based on signals Sup, Sdown and en to control the first drive circuit 71.

[0092] Furthermore, when the signal Sup becomes "H" level, the adjustment circuit 81 extends the voltage drive period for the first drive circuit 71 to drive the power transistor 23, and when the signal Sdown becomes "H" level, the adjustment circuit 81 shortens the voltage drive period. Additionally, when the signals Sup and Sdown are at "L" level, the adjustment circuit 81 maintains the voltage drive period.

[0093] Specifically, the adjustment circuit 81 adjusts the duration of the output "H" level control signals D0 to D2 according to the length of the voltage drive period. The structure / operation of the first drive circuit 71 is described later. Furthermore, the determination circuit 80 is equivalent to the "first determination circuit", and the signals Sup and Sdown are equivalent to the "determination result".

[0094] <<<Structure / Operation of First Drive Circuit 71 and Operation of Adjustment Circuit 81>>> Figure 6This diagram illustrates an example of the first drive circuit 71. If the enable circuit 54 outputs an "H" level signal *en*, and the determination circuit 80 outputs an "H" level signal *Sup*, then the adjustment circuit 81 extends the period during which the control signals D0 to D2 become "H" level. Conversely, if the enable circuit 54 outputs an "H" level signal *en*, and the determination circuit 80 outputs an "H" level signal *Sdown*, then the adjustment circuit 81 shortens the period during which the control signals D0 to D2 become "H" level. Furthermore, the period during which any one of the control signals D0 to D2 becomes "H" level corresponds to the voltage drive period.

[0095] Furthermore, if the enable circuit 54 outputs an "H" level signal en and the SR flip-flop 57 outputs an "H" level signal IN, then the adjustment circuit 81 outputs control signals D0, etc., to the first drive circuit 71, causing it to sequentially switch to four states: state 1, state 2, state 3, and non-drive state. The logic levels of the control signals D0 to D3 in each state are as follows: Figure 7 As shown, the explanation is as follows.

[0096] like Figure 7 As shown, in state 1, the adjustment circuit 81 sets control signals D0-D2 to "H" level and control signal D3 to "L" level. In state 2, the adjustment circuit 81 sets control signal D0 to "L" level, control signals D1-D2 to "H" level, and control signal D3 to "L" level. In state 3, the adjustment circuit 81 sets control signals D0-D1 to "L" level, control signal D2 to "H" level, and control signal D3 to "L" level. In the non-driving state, the adjustment circuit 81 sets control signals D0-D2 to "L" level and control signal D3 to "L" level.

[0097] On the other hand, such as Figure 7 As shown, when the enable circuit 54 outputs an "L" level signal en and the SR flip-flop 57 outputs an "H" level signal IN, the adjustment circuit 81 outputs control signals D0, etc., to the first drive circuit 71, so that the circuit sequentially transitions to states 4 and 5. Regarding the logic level of the control signals D0, etc., in each state, the logic level of the control signals D0, etc., in state 4 is the same as in state 1, and the logic level of the control signals D0, etc., in state 5 is the same as in state 3.

[0098] Furthermore, when the SR flip-flop 57 outputs an "L" level signal IN, such as Figure 7 As shown, the logic levels of control signals D0 to D3 are "L" level, while the logic level of control signal D3 is "H" level, which is independent of the logic level of signal en.

[0099] The first driving circuit 71 is a circuit for driving the power transistor 23 with voltage, and is configured to include a level shifting circuit 100, a voltage output circuit 101, and an output circuit 102.

[0100] The level shifting circuit 100 is a circuit that converts a control signal D0 that operates on voltage Vdd into a signal Vn0 that operates on power supply voltage Vcc. The level shifting circuit 100 is configured to include NMOS transistors 110 and 113, PMOS transistors 111 and 112, resistors 115 and 117, and Zener diodes 114 and 116.

[0101] In other words, the level shift circuit 100 outputs a signal Vn0 with the logic level of the control signal D0. Specifically, the level shift circuit 100 is a circuit that outputs an "H" level control signal D0 when the control circuit 70 outputs an "H" level control signal D0, and outputs an "L" level signal Vn0 when the control circuit 70 outputs an "L" level control signal D0.

[0102] The voltage output circuit 101 is a circuit used to control the gate voltage Vg of the PMOS transistor 130 (described later) of the output circuit 102 based on control signals D0 to D2 and signal Vn0. The voltage output circuit 101 is configured to include a first variable resistor 121, an NMOS transistor 122, and a second variable resistor 123. In addition, the first variable resistor 121, the NMOS transistor 122, and the second variable resistor 123 are equivalent to a "voltage divider circuit".

[0103] The first variable resistor 121 is a circuit that changes its resistance value according to the signal Vn0, and the second variable resistor 123 is a circuit that changes its resistance value according to control signals D0 to D1 and limits the current flowing through the Zener diode 132 (described later). Furthermore, in states 1 to 3 where the control signal D2 is at a "H" level, the second variable resistor 123 is connected to the first variable resistor via the NMOS transistor 122. Additionally, the NMOS transistor 122 is equivalent to a "second transistor".

[0104] Specifically, the first variable resistor 121 and the second variable resistor 123 generate the gate voltage Vg of the PMOS transistor 130, minimizing Vg in state 1 to maximize its driving capability. Then, as the system transitions from state 2 to state 3, the gate voltage Vg increases, reducing the driving capability of the PMOS transistor 130. Furthermore, in the non-driving state, the voltage Vcc, i.e., the gate voltage Vg, is applied to the PMOS transistor 130, stopping the driving of the PMOS transistor 130 to terminal OUT. States 4 and 5 are the same as states 1 and 3.

[0105] The output circuit 102 is a circuit that applies a gate voltage Vg to the PMOS transistor 130 to drive the terminal OUT, and is configured to include a PMOS transistor 130, an NMOS transistor 131 and a Zener diode 132.

[0106] <<<Operation of the first drive circuit 71 when signal IN is at "H" level and signal en is at "H" level>>> When both the IN and en signals are at the "H" level, the first drive circuit 71 operates to experience four states: state 1, state 2, state 3, and non-drive state.

[0107] According to the above structure, when the enable circuit 54 outputs a "H" level signal en, the first drive circuit 71 causes the PMOS transistor 130 to gradually reduce its drive capability and gradually increase its on-resistance based on the rise of the gate voltage Vg corresponding to the state transition from state 1 to the non-drive state. Here, "drive capability" refers to the ability of the PMOS transistor 130 to output current to the terminal OUT.

[0108] Specifically, in state 1, the first driving circuit 71 applies the minimum gate voltage Vg to the PMOS transistor 130, provides the maximum driving capability to the PMOS transistor 130, and minimizes the on-resistance of the PMOS transistor 130.

[0109] Then, in state 2, the first driving circuit 71 applies a gate voltage Vg to the PMOS transistor 130 that is higher than the gate voltage in state 1, applies a driving capability to the PMOS transistor 130 that is lower than the driving capability in state 1, and makes the on-resistance of the PMOS transistor 130 greater than the on-resistance in state 1.

[0110] In addition, in state 3, the first driving circuit 71 applies a gate voltage Vg to the PMOS transistor 130 that is higher than the gate voltage in state 2, applies a driving capability to the PMOS transistor 130 that is lower than the driving capability in state 2, and makes the on-resistance of the PMOS transistor 130 greater than the on-resistance in state 2.

[0111] Finally, in the non-driving state, the first driving circuit 71 applies the power supply voltage Vcc, i.e. the gate voltage Vg, to the PMOS transistor 130, causing the PMOS transistor 130 to be turned off and maximizing the on-resistance of the PMOS transistor 130.

[0112] Specifically, the operation of the first drive circuit 71 in each state from state 1 to the non-drive state is described below, and how the gate voltage Vg changes is explained.

[0113] <<<<Operation of the first drive circuit in state 1>>>> In state 1, the control circuit 70 sets the control signals D0 to D2 to the "H" level and the control signal D3 to the "L" level.

[0114] Therefore, when the control circuit 70 outputs a control signal D0 at the "H" level, the level shift circuit 100 in state 1 operates to turn on the NMOS transistor 110, and the logic level of node N1 becomes "L". Then, the PMOS transistor 111 turns on, and node N0 becomes "H". As a result, the PMOS transistor 112 turns off, and the level shift circuit 100 outputs a signal Vn0 at the "H" level.

[0115] In addition, Zener diode 114 is connected between the gate and source of PMOS transistor 111 as a clamping element. Zener diode 114 is a circuit used to protect PMOS transistor 111 so that excessive voltage is not applied between the gate and source of PMOS transistor 111 when PMOS transistor 111 is turned on.

[0116] However, when PMOS transistor 111 is turned on, the potential difference between the power supply voltage Vcc and node N1, which has a reduced potential, is applied across Zener diode 114. As a result, the current flowing through Zener diode 114 increases, the voltage clamped by Zener diode 114 becomes excessive, and the gate / source voltage of PMOS transistor 111 may exceed its breakdown voltage.

[0117] In addition, in order to suppress voltage exceeding the withstand voltage of PMOS transistor 111, the current flowing through Zener diode 114 is limited by the resistance value Rs.

[0118] When the level shift circuit 100 outputs a "H" level signal Vn0, the first variable resistor 121 causes the gate voltage Vg of the PMOS transistor 130 to rise to voltage Vcc. However, since the NMOS transistor 122 is turned on by the "H" level control signal D2, the second variable resistor 123 is connected to the first variable resistor 121. Therefore, through the first variable resistor 121, the second variable resistor 123, and the Zener diode 132, the gate voltage Vg of the PMOS transistor 130 becomes the minimum voltage generated based on voltage Vcc.

[0119] At this time, when the resistance value of the second variable resistor 123 is set to R2a, since the "H" level signal D2 (i.e., the 5V signal D2) is input to the gate electrode of the NMOS transistor 122, the potential of the source electrode of the NMOS transistor 122 becomes 5V-Vgs. Here, Vgs is the gate / source voltage of the NMOS transistor 122.

[0120] Even if the power supply voltage Vcc changes, the potential of the source electrode of the NMOS transistor 122 remains unchanged. Therefore, the current Ids122a flowing through the NMOS transistor 122 also remains unchanged, and this current Ids122a becomes the current used to pull down the gate electrode of the PMOS transistor 130. Furthermore, the impedance between the power supply voltage Vcc and the gate electrode of the PMOS transistor 130 is a combination of the resistance values ​​of the Zener diode 132 and R1a (with the resistance value of the first variable resistor 121 set to R1a) connected in parallel.

[0121] Therefore, the gate voltage Vg of the PMOS transistor 130 has the following relationship. Vg=Vcc-(Vz+Rz×Ids122a) / (1+Rz / R1a)··· (1)

[0122] Here, Vz is the voltage at which the current of Zener diode 132 begins to flow, Rz is the operating resistance of Zener diode 132, and the current Ids122a is the pull-down current of the gate electrode of PMOS transistor 130 in state 1 (i.e., the drain / source current of NMOS transistor 122).

[0123] Output circuit 102 applies the gate voltage Vg output by voltage output circuit 101 to PMOS transistor 130, thereby generating voltage Vdr. Additionally, because control signal D3 is at "L" level, NMOS transistor 131 is turned off.

[0124] <<<<Operation of the first drive circuit in state 2>>>> In state 2, the control circuit 70 sets the control signal D0 to the "L" level, sets the control signals D1 to D2 to the "H" level, and sets the control signal D3 to the "L" level.

[0125] Therefore, when the control circuit 70 outputs a control signal D0 at the "L" level, the level shift circuit 100 in state 2 turns on the NMOS transistor 113 and operates to change the logic level of node N1 to the "L" level. Similarly to the operation of the level shift circuit 100 in state 1, the PMOS transistor 112 turns on, and the level shift circuit 100 outputs a signal Vn0 at the "L" level.

[0126] When the control circuit 70 is in state 2 and the control signal D0 is at the "L" level, the current flowing through the Zener diode 116 is limited by the resistance value Rs.

[0127] When the level shift circuit 100 outputs an "L" level signal Vn0, the first variable resistor 121 causes the gate voltage Vg of the PMOS transistor 130 to rise to the voltage Vcc. However, because the NMOS transistor 122 is turned on by the "H" level control signal D2, the second variable resistor 123 is connected to the first variable resistor 121. Therefore, through the first variable resistor 121, the second variable resistor 123, and the Zener diode 132, the gate voltage Vg of the PMOS transistor 130 becomes a voltage based on the voltage Vcc. In this case, the gate voltage Vg is higher than the gate voltage Vg in state 1.

[0128] At this point, since the Zener diode 132 and the first variable resistor 121 (with a resistance value of R1b) are connected in parallel, the impedance between the voltage Vcc and the gate electrode of the PMOS transistor 130 becomes their combined value. The resistance value R1b is less than the resistance value R1a.

[0129] The resistance of the second variable resistor 123 is R2b, and the current Ids122b is less than the current Ids122a. Furthermore, the resistance value R2b is greater than the resistance value R2a.

[0130] Here, the current Ids122b becomes (5V-Vgs2) / R2b. Since the current Ids122b flowing through the NMOS transistor 122 is less than the current Ids122a in state 1, the voltage Vgs2 is slightly less than Vgs in state 1.

[0131] Therefore, the gate voltage Vg of the PMOS transistor 130 has the following relationship. Vg=Vcc-(Vz+Rz×Ids122b) / (1+Rz / R1b)··· (2)

[0132] Here, Vz is the voltage at which current begins to flow through Zener diode 132, and Rz is the operating resistance of Zener diode 132 when current flows through it. Furthermore, the current Ids 151b is the pull-down current of the gate electrode of PMOS transistor 130 in state 2 (i.e., the drain / source current of NMOS transistor 122).

[0133] Output circuit 102 applies the gate voltage Vg output by voltage output circuit 101 to PMOS transistor 130, thereby generating voltage Vdr. Additionally, since control signal D3 is at "L" level, NMOS transistor 131 is turned off.

[0134] <<<<Operation of the first drive circuit in state 3>>>> In state 3, the control circuit 70 sets the control signals D0 to D1 to “L” level, the control signal D2 to “H” level, and the control signal D3 to “L” level.

[0135] Therefore, when the control circuit 70 outputs a control signal D0 at the "L" level, the level shifting circuit 100 in state 3 outputs a signal Vn0 at the "L" level, just like in state 2.

[0136] When the level shift circuit 100 outputs an "L" level signal Vn0, the first variable resistor 121 causes the gate voltage Vg of the PMOS transistor 130 to rise to the voltage Vcc. However, because the NMOS transistor 122 is turned on by the "H" level control signal D2, the second variable resistor 123 is connected to the first variable resistor 121. Therefore, through the first variable resistor 121, the second variable resistor 123, and the Zener diode 132, the gate voltage Vg of the PMOS transistor 130 becomes a voltage based on the voltage Vcc. In this case, the gate voltage Vg is higher than the gate voltage Vg in state 2.

[0137] At this point, the resistance value of the second variable resistor 123 becomes R2c, and the pull-down current Ids122c of the gate electrode of the PMOS transistor 130 becomes a smaller value than Ids122b. Furthermore, the resistance value R2c is greater than the resistance value R2b.

[0138] Here, the current Ids122c becomes (5V-Vgs3) / R2c. Since the current Ids122c flowing through the NMOS transistor 122 is less than the current Ids122b in state 2, the voltage Vgs3 is slightly less than Vgs2 in state 2.

[0139] Therefore, the gate voltage Vg of the PMOS transistor 130 has the following relationship. Vg=Vcc-(Vz+Rz×Ids122c) / (1+Rz / R1b)··· (3a)

[0140] Here, Vz is the voltage at which current begins to flow in Zener diode 132, and Rz is the operating resistance when current flows in Zener diode 132. In addition, the current Ids122c is the pull-down current of the gate electrode of PMOS transistor 130 in state 3 (i.e., the drain / source current of NMOS transistor 122).

[0141] Furthermore, when the voltage difference between voltage Vg and power supply voltage Vcc becomes less than voltage Vz and no current flows through Zener diode 132, the gate voltage Vg of PMOS transistor 130 has the following relationship. Vg=Vcc-R1b×Ids122c··· (3b)

[0142] Output circuit 102 applies the gate voltage Vg output by voltage output circuit 101 to PMOS transistor 130, thereby generating voltage Vdr. Additionally, because control signal D3 is at "L" level, NMOS transistor 131 is turned off.

[0143] <<<<Operation of the first drive circuit in non-drive state>>>> In the non-driving state, the control circuit 70 sets the control signals D0 to D2 to the "L" level and the control signal D3 to the "L" level.

[0144] Therefore, in the non-driving state, the control signal D0 will not change compared to the case of state 3, so the description of the level shifting circuit 100 is omitted.

[0145] When the level shift circuit 100 outputs an "L" level signal Vn0, the first variable resistor 121 causes the gate voltage Vg of the PMOS transistor 130 to rise to voltage Vcc. Furthermore, since the NMOS transistor 122 is turned off by the "L" level control signal D2, the second variable resistor 123 is not connected to the first variable resistor 121. Therefore, the gate voltage Vg of the PMOS transistor 130 becomes voltage Vcc.

[0146] Output circuit 102 applies the gate voltage Vg output by voltage output circuit 101 to PMOS transistor 130, thereby generating voltage Vdr. Additionally, because control signal D3 is at "L" level, NMOS transistor 131 is turned off.

[0147] Therefore, when transitioning from state 1 to state 3, the driving capability of PMOS transistor 130 gradually decreases, the gate voltage Vg gradually increases, and the on-resistance of power transistor 23 also gradually increases.

[0148] Furthermore, the voltage-driven period includes a period of state 1 with relatively high driving capability and periods of states 2 and 3 following state 1 with relatively low driving capability. Moreover, here, the period of state 1 is equivalent to the "first sub-period", and the periods of states 2 and 3 are equivalent to the "second sub-period".

[0149] Furthermore, in state 1, the gate voltage Vg of the PMOS transistor 130 is approximately 5V lower than the power supply voltage Vcc. In state 2, the gate voltage Vg of the PMOS transistor 130 is approximately 3V lower than the power supply voltage Vcc, and in state 3, the gate voltage Vg of the PMOS transistor 130 is approximately 2.5V lower than the power supply voltage Vcc.

[0150] Therefore, the PMOS transistor 130 gradually decreases its driving capability and gradually increases its on-resistance according to the rise in gate voltage Vg corresponding to the state transition from state 1 to the non-driven state. In this embodiment, the gate voltage Vg is changed gradually, but it is also possible to change the gate voltage Vg gradually.

[0151] <<<Operation of the first drive circuit 71 when signal IN is at "H" level and signal en is at "L" level>>> When the signal IN is at the "H" level and the signal en is at the "L" level, the first drive circuit 71 operates to go through states 4 and 5.

[0152] According to the above structure, when the enable circuit 54 outputs an "L" level signal en, the first drive circuit 71 causes the PMOS transistor 130 to reduce its driving capability in stages and increase its on-resistance in stages according to the rise of the gate voltage Vg corresponding to the state transition from state 4 to state 5.

[0153] Specifically, in state 4, the first driving circuit 71 applies the minimum gate voltage Vg to the PMOS transistor 130, provides the maximum driving capability to the PMOS transistor 130, and minimizes the on-resistance of the PMOS transistor 130.

[0154] Then, in state 5, the first driving circuit 71 applies a gate voltage Vg to the PMOS transistor 130 that is higher than the gate voltage in state 4, applies a driving capability to the PMOS transistor 130 that is lower than the driving capability in state 4, and makes the on-resistance of the PMOS transistor 130 greater than the on-resistance in state 4.

[0155] Specifically, the operation of the first drive circuit 71 in each state from state 4 to state 5 is described below, and how the gate voltage Vg changes is explained.

[0156] <<<<Operation of the first drive circuit in state 4>>>> In state 4, similar to state 1, the control circuit 70 sets the control signals D0 to D2 to the "H" level and the control signal D3 to the "L" level.

[0157] Therefore, when the control circuit 70 outputs a control signal D0 at the "H" level, the level shift circuit 100 in state 4 operates to turn on the NMOS transistor 110 and make the logic level of node N1 "L". Consequently, the level shift circuit 100 operates, turning on the PMOS transistor 111, making node N0 "H", and as a result, the PMOS transistor 112 is turned off. Then, the level shift circuit 100 outputs a signal Vn0 at the "H" level.

[0158] When the level shift circuit 100 outputs a "H" level signal Vn0, the first variable resistor 121 causes the gate voltage Vg of the PMOS transistor 130 to rise to voltage Vcc. However, since the NMOS transistor 122 is turned on by the "H" level control signal D2, the second variable resistor 123 is connected to the first variable resistor 121. Therefore, through the first variable resistor 121, the second variable resistor 123, and the Zener diode 132, the gate voltage Vg of the PMOS transistor 130 becomes the minimum voltage generated based on voltage Vcc. The gate voltage Vg at this time is generated based on the relationship (1) in state 1.

[0159] Output circuit 102 applies the gate voltage Vg output by voltage output circuit 101 to PMOS transistor 130, thereby generating voltage Vdr. Additionally, because control signal D3 is at "L" level, NMOS transistor 131 is turned off.

[0160] <<<<Operation of the first drive circuit in state 5>>>> In state 5, similar to state 3, the control circuit 70 sets the control signals D0 to D1 to “L” level, the control signal D2 to “H” level, and the control signal D3 to “L” level.

[0161] Therefore, when the control circuit 70 outputs a control signal D0 at the "L" level, the level shift circuit 100 in state 5 operates to turn on the NMOS transistor 113 and change the logic level of node N0 to the "L" level. Thus, the level shift circuit 100 outputs a signal Vn0 at the "L" level.

[0162] When the level shift circuit 100 outputs an "L" level signal Vn0, the first variable resistor 121 causes the gate voltage Vg of the PMOS transistor 130 to rise to the voltage Vcc. However, since the NMOS transistor 122 is turned on by the "H" level control signal D2, the second variable resistor 123 is connected to the first variable resistor 121. Therefore, through the first variable resistor 121, the second variable resistor 123, and the Zener diode 132, the gate voltage Vg of the PMOS transistor 130 becomes a voltage based on the voltage Vcc. The gate voltage Vg in this case is higher than the gate voltage Vg in state 4. The gate voltage Vg at this time is generated based on the relationship (3a) or (3b) in state 1.

[0163] Output circuit 102 applies the gate voltage Vg output by voltage output circuit 101 to PMOS transistor 130, thereby generating voltage Vdr. Additionally, because control signal D3 is at "L" level, NMOS transistor 131 is turned off.

[0164] Therefore, when transitioning from state 4 to state 5, the driving capability of PMOS transistor 130 is reduced, the gate voltage Vg increases, and the on-resistance of power transistor 23 also increases.

[0165] Furthermore, the voltage-driven period includes a period of state 4 with relatively high driving capability and a period of state 5 following state 4 with relatively low driving capability. Moreover, here, the period of state 4 corresponds to the "first sub-period" and the period of state 5 corresponds to the "second sub-period".

[0166] Therefore, the PMOS transistor 130 changes its driving capability in stages according to the change in gate voltage Vg corresponding to the state transition from state 4 to state 5, and the on-resistance also increases in stages. At this point, the voltage Vdr becomes the power supply voltage Vcc.

[0167] <<<Operation of the first drive circuit 71 when the signal IN is at the "L" level>>> When the signal IN is at the "L" level, because the control circuit 70 outputs the "H" level control signal D3, the first drive circuit 71 operates to set the voltage Vdr to ground level via the terminal OUT. When the signal IN is at the "L" level, the logic levels of control signals D0 to D3 are independent of the logic level of the signal en; control signals D0 to D2 are at the "L" level, and control signal D3 is at the "H" level. The operation of the first drive circuit 71 when the signal IN is at the "L" level will be explained below.

[0168] When the signal IN is at the "L" level, the level shifting circuit 100 operates, causing the NMOS transistor 113 to turn on and the logic level of node N0 to change to the "L" level if the control circuit 70 outputs the control signal D0 at the "L" level. Then, the PMOS transistor 112 turns on, and node N0 becomes the "H" level. As a result, the PMOS transistor 111 turns off, and the level shifting circuit 100 outputs the signal Vn0 at the "L" level.

[0169] When the level shift circuit 100 outputs an "L" level signal Vn0, the first variable resistor 121 causes the gate voltage Vg of the PMOS transistor 130 to rise to voltage Vcc. Furthermore, since the NMOS transistor 122 is turned off by the "L" level control signal D2, the second variable resistor 123 is not connected to the first variable resistor 121. Therefore, the gate voltage Vg of the PMOS transistor 130 becomes voltage Vcc.

[0170] Because control circuit 70 outputs a "H" level control signal D3, output circuit 102 turns on NMOS transistor 131. At this time, voltage Vdr becomes ground voltage. Additionally, because gate voltage Vg becomes power supply voltage Vcc, PMOS transistor 130 is turned off.

[0171] In addition, the voltage driving period is equivalent to the "first period", the PMOS transistor 130 is equivalent to the "first transistor", the gate electrode of the PMOS transistor 130 is equivalent to the "control electrode", and the voltage Vg is equivalent to the "voltage divider voltage" and the "control voltage".

[0172] <<<Structure / Operation of the Second Drive Circuit 72>>> Figure 8 This is a diagram showing an example of the second drive circuit 72. When the signal IN is at the "H" level and the signal en is at the "H" level, the second drive circuit 72 supplies pull current to the terminal OUT and draws current from the terminal OUT, and is configured to include a pull current circuit 140 and a sink current circuit 141.

[0173] The current sourcing circuit 140 supplies current to the terminal OUT based on the difference between the voltage Vdr_div and the reference voltage VREF3 (e.g., 1.5V), and is configured to include an AND gate circuit 150 and a voltage-controlled current source circuit (Operational Transconductance Amplifier) ​​151.

[0174] AND gate 150 performs a logical AND operation on signals IN and en, and outputs this as signal Ven. When signal Ven is at a "H" level, voltage-controlled current source circuit 151 operates. Conversely, when signal Ven is at a "L" level, voltage-controlled current source circuit 151 stops operating. Furthermore, the period during which signal Ven is at a "H" level is defined as the current drive period. Moreover, the current drive period is longer than the voltage drive period and includes at least a portion of the voltage drive period.

[0175] The voltage-controlled current source circuit 151 provides a pull-up current to the terminal OUT based on the difference between the voltage Vdr_div and the reference voltage VREF3, and operates to make the voltage Vdr_div equal to the reference voltage VREF3.

[0176] Therefore, when the voltage Vdr_div is higher than the reference voltage VREF3, the spooling current stops. Conversely, if the voltage Vdr_div is lower than the reference voltage VREF3, the spooling current increases, and the voltage Vdr rises slowly. Furthermore, the reference voltage VREF3 is set to be higher than the threshold voltage of power transistor 23 and lower than its withstand voltage. Here, "withstand voltage" refers to the withstand voltage between the gate and source of power transistor 23. Additionally, the reference voltage VREF3 corresponds to the "first level".

[0177] The current sinking circuit 141 generates a sinking current for drawing current from the terminal OUT based on the difference between the voltage Vdr_div and the reference voltage VREF1 (e.g., 1.6V). The current sinking circuit 141 is configured to include a comparator 160, a current-limiting resistor 161, an output transistor (NMOS transistor) 162, a phase-compensating resistor 163, and a capacitor 164. Although a comparator 160 is used in this embodiment, an operational amplifier can also be used instead.

[0178] When the signal Ven is at a "H" level, comparator 160 operates. On the other hand, when the signal Ven is at a "L" level, comparator 160 does not operate and is designed to turn off NMOS transistor 162, therefore, no sink current flows. That is, when the signal Ven is at a "L" level, the current sinking circuit 141 stops operating.

[0179] That is, when the voltage Vdr_div is higher than the reference voltage VREF1, current is supplied to the gate electrode of NMOS transistor 162, and the on-resistance of NMOS transistor 162 is reduced. Conversely, when the voltage Vdr_div is lower than the reference voltage VREF1, current is drawn from the gate electrode of NMOS transistor 162, and the on-resistance of NMOS transistor 162 is increased.

[0180] When the on-resistance of NMOS transistor 162 decreases, the current sinking circuit 141 draws more current from terminal OUT via resistor 161. Conversely, when the on-resistance of NMOS transistor 162 increases, the current sinking circuit 141 draws less current from terminal OUT compared to the case where the on-resistance of NMOS transistor 162 is lower.

[0181] Therefore, when the voltage Vdr_div is higher than the reference voltage VREF1, the sink current increases compared to when the voltage Vdr_div is lower than the reference voltage VREF1. That is, if the voltage Vdr_div is higher than the reference voltage VREF1, the sink current increases further, and the rise in voltage Vdr is suppressed. Furthermore, the reference voltage VREF1 is set to be higher than the reference voltage VREF3 but lower than the withstand voltage of the power transistor 23.

[0182] Furthermore, the driving capability of the second driving circuit 72 is less than that of the first driving circuit 71. In addition, the current driving period corresponds to the "second period", the period when the signal en is at the "L" level and the control signal SH2 is at the "H" level corresponds to the "third period", and the reference voltage VREF1 corresponds to the "second level".

[0183] <<<Example of the operation of switch control IC22 when signal en is at "H" level>>> The following text describes the operation of the switch control IC22 when the signal en is at the "H" level. Additionally, in... Figure 8 and Figure 9 In this context, the output current Iout is described as such that the current output from terminal OUT is negative.

[0184] Figure 9 This diagram illustrates an example of the operation of the switch control IC22 when the voltage Vdr is below the lower limit level. Furthermore, Figure 8 This diagram illustrates the operation of the switch control IC22 when the reset signal rst is at the "H" level and the voltage drive is in its initial state.

[0185] When the SR flip-flop 57 outputs an "H" level signal IN at time t20, the adjustment circuit 81 outputs "H" level control signals D0 to D2 in state 1, and the voltage drive period begins. At this time, the adjustment circuit 81 outputs an "L" level control signal D3.

[0186] In addition, the second drive circuit 72 supplies pull current to terminal OUT according to voltage Vdr_div, and then timer 92 starts measuring for a specified time ta.

[0187] At this point, the gate voltage Vg of the PMOS transistor 130 becomes the minimum voltage, the driving capability of the PMOS transistor 130 becomes the maximum, the on-resistance becomes the minimum, and the output current Iout becomes the maximum. As a result, the voltage Vdr rises with the maximum slope.

[0188] In addition, Figure 9 During the period P0 shown, the current corresponding to the gate voltage Vg of the PMOS transistor 130 is charged to the parasitic capacitance Cgs between the gate and source of the power transistor 23 until the power transistor 23 changes from the off state to the on state, thus causing a rapid rise in voltage Vdr.

[0189] At time t21, the adjustment circuit 81 outputs a control signal D0 at the "L" level in state 2.

[0190] At this point, the gate voltage Vg of PMOS transistor 130 becomes higher than the voltage in state 1. Compared to state 1, the driving capability of PMOS transistor 130 decreases, the on-resistance increases, and the output voltage Iout decreases. As a result, the voltage Vdr becomes flat.

[0191] Furthermore, during period P1, power transistor 23 is turned on, causing its drain electrode to drop. At this time, the current corresponding to the gate voltage Vg of PMOS transistor 130 charges the parasitic capacitance Cgd between the gate and drain of power transistor 23. Therefore, due to the drain drop of power transistor 23 caused by its turn-on and the charging of parasitic capacitance Cgd, the voltage Vdr becomes flat.

[0192] At time t22, the adjustment circuit 81 outputs a control signal D1 at the "L" level in state 3.

[0193] At this point, the gate voltage Vg of the PMOS transistor 130 becomes higher than the voltage in state 2. Compared with states 1 and 2, the driving capability of the PMOS transistor 130 is further reduced, the on-resistance is further increased, and the output voltage Iout is further reduced. As a result, the voltage Vdr rises with a smaller slope compared to state 1.

[0194] Additionally, during period P2, the drain of power transistor 23 is sufficiently close to ground. The voltage Vdr rises by charging the parasitic capacitances Cgd and Cgs of power transistor 23 with a current corresponding to the gate voltage Vg of PMOS transistor 130. Since the gate voltage Vg of PMOS transistor 130 is higher than the voltage during period P0, the increase in voltage Vdr becomes gradual.

[0195] During periods P1 and P2, in order to turn on the power transistor 23, the first drive circuit 71 reduces the drive capability during the voltage drive period and charges the parasitic capacitance of the power transistor 23. After the voltage level change of the output electrode of the power transistor 23 is balanced with the above charging, the parasitic capacitance of the power transistor 23 is further charged.

[0196] As a result, in order to turn on the power transistor 23, the first driving circuit 71 discontinuously changes the rate of increase of the voltage Vdr used to drive the power transistor 23. That is, the voltage Vdr initially rises with a large slope A1 based on the charging current used to turn on the power transistor 23. Then, when the power transistor 23 is turned on, the slope A2 of the voltage Vdr decreases based on the change in charging current caused by the turn-on of the power transistor 23, and the voltage Vdr becomes almost flat. Thereafter, when the power transistor 23 is turned on by the charging current, the change in charging current stabilizes, and the voltage Vdr rises with a slope A3 that is smaller than the slope A1. Therefore, the voltage Vdr rises with two inflection points. In this embodiment, "inflection point" refers to the point where the slope of the voltage Vdr changes.

[0197] At time t23, the adjustment circuit 81 outputs a control signal D2 at the "L" level in the non-drive state, and the voltage drive period ends.

[0198] At this time, the gate voltage Vg of PMOS transistor 130 is pulled up and gradually becomes the power supply voltage Vcc.

[0199] At time t24, after a specified period ta from time t20, timer 92 outputs a clock signal trd at the "H" level.

[0200] At this time, the voltage Vdr is below the lower limit level (i.e., the voltage Vdr_div is below the reference voltage VREF2). Therefore, if the voltage Vdr_div is below the reference voltage VREF2 twice after the rising edge of the clock signal trd, the determination circuit 80 outputs the signal Sup.

[0201] At time t25, when SR flip-flop 57 outputs an "L" level signal IN, timer 92 outputs an "L" level clock signal trd.

[0202] In addition, the second drive circuit 72 stops supplying pull current to the terminal OUT based on the voltage Vdr_div.

[0203] Figure 10 This diagram illustrates an example of the operation of the switch control IC22 when the voltage Vdr is above the lower limit level. The operation of each circuit from time t30 to time t35 is shown. Figure 8The operation of each circuit from time t20 to time t25 is roughly the same. Furthermore, Figure 9 The reason for the change in voltage Vdr from period P10 to P12 is Figure 8 The reason for the change in voltage Vdr from P0 to P2 during the same period is the same.

[0204] exist Figure 10 In, with Figure 9 The difference is that after the decision circuit 80 outputs the signal Sup, the voltage drive period becomes longer. As a result, at time t34, the voltage Vdr is higher than the lower limit level (i.e., the voltage Vdr_div is higher than the reference voltage VREF2). Therefore, at time t34, the decision circuit 80 stops outputting the signal Sup.

[0205] Therefore, when the voltage Vdr is lower than the lower limit level, the switch control IC22 controls the first drive circuit 71 and the second drive circuit 72, thereby controlling the voltage Vdr within the specified range.

[0206] Figure 11 This diagram illustrates an example of the operation of the switch control IC22 when the voltage Vdr is higher than the upper limit level. Additionally, in Figure 10 and Figure 11 In this context, the output current Iout is described as such that the current output from terminal OUT is negative.

[0207] When the SR flip-flop 57 outputs an "H" level signal IN at time t40, the adjustment circuit 81 outputs "H" level control signals D0 to D2 in state 1, and the voltage drive period begins. At this time, the adjustment circuit 81 outputs an "L" level control signal D3.

[0208] In addition, the second drive circuit 72 supplies pull-up current to terminal OUT according to voltage Vdr_div. Then, timer 92 starts measuring a predetermined time ta.

[0209] At this point, the gate voltage Vg of the PMOS transistor 130 becomes the minimum voltage, the driving capability of the PMOS transistor 130 becomes the maximum, the on-resistance becomes the minimum, and the output current Iout becomes the maximum. As a result, the voltage Vdr rises with the maximum slope.

[0210] in addition, Figure 11 During the period P20 shown, the current corresponding to the gate voltage Vg of the PMOS transistor 130 is charged to the parasitic capacitance Cgs between the gate and source of the power transistor 23 until the power transistor 23 changes from the off state to the on state, thus causing a rapid rise in voltage Vdr.

[0211] At time t41, the adjustment circuit 81 outputs a control signal D0 at the "L" level in state 2.

[0212] At this point, the gate voltage Vg of PMOS transistor 130 becomes higher than the voltage in state 1. Compared to state 1, the driving capability of PMOS transistor 130 decreases, the on-resistance increases, and the output voltage Iout decreases. As a result, the voltage Vdr decreases slightly.

[0213] Furthermore, during period P21, power transistor 23 is turned on, causing its drain electrode to drop. At this time, the current corresponding to the gate voltage Vg of PMOS transistor 130 charges the parasitic capacitance Cgd between the gate and drain of power transistor 23. Therefore, the drain drop of power transistor 23 caused by its turn-on balances the charging of parasitic capacitance Cgd.

[0214] However, since the resistor 163 and capacitor 164 used for phase compensation in the current sinking circuit 141 are coupled to the gate electrode of the NMOS transistor 162, the gate voltage of the NMOS transistor 162 rises sharply. Therefore, due to the operation of the current sinking circuit 141, the voltage Vdr decreases slightly, and the voltage Vdr changes in an upward sloping manner.

[0215] At time t42, the adjustment circuit 81 outputs a control signal D1 at the "L" level in state 3.

[0216] At this point, the gate voltage Vg of the PMOS transistor 130 becomes higher than the voltage in state 2. Compared with states 1 and 2, the driving capability of the PMOS transistor 130 is further reduced, the on-resistance is further increased, and the output voltage Iout is further reduced. As a result, the voltage Vdr rises with a smaller slope compared to state 1.

[0217] Additionally, during period P22, the drain electrode of power transistor 23 is sufficiently close to ground. The voltage Vdr rises by charging the parasitic capacitances Cgd and Cgs of power transistor 23 with a current corresponding to the gate voltage Vg of PMOS transistor 130. Since the gate voltage Vg of PMOS transistor 130 is higher than the voltage during period P20, the increase in voltage Vdr becomes gradual.

[0218] However, similar to period P21, the resistor 163 and capacitor 164 for phase compensation in the current sinking circuit 141 are coupled to the gate electrode of the NMOS transistor 162, causing the gate voltage of the NMOS transistor 162 to rise sharply. Therefore, due to the operation of the current sinking circuit 141, the voltage Vdr decreases slightly, and the voltage Vdr changes in an upward sloping manner.

[0219] During periods P21 and P22, in order to turn on the power transistor 23, the first drive circuit 71 reduces the drive capability during the voltage drive period and charges the parasitic capacitance of the power transistor 23. After the voltage level change at the output electrode of the power transistor 23 balances with the charging, the parasitic capacitance of the power transistor 23 is further charged. At this time, the second drive circuit 72 generates a sink current to reduce the drive capability.

[0220] Therefore, in order to turn on the power transistor 23, the first driving circuit 71 discontinuously increases the voltage Vdr used to drive the power transistor 23. Simultaneously, the second driving circuit 72 generates a sinking current. As a result, the voltage Vdr used to drive the power transistor 23 rises with two maximum values ​​and then returns to a roughly predetermined voltage.

[0221] That is, the voltage Vdr initially rises with a large slope B1 based on the charging current used to turn on power transistor 23. Then, when power transistor 23 is turned on, the slope B2 of voltage Vdr becomes negative due to the change in charging current caused by the turn-on of power transistor 23 and the influence of the sinking current used to turn off power transistor 23, and voltage Vdr decreases. Subsequently, when power transistor 23 is further turned on by the charging current, the change in charging current stabilizes, and voltage Vdr rises with a slope B3 that is smaller than the slope B1. However, thereafter, due to the influence of the sinking current, the slope B4 of voltage Vdr becomes negative, and voltage Vdr decreases. Then, voltage Vdr almost becomes the specified voltage.

[0222] At time t43, the adjustment circuit 81 outputs a control signal D2 at the "L" level in the non-drive state, and the voltage drive period ends.

[0223] At this time, the gate voltage Vg of PMOS transistor 130 is pulled up and gradually becomes the power supply voltage Vcc.

[0224] At time t44, after a specified period ta from time t40, timer 92 outputs a clock signal trd at the "H" level.

[0225] At this time, the voltage Vdr is higher than the upper limit level (i.e., the voltage Vdr_div is higher than the reference voltage VREF3). Therefore, if the voltage Vdr_div is higher than the reference voltage VREF3 twice after the rising edge of the clock signal trd, the determination circuit 80 outputs the signal Sdown.

[0226] At time t45, when SR flip-flop 57 outputs an "L" level signal IN, timer 92 outputs an "L" level clock signal trd.

[0227] In addition, the second drive circuit 72 stops supplying pull current to terminal OUT based on voltage Vdr_div.

[0228] Figure 12 This diagram illustrates an example of the operation of the switch control IC22 when the voltage Vdr is below the upper limit level. The operation of each circuit from time t50 to time t55 is shown. Figure 11 The operation of each circuit from time t40 to time t45 is roughly the same. Furthermore, Figure 12 The reason for the change in voltage Vdr from period P30 to P32 is... Figure 11 The reason for the change in voltage Vdr from period P20 to P22 is the same.

[0229] exist Figure 12 In, with Figure 11 The difference is that after the decision circuit 80 outputs the signal Sdown, the voltage drive period is shortened. As a result, at time t54, the voltage Vdr becomes lower than the upper limit level (i.e., the voltage Vdr_div is lower than the reference voltage VREF3). Therefore, at time t54, the decision circuit 80 stops outputting the signal Sdown.

[0230] Therefore, when the voltage Vdr is higher than the upper limit level, the switch control IC22 controls the first drive circuit 71 and the second drive circuit 72, thereby controlling the voltage Vdr within the specified range.

[0231] In addition, refer to the following again Figure 3 , Figure 4 To explain Figures 9-12 The relationship. In Figure 3 and Figure 4 During the (N-2)th and (N-1)th periods, the switch control IC22 sometimes performs... Figure 9 The action, and Figure 3 and Figure 4 During the Nth period, the switch control IC22 will sometimes perform... Figure 9 The action. In this case, Figure 3 and Figure 4 During the Nth period, the determination circuit 80 outputs a signal Sup at the "H" level. As a result, in Figure 3 and Figure 4 During the (N+1)th period, the switch control IC22 performs... Figure 10 The action.

[0232] On the other hand, Figure 3 and Figure 4 During the (N-2)th and (N-1)th periods, the switch control IC22 sometimes performs... Figure 11 The action, and Figure 3 and Figure 4 During the Nth period, the switch control IC22 will sometimes perform... Figure 11The action. In this case, Figure 3 and Figure 4 During the Nth period, the determination circuit 80 outputs a signal Sdown at the "H" level. As a result, in Figure 3 and Figure 4 During the (N+1)th period, the switch control IC22 performs... Figure 12 The action.

[0233] <<<Example of the operation of switch control IC22 when signal en is at "L" level>>> The following describes the operation of the switch control IC22 when the signal en is at the "L" level. Figure 13 This is a diagram illustrating an example of the operation of the switch control IC22 when the signal en is "L".

[0234] When the SR flip-flop 57 outputs an "H" level signal IN at time t60, the adjustment circuit 81 outputs "H" level control signals D0 to D2. At this time, the adjustment circuit 81 outputs an "L" level control signal D3.

[0235] In addition, since the signal en is at the "L" level, the second drive circuit 72 stops operating.

[0236] At this point, in state 4, the gate voltage Vg of the PMOS transistor 130 becomes the minimum voltage, and the drive capability of the PMOS transistor 130 becomes the maximum while the on-resistance becomes the minimum. As a result, the voltage Vdr rises with the maximum slope.

[0237] The ratio of the drive voltage to the supply voltage Vcc Figures 9-12 The state described in the text is low, and the state where the gate voltage Vg becomes the minimum voltage sometimes lasts for a long time, and the voltage Vdr transition with two inflection points is not obtained as described during the use of P0~P2.

[0238] Similarly, the driving voltage is proportional to the supply voltage Vcc. Figures 9-12 When the state described in the diagram is low, the gate voltage Vg becomes the minimum voltage state and sometimes lasts for a long time. The second drive circuit 72 sometimes does not operate and does not achieve the voltage Vdr shift that is raised twice as described in P20 to P22 during use.

[0239] At time t61, the adjustment circuit 81 outputs control signals D0 to D1 at the "L" level in state 5.

[0240] At this point, the gate voltage Vg of PMOS transistor 130 becomes higher than the voltage in state 4. Compared to state 4, the driving capability of PMOS transistor 130 decreases, and the on-resistance increases. As a result, the voltage Vdr rises with a smaller slope compared to state 4. Then, when the voltage Vdr reaches the supply voltage Vcc, the voltage Vdr flattens out.

[0241] At time t62, when the SR flip-flop 57 outputs the "L" level signal IN, the adjustment circuit 81 outputs the "L" level control signal D2.

[0242] ===Summary=== The DC-DC converter 10 of this embodiment has been described above. The switch control IC 22 uses a first drive circuit 71 to drive the power transistor 23 via terminal OUT during voltage drive, and uses a second drive circuit 72 with a drive capability less than that of the first drive circuit 71 to drive the power transistor 23 via terminal OUT during current drive. Therefore, the switch control IC 22 can make the rising edge of the voltage Vdr steep, and then gradually change the voltage Vdr to the target voltage. Thus, an integrated circuit that can safely drive the power transistor even when the power supply voltage is high can be provided.

[0243] Furthermore, the control circuit 70 controls the first drive circuit 71 by comparing the voltage Vdr at terminal OUT when the power transistor 23 is turned on with reference voltages VREF2 and VREF3, thereby ensuring that the voltage Vdr remains within a specified range. Therefore, the switch control IC 22 can control the voltage Vdr to keep it within the specified range.

[0244] Furthermore, the control circuit 70 includes a determination circuit 80 for determining whether the voltage Vdr is higher or lower than a specified range, and an adjustment circuit 81 for controlling the voltage drive period based on signals Sup and Sdown. Therefore, the voltage drive period can be controlled, and the voltage Vdr can be controlled to the target voltage.

[0245] Furthermore, the determination circuit 80 determines whether the voltage Vdr is within a specified range, and when the voltage Vdr is within the specified range, the adjustment circuit 81 maintains the voltage drive period. Thus, the switch control IC 22 can maintain the state where the voltage Vdr is within the specified range.

[0246] Furthermore, the second drive circuit 72 drives the power transistor 23 via the current drive period terminal OUT. Therefore, the switch control IC 22 can slowly control the voltage Vdr to the target voltage after the voltage drive period ends.

[0247] Furthermore, the first drive circuit 71 reduces its drive capability during voltage drive. Therefore, the switch control IC 22 increases the drive capability immediately after the signal IN rises, and then reduces the drive capability, thereby enabling the voltage Vdr to be slowly changed to the target voltage while advancing the rise of the voltage Vdr.

[0248] Furthermore, the first drive circuit 71 controls the PMOS transistor 130 during the voltage drive period based on control signals such as D0, and changes the gate voltage Vg during the voltage drive period to increase the on-resistance of the PMOS transistor 130. Therefore, the switch control IC 22 can reduce the drive capability of the PMOS transistor 130, and while advancing the rise of the voltage Vdr, slowly change the voltage Vdr to the target voltage.

[0249] Furthermore, the first driving circuit 71 also includes a Zener diode 132, and the voltage output circuit 101 is a voltage divider circuit that includes a resistor with a resistance value R1a or R1b connected in parallel with the Zener diode 132, and the value of the voltage divider resistor is changed based on a control signal D0, etc., so that a voltage Vg is applied to the gate electrode of the PMOS transistor 130 during voltage driving. Therefore, while the Zener diode 132 protects the PMOS transistor 130, a voltage Vg based on the voltage Vcc can be generated according to the decrease in the current flowing through the Zener diode 132.

[0250] Furthermore, the voltage divider circuit includes a first variable resistor 121 and a second variable resistor 123 connected in parallel with the Zener diode 132, and an NMOS transistor 122 connected between the first variable resistor 121 and the second variable resistor 123 and turned on during voltage driving in order to apply a voltage Vg to the gate electrode of the PMOS transistor 130 during voltage driving. Moreover, the resistance values ​​R1a or R1b of the first variable resistor 121 and R2a, R2b, or R2c of the second variable resistor 123 change during voltage driving based on a control signal D0, etc. Therefore, the switch control IC 22 can change the voltage Vg in stages, advancing the rise of the voltage Vdr while slowly changing the voltage Vdr to the target voltage.

[0251] Furthermore, the voltage output circuit 101 is a voltage divider circuit that applies a voltage Vg generated based on the voltage Vcc to the PMOS transistor 130 based on the control signal D0, etc. Here, by appropriately designing the resistance value of the voltage divider circuit so as not to damage the PMOS transistor 130, the switch control IC 22 can change the voltage Vg in stages without the Zener diode 132, and slowly change the voltage Vdr to the target voltage while advancing the rise of the voltage Vdr.

[0252] Furthermore, the second drive circuit 72 includes a current-pull circuit 140 that outputs a current from terminal OUT corresponding to the difference between the voltage Vdr and a voltage level that is higher than the threshold voltage of power transistor 23 but lower than the withstand voltage of power transistor 23. Therefore, after the voltage drive period ends and PMOS transistor 130 no longer drives terminal OUT, the switch control IC 22 can slowly change the voltage Vdr to the target voltage. Furthermore, by setting the target voltage relatively low, inexpensive power transistors can be used.

[0253] Furthermore, the second drive circuit 72 also includes a current sinking circuit 141, which increases the sinking current drawn through terminal OUT when the voltage Vdr_div becomes higher than the reference voltage VREF1. Therefore, the switch control IC 22 controls the voltage Vdr so that even if the power supply voltage Vcc rises, the voltage Vdr remains within a specified range.

[0254] Furthermore, the enable circuit 54 determines whether the power supply voltage Vcc_div is higher than the reference voltage VREF1 or VREF2 and outputs a signal en. Then, the first drive circuit 71 changes its operation based on the control signal D0, etc., which changes based on the signal en, while the second drive circuit 72 stops operating based on the "L" level signal en. Therefore, when the power supply voltage Vcc decreases and can be used as the voltage Vdr applied to the power transistor 23, the switch control IC 22 can drive the power transistor 23 with the power supply voltage Vcc.

[0255] Furthermore, in this invention, the switch control IC 22 regulates the power supply voltage Vcc. If a suitable power supply voltage for obtaining voltage Vdr can be generated internally, then the switch control IC 22 does not need to regulate the power supply voltage Vcc. This is because the drive circuit 60 can use a suitable power supply voltage. However, in order to generate such a suitable power supply voltage from the power supply voltage Vcc, a suitable power supply voltage (e.g., a constant voltage of about 15V to 20V) needs to be generated from a power supply voltage Vcc with a large actual deviation (e.g., as an auxiliary winding voltage, around 10V to 60V). The voltage regulator used for this purpose has a large area, and components from standard manufacturing processes cannot be used. In addition, since a large-capacity capacitor for stabilization cannot be built in, terminals for connecting external capacitors must be prepared separately from the terminal VCC. By adopting this invention, such a voltage regulator is not required, the cost of the switch control IC 22 can be reduced, and unnecessary voltage regulators can be eliminated.

[0256] In addition, the switch control IC22 is suitable for use with AC-DC converter 10.

[0257] The above embodiments are provided to facilitate understanding of the present invention, but are not intended to limit or explain the present invention. Furthermore, modifications and improvements can be made to the present invention without departing from its spirit, and equivalent inventions are naturally included within the scope of the present invention. Label Explanation

[0258] 101 AC-DC Converter 11 Load 20 Full-wave rectifier circuit 21, 31, 33, 41, 164 capacitors 22 Switch control circuit 23 Power Transistors 24 Transformers Resistors with ratings of 25, 27, 28, 53, 115, 117, 161, and 163. 26, 30, 40 diodes 32 phototransistors 42 Constant Voltage Circuit 43 Light Emitting Diode 50V divider circuit Comparators 51, 59, 62, 90, 91, 160 52 Internal Power Supply 54 Enable Circuit 55 Oscillator 56 Single Trigger Circuit 57 SR trigger 58 voltage divider circuit 60 Drive Circuit 61 Voltage Divider Circuit 63 Inverter 64 D flip-flops Transmission gates 65 and 66 70 Control Circuit 71 First driving circuit 72 Second drive circuit 80 Decision Circuit 81 Adjustment Circuit 92 Timer 93 Logic Circuits 100-level shift circuit 101 Voltage Output Circuit 102 Output Circuit 110, 113, 122, 131, 162 NMOS transistors 111, 112, 130 PMOS transistors Zener diodes 114, 116, and 132 121 First Variable Resistor 123 Second Variable Resistor 140 Current-collecting circuit 141 Current Sinking Circuit 150 AND gate circuit 151 Voltage-controlled current source circuit.

Claims

1. An integrated circuit, The integrated circuit includes an inductor to which a rectified voltage corresponding to an AC voltage is applied and a power transistor for controlling the inductor current flowing through the inductor. The integrated circuit drives the power transistor in a power supply circuit that generates an output voltage of a target level according to the AC voltage. The integrated circuit is characterized by comprising: A first terminal is supplied with a power supply voltage that is generated according to the change in the inductor current and causes the integrated circuit to operate; The second terminal is connected to the control electrode of the power transistor; A first driving circuit drives the power transistor via the second terminal during a first period in order to turn on the power transistor; A second driving circuit drives the power transistor via the second terminal in order to turn it on during a second period, including at least a portion of the first period, and the driving capability of the second driving circuit is smaller than that of the first driving circuit. as well as A control circuit controls the first drive circuit based on the voltage at the second terminal when the power transistor is turned on, ensuring that the voltage at the second terminal remains within a specified range. The control circuit includes: A first determination circuit determines whether the voltage at the second terminal is higher or lower than the specified range; as well as An adjustment circuit, based on the determination result of the first determination circuit, extends the first period when the voltage of the second terminal is lower than the specified range, and shortens the first period when the voltage of the second terminal is higher than the specified range.

2. The integrated circuit as described in claim 1, characterized in that, The first determining circuit also determines whether the voltage at the second terminal is within the specified range. When the voltage at the second terminal is within the specified range, the adjustment circuit maintains the first period.

3. The integrated circuit as described in claim 1 or 2, characterized in that, The second driving circuit drives the power transistor via the second terminal during a second period that includes the first period and is longer than the first period.

4. The integrated circuit as described in claim 1 or 2, characterized in that, The first period has a first sub-period with relatively high driving capability and a second sub-period with relatively low driving capability following the first sub-period.

5. The integrated circuit as described in claim 4, characterized in that, The first driving circuit includes: A first transistor, the first transistor being connected between the first terminal and the second terminal; and A voltage output circuit, which, based on a control signal that turns on the power transistor, applies a control voltage that increases the on-resistance of the first transistor to the control electrode of the first transistor during the first period.

6. The integrated circuit as described in claim 5, characterized in that, The first driving circuit further includes a clamping element connected between the control electrode of the first transistor and the first terminal. The voltage output circuit includes a resistor connected in parallel with the clamping element, and is a voltage divider circuit that changes the value of the voltage divider resistor based on the control signal so that the control voltage is applied to the control electrode during the first period.

7. The integrated circuit as described in claim 6, characterized in that, The voltage divider circuit includes: A first variable resistor is connected in parallel with the clamping element; A second variable resistor; and A second transistor is connected between the first variable resistor and the second variable resistor, and is turned on during the first period in order to apply the control voltage to the control electrode during the first period. The resistance values ​​of the first variable resistor and the second variable resistor change during the first period based on the control signal.

8. The integrated circuit as described in claim 5, characterized in that, The voltage output circuit is a voltage divider circuit that applies a voltage divider obtained by dividing the power supply voltage based on the control signal to the control electrode of the first transistor.

9. The integrated circuit as described in any one of claims 1, 2, 5 to 8, characterized in that, The second driving circuit includes a current-splitting circuit. When the voltage obtained after voltage division of the second terminal is lower than the first level, the current-splitting circuit increases the output of the current-splitting circuit; and when the voltage obtained after voltage division of the second terminal is higher than the first level, the current-splitting circuit stops the output of the current-splitting circuit. The first level is higher than the threshold voltage of the power transistor and lower than the withstand voltage of the power transistor.

10. The integrated circuit as claimed in claim 9, characterized in that, The second driving circuit also includes a current sinking circuit. When the voltage obtained after dividing the voltage at the second terminal is higher than the second level, the current sinking circuit increases the current drawn through the second terminal; when the voltage obtained after dividing the voltage at the second terminal is lower than the second level, the current sinking circuit decreases the current drawn through the second terminal. The second level is higher than the first level and lower than the breakdown voltage of the power transistor.

11. The integrated circuit according to any one of claims 1, 2, 5 to 8, and 10, characterized in that, The system includes a second determination circuit that determines whether the power supply voltage is higher than a specified level. When the power supply voltage is higher than the specified level, the first driving circuit drives the power transistor during a first period; when the power supply voltage is lower than the specified level, the first driving circuit drives the power transistor during a third period corresponding to the target level of the output voltage. When the power supply voltage is higher than the specified level, the second driving circuit drives the power transistor during the second period; when the power supply voltage is lower than the specified level, the second driving circuit stops operating.

12. A power supply circuit that generates a DC voltage based on an AC voltage, characterized in that it comprises: An inductor to which a rectified voltage corresponding to the AC voltage is applied; A power transistor that controls the inductor current flowing through the inductor; as well as An integrated circuit that drives the power transistor. The integrated circuit includes: A first terminal is supplied with a power supply voltage that is generated according to the change in the inductor current and causes the integrated circuit to operate; The second terminal is connected to the control electrode of the power transistor; A first driving circuit drives the power transistor via the second terminal during a first period in order to turn on the power transistor; A second driving circuit drives the power transistor via the second terminal during a second period, including at least a portion of the first period, to turn on the power transistor, and the driving capability of the second driving circuit is smaller than that of the first driving circuit; and A control circuit controls the first drive circuit based on the voltage at the second terminal when the power transistor is turned on, ensuring that the voltage at the second terminal remains within a specified range. The control circuit includes: A first determination circuit determines whether the voltage at the second terminal is higher or lower than the specified range; and An adjustment circuit, based on the determination result of the first determination circuit, extends the first period when the voltage of the second terminal is lower than the specified range, and shortens the first period when the voltage of the second terminal is higher than the specified range.

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