Switching circuit with parallel transistor stacks and method of operation thereof

Abstract

The invention relates to a switching circuit having parallel transistor stacks and a method of operation thereof. A switching circuit includes a first transistor stack and a second transistor stack coupled in parallel between a first port and a second port. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variable conduction path between the first and second ports. Each transistor of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variable conduction path between the first and second ports. Each transistor of the second plurality of transistors has a gate terminal coupled to a second control terminal. When implemented in a transceiver, a first driver and a second driver are configured to simultaneously configure the first and second variable conduction paths to a low impedance state.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to RF switches and methods for operating such RF switches. Background Technology

[0002] Radio frequency (RF) switches are commonly used in communication transceivers to selectively connect transmitter and receiver circuitry to antennas or other communication components. To configure the transceiver for transmit mode, the RF switch is controlled to provide a signal path between the transmitter and antenna ports of the RF switch, while simultaneously establishing a high impedance (e.g., an open circuit) between the antenna and receiver ports of the RF switch. Conversely, to configure the transceiver for receive mode, the RF switch is controlled to provide a signal path between the antenna and receiver ports, while simultaneously establishing a high impedance (e.g., an open circuit) between the transmitter and antenna ports.

[0003] Some RF switches incorporate stacks of field-effect transistors (FETs) (i.e., a series-coupled arrangement) between their transmit, receive, and antenna ports to achieve higher power handling capabilities. However, in high-power switches involving relatively large FET stacks, the settling time associated with switching between transmit and receive states can be relatively slow, thus limiting system performance. Therefore, what is needed are RF switches characterized by faster settling times when compared to conventional RF switches. Summary of the Invention

[0004] According to a first aspect of the present invention, a switching circuit is provided, comprising:

[0005] First port;

[0006] Second port;

[0007] A first transistor stack coupled between the first port and the second port, wherein the first transistor stack includes a plurality of first transistors series coupled between the first port and the second port to provide a first variable conduction path between the first port and the second port, and wherein each of the plurality of first transistors has a gate coupled to a first control terminal; and

[0008] A second transistor stack coupled in parallel with the first transistor stack between the first port and the second port, wherein the second transistor stack includes a second plurality of transistors coupled in series between the first port and the second port to provide a second variable conduction path between the first port and the second port, and wherein each of the second plurality of transistors has a gate terminal coupled to a second control terminal.

[0009] In one or more embodiments, the switching circuit further includes:

[0010] A first driver, coupled to the first control terminal; and

[0011] A second driver is coupled to the second control terminal, wherein the first driver and the second driver are configured to simultaneously turn on or off the first plurality of transistors and the second plurality of transistors.

[0012] In one or more embodiments, the switching circuit further includes:

[0013] The third port; and

[0014] A third transistor stack coupled between the first port and the third port, wherein the third transistor stack includes a third plurality of transistors coupled in series between the first port and the third port, and wherein each of the third plurality of transistors has a gate terminal coupled to a third control terminal.

[0015] In one or more embodiments, the switching circuit further includes:

[0016] A fourth transistor stack coupled between the third port and the ground reference node, wherein the fourth transistor stack includes a fourth plurality of transistors coupled in series between the third port and the ground reference node, and wherein each of the fourth plurality of transistors has a gate terminal coupled to a fourth control terminal.

[0017] In one or more embodiments, the switching circuit further includes:

[0018] A fifth transistor stack coupled between the third port and the ground reference node, wherein the fifth transistor stack includes a fifth plurality of transistors coupled in series between the third port and the ground reference node, and wherein each of the fifth plurality of transistors has a gate terminal coupled to a fifth control terminal.

[0019] In one or more embodiments, the first transistor stack and the second transistor stack form part of a first branch between the first port and the second port, and the switching circuit further includes:

[0020] Third port;

[0021] A second branch coupled between the first port and the third port;

[0022] The third branch coupled between the second port and the ground reference node; and

[0023] A fourth branch is coupled between the third port and the ground reference node.

[0024] In one or more embodiments, each of the first plurality of transistors and the second plurality of transistors is a field-effect transistor.

[0025] In one or more embodiments, each of the first plurality of transistors and the second plurality of transistors is a multi-gate field-effect transistor.

[0026] According to a second aspect of the present invention, a transceiver is provided, comprising:

[0027] Switching circuit, which includes

[0028] First port,

[0029] Second port,

[0030] Third port,

[0031] A first transistor stack coupled between the first port and the second port, wherein the first transistor stack includes a plurality of first transistors series coupled between the first port and the second port to provide a first variable conduction path between the first port and the second port, and wherein each of the plurality of first transistors has a gate coupled to a first control terminal.

[0032] A second transistor stack coupled in parallel with the first transistor stack between the first port and the second port, wherein the second transistor stack includes a second plurality of transistors series coupled between the first port and the second port to provide a second variable conduction path between the first port and the second port, and wherein each of the second plurality of transistors has a gate terminal coupled to a second control terminal, and

[0033] A third transistor stack coupled between the second port and the third port, wherein the third transistor stack includes a third plurality of transistors coupled in series between the second port and the third port to provide a third variable conduction path between the second port and the third port, and wherein each of the third plurality of transistors has a gate terminal coupled to a third control terminal.

[0034] In one or more embodiments, the first port is coupled to one of a receiver or a transmitter;

[0035] The second port is coupled to the antenna; and

[0036] The third port is coupled to either the transmitter or the receiver.

[0037] In one or more embodiments, the transceiver further includes:

[0038] A circulator having a first, second, and third circulator port, wherein the first circulator port is coupled to a transmitter, the second circulator port is coupled to the second port of the switching circuit, and the third circulator port is coupled to an antenna.

[0039] In one or more embodiments, the transceiver further includes:

[0040] A switch controller configured to simultaneously configure the first and second variable conduction paths to a low-impedance state and the third variable conduction path to a high-impedance state.

[0041] In one or more embodiments, the switch controller includes:

[0042] A first driver, coupled to the first control terminal; and

[0043] A second driver coupled to the second control terminal, wherein the first driver and the second driver are configured to simultaneously configure the first variable conduction path and the second variable conduction path to the low impedance state.

[0044] In one or more embodiments, the transceiver further includes:

[0045] A fourth transistor stack coupled between the first port and a ground reference node, wherein the fourth transistor stack includes a fourth plurality of transistors series coupled between the first port and the ground reference node to provide a fourth variable conduction path between the first port and the ground reference node, and wherein each of the fourth plurality of transistors has a gate coupled to a fourth control terminal; and

[0046] A fifth transistor stack coupled between the third port and the ground reference node, wherein the fifth transistor stack includes a fifth plurality of transistors coupled in series between the third port and the ground reference node to provide a fifth variable conduction path between the third port and the ground reference node, and wherein each of the fifth plurality of transistors has a gate terminal coupled to a fifth control terminal.

[0047] In one or more embodiments, the transceiver further includes:

[0048] A switch controller configured to simultaneously configure the first, second, and fifth variable conduction paths to a low-impedance state and the third and fourth variable conduction paths to a high-impedance state.

[0049] In one or more embodiments, the transceiver is encapsulated in a surface mount package.

[0050] In one or more embodiments, the transceiver is configured as a printed circuit board module.

[0051] According to a third aspect of the present invention, a method for operating a switching circuit is provided, the method comprising:

[0052] A switch controller simultaneously configures a first variable conduction path and a second variable conduction path of a switching circuit to a low-impedance state, wherein the first and second variable conduction paths are coupled in parallel between a first port and a second port of the switching circuit, and wherein the switching circuit further includes

[0053] A first transistor stack coupled between the first port and the second port, wherein the first transistor stack includes a plurality of first transistors series coupled between the first port and the second port to provide the first variable conduction path, and

[0054] A second transistor stack coupled in parallel with the first transistor stack between the first port and the second port, wherein the second transistor stack includes a second plurality of transistors coupled in series between the first port and the second port to provide the second variable conduction path.

[0055] In one or more embodiments, the configuration includes:

[0056] A first control signal is provided by a first driver to a first control terminal, the first control terminal being coupled to the gate terminal of one of the first plurality of transistors; and

[0057] While providing the first control signal, a second driver provides a second control signal to a second control terminal, which is coupled to the gate terminal of the transistor in the second plurality of transistors.

[0058] In one or more embodiments, the method further includes:

[0059] While configuring the first and second variable conduction paths, the switch controller also configures the third variable conduction path of the switch circuit to a high-impedance state, wherein the third variable conduction path is coupled between the second port and the third port of the switch circuit.

[0060] These and other aspects of the invention will become apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description

[0061] A more complete understanding of the subject matter can be obtained by considering the following figures and referring to the specific embodiments and claims, where similar reference numerals refer to similar elements in each figure.

[0062] Figure 1 This is a simplified block diagram of an embodiment of a radio frequency (RF) transceiver system;

[0063] Figure 2 This is a simplified block diagram of another embodiment of the RF transceiver system;

[0064] Figure 3 This is an embodiment based on the example. Figure 1 or Figure 2 A top view of a surface-mount device, part of an RF transceiver system;

[0065] Figure 4 This is an embodiment based on the example. Figure 1 or Figure 2 A top view of a module that is part of an RF transceiver system;

[0066] Figure 5 This is a simplified circuit diagram of an RF switch having a stack of transistors in parallel in all branches according to an embodiment;

[0067] Figure 6 This is a simplified circuit diagram of an RF switch having a parallel transistor stack in a branch subgroup according to an embodiment;

[0068] Figure 7 According to the embodiments Figure 6 More detailed circuit diagram of the RF switch;

[0069] Figure 8 This is an embodiment based on the example. Figure 7 A top view of a monolithic RF switch integrated circuit (IC);

[0070] Figure 9 This is a simplified circuit diagram of the single-gate FET and associated circuit system according to an embodiment;

[0071] Figure 10 A simplified circuit diagram of a multi-gate FET and associated circuitry system according to another embodiment; and

[0072] Figure 11 This is a flowchart of a method for operating an RF switch in an RF transceiver according to an embodiment. Detailed Implementation

[0073] Embodiments of the subject matter of this invention include radio frequency (RF) switches and transceivers for cellular base stations or other applications. In various embodiments, an RF switch includes at least one branch having multiple FET stacks arranged in parallel between switch ports (e.g., between a transmit port and an antenna port, between an antenna port and a receive port, and / or between a ground reference and a transmit port and / or a receive port). During operation, the RF signal transmitted through the branch with the parallel FET stacks is segmented and therefore has relatively low power in each stack. Therefore, given the same signal power transmitted through the branch, the FETs in the parallel FET stacks may be smaller in peripheral respects compared to a conventional RF switch that includes only a single FET stack in the branch between switch ports. Furthermore, since the relatively small FETs have lower gate capacitance, the time constant of the relatively small FETs is also smaller than the time constant of the larger corresponding FETs. Therefore, the settling time associated with switching between transmit and receive states can be relatively fast when using embodiments of various embodiments, compared to the settling time of a conventional RF switch. This allows the system to support increasingly faster switching speeds between send and receive modes, and consequently, higher data throughput.

[0074] Before describing the RF switch embodiments in detail, in conjunction with Figures 1 to 4 Examples of systems, apparatuses, and modules in which such RF switch embodiments may be implemented are described. It should be understood that the RF switch embodiments described later can be implemented in a wide variety of other systems, apparatuses, modules, and circuits. Therefore, Figures 1 to 4 The example systems, devices, and modules shown should not be construed as limiting the scope of the subject matter of this invention.

[0075] Figure 1 This is a simplified block diagram of an example of an RF transceiver system 100, including an RF switch 110, a transmitter 120, a receiver 130, an antenna 140, and an RF switch controller 150. The transceiver system 100 is a half-duplex transceiver, wherein at any given time, only one of the transmitter 120 or the receiver 130 is coupled to the antenna 140 via the RF switch 110. More specifically, the state of the RF switch 110 is controlled by the RF switch controller 150 to alternate between coupling the RF transmit signal generated by the transmitter 120 to the antenna 140 or coupling the RF receive signal received by the antenna 140 to the receiver 130.

[0076] Transmitter 120 may include, for example, a transmit (TX) signal processor 122 and a power amplifier 124. Transmit signal processor 122 is configured to generate a transmit signal and provide the transmit signal to power amplifier 124. Power amplifier 124 amplifies the transmit signal and provides the amplified transmit signal to RF switch 110. Receiver 130 may include, for example, a receive amplifier 132 (e.g., a low-noise amplifier) ​​and a receive (RX) signal processor 134. Receive amplifier 132 is configured to amplify a relatively low-power signal received from RF switch 110 and provide the amplified received signal to receive signal processor 134. Receive signal processor 134 is configured to use or process the received signal.

[0077] During each transmission time interval, when transceiver 100 is in "transmit mode", RF switch controller 150 controls RF switch 110 to be in the following state: Figure 1 The first or "transmit" state depicted in the diagram establishes a conducted transmit signal path between transmitter node 128 and antenna node 148, and the receive signal path between antenna node 148 and receiver node 138 is in a high-impedance state (e.g., open circuit). Conversely, during each receive time interval, when transceiver 100 is in "receive mode," RF switch controller 150 controls RF switch 110 to be in a second or "receive" state, wherein a conducted transmit signal path is established between antenna node 148 and receiver node 138. Figure 1 The dashed line in the diagram indicates the conducted received signal path, and the transmitted signal path between transmitter node 128 and antenna node 148 is in a high impedance state (e.g., open circuit).

[0078] According to an embodiment, the RF switch controller 150 includes up to n drivers D1 151 to Dn 152. As will be described in more detail later, n is a parallel switch or FET stack in any branch of the RF switch 110 (e.g., Figures 5 to 7 The maximum number of parallel switches 531 / 532, 525 / 526, 631 / 632, 625 / 626, and each driver 151 to 152 is used to turn on and off the FETs in a given stack (i.e., to turn the FET channel on or off). According to the embodiment, n can be any integer between 2 and 5, but n can also be greater than 5.

[0079] Figure 2This is a simplified block diagram of another example of an RF transceiver system 200, including an RF switch 210, a circulator 216, a transmitter 220, a receiver 230, an antenna 240, and an RF switch controller 250. The transmitter 220 and receiver 230 are coupled to the antenna 240 via the circulator 216. More specifically, the circulator 216 is a three-port device having a first port 217 coupled to the transmitter 220, a second port 218 coupled to the receiver 230 via the RF switch 210, and a third port 219 coupled to the antenna 240. The RF switch 210 is also a three-port device having a first port 248 coupled to the receiver port 218 of the circulator 216, a second port 238 coupled to the receiver 230, and a third port 228 coupled to a ground reference node 254 via a resistor 256.

[0080] Similarly, transmitter 220 may include, for example, a TX signal processor 222 and a power amplifier 224. The TX signal processor 222 is configured to generate a transmit signal and provide it to the power amplifier 224. The power amplifier 224 amplifies the transmit signal and provides the amplified transmit signal to antenna 240 via circulator 216. Receiver 230 may include, for example, a receive amplifier 232 (e.g., a low-noise amplifier) ​​and an RX signal processor 234. The receive amplifier 232 is configured to amplify (via circulator 216 and RF switch 210) a relatively low-power received signal from antenna 240 and provide the amplified received signal to receive signal processor 234. Receive signal processor 234 is configured to use or process the received signal.

[0081] Circulator 216 is characterized by the signal conduction directionality indicated by the arrows within the drawing of circulator 216. Essentially, the RF signal is transmitted between circulator ports 217 and 219 in the indicated direction (counter-clockwise) rather than the opposite direction (clockwise). Therefore, during normal operation, signals can be transmitted through circulator 216 from transmitter port 217 to antenna port 219 and from antenna port 219 to receiver port 218, but not directly from transmitter port 217 to receiver port 218 or from receiver port 218 to antenna port 219.

[0082] In some cases, when transceiver 200 is in transmit mode, circulator 216 may be unable to transmit signal energy received through transmitter port 217 from transmitter 220 to antenna 240 via antenna port 219. For example, antenna 240 may be disconnected from antenna port 219 or may otherwise be in a state of extremely high impedance. In such cases, circulator 216 may transmit signal energy from transmitter 220 (i.e., signal energy received through transmitter port 217) via antenna port 219 to receiver port 218. To prevent the transmission of transmitter signal energy to receiver 230 when transceiver 200 is in transmit mode, RF switch controller 250 operates RF switch 210 as a fault-protected switch by coupling first port 248 to ground reference node 254.

[0083] More specifically, when transceiver 200 is in receive mode, RF switch 210 is controlled by RF switch controller 250 to be in receive state, such as... Figure 2 As shown in the diagram. In the receive state, the receiver port 218 of the circulator 216 is coupled to the receiver 230 via the RF switch 210 (i.e., the RF switch controller 250 configures the RF switch 210 to have a conductive path between ports 248 and 238, and a high-impedance open-circuit condition between ports 248 and 228). Conversely, when the transceiver 200 is in the transmit mode, the RF switch 210 is controlled by the RF switch controller 250 to be in the transmit state, wherein the receiver port 218 of the circulator 216 is coupled to the ground terminal 254 via the RF switch 210 through the resistor 256 (i.e., the RF switch controller 250 configures the RF switch 210 to have a high-impedance open-circuit condition between ports 248 and 228). Figure 2 The dashed lines in the diagram indicate the conduction path and the open-circuit condition with high impedance between ports 248 and 238. Therefore, if transmitter signal energy bypasses antenna port 219 when transceiver 200 is in transmit mode, any signal energy transmitted to RF switch 210 via receiver port 218 of circulator 216 will be shunt to ground terminal 254 via port 228 of RF switch 210.

[0084] According to an embodiment, the RF switch controller 250 includes up to n drivers D1 251 to Dn 252. Again, as will be described in more detail later, n is the parallel FET stack in any branch of the RF switch 210 (e.g., ...). Figure 7 The maximum number of FET stacks (631 / 632 or 625 / 626) and each driver 251 to 252 is used to turn on and off the FETs in a given stack (i.e., to make the FET channel present as on or off). According to the embodiment, n can be any integer between 2 and 5, but n can also be greater than 5.

[0085] RF transceiver system 100, 200 ( Figure 1 , 2 A variety of active and passive electrical devices may be physically implemented, which may be housed in one or more device packages and / or on one or more printed circuit boards (PCBs) and / or other substrates. More specifically, various components of the RF transceiver systems 100, 200 may be implemented in self-contained modules or electrical devices that may be coupled to a substrate that electrically connects the module / device to other parts of the RF transceiver systems 100, 200. As used herein, the term "module" means a group of active and / or passive electrical devices (e.g., ICs and components) physically contained within a single housing (e.g., the devices are coupled to a common "module substrate" or a single device package). A "module" also includes multiple conductive terminals for electrically connecting the group of devices to external circuitry forming other parts of the electrical system. Essentially, the module substrate configuration, the method of coupling devices to the terminals of the module, and the number of devices within the module define the module type. For example, in various embodiments, the module may take the form of a PCB-based system, a surface mount device, a chip carrier device, a ball, pin, or pad grid array device, a flat package device (e.g., a square or double flat package), a chip-scale package device, a system-in-package (SIP) device, or some other type of integrated circuit package. Although the following is combined with... Figure 3 and 4 Two specific types of modules / devices are described, but it should be understood that embodiments of the subject matter of this invention may also be included in other types of modules / devices.

[0086] For example, Figure 3 This is an embodiment based on the example. Figure 1 A top view of device 300, a part of the RF transceiver system 100. More specifically, Figure 3 The transceiver portion is shown to be packaged in a surface mount package. Device 300 is packaged as a quad flat no-lead (QFN) device, which includes a conductive pad 302 in a fixed spatial relationship with a non-conductive encapsulation 303 (e.g., a plastic encapsulation) and multiple terminals (e.g., terminals 328, 338, 348, 352, 360, 361, 362). Device 300 also includes multiple ICs coupled to the conductive pad 302, including an RF switch integrated circuit (IC) 310 (e.g., embodying...). Figure 1 The RF switch 110 IC and the receiver amplifier IC 332 (e.g., Figure 1 The receiver amplifier 132), receiver matching circuit IC 334, and RF switch controller IC 350 (e.g., embodying...) Figure 1 The IC of the RF switch controller 150 in the device 300. Additionally, the device 300 includes a transmit signal input terminal 328 (e.g., corresponding to...). Figure 1 The transmitter node 128), the receiver signal output terminal 338 (for example, corresponding to the transmitter node 128), and the receiver signal output terminal 338 (for example, corresponding to the transmitter node 128). Figure 1 Receiver node 138) Antenna end 348 (e.g., corresponding to Figure 1 It includes an antenna terminal 148, a transmit / receive (TX / RX) control signal terminal 352, one or more ground terminals 360, 361, and one or more power supply terminals 362.

[0087] The individual ICs 310, 332, 334, 350 and terminals 328, 338, 348, 352, 360 to 362 are electrically connected together via multiple bonding wires (e.g., bonding wire 370). In other embodiments, the individual ICs 310, 332, 334, 350 and terminals 328, 338, 348, 352, 360 to 362 may be electrically connected together using other conductive structures. In various embodiments, device 300 may be housed in an air-cavity package or an overmolded (e.g., encapsulated) package, but device 300 may also be considered complete without such a package.

[0088] When device 300 is incorporated into a transceiver system (e.g., Figure 1 After the system 100 is connected, and during operation of the transceiver system, power and ground reference voltages are provided to device 300 via power and ground terminals 360 to 362. RF switch controller IC 350 receives transmit / receive mode control signals via control signal terminal 352. Based on the received mode control signals, RF switch controller IC 350 provides switch control signals to or "drives" various transistors of RF switch IC 310 (e.g., ...). Figures 5 to 8 The control terminal (e.g., the gate) of the transistors in branches 520, 524, 530, 534, 620, 624, 630, 634, 820, 824, 830, and 834. As will be described in more detail later, the switch control signal determines whether each of the various transistors is in a conducting state or a non-conducting state at any given time. More specifically, the switch control signal determines whether the RF switch IC 310 is in a transmitting state (i.e., the state in which the switch is configured to transmit an RF signal from the transmitter 120 to the antenna 140) or a receiving state (i.e., the state in which the switch is configured to transmit an RF signal from the antenna 140 to the receiver 130) at any given time.

[0089] When the switch control signal configures the RF switch IC 310 to transmit mode, the RF switch IC 310 transmits the signal from the power amplifier (e.g., ...) through the transmit signal input terminal 328. Figure 1The transmit signal received by the power amplifier 332 (RF switch IC 310) passes through the RF switch IC 310 to the antenna terminal 348. Conversely, when the switch control signal puts the RF switch IC 310 into the receive state, the signal received from the antenna terminal 348 passes through the RF switch IC 310 to the receive matching circuit IC 334. The receive matching circuit IC 334 may include one or more integrated passive devices (e.g., capacitors, inductors, and / or resistors). The integrated passive devices, together with the inductance of the bonding wire 370 between the receive matching circuit IC 334, the RF switch IC 310, and the receive amplifier IC 332, form an impedance matching circuit between the RF switch IC 310 and the receive amplifier IC 332. In an alternative embodiment, the receive matching circuit IC 334 may be replaced by discrete components. In either case, the impedance matching circuit may also perform filtering of the received signal that is passed from the RF switch IC 310 to the receive amplifier IC 332 through the impedance matching circuit. The receiver amplifier IC 332 receives the received signal from the receiver matching circuit IC 334 and amplifies the received signal. The receiver amplifier IC 332 then provides the amplified received signal to the receive signal output terminal 338.

[0090] Figure 4 This is an embodiment based on the example. Figure 2 A perspective view of module 400, a part of the RF transceiver system 200. More specifically, Figure 4 The transceiver portion shown can be configured as a printed circuit board (PCB) module. Components of module 400 are mounted (or coupled to) a system substrate 402, which may be, for example, a multilayer PCB or other type of substrate. More specifically, module 400 includes multiple ICs and devices coupled to system substrate 402, including a transmit amplifier module 424 (e.g., embodying...). Figure 2 The RF amplifier 224 module), RF switch and receiver amplifier module 410 (e.g., embodying Figure 2 The module of RF switch 210 and receiver amplifier 232), circulator 416 (e.g., Figure 2 The circulator 216) and the RF switch controller IC 450 (e.g., embodying Figure 2 The RF switch controller 250 IC). Additionally, the device 400 includes a transmit signal input connector 420 (e.g., corresponding to...). Figure 2 The input of amplifier 224), and the receive signal output connector 430 (e.g., corresponding to the input of amplifier 224). Figure 2 The output of amplifier 232) and antenna connector 440 (e.g., corresponding to Figure 2(Input of antenna 240). Various ICs, devices and connectors 410, 416, 420, 424, 430, 440, 450 are electrically connected together through multiple conductive traces on and inside the system substrate 402.

[0091] When module 400 is incorporated into the transceiver system (e.g., Figure 2 After entering system 200, and during operation of the transceiver system, power and ground reference voltages are provided to device 400 via power and ground terminals (unnumbered). RF switch controller IC 450 receives transmit / receive mode control signals via control signal terminals (unnumbered). Based on the received mode control signals, RF switch controller IC 450 provides switch control signals to the RF switch IC (e.g., within RF switch and receive amplifier module 410). Figure 2 Various transistors (e.g., RF switch 210) of the RF switch 210 Figures 5 to 8 The control terminal (e.g., gate) of the transistors in branches 520, 524, 530, 534, 620, 624, 630, 634, 820, 824, 830, and 834. As will be described in more detail later, the switch control signal determines whether each of the various transistors is in an on or off state at any given time. More specifically, the switch control signal determines whether the RF switch within module 410 is in a transmit or receive state at any given time. When the RF switch is in the transmit state, the RF switch is configured to transmit an RF signal from circulator 416 to a ground reference terminal (e.g., ...). Figure 2 Node 254). When the RF switch is in the receive state, the RF switch is configured to transmit the RF signal from the circulator 416 to the receive amplifier within the module 410 (e.g., Figure 2 Amplifier 232).

[0092] Based on the description herein, those skilled in the art will understand that, although Figure 1 The transceiver 100 in Figure 3 The embodiment shown is a surface-mount device (i.e., Figure 3 The transceiver 100 can be implemented as a PCB-based module (e.g., similar to the QFN device 300), but alternatively, the transceiver 100 can be implemented as a PCB-based module (e.g., similar to the QFN device 300). Figure 4 (PCB-based module 400). Similarly, based on the description herein, those skilled in the art will understand that, although Figure 2 The transceiver 200 in Figure 4 The diagram shows a PCB-based module (i.e., Figure 4 Module 400), but alternatively, transceiver 200 may be implemented as a surface-mount device (e.g., similar to...). Figure 3 (QFN device 300). Transceivers 100 and 200 may also be implemented and / or packaged in other forms.

[0093] The following discussion concerns RF switches (e.g., Figure 1 , 2 Details of embodiments of the RF switches 110, 210. Specifically, Figure 5 This is a simplified circuit diagram of RF switch 500 according to an embodiment. RF switch 500 may provide RF switch 110 ( Figure 1 ) and / or RF switch 210 ( Figure 2 The RF switch 500 includes multiple input / output (I / O) ports, including a first port 528 (e.g., Figure 1 , 2 Ports 128 and 228), and the second port 538 (for example, Figure 1 , 2 Ports 138 and 238), and the third port 548 (for example, Figure 1 , 2 Ports 148 and 248) and reference voltage ports 552 and 553.

[0094] Furthermore, the RF switch 500 includes multiple “branches” 520, 524, 530, and 534 electrically coupled between various ports 528, 538, 548, 552, and 553. As used herein, a switch “branch” includes a switching circuit system connected between any two ports of the RF switch. Thus, the RF switch 500 is shown as including four branches, wherein the first branch 520 (“TX series branch”) includes the switching circuit system between ports 528 and 548, the second branch 524 (“TX shunt branch”) includes the switching circuit system between ports 528 and 552, the third branch 530 (“RX series branch”) includes the switching circuit system between ports 538 and 548, and the fourth branch 534 (“RX shunt branch”) includes the switching circuit system between ports 538 and 553.

[0095] According to the illustrated embodiment, each branch 520, 524, 530, 534 includes multiple parallel-coupled "switches" 521 / 522, 525 / 526, 531 / 532, 535 / 536. Figure 5 and 6 In the context of this document, when applied to each of elements 521, 522, 525, 526, 531, 532, 535, 536, 622, 625, 626, 631, 632, and 635, the term "switch" may mean a single active switching device (e.g., a single FET) or multiple active switching devices (e.g., multiple FETs) series coupled between the two ports of an RF switch, and thus includes a "stack" or "FET stack" of FET switches, as will be defined below. Figure 5In the embodiments shown, each branch 520, 524, 530, 534 is shown to include two parallel-coupled switches. However, as indicated by the ellipses between each group of parallel-coupled switches, each branch 520, 524, 530, 534 may include more than two parallel-coupled switches. For example, each branch 520, 524, 530, 534 may include 2 to n branches, where n can be any integer between 2 and 5. In other embodiments, n may be greater than 5. As will be described in more detail later, the maximum number of parallel-coupled switches in any branch 520, 524, 530, 534 is equal to the number of drivers in the RF switch controller (e.g., Figure 1 , 2 The number of drives 151, 152, 251, 252.

[0096] In some embodiments, the number of parallel-coupled switches in each branch 520, 524, 530, 534 may be the same (e.g., each branch 520, 524, 530, 534 may include two parallel-coupled switches). In other embodiments, the number of parallel-coupled switches in each branch 520, 524, 530, 534 may be different (e.g., branches 520 and 534 may each include two parallel-coupled switches, and branches 524 and 530 may each include three parallel-coupled switches). In other embodiments, some branches may include multiple parallel-coupled switches, while other branches may include only a single switch.

[0097] For example, Figure 6 This is a simplified circuit diagram of an RF switch 600 according to an embodiment, where only the subgroups of branches 624 and 630 have parallel switches while the other branches 620 and 634 include only a single switch. In the embodiment, similar to RF switch 500 ( Figure 5 The RF switch 600 also includes multiple I / O ports, including the first port 628 (e.g., Figure 1 , 2 Ports 128 and 248), and port 638 (for example, Figure 1 , 2 Ports 138 and 238), and the third port 648 (for example, Figure 1 , 2 Ports 148 and 228) and reference voltage ports 652 and 653.

[0098] According to the illustrated embodiment, each of branches 620 and 634 includes only a single switch 622, 635, while each of branches 624 and 630 includes multiple parallel-coupled switches 625 / 626, 631 / 632. Figure 6In the embodiments shown, each branch 624, 630 is shown to include two parallel-coupled switches. However, as indicated by the ellipses between each group of parallel-coupled switches, each branch 624, 630 may include more than two parallel-coupled switches. For example, each branch 624, 630 may include 2 to n parallel-coupled switches, where n can be any integer between 2 and 5. In other embodiments, n may be greater than 5. As will be described in more detail later, the maximum number of parallel-coupled switches in any branch 624 or 630 may be equal to the number of drivers in the RF switch controller (e.g., Figure 1 , 2 The number of drivers 151, 152, 251, 252. In addition, the number of parallel-coupled switches in branches 624 and 630 may be equal or unequal.

[0099] although Figure 6 The diagram illustrates parallel-coupled switches 625 / 626 and 631 / 632 in two specific branches 624 and 630. However, in other embodiments, the parallel-coupled switches may be implemented only in a single branch (e.g., only branches 620, 624, 630, or 634), with each other branch comprising only a single switch. In other embodiments, the parallel-coupled switches may be implemented in another subgroup of branches (e.g., in branches 620 / 624, 620 / 630, 620 / 634, 620 / 624 / 630, 620 / 624 / 634, 620 / 630 / 634, 624 / 634, or 630 / 634), with each other branch comprising only a single switch. Regardless of the approach, in some embodiments, the number of parallel-coupled switches in each branch may be the same, while in other embodiments, the number of parallel-coupled switches in each branch may be different.

[0100] If, for example, any of the RF switches 500 and 600 are implemented in Figure 1 In transceiver 100, ports 528 / 628 may correspond to port 128 and are therefore coupled to transmitter 120. Ports 538 and 638 may correspond to port 138 and are therefore coupled to receiver 130. Ports 548 and 648 may correspond to port 148 and are therefore coupled to antenna 140. Finally, ports 552, 553, 652, and 653 may be coupled to a ground reference node. In an alternative embodiment, if any of the RF switches 500 and 600 is implemented in Figure 1 In the transceiver, ports 528 / 628 can correspond to port 138 and are therefore coupled to receiver 130, while ports 538 and 638 can correspond to port 128 and are therefore coupled to transmitter 120.

[0101] Conversely, if, for example, any one of the RF switches 500 or 600 is implemented in Figure 2 In transceiver 200, ports 548 / 648 may correspond to port 248 and are therefore coupled to receiver port 218 of circulator 216. Ports 538 and 638 may correspond to port 238 and are therefore coupled to receiver 230. Ports 528 and 628 may correspond to port 228 and are therefore coupled to ground reference node 254 via resistor 256. Finally, ports 552, 553, 652, and 653 may also be coupled to ground reference node. In an alternative embodiment, if any of the RF switches 500 and 600 are implemented in Figure 2 In the transceiver, ports 528 / 628 can correspond to port 238 and are therefore coupled to receiver port 218 of circulator 216, while ports 538 and 638 can correspond to port 228 and are therefore coupled to ground reference node 254 via resistor 256.

[0102] To illustrate the various aspects of the subject matter of this invention in more detail, Figure 7 Describing corresponds to Figure 6 Detailed circuit diagrams of embodiments of RF switch 600 and RF switch 700. Figure 7 In, corresponding to Figure 6 The same elements in the figures have the same reference numerals (e.g., ports 628, 638, 648, 652, 653, branches 620, 624, 630, 634, and switches 622, 625, 626, 631, 632, 635).

[0103] As used herein, the terms “stack” and “FET stack” refer to multiple FETs coupled in series (or “series coupled”) between two ports of an RF switch. Each stack can be considered a “switch” or a “variable conduction path” because the signal conduction through the stack (or more specifically, through the series connection of the channels of the FETs in the stack) can be based on the stack control terminals (e.g., Figure 7 The stack (or switch or variable conduction path) is controlled or altered (i.e., increased or decreased) by control signals provided at terminals 722, 725, 726, 731, 732, and 735. In other words, based on control signals provided at the stack control terminals, the stack (or switch or variable conduction path) can be placed in a low-impedance (e.g., closed) state or a high-impedance (e.g., open) state. Furthermore, the terms "series coupling" and "series coupling" regarding the electrical coupling between multiple FETs in the stack mean that the conductive terminals (e.g., source / drain terminals) of multiple FETs are connected together to provide a continuous conductive channel / path between a first port (e.g., port 628) and a second port (e.g., port 648) when the multiple FETs are in a conducting state (e.g., "on" or "off").

[0104] According to an embodiment, in Figures 5 to 7 In this configuration, each switch 521, 522, 525, 526, 531, 532, 535, 536, 622, 625, 626, 631, 632, 635 is implemented as an electrically coupled FET 701 to 703, 704 to 706, 707 to 709, 710 to 712, 713 to 715, 716 to 718 in a stack with series coupling between two ports. This is in contrast to a configuration consisting of only a single switch (e.g., ...). Figure 6 , 7 In branches 620 and 634, a single stack of series-coupled FETs is electrically coupled between the respective ports, while in branches including multiple parallel-coupled switches (e.g., branches 520, 524, 530, 534, 624, 630), multiple stacks of series-coupled FETs are electrically coupled between the respective ports.

[0105] according to Figure 6 and 7 In the embodiment shown, branch 620 includes a single switch 622, which can be implemented as a first stack of FETs 701, 702, 703 electrically coupled in series between ports 628 and 648. Branch 624 includes two parallel-coupled switches 625, 626, which can be implemented as a second and third stack of FETs 704, 705, 706 and 707, 708, 709 electrically coupled in series between ports 628 and 652, respectively. Branch 630 also includes two parallel-coupled switches 631, 632, which can be implemented as a fourth and fifth stack of FETs 710, 711, 712 and 713, 714, 715 electrically coupled in series between ports 638 and 648, respectively. Finally, branch 634 includes a single switch 635, which may be implemented as a sixth stack of FETs 716, 717, and 718 electrically coupled in series between port 638 and port 653. When incorporated into a larger electrical system, ports 652 and 653 are typically coupled to a ground reference (e.g., zero volts), but alternatively, ports 652 and 653 may also be coupled to a positive or negative DC reference voltage.

[0106] Each FET 701 to 718 includes a source terminal (e.g., terminal 771 of FET 701), a drain terminal (e.g., terminal 781 of FET 701), and a gate terminal (e.g., gate terminal 761 of FET 701). The conductivity of the variable conduction channel between the source and drain terminals of any given FET is controlled by a control signal provided to the gate terminal (e.g., terminal 761) of the FET. Some (and possibly all) of the FETs discussed above may be “single-gate FETs,” but some or all of the FETs may also be multi-gate FETs. Essentially, as will be combined Figure 9 In more detail, a single-gate FET is a monolithic transistor device comprising a variable conduction channel between the drain and source terminals and a single gate positioned above said channel. Conversely, as combined with Figure 10 In more detail, a multi-gate FET is a monolithic transistor device comprising a variable conduction channel between the drain and source terminals and multiple gates positioned above the channel. During operation of the FET, electrical signals are provided to the multiple gates to control the conductivity of the channel. In some applications, the use of multiple gates allows for better electrical control of the channel compared to a single-gate FET. This, in turn, enables more effective suppression of leakage current in the "off state" and / or boosted current (i.e., drive current) in the "on" state.

[0107] In the series-coupled sequence of the multi-gate FETs corresponding to switch 622, the source terminal 771 of FET 701 may be coupled to port 628, the drain terminal 781 of FET 701 may be coupled to the source terminal of FET 702, the drain terminal of FET 702 may be coupled to the source terminal of FET 703, and the drain terminal of FET 703 may be coupled to port 648. Although the description herein refers to a series-coupled arrangement in which the first FET has a source terminal connected to the port and a drain terminal connected to the source terminal of the second FET, in other embodiments, the source and drain terminal connections may be reversed (e.g., a series-coupled arrangement may have a first FET with its drain terminal connected to the port and its source terminal connected to the drain terminal of the second FET). More generally, each of the source and drain terminals of the FET may be referred to as a “conductive terminal,” and the terminology may be used interchangeably for the source terminal or the drain terminal.

[0108] According to an embodiment, during operation, control signals provided to the series-coupled FETs in any particular switch 622, 625, 626, 631, 632, 635 are synchronized because the control signals simultaneously cause all FETs in the switches to be substantially turned on (e.g., "on" or "off") or substantially de-conducted (e.g., "off" or "open"). To achieve simultaneous control of all FETs in each switch, the gate of the FET in each switch can be electrically coupled to a single control node. For example, in... Figure 7 In this configuration, the gate terminals of FETs 701 to 703 are electrically coupled to control terminal 722, the gate terminals of FETs 704 to 706 are electrically coupled to control terminal 725, the gate terminals of FETs 707 to 709 are electrically coupled to control terminal 726, the gate terminals of FETs 710 to 712 are electrically coupled to control terminal 731, the gate terminals of FETs 713 to 715 are electrically coupled to control terminal 732, and the gate terminals of FETs 716 to 718 are electrically coupled to control terminal 735.

[0109] As previously indicated, a system including the RF switch 700 may include multiple drivers (e.g., Figure 1 , 2 The switch controller (e.g., the driver 151, 152, 251, 252) Figure 1 , 2 The switch controllers 150 and 250 are configured such that each driver is coupled to one or more control terminals 722, 725, 726, 731, 732, and 735 of switches 622, 625, 626, 631, 632, and 635. To make the entire switch substantially conductive between the ports to which the switch is connected (e.g., to "on" or "off" the switch), a driver connected to the control node associated with the switch provides a control signal (or "drive signal") to the control node, and this control signal causes all FETs within the switch to become substantially conductive simultaneously. For example, a driver coupled to control terminal 722 (e.g., driver 151, 251) can provide a control signal to terminal 722, which simultaneously makes all FETs 701 to 703 substantially conductive (e.g., "on" or "off"), thus making switch 622 substantially conductive between ports 628 and 648. Alternatively, the driver may provide a control signal to terminal 722 that simultaneously renders all FETs 701 to 703 substantially non-conductive (e.g., "off" or "open"), thus rendering switch 622 substantially non-conductive between ports 628 and 648.

[0110] Furthermore, according to an embodiment, in a branch comprising multiple parallel-coupled switches / stacks (e.g., branches 624 and 630), the control signals provided to the FETs of the parallel-coupled switches in the branch are also synchronized, because the control signals simultaneously make all FETs in the entire branch substantially turn on (e.g., "on" or "off") or substantially de-conduct (e.g., "off" or "open"). Although a single driver can provide control signals to all FETs of the parallel-coupled switches in a branch, a separate driver (e.g., Figure 1 , 2The drivers 151, 152, 251, 252) are used to drive each of the multiple switches in any given multi-switch branch. For example, in the branch between ports 638 and 648, the first driver (e.g., Figure 1 , 2 The second driver (e.g., driver 151, 251) can be coupled to the control terminal 731, and the driver can provide control signals to the control terminal 731. Figure 1 , 2 The drivers 152 and 252 can be coupled to the control terminal 732, and the driver can provide a second control signal to the control terminal 732. The control signals provided by the first and second drivers are synchronized to synchronously turn switches 631 and 632 on or off. In other words, according to an embodiment, a single driver is used to synchronously drive the parallel-coupled switches / stacks of any given branch.

[0111] As will now be explained, the above configuration, which includes branches of multiple parallel-coupled FET stacks (e.g., the branch between ports 638 and 648, or the branch between ports 628 and 652), can have improved settling time compared to a conventional branch having a single FET stack designed to conduct signals of the same power level. More specifically, during operation, the RF signal transmitted through a branch with multiple parallel-coupled FET stacks is split between the parallel stacks. When the parallel-coupled FET stacks are substantially identical, each stack will transmit approximately 50% of the total power of the RF signal. Therefore, compared to a conventional switching branch that only includes a single stack designed to conduct signals of the same power, the parallel-coupled FET stacks of the embodiments of the present invention only need to be designed to conduct signals of approximately half the power in each stack. Thus, given the same signal power transmitted through a branch with parallel-coupled FET stacks and a conventional branch with a single stack, the FETs in the parallel-coupled FET stack can have smaller gate width / perimeter. For example, a conventional RF switch may include a single FET stack between switch ports, where each FET has a gate width of 4 mm, and each parallel-coupled FET stack may include a FET with a gate width of only 2 mm.

[0112] Furthermore, the parasitic capacitance on the gate of a FET is proportional to the gate width. Therefore, when compared to a larger corresponding FET in a conventional single-stack branch, the relatively small FETs associated with various embodiments have shorter gate widths and thus lower gate capacitances. Each FET stack in a parallel-coupled FET stack is also driven individually (e.g., via...). Figure 1 , 2With individual drivers 151, 152, 251, 252, according to various embodiments, the time constant of the relatively small FET in the parallel-coupled FET stack is also smaller than the time constant of its larger conventional counterpart FET. When using implementations of the various embodiments, this can result in a significantly faster (e.g., about 50% faster) settling time associated with the switching between transmit and receive states when compared to the settling time of a conventional RF switch.

[0113] exist Figure 7 In the diagram, each of switches 620, 625, 626, 631, 632, and 635 is shown as a stack comprising three series-coupled FETs 701 to 703, 704 to 706, 707 to 709, 710 to 712, 713 to 715, and 716 to 718. Although each of switches 620, 625, 626, 631, 632, and 635 may comprise a stack of three series-coupled FETs, in some embodiments, each of switches 620, 625, 626, 631, 632, and 635 may alternatively comprise a single FET, two FETs, or more than three FETs (as indicated by the ellipses in each FET stack). In some embodiments, either or both of shunt branches 624 and 634 may not include any FETs; alternatively, ports 628 and / or 638 may be directly coupled to the corresponding reference voltage nodes 652 and 653, respectively.

[0114] According to embodiments, parallel-coupled switches (or parallel-coupled FET stacks) in the same branch are substantially identical (e.g., switches 631 and 632 are substantially identical), but switches in different branches may differ from each other (e.g., switches 631 and 625 may differ, but they may also be substantially identical). More specifically, within the same branch, each of the parallel-coupled switches may include the same number of series-coupled FETs and have the same total perimeter and / or gate width. In other embodiments, parallel-coupled switches (or parallel-coupled FET stacks) in the same branch may differ from each other (e.g., the parallel-coupled switches or FET stacks may have different numbers of parallel-coupled FETs and / or different total perimeter and / or gate widths).

[0115] In addition to the FET, in embodiments where each resistor is coupled between the source and drain terminals of the FET, each stack may include high-value (e.g., several thousand ohms) resistors (e.g., ...). Figure 7 The DC bias distribution network (resistors 791 to 793) essentially ensures that the DC bias voltage supplied to the drain / source of each FET in the stack is the same. Although only in... Figure 7The DC bias distribution network is shown in switches 622, 631, and 632, but such a network can also be included in switches 625, 626, and 635.

[0116] In embodiments, each stack may further include a control terminal coupled to the gate terminal of the FET and the stack (e.g., Figure 7 High-value (e.g., several thousand ohms) resistors between the control terminals 722 and (e.g., Figure 7 An RF blocking network (resistors 794 to 796) is used. The RF blocking network presents a high impedance to RF signal energy to ensure that RF signal energy transmitted through the branches does not leak into the control / driver circuitry (e.g., to...). Figure 1 , 2 Controllers 150 and 250).

[0117] Furthermore, each stack may also include a body node (if included) coupled to a body bias terminal (e.g., ) of each FET. Figure 7 A body bias circuit system between the body bias terminal 790 of the FET and the body bias terminal of the stack. In an embodiment, the body bias circuit system may also include a high-value (e.g., several thousand ohms) resistor coupled between the body node of the FET and the body bias terminal of the stack. Figure 7 An RF blocking network with resistors 797 to 799. Similarly, the RF blocking network presents a high impedance to RF signal energy to ensure that RF signal energy transmitted through the branch does not leak into the body bias circuitry (not shown). Although only in Figure 7 The switches 622, 631, and 632 show an external bias circuit system, but such a circuit system can also be included in switches 625, 626, and 635.

[0118] Such as combination Figure 1 and 2 As described, in RF switches (e.g., Figure 1 , 2 During operation of embodiments of switches 110, 210, 500, 600, and 700 (5 to 7), based on the system (e.g., Figure 1 , 2 Whether the transceivers 100 and 200 are in transmit mode or receive mode (e.g., during the transmit or receive time interval of a wireless communication session, respectively) is determined (e.g., via...). Figure 1 , 2RF switch controllers 150 and 250 control the state of the RF switches. More specifically, when the system is in transmit mode, the RF switch states are controlled to establish low-impedance connections between ports 148, 248, 548, and 648 and ports 128, 228, 528, and 628, and high impedance connections between ports 148, 248, 548, and 648 and ports 138, 238, 538, and 638. Furthermore, in transmit mode, the RF switch states are controlled to establish low-impedance connections between ports 538 and 638 and ports 553 and 653, and high impedance connections between ports 528 and 628 and ports 552 and 652. In other words, in transmit mode, switches 521, 522, 535, 536, 622, and 635 are closed, while switches 525, 526, 531, 532, 631, and 632 are open. (Reference) Figure 7 This means that the RF switch controller sends control signals to control terminals 722 and 735 to put FETs 701 to 703 and 716 to 718 into a substantially on state, and sends control signals to control terminals 726, 731, and 732 to put FETs 704 to 709 and 710 to 715 into a substantially off state. Therefore, in the transmit state, the signal energy present at node 628 is transmitted to node 648 via switch 622 (or branch 620), and the conduction path between node 628 and reference voltage node 652 is broken. Additionally, in the transmit state, the signal energy present at node 638 is transmitted to reference voltage node 653 via switch 635 (or branch 634), and the conduction path between node 638 and node 648 is broken.

[0119] Conversely, when the system is in receive mode, the state of the RF switches is controlled to establish low-impedance connections between ports 148, 248, 548, and 648 and ports 138, 238, 538, and 638, and high impedance connections between ports 148, 248, 548, and 648 and ports 128, 228, 528, and 628. Furthermore, in receive mode, the state of the RF switches is controlled to establish low-impedance connections between ports 528 and 628 and ports 552 and 652, and high impedance connections between ports 538 and 638 and ports 553 and 653. In other words, in receive mode, switches 525, 526, 531, 532, 631, and 632 are closed, while switches 521, 522, 535, 536, 622, and 635 are open. (Reference) Figure 7This means that the RF switch controller sends control signals to control terminals 722 and 735 to keep FETs 701 to 703 and 716 to 718 substantially non-conducting, and sends control signals to control terminals 726, 731, and 732 to keep FETs 704 to 709 and 710 to 715 substantially on. Therefore, in the receiving state, the signal energy present at node 638 is transmitted to node 648 via switches 631 and 632 (or branch 630), while the conduction path between node 638 and the reference voltage node 653 is broken. Additionally, in the receiving state, the signal energy present at node 628 is transmitted to the reference voltage node 652 via switches 625 and 626 (or branch 624), while the conduction path between node 628 and node 648 is broken.

[0120] The description is now presented. Figure 6 and 7 An example of an RF switch integrated circuit (IC) for a circuit system. More specifically, Figure 8 According to the embodiments, it includes Figure 6 and 7 A top view of a monolithic RF switch IC 800, consisting of a stack of FETs. The RF switch IC 800 includes multiple branches 820, 824, 830, 834 (e.g., Figure 6 Branches 620, 624, 630, and 634 in the diagram. Each branch includes one or two switch / FET stacks 822, 825, 826, 831, 832, and 835 (e.g., ...). Figure 6 , 7 (the switches), and each FET stack includes three series-coupled FETs 801 to 803, 804 to 806, 807 to 809, 810 to 812, 813 to 815, 816 to 818 (e.g., the ...). Figure 7 (FETs 701 to 703, 704 to 706, 707 to 709, 710 to 712, 713 to 715, 716 to 718). According to an embodiment, branches 820, 824, 830, and 834 may form portions of a single monolithic semiconductor chip (i.e., a single semiconductor substrate). Alternatively, some or all of branches 820, 824, 830, and 834 may be included within different semiconductor chips electrically connected together using bonding wires and / or other conductive structures.

[0121] According to an embodiment, the RF switch IC 800 is "monolithic" because FETs 801 to 818 are formed in and on a single integrated circuit substrate 860. For example, according to an embodiment, the RF switch IC 800 may be formed on a gallium arsenide (GaAs)-based substrate 860, but those skilled in the art will understand that, based on the description herein, the circuitry of the RF switch may also be formed on other types of substrates, including silicon (Si)-based substrates (e.g., bulk silicon CMOS, silicon-on-insulator (SoI) CMOS, etc.) and gallium nitride (GaN)-based substrates (e.g., GaN on silicon, GaN on silicon carbide (SiC), etc.). Furthermore, the FET may include metal-oxide-semiconductor FETs (MOSFETs), high electron mobility transistors (HEMTs), metal-semiconductor field-effect transistors (MESFETs), laterally diffused metal-oxide-semiconductor (LDMOS) FETs, enhancement-mode MOSFETs (EMOSFETs), and / or junction-gate FETs (JFETs), to name just a few.

[0122] In addition to branches 820, 824, 830, and 834, the RF switch IC 800 also includes multiple I / O, control, and reference voltage nodes 828, 838, 848, 852, and 853, each of which provides electrical connections to external circuitry (e.g., connections to antenna 140, transmitter 120, receivers 130 and 230, circulator 216, RF switch controllers 150 and 250, etc.) and / or to one or more power supplies and / or reference voltages (e.g., power supply, ground, and other reference voltages). For example, some or all of the I / O, control, and reference voltage nodes 828, 838, 848, 852, and 853 may be implemented as conductive pads exposed on the top surface of the RF switch IC 800. Therefore, the various nodes 828, 838, 848, 852, and 853 can serve as bonding pads (e.g., ...). Figure 3 The bonding pads (370) of the bonding wire provide electrical connection to the aforementioned external circuitry or to other circuitry. According to embodiments, various nodes include a first node 828 (e.g., Figure 1 , 2 Nodes 128, 228, 528, and 628 from 5 to 7), and the second node 838 (for example, Figure 1 , 2 Nodes 5 to 7 (138, 238, 538, 638), and the third node (848, for example, Figure 1 , 2 Nodes 148, 248, 548, and 648 (from 5 to 7) and reference voltage nodes 852 and 853 (e.g., Figures 5 to 7 (Reference nodes 552, 553, 652, 653).

[0123] For each FET 801 to 818, the conductivity of the FET channel between the source and drain terminals is determined by the conductivity through the gate terminal (e.g., Figure 7 Terminal 761) provides control signals to each gate structure for control. To achieve this type of channel conductivity control, the RF switch IC 800 also includes multiple control nodes (not in...) Figure 8 As shown, but corresponding to Figure 7 The control terminals 722, 725, 726, 731, 732, and 735) enable control signals to be provided by an external circuit system to the gate terminals of FETs 801 to 818. According to an embodiment, the control signals provided to any particular branch 820, 824, 830, and 834 are synchronized because the control signals simultaneously cause all FETs in that branch to be substantially turned on (e.g., "on" or "off") or substantially de-conducted (e.g., "off" or "open").

[0124] FETs 801, 802, 803 (e.g., series-coupled) Figure 7 A first branch 820, consisting of a first stack 822 of FETs 701 to 703, is electrically coupled between nodes 828 and 848. More specifically, in an embodiment, the drain terminal of FET 801 is electrically coupled to node 828, the source terminal of FET 801 is electrically coupled to the drain terminal of FET 802, the source terminal of FET 802 is electrically coupled to the drain terminal of FET 803, and the source terminal of FET 803 is electrically coupled to node 848.

[0125] 825, 826 are stacked from two parallel-coupled FETs (e.g., including...). Figure 7 A second branch 824, consisting of FETs 704 to 709, is electrically coupled between node 828 and reference voltage node 852. More specifically, in stack 825, the drain terminal of FET 804 is electrically coupled to node 828, the source terminal of FET 804 is electrically coupled to the drain terminal of FET 805, the source terminal of FET 805 is electrically coupled to the drain terminal of FET 806, and the source terminal of FET 806 is electrically coupled to reference voltage node 852. In stack 826, the drain terminal of FET 807 is electrically coupled to node 828, the source terminal of FET 807 is electrically coupled to the drain terminal of FET 808, the source terminal of FET 808 is electrically coupled to the drain terminal of FET 809, and the source terminal of FET 809 is electrically coupled to reference voltage node 852.

[0126] 831, 832 are composed of two parallel-coupled FET stacks (e.g., including...). Figure 7A third branch 830, consisting of FETs 710 to 715, is electrically coupled between nodes 848 and 838. More specifically, in stack 831, the drain terminal of FET 810 is electrically coupled to node 848, the source terminal of FET 810 is electrically coupled to the drain terminal of FET 811, the source terminal of FET 811 is electrically coupled to the drain terminal of FET 812, and the source terminal of FET 812 is electrically coupled to node 838. In stack 832, the drain terminal of FET 813 is electrically coupled to node 848, the source terminal of FET 813 is electrically coupled to the drain terminal of FET 814, the source terminal of FET 814 is electrically coupled to the drain terminal of FET 815, and the source terminal of FET 815 is electrically coupled to node 838.

[0127] Finally, the series-coupled FETs 816, 817, and 818 (e.g., Figure 7 A fourth branch 834, consisting of a sixth stack 835 of FETs 716 to 718, is electrically coupled between node 838 and reference voltage node 853. More specifically, in an embodiment, the drain terminal of FET 816 is electrically coupled to node 838, the source terminal of FET 816 is electrically coupled to the drain terminal of FET 817, the source terminal of FET 817 is electrically coupled to the drain terminal of FET 818, and the source terminal of FET 818 is electrically coupled to reference voltage node 853. When incorporated into a larger electrical system (e.g., Figure 1 , 2 In transceivers 100 and 200, reference voltage nodes 852 and 853 are typically coupled to a ground reference (e.g., zero volts), but nodes 852 and 853 may alternatively be coupled to a positive or negative DC reference voltage.

[0128] A comparison of FETs 801 to 803 in branch 820 with FETs 810 to 815 in branch 830 illustrates that, to conduct signals with substantially the same maximum power, a conventional switching branch consisting of only a single stack (e.g., stack 822 in branch 820) will include significantly larger FETs (e.g., FETs 801 to 803) compared to FETs (e.g., FETs 810 to 815) in an embodiment that includes multiple stacks (e.g., stacks 831, 832 in branch 830). In other words, given the same signal power transmitted through a branch with parallel-coupled FET stacks (e.g., branch 830) and a conventional branch with a single stack (e.g., branch 820), the FETs in the parallel-coupled FET stack (e.g., FETs 810 to 815) can be smaller in terms of gate width / perimeter than the FETs in the conventional FET stack (e.g., FETs 801 to 803). Because relatively small FETs have lower gate capacitance, their time constants are also smaller than those of their larger counterparts. Therefore, the settling time of a parallel-coupled FET stack can be significantly faster than that of a conventional single FET stack.

[0129] As previously mentioned, the various FETs in the above embodiments of the RF switch may include single-gate FETs and / or multi-gate FETs. For example, Figure 9 According to the embodiments, some or all of the FETs can be used in an RF switch (e.g., Figure 7 , 8 A simplified circuit depiction of a single-gate FET 900 (FETs 701 to 718, 801 to 818). The single-gate FET 900 has a source terminal 970, a drain terminal 980, and a gate 960. The gate 960 is covered by a FET channel (depicted by dashed line 990) extending between the source terminal 970 and the drain terminal 980. Although Figure 9 Not shown, but the body bias terminal can be connected to FET 900 so that the body bias voltage can be supplied to FET 900 from an external voltage source.

[0130] Gate 960 is electrically coupled to control terminal 910 via resistor 912 (e.g., Figure 7 Terminal 761). Source terminal 970 is electrically coupled to first node 914 (e.g., directly or indirectly coupled to). Figure 7 The drain terminal 980 is electrically coupled to a second node 916 (e.g., directly or indirectly coupled to any of nodes 628, 638, 648, 652, 653, or to the drain terminal of another FET), and the drain terminal 980 is electrically coupled to the second node 916 (e.g., directly or indirectly coupled to...). Figure 7 (any of nodes 628, 638, 648, 652, 653, or to the source terminal of another FET).

[0131] In other embodiments, some or all of the FETs in the various FETs described in the above embodiments of the RF switch may include multi-gate FETs and / or multi-gate FET components. For example, Figure 10 It is a replacement for some or all of the FETs in an RF switch according to another embodiment (e.g., Figure 7 , 8 A simplified circuit diagram of a multi-gate FET assembly 1000 used for FETs 701 to 718, 801 to 818. The multi-gate FET assembly 1000 includes a multi-gate FET 1020 and a voltage leveling circuit 1030. According to an embodiment, the multi-gate FET assembly 1000 is monolithically and integrally formed in and on a semiconductor substrate.

[0132] The multi-gate FET 1020 includes a source terminal 1070 (e.g., Figure 7 The source extreme 771), the drain extreme 1080 (for example, Figure 7 The drain terminal 781), the multi-gate FET channel between the source terminal 1070 and the drain terminal 1080 (depicted by dashed line 1090), and the multi-gate assembly 1060 having multiple gate structures 1061, 1062, 1063 on the multi-gate FET channel 1090 (e.g., similar to...). Figure 7 (Gate terminal 761). As used herein, the term "multi-gate FET channel" refers to the entire variable conductivity path between the source and drain terminals of a multi-gate FET (e.g., between source terminal 1070 and drain terminal 1080). As previously mentioned, the use of multiple gates allows for better electrical control of channel 1090 when compared to a single-gate FET. This, in turn, allows for more effective suppression of leakage current in the "off state" and / or boosted current (i.e., drive current) in the "on" state. Although Figure 10 Not shown, but the body bias terminal can be connected to FET1020 so that the body bias voltage can be supplied to FET1020 from an external voltage source.

[0133] The multi-gate component 1060 is electrically coupled to the control terminal 1010 via multiple resistors 1012 (e.g., Figure 7 Terminal 761). Source terminal 1070 is electrically coupled to the first node 1014 (e.g., directly or indirectly coupled to). Figure 7 The drain terminal 1080 is electrically coupled to the second node 1016 (e.g., directly or indirectly coupled to any of nodes 628, 638, 648, 652, 653, or to the drain terminal of another FET), and the drain terminal 1080 is electrically coupled to the second node 1016 (e.g., directly or indirectly coupled to...). Figure 7 (any of nodes 628, 638, 648, 652, 653, or to the source terminal of another FET).

[0134] A voltage leveling circuit 1030 is electrically connected between the source terminal 1070, the drain terminal 1080, and the multi-gate assembly 1060. According to an embodiment, circuit 1030 includes a plurality of channel contacts 1032, 1033, a plurality of capacitors 1034, 1036, 1037, 1038, 1043, and a plurality of resistors 1041, 1042. Each channel contact 1032, 1033 may be, for example, an ohmic contact electrically coupled to the semiconductor substrate action surface on the multi-gate FET channel 1080 between the first and second pairs of adjacent gate structures 1061-1063.

[0135] Through various electrical connections, channel contacts 1032, 1033 are electrically coupled to capacitors 1034, 1036 to 1038, 1043, which in turn are electrically coupled to the multi-gate assembly 1060 and to the source terminal 1070 and the drain terminal 1080, as shown below. Figure 10 As shown in the diagram, each of capacitors 1034, 1036 through 1038, 1043 may be a metal-insulator-metal (MIM) capacitor integrally formed with the substrate (e.g., a first electrode formed from a portion of a first metal layer, a second electrode formed from a portion of a second metal layer, and an insulating layer (e.g., silicon nitride or other suitable insulating material) sandwiched between the first and second electrodes). In other embodiments, some or all of capacitors 1034, 1036 through 1038, 1043 may be discrete capacitors electrically coupled to the top surface of the semiconductor substrate.

[0136] When implemented in a system with a stack of multi-gate FETs, the voltage leveling circuit 1030 can produce a more uniform, off-state AC voltage distribution across the stacked FETs. More specifically, by utilizing, as Figure 10 The balancing capacitors 1036 to 1038 shown in the diagram substantially equalize the AC voltage swing across all FETs (or multi-gate FETs across different types of circuits) in the off-state FET branch of the RF switch, thereby potentially preventing the first and / or a first minority of multi-gate FETs from experiencing stack breakdown voltage before the rest of the multi-gate FETs in the off-state branch. This can significantly improve the power handling capability of the switching branch.

[0137] In one embodiment, circuit 1030 further includes relatively high-value resistors 1041 and 1042, respectively, electrically connected in parallel with capacitors 1036 and 1038. In various embodiments, resistors 1041 and 1042 may be integrally formed with the semiconductor substrate (e.g., stripline resistors, polysilicon resistors, etc.) or may be discrete resistors coupled to the top surface of the substrate. Resistors 1041 and 1042 of voltage leveling circuit 1030 can produce a more uniform, off-state DC voltage distribution across the stacked FETs. More specifically, the relatively high-value resistors 1041 and 1042 act as conductors for DC signals that are intentionally and parasiticly blocked by capacitance, while a large portion of the RF signal is transmitted primarily through the capacitance. This leveling is achieved by selecting resistors and capacitors with appropriate values ​​in the parallel resistor / capacitor combination.

[0138] Figure 11 It is an operating RF transceiver according to an embodiment (e.g., Figure 1 , 2 RF switches in transceivers 100, 200 (e.g., Figures 1 to 8 A flowchart of a method for using RF switches 110, 210, 310, 410, 500, 600, 700, and 800. The method may begin in block 1102, at which point (e.g., by...) Figure 1 , 2 The RF switch controllers 150 and 250 determine whether the RF transceiver should be configured in transmit (TX) mode or receive (RX) mode. For example, this determination can be made based on TX / RX control signals from a higher-level communication controller.

[0139] When the transceiver is to be configured for transmit mode, then in box 1104, the TX cascade and RX shunt branches (e.g., Figure 7 The FET stacks in branches 620 and 634 are simultaneously turned on, while the RX series and TX shunt branches (e.g., Figure 7 The FET stacks in branches 630 and 624 are simultaneously turned off. To achieve this, the driver of the RF switch controller (e.g., Figure 1 , 2 The drivers 151, 152, 251, 252) provide control signals to the control nodes of various FET stacks of the RF switch (e.g., Figure 7 Terminals 722, 725, 726, 731, 732, and 735 can be used to configure the RF switch to transmit mode. For example, to configure... Figure 7The RF switch 700 is configured in transmit mode. One or more drivers of the RF switch controller can send a first control signal to control terminals 722 and 735 to simultaneously turn on branches 620 and 634 (i.e., close switches 622 and 635 to establish low-impedance paths between nodes 628 and 648 and between nodes 638 and 653). Simultaneously, one or more drivers of the RF switch controller can send a second control signal to control nodes 725, 726, 731, and 732 to simultaneously turn off branches 624 and 630 (i.e., open switches 625, 626, 631, and 632 to establish high-impedance conditions between nodes 628 and 652 and between nodes 638 and 648). The RF switch controller continues to send these control signals to the various control nodes until (in block 1102) it is determined that the transceiver will be configured in receive mode.

[0140] When the transceiver is to be configured for receive mode, then in box 1106, the RX cascade and TX shunt branches (e.g., Figure 7 The FET stacks in branches 630 and 624 are simultaneously turned on, while the TX series and RX shunt branches (e.g., Figure 7 The FET stacks in branches 620 and 634 are simultaneously turned off. To achieve this, the driver of the RF switch controller (e.g., Figure 1 , 2 The drivers 151, 152, 251, 252) provide control signals to the control nodes of various FET stacks of the RF switch (e.g., Figure 7 Terminals 722, 725, 726, 731, 732, and 735 can be used to configure the RF switch to receive mode. For example, to configure... Figure 7The RF switch 700 is configured in receive mode, and different drivers of the RF switch controller (e.g., drivers 151 and 152, or drivers 251 and 252) can simultaneously send a first control signal and a second control signal to control nodes 725, 726, 731, and 732 respectively to simultaneously turn on branches 624 and 630 (i.e., to close switches 625, 626, 631, and 632 to establish low-impedance paths between nodes 638 and 648 and between nodes 628 and 652). Similarly, as previously discussed, according to the embodiment, a separate driver will be used to provide control signals to control nodes 731 and 732, and a separate driver will also be used to provide control signals to control nodes 725 and 726. Simultaneously, one or more drivers of the RF switch controller can send a third control signal to control terminals 722 and 735 to simultaneously shut off branches 620 and 634 (i.e., to open switches 622 and 635 to establish high impedance conditions between nodes 628 and 648 and between nodes 638 and 653). The RF switch controller continues to send these control signals to the various control nodes until it is determined again (in block 1102) that the transceiver will be configured to transmit mode.

[0141] An embodiment of a switching circuit includes a first transistor stack and a second transistor stack coupled in parallel between a first port and a second port. The first transistor stack includes a first plurality of transistors series coupled between the first port and the second port to provide a first variable conduction path between the first port and the second port. Each of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors series coupled between the first port and the second port to provide a second variable conduction path between the first port and the second port. Each of the second plurality of transistors has a gate terminal coupled to a second control terminal.

[0142] An embodiment of a transceiver includes a switching circuit having a first, second, and third transistor stack. The first transistor stack, coupled between a first port and a second port, includes a first plurality of transistors, which are series-coupled between the first and second ports to provide a first variable conduction path between them. Each of the first plurality of transistors has a gate coupled to a first control terminal. A second transistor stack, also coupled in parallel with the first transistor stack between the first and second ports, includes a second plurality of transistors, which are series-coupled between the first and second ports to provide a second variable conduction path between them. Each of the second plurality of transistors has a gate coupled to a second control terminal. The third transistor stack, coupled between the second and third ports, includes a third plurality of transistors, which are series-coupled between the second and third ports to provide a third variable conduction path between them. Each of the third plurality of transistors has a gate coupled to a third control terminal.

[0143] An embodiment of a method of operating a switching circuit includes simultaneously configuring a first variable conduction path and a second variable conduction path of the switching circuit to a low-impedance state by a switching controller, wherein the first and second variable conduction paths are coupled in parallel between a first port and a second port of the switching circuit. The switching circuit also includes a first transistor stack and a second transistor stack coupled between the first and second ports. The first transistor stack includes a first plurality of transistors series coupled between the first and second ports to provide the first variable conduction path. The second transistor stack includes a second plurality of transistors series coupled between the first and second ports to provide the second variable conduction path.

[0144] The foregoing detailed description is illustrative in nature only and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the terms "exemplary" or "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or illustrative should not necessarily be construed as preferred or advantageous over other embodiments. Furthermore, one is not expected to be bound by any expressed or implied theory presented in the foregoing technical field, background art, or specific embodiments.

[0145] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. Additionally, certain terms may be used herein for reference only and are therefore not intended to be restrictive; and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence.

[0146] The foregoing description refers to elements or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly connected to (or directly connected to) another element, and not necessarily mechanically. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly connected to (or directly or indirectly connected to) another element, and not necessarily mechanically. Therefore, while the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0147] While at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed descriptions will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. A switching circuit, characterized in that, include: First port; Second port; Third port; A first transistor stack coupled between a first port and a second port, wherein the first transistor stack includes a plurality of first transistors coupled in series between the first port and the second port to provide a first variable conduction path between the first port and the second port, and wherein each of the plurality of first transistors has a gate end coupled to a first control terminal, and wherein the plurality of first transistors has a first total gate width. A second transistor stack coupled in parallel with the first transistor stack between the first port and the second port, wherein the second transistor stack includes a second plurality of transistors coupled in series between the first port and the second port to provide a second variable conduction path between the first port and the second port, and wherein each of the second plurality of transistors has a gate terminal coupled to a second control terminal, and wherein the second plurality of transistors has a second total gate width equal to the first total gate width; as well as A single third transistor stack coupled between the first port and the third port, wherein the third transistor stack includes a third plurality of transistors coupled in series between the first port and the third port to provide a third variable conduction path between the first port and the third port, and wherein the third plurality of transistors has a third total gate width greater than the first total gate width and greater than the second total gate width.

2. The switching circuit according to claim 1, characterized in that, In addition, including: A first driver, which is coupled to the first control terminal; as well as A second driver is coupled to the second control terminal, wherein the first driver and the second driver are configured to simultaneously turn on or off the first plurality of transistors and the second plurality of transistors.

3. The switching circuit according to claim 1, characterized in that, Each of the third plurality of transistors has a gate terminal coupled to a third control terminal.

4. The switching circuit according to claim 3, characterized in that, In addition, including: A fourth transistor stack coupled between the third port and the ground reference node, wherein the fourth transistor stack includes a fourth plurality of transistors coupled in series between the third port and the ground reference node, and wherein each of the fourth plurality of transistors has a gate terminal coupled to a fourth control terminal.

5. The switching circuit according to claim 4, characterized in that, In addition, including: A fifth transistor stack coupled between the third port and the ground reference node, wherein the fifth transistor stack includes a fifth plurality of transistors coupled in series between the third port and the ground reference node, and wherein each of the fifth plurality of transistors has a gate terminal coupled to a fifth control terminal.

6. The switching circuit according to claim 1, characterized in that, The first transistor stack and the second transistor stack form part of a first branch between the first port and the second port, the second transistor stack forms a second branch between the first port and the third port, and the switching circuit further includes: The third branch coupled between the second port and the ground reference node; and A fourth branch is coupled between the third port and the ground reference node.

7. The switching circuit according to claim 1, characterized in that, Each of the first plurality of transistors and the second plurality of transistors is a field-effect transistor.

8. The switching circuit according to claim 7, characterized in that, Each of the first plurality of transistors and the second plurality of transistors is a multi-gate field-effect transistor.

9. A transceiver, characterized in that, include: Switching circuit, which includes First port, Second port, Third port, A first transistor stack coupled between the first port and the second port, wherein the first transistor stack includes a plurality of first transistors series coupled between the first port and the second port to provide a first variable conduction path between the first port and the second port, wherein each of the plurality of first transistors has a gate terminal coupled to a first control terminal, and wherein the plurality of first transistors has a first total gate width. A second transistor stack coupled in parallel with the first transistor stack between the first port and the second port, wherein the second transistor stack includes a second plurality of transistors series coupled between the first port and the second port to provide a second variable conduction path between the first port and the second port, and wherein each of the second plurality of transistors has a gate terminal coupled to a second control terminal, and wherein the second plurality of transistors has a second total gate width equal to the first total gate width, and A third transistor stack coupled between the second port and the third port, wherein the third transistor stack includes a third plurality of transistors coupled in series between the second port and the third port to provide a third variable conduction path between the second port and the third port, and wherein each of the third plurality of transistors has a gate terminal coupled to a third control terminal, and wherein the third plurality of transistors has a third total gate width greater than the first total gate width and greater than the second total gate width.

10. A method for operating a switching circuit, characterized in that, The method includes: A switch controller simultaneously configures a first variable conduction path and a second variable conduction path of a switching circuit to a low-impedance state, wherein the first and second variable conduction paths are coupled in parallel between a first port and a second port of the switching circuit, and wherein the switching circuit further includes A first transistor stack coupled between the first port and the second port, wherein the first transistor stack includes a first plurality of transistors series coupled between the first port and the second port to provide the first variable conduction path, and wherein the first plurality of transistors have a first total gate width, and A second transistor stack coupled in parallel with the first transistor stack between the first port and the second port, wherein the second transistor stack includes a second plurality of transistors series coupled between the first port and the second port to provide the second variable conduction path, and wherein the second plurality of transistors has a second total gate width equal to the first total gate width; and While configuring the first and second variable conduction paths, the switch controller also configures the third variable conduction path of the switch circuit to a high-impedance state, wherein the third variable conduction path is coupled between the second port and the third port of the switch circuit, and wherein the third plurality of transistors have a third total gate width that is greater than the first total gate width and greater than the second total gate width.

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