Digital loop filter in all-digital phase-locked loop

Abstract

The present disclosure discloses a digital loop filter in a fully digital phase-locked loop. The digital loop filter can include a selection circuit, a first operation circuit, a first register circuit, a second operation circuit, and a second register circuit, wherein the selection circuit is configured to output one of a first data signal and a second data signal as a valid data, the first operation circuit is configured to output a first operation signal by adding or subtracting the valid data and a first register signal, the first register circuit is configured to register the first operation signal and output the first operation signal as the first register signal, the second operation circuit is configured to output a second operation signal by adding or subtracting a value of at least one bit of the valid data and the first register signal, and the second register circuit is configured to store the second operation signal and output the second operation signal as a control signal.

Description

Technical Field

[0001] This disclosure relates to all-digital phase-locked loops, and more specifically, to digital loop filters that enable easy and high-speed verification of all-digital phase-locked loops. Background Technology

[0002] Typically, the output of a phase-locked loop (PLL) has a stable oscillation signal with the same frequency as the reference signal.

[0003] Phase-locked loops (PLLs) can be used as source drivers in display devices and can also be used to recover clock signals by multiplying the input signal.

[0004] A digital phase-locked loop (PLL) may include a digital loop filter. The digital loop filter outputs a control signal that determines the oscillation frequency of a numerically controlled oscillator by using a digital signal corresponding to the phase difference between the reference signal and the feedback signal.

[0005] However, digital loop filters based on conventional techniques are implemented using signal synthesis blocks, integrators, and adders for digital encoding, and therefore have the problem that complexity and computation time increase due to the mixing of signal synthesis blocks and circuits used for digital encoding when verifying the phase-locked loop. Summary of the Invention

[0006] Various embodiments are intended to provide a digital loop filter that enables easy and high-speed verification of an all-digital phase-locked loop.

[0007] In an embodiment, the digital loop filter in the all-digital phase-locked loop may include a selection circuit, a first arithmetic circuit, a first register circuit, a second arithmetic circuit, and a second register circuit. The selection circuit is configured to output one of a first data signal and a second data signal as valid data. The first arithmetic circuit is configured to output a first arithmetic signal by adding or subtracting the valid data from the first register signal. The first register circuit is configured to store the first arithmetic signal and output it as a first register signal. The second arithmetic circuit is configured to output a second arithmetic signal by adding or subtracting the value of at least one bit of the valid data from the first register signal. The second register circuit is configured to store the second arithmetic signal and output it as a control signal.

[0008] In an embodiment, the digital loop filter in the all-digital phase-locked loop may include a selection circuit, a frequency integration path, and a scaling path. The selection circuit is configured to receive a first data signal and a second data signal corresponding to the phase difference between the reference signal and the feedback signal, and output one of the first data signal and the second data signal as valid data. The frequency integration path is configured to store a first operational signal obtained by adding or subtracting the value of the valid data from a first register signal and output a first register signal corresponding to the first register signal. The scaling path is configured to store a second operational signal obtained by adding or subtracting the value of at least one low bit of the valid data from the first register signal and output a control signal corresponding to the second operational signal.

[0009] In an embodiment, the all-digital phase-locked loop may include a time-to-digital converter circuit, a digital loop filter, a numerically controlled oscillator, and a divider. The time-to-digital converter circuit is configured to convert the phase difference between a reference signal and a feedback signal into a digital value and output a first data signal and a second data signal corresponding to the digital value. The digital loop filter is configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating on the valid data and a first register signal. The numerically controlled oscillator is configured to generate an oscillation signal and control the frequency of the oscillation signal in response to the control signal. The divider is configured to output a feedback signal to the time-to-digital converter circuit by dividing the oscillation signal.

[0010] In an embodiment, the all-digital phase-locked loop may include a clock generator, a first time-to-digital converter (TD-SCDMA) circuit, a second time-to-digital converter (TD-SCDMA) circuit, a digital loop filter, and a numerically controlled oscillator (CNC). The clock generator is configured to generate a first clock signal, a second clock signal, and a third clock signal using a reference signal. The first TD-SCDMA circuit is configured to output a first data signal corresponding to a digital value in response to the first clock signal when the reference signal has a phase earlier than the feedback signal. The second TD-SCDMA circuit is configured to output a second data signal corresponding to a digital value in response to the first clock signal when the reference signal has a phase later than the feedback signal. The digital loop filter is configured to perform an operation using either the first or second data signal in response to the second clock signal and to output a control signal in response to the third clock signal. The CNC oscillator is configured to control the frequency of the oscillation signal and output an oscillation signal in response to the control signal.

[0011] As described above, according to the embodiments, because the digital loop filter can be implemented using digital circuitry without requiring a signal synthesis block for digital encoding, the digital loop filter can be easily and quickly verified as an all-digital phase-locked loop. Attached Figure Description

[0012] Figure 1This is a block diagram of a digital loop filter in an all-digital phase-locked loop according to an embodiment.

[0013] Figure 2 This is a detailed block diagram of the digital loop filter in an all-digital phase-locked loop according to an embodiment.

[0014] Figure 3 This is a flowchart illustrating the operation of a digital loop filter in an all-digital phase-locked loop according to an embodiment.

[0015] Figure 4 yes Figure 1 and Figure 2 The circuit diagram of the operational circuit shown is shown.

[0016] Figure 5 This is a block diagram of a fully digital phase-locked loop according to an embodiment.

[0017] Figure 6 This is a detailed block diagram of the all-digital phase-locked loop according to an embodiment.

[0018] Figure 7 This is a flowchart describing the operation of a fully digital phase-locked loop according to an embodiment. Detailed Implementation

[0019] The embodiment provides a digital loop filter that enables easy and high-speed verification of an all-digital phase-locked loop and an all-digital phase-locked loop including the digital loop filter.

[0020] The digital loop filter can be configured to output a control signal VCON that determines the oscillation frequency of the numerically controlled oscillator by using a digital signal corresponding to the phase difference between the reference signal REF and the feedback signal FEB. In this case, refer to the description below. Figure 5 and Figure 6 Understand the reference signal REF and the feedback signal FEB. The reference signal REF can be understood as the input signal of the digital loop filter. The feedback signal FEB can be understood as the feedback signal from the output signal of the digital loop filter.

[0021] In an embodiment, when the reference signal has an earlier phase than the feedback signal, the first data signal can be defined as a digital value corresponding to the phase difference between the reference signal and the feedback signal. When the reference signal has a later phase than the feedback signal, the second data signal can be defined as a digital value corresponding to the phase difference between the reference signal and the feedback signal.

[0022] In the embodiments, terms such as first and second may be used to distinguish various elements. These elements are not limited by terms such as first and second.

[0023] Figure 1This is a block diagram of a digital loop filter 20 in an all-digital phase-locked loop according to an embodiment.

[0024] The digital loop filter 20 can output a control signal VCON that determines the oscillation frequency of the numerically controlled oscillator by using the first data signal IN1 and the second data signal IN2.

[0025] In this case, each of the first data signal IN1 and the second data signal IN2 is a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB, and each of the first data signal IN1 and the second data signal IN2 can be received from the time-to-digital converter 10 (in relation to the reference). Figure 5 (The given description).

[0026] refer to Figure 1 The digital loop filter 20 may include a selection circuit 21, a first operational circuit FAFS1, a first register circuit REG1, a second operational circuit FAFS2, and a second register circuit REG2.

[0027] First, the selection circuit 21 can select one of the first data signal IN1 and the second data signal IN2 as the valid data VDATA based on the value of the first data signal IN1.

[0028] Selection circuit 21 can receive first data signal IN1 and second data signal IN2 from time-to-digital converter circuit 10 (reference) Figure 5 The time-to-digital converter 10 can convert the phase difference between the reference signal REF and the feedback signal FEB into a digital value, store the digital value, and provide the digital loop filter 20 with a first data signal IN1 and a second data signal IN2 corresponding to the digital value in response to the first clock signal CLK1.

[0029] When the reference signal REF has an earlier phase than the feedback signal FEB, the selection circuit 21 can receive the first data signal IN1 as a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB, and when the reference signal REF has a later phase than the feedback signal FEB, the selection circuit 21 can receive the second data signal IN2 as a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB.

[0030] The selection circuit 21 can select either the first data signal IN1 or the second data signal IN2 as valid data VDATA based on the value of the first data signal IN1 (i.e., the digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB).

[0031] For example, when the reference signal REF has an earlier phase than the feedback signal FEB, the selection circuit 21 can select the first data signal IN1 as the valid data VDATA. Furthermore, when the reference signal REF has a later phase than the feedback signal FEB, the selection circuit 21 can select the second data signal IN2 as the valid data VDATA.

[0032] Selection circuit 21 may include logic circuit 24 and multiplexer 22.

[0033] The logic circuit 24 can output a selection signal SEL corresponding to the result of a logical operation on the bit values ​​of the first data signal IN1. For example, the logic circuit 24 may include a NOR operation circuit.

[0034] Multiplexer 22 can respond to selection signal SEL by outputting first data signal IN1 or second data signal IN2 as valid data VDATA.

[0035] For example, when the reference signal REF has a later phase than the feedback signal FEB, the selection circuit 21 can receive a first data signal IN1 with the value "0000...", and the selection circuit 21 can receive a second data signal IN2 as a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB.

[0036] By performing a NOR operation on the first data signal IN1 with the value "00000...", logic circuit 24 can output a selection signal SEL with a high logic level.

[0037] Multiplexer 22 can respond to a selection signal SEL with a high logic level and output a second data signal IN2 as valid data VDATA.

[0038] Furthermore, when the reference signal REF has an earlier phase than the feedback signal FEB, the selection circuit 21 can receive the first data signal IN1 as a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB.

[0039] When the reference signal REF has an earlier phase than the feedback signal FEB, the logic circuit 24 can output a selection signal SEL with a low logic level because the logic circuit 24 performs a NOR operation on the first data signal IN1, which has a digital value corresponding to the phase difference.

[0040] Multiplexer 22 can output a first data signal IN1 as valid data VDATA in response to a select signal SEL with a low logic level.

[0041] The first arithmetic circuit FAFS1 can output a first arithmetic signal by adding or subtracting the valid data VDATA from the stored value. It can be understood that the stored value corresponds to the first register signal REGS1 received from the first register circuit REG1.

[0042] The first register circuit REG1 can store the first arithmetic signal and can output the first arithmetic signal as the first register signal REGS1 in response to the second clock signal CLK2. When the arithmetic operation of the first arithmetic circuit FAFS1 terminates, it can receive the second clock signal CLK2.

[0043] The first register circuit REG1 can provide the first register signal REGS1 to the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2.

[0044] The second operational circuit FAFS2 can output a second operational signal by adding or subtracting the value of at least one bit of the valid data VDATA from the first register signal REGS1. The value of at least one bit can be set to the value of the least significant bit (LSB) of the valid data VDATA.

[0045] The second register circuit REG2 can store the second operation signal and can output the second operation signal as the control signal VCON in response to the third clock signal CLK3. When the operation of the second operation circuit FAFS2 terminates, it can receive the third clock signal CLK3.

[0046] The first operational circuit FAFS1 and the second operational circuit FAFS2 can each act as an adder or a subtractor to perform operations, depending on whether the first data signal IN1 or the second data signal IN2 is selected as the valid data VDATA.

[0047] When the first data signal IN1 is selected as the valid data VDATA, the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each act as adders. When the second data signal IN2 is selected as the valid data VDATA, the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each act as subtractors.

[0048] The first operational circuit FAFS1 and the second operational circuit FAFS2 can receive the selection signal SEL from the logic circuit 24 of the selection circuit 21, and can each perform operations as an adder or a subtractor in response to the logic level of the selection signal SEL.

[0049] Therefore, when the reference signal REF has an earlier phase than the feedback signal FEB, the first operational circuit FAFS1 and the second operational circuit FAFS2 can each act as adders, and when the reference signal REF has a later phase than the feedback signal FEB, the first operational circuit FAFS1 and the second operational circuit FAFS2 can each act as subtractors.

[0050] The first operational circuit FAFS1 and the first register circuit REG1 can be used as a frequency integration path. The second operational circuit FAFS2 and the second register circuit REG2 can be used as a scaling path.

[0051] In the frequency integration path, the first arithmetic circuit FAFS1 adds or subtracts the valid data VDATA and the first register signal REGS1 to generate the first arithmetic signal. The first arithmetic signal can be stored in the first register circuit REG1. In response to the second clock signal CLK2, the first arithmetic signal of the first register circuit REG1 can be output as the first register signal REGS1.

[0052] In the proportional path, the second arithmetic circuit FAFS2 adds or subtracts the least significant bit (LSB) of the valid data VDATA from the first register signal REGS1 to generate a second arithmetic signal. This second arithmetic signal can be stored in the second register circuit REG2. In response to the third clock signal CLK3, the second arithmetic signal from the second register circuit REG2 can be output as the control signal VCON.

[0053] In the frequency integration path and the proportional path, when the reference signal REF has an earlier phase than the feedback signal FEB, the first operational circuit FAFS1 and the second operational circuit FAFS2 can each perform operations as adders, and when the reference signal REF has a later phase than the feedback signal FEB, the first operational circuit FAFS1 and the second operational circuit FAFS2 can each perform operations as subtractors.

[0054] Figure 2 This is a detailed block diagram of the digital loop filter 20 in an all-digital phase-locked loop according to an embodiment.

[0055] refer to Figure 2 When the reference signal REF has an earlier phase than the feedback signal FEB, the digital loop filter 20 can receive the first data signal IN1 from the first time-to-digital converter circuit TDC_P as a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB.

[0056] Furthermore, when the reference signal REF has a later phase than the feedback signal FEB, the digital loop filter 20 can receive the second data signal IN2 from the second time-to-digital converter circuit TDC_N as a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB.

[0057] Selection circuit 21 can select either the first data signal IN1 or the second data signal IN2 as valid data VDATA based on the value of the first data signal IN1 by using logic circuit 24 and multiplexer 22.

[0058] The first arithmetic circuit FAFS1 can output the first arithmetic signal FAS1[0:n-1] by adding or subtracting the value of the preset bits VDATA[0:n-2] of the valid data VDATA from the first register circuit REG1, which is the stored value of the first register signal REGS1. The first arithmetic circuit FAFS1 can receive the stored value (i.e., the value of the first register signal REGS1[0:n-1]) from the first register circuit REG1.

[0059] The first register circuit REG1 can store the first operation signal FAS1[0:n-1], and can output the first operation signal FAS1[0:n-1] as the first register signal REGS1[0:n-1] in response to the second clock signal CLK2.

[0060] When the operation of the first arithmetic circuit FAFS1 terminates, the first register circuit REG1 can receive the second clock signal CLK2.

[0061] The first register circuit REG1 can provide the first register signal REGS1[0:n-1] to the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2.

[0062] The second operational circuit FAFS2 can output the second operational signal FAS2[0:n-1] to the second register circuit REG2 by adding or subtracting the value of the LSB VDATA[0] of the valid data VDATA from the first register signal REGS1[0:n-1].

[0063] The second register circuit REG2 can store the second operation signal FAS2[0:n-1], and can output the second operation signal FAS2[0:n-1] as the control signal VCON in response to the third clock signal CLK3.

[0064] When the operation of the second arithmetic circuit FAFS2 terminates, the second register circuit REG2 can receive the third clock signal CLK3.

[0065] The first operational circuit FAFS1 and the second operational circuit FAFS2 can receive the selection signal SEL from the logic circuit 24 of the selection circuit 21, and can each perform operations as an adder or a subtractor in response to the logic level of the selection signal SEL.

[0066] When the first data signal IN1 is selected as the valid data VDATA, the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each perform operations as adders in response to the selection signal SEL with a low logic level.

[0067] When the second data signal IN2 is selected as the valid data VDATA, the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each act as subtractors in response to the selection signal SEL with a high logic level.

[0068] That is, when the reference signal REF has a phase earlier than the feedback signal FEB, the first data signal IN1 can be selected as the valid data VDATA, and the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each perform operations as adders. When the reference signal REF has a phase later than the feedback signal FEB, the second data signal IN2 can be selected as the valid data VDATA, and the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each perform operations as subtractors.

[0069] As described above, because the digital loop filter 20 can be implemented using digital circuits such as adders, subtractors, and registers, without requiring a signal synthesis block for digital encoding, the digital loop filter 20 can be easily and quickly verified as a digital phase-locked loop.

[0070] In the first operational circuit FAFS1 and the second operational circuit FAFS2, A[0] and A[1:n] correspond to the first input signal A, and B[0:n-1] and B[n] correspond to the second input signal B. (Refer to...) Figure 4 Describe the first input signal A and the second input signal B. It is understood that the first input signal A and the second input signal B have the same number of bits. Furthermore, VSS can be understood as fixed values ​​corresponding to A[1:n] and B[n] respectively.

[0071] Figure 3 This is a flowchart illustrating the operation of a digital loop filter 20 in an all-digital phase-locked loop according to an embodiment.

[0072] First, the digital loop filter 20 receives the first data signal IN1 and the second data signal IN2 through the time-to-digital conversion circuit, that is, the digital values ​​corresponding to the phase difference between the reference signal REF and the feedback signal FEB, respectively (S11).

[0073] Next, the digital loop filter 20 selects the valid data VDATA through the selection circuit 21 (S12). For example, when the value of the first data signal IN1 is “0”, the digital loop filter 20 outputs the second data signal IN2 as the valid data VDATA, and when the value of the first data signal IN1 is not “0”, the digital loop filter 20 outputs the first data signal IN1 as the valid data VDATA.

[0074] In the frequency integration path, the first arithmetic circuit FAFS1 adds or subtracts the value of the preset bits VDATA[0:n-2] of the valid data VDATA with the stored value of the first register circuit REG1, and stores the first arithmetic signal FAS1[0:n-1] in the first register circuit REG1 (S13).

[0075] Furthermore, in the proportional path, when the operation of the first operation circuit FAFS1 terminates, the second operation circuit FAFS2 receives the first register signal REGS1[0:n-1] provided in response to the second clock signal CLK2, adds or subtracts the value of the LSB of the first register signal REGS1[0:n-1] and the valid data VDATA, and stores the second operation signal FAS2[0:n-1] in the second register circuit REG2 (S14).

[0076] After the operation of the second operational circuit FAFS2, the digital loop filter 20 outputs the control signal VCON (S15) in response to the third clock signal CLK3.

[0077] Figure 4 yes Figure 1 and Figure 2 The circuit diagram of the operational circuit shown is shown.

[0078] Reference Figure 4 In response to the selection signal SEL, the arithmetic circuit can perform operations as an adder or a subtractor.

[0079] For example, when a selection signal SEL with a low logic level is received, the arithmetic circuit can perform operations as an adder to add the first input signal A and the second input signal B. When a selection signal SEL with a high logic level is received, the arithmetic circuit can perform operations as a subtractor to add the inverted signal of the first input signal A and the second input signal B, that is, to subtract the first input signal A and the second input signal B.

[0080] Figure 4In this diagram, FA is an adder. Each of A0, A1, A2, and A3 corresponds to the first input signal A. Each of B0, B1, B2, and B3 corresponds to the second input signal B. Each of S0, S1, S2, and S3 corresponds to the output signal of the arithmetic circuit. Furthermore, each of Cn, C0, C1, C2, C3, and C4 corresponds to the shift signal of the selection signal SEL used to control the adder FA.

[0081] Figure 5 This is a block diagram of a fully digital phase-locked loop according to an embodiment.

[0082] Reference Figure 5 The digital phase-locked loop may include a time-to-digital converter 10, a digital loop filter 20, a digitally controlled oscillator (DCO) 30, a divider 40, and a clock generator 50.

[0083] The time-to-digital converter circuit 10 can convert the phase difference between the reference signal REF and the feedback signal FEB into a digital value, and can output the second data signal IN2 and the first data signal IN1 corresponding to the digital value to the digital loop filter 20.

[0084] When the reference signal REF has an earlier phase than the feedback signal FEB, the time-to-digital converter 10 can output a first data signal IN1 as a digital value, and when the reference signal REF has a later phase than the feedback signal FEB, the time-to-digital converter 10 can output a second data signal IN2 as a digital value.

[0085] The digital loop filter 20 can select one of the first data signal IN1 and the second data signal IN2 as the valid data VDATA, and can output the control signal VCON by performing operations on the valid data VDATA and the stored value.

[0086] DCO 30 can generate an oscillation signal DCO_OUT, and the frequency of the oscillation signal DCO_OUT can be controlled in response to the control signal VCON.

[0087] The divider 40 generates a feedback signal FEB by dividing the oscillation signal DCO_OUT by a preset division ratio N (N is a natural number), and outputs the feedback signal FEB to the time-to-digital converter 10. The division ratio N can be determined according to the protocol between the external device and the application using a phase-locked loop.

[0088] Clock generator 50 can receive reference signal REF and can generate first clock signal CLK1, second clock signal CLK2 and third clock signal CLK3 by using reference signal REF.

[0089] The clock generator 50 can provide the first clock signal CLK1 to the time-to-digital conversion circuit 10, and can provide the second clock signal CLK2 and the third clock signal CLK3 to the digital loop filter 20.

[0090] In response to the first clock signal CLK1, the time-to-digital converter 10 can output the first data signal IN1 and the second data signal IN2 to the digital loop filter 20.

[0091] The digital loop filter 20 can perform an operation in response to the second clock signal CLK2, and can provide the control signal VCON to the DCO 30 in response to the third clock signal CLK3.

[0092] Figure 6 This is a detailed block diagram of the all-digital phase-locked loop according to an embodiment.

[0093] Reference Figure 6 The digital phase-locked loop may include a time-to-digital converter 10, a digital loop filter 20, a DCO 30, a divider 40, and a clock generator 50.

[0094] The time-to-digital conversion circuit 10 may include a first time-to-digital conversion circuit and a second time-to-digital conversion circuit. The first time-to-digital conversion circuit and... Figure 2 The first time-to-digital converter circuit TDC_P corresponds to, and the second time-to-digital converter circuit corresponds to... Figure 2 The second time-to-digital converter circuit TDC_N corresponds to this.

[0095] When the reference signal REF has a phase earlier than the feedback signal FEB, the first time-to-digital converter can output a first data signal IN1 as a digital value. When the reference signal REF has a phase later than the feedback signal FEB, the second time-to-digital converter can output a second data signal IN2 as a digital value.

[0096] The first time-to-digital conversion circuit may include a positive time-to-digital converter TDC_PS 11, a first encoder 13, and a first register 15.

[0097] The positive time-to-digital converter 11 converts the phase difference between the reference signal REF and the feedback signal FEB into a digital value. The first encoder 13 converts the digital value of the positive time-to-digital converter 11 into a binary number.

[0098] The first register 15 can store the binary number of the first encoder 13, and can output the binary number of the first encoder 13 as the first data signal IN1 in response to the first clock signal CLK1.

[0099] The second time-to-digital converter circuit may include a negative time-to-digital converter TDC_NS 12, a second encoder 14, and a second register 16.

[0100] The negative time-to-digital converter 12 converts the phase difference between the reference signal REF and the feedback signal FEB into a digital value. The second encoder 14 converts the digital value from the negative time-to-digital converter 12 into a binary number.

[0101] The second register 16 can store the binary number of the second encoder 14, and can output the binary number of the second encoder 14 as the second data signal IN2 in response to the first clock signal CLK1.

[0102] The digital loop filter 20 may include a selection circuit 21, a first operational circuit FAFS1, a first register circuit REG1, a second operational circuit FAFS2, and a second register circuit REG2.

[0103] The selection circuit 21 can select one of the first data signal IN1 and the second data signal IN2 as the valid data VDATA based on the value of the first data signal IN1.

[0104] When the reference signal REF has an earlier phase than the feedback signal FEB, the selection circuit 21 can select the first data signal IN1 as the valid data VDATA. Furthermore, when the reference signal REF has a later phase than the feedback signal FEB, the selection circuit 21 can select the second data signal IN2 as the valid data VDATA.

[0105] The first arithmetic circuit FAFS1 can output the first arithmetic signal by adding or subtracting the valid data VDATA and the stored value of the first register circuit REG1.

[0106] The first register circuit REG1 can store the first arithmetic signal and, in response to the second clock signal CLK2, output the first arithmetic signal as the first register signal REGS1 to the second arithmetic circuit FAFS2.

[0107] The second operational circuit FAFS2 can output the second operational signal by adding or subtracting the value of the LSB of the valid data VDATA from the output signal of the first register circuit REG1.

[0108] The second register circuit REG2 can store the second operation signal and can output the second operation signal as the control signal VCON in response to the third clock signal CLK3.

[0109] Depending on whether the first data signal IN1 or the second data signal IN2 is selected as the valid data VDATA, the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each be used as an adder or a subtractor to perform operations.

[0110] When the first data signal IN1 is selected as the valid data VDATA, the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each act as adders to perform operations. When the second data signal IN2 is selected as the valid data VDATA, the first arithmetic circuit FAFS1 and the second arithmetic circuit FAFS2 can each act as subtractors to perform operations.

[0111] DCO 30 can control the frequency of the oscillation signal DCO_OUT in response to the control signal VCON, and can provide the oscillation signal DCO_OUT to the divider 40.

[0112] The divider 40 can provide the time-to-digital converter 10 with a feedback signal FEB obtained by dividing the oscillation signal DCO_OUT by a preset division ratio N.

[0113] The clock generator 50 can generate a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3 using a reference signal REF. The first clock signal CLK1 can be provided to the time-to-digital conversion circuit 10, and the second clock signal CLK2 and the third clock signal CLK3 can be provided to the digital loop filter 20.

[0114] The time-to-digital converter circuit 10 can respond to the first clock signal CLK1 of the clock generator 50 and provide the first data signal IN1 and the second data signal IN2 to the digital loop filter 20.

[0115] The digital loop filter 20 can operate in response to the second clock signal CLK2 of the clock generator 50, and can provide the control signal VCON to the DCO 30 in response to the third clock signal CLK3.

[0116] Figure 7 This is a flowchart describing the operation of a fully digital phase-locked loop according to an embodiment.

[0117] Reference Figure 7 The all-digital phase-locked loop can detect the rising edges of the reference signal REF and the feedback signal FEB through the positive time-to-digital converter TDC_PS11 and the negative time-to-digital converter TDC_NS12 respectively, and can output a digital value corresponding to the time difference between the two rising edges (S21).

[0118] When the reference signal REF has an earlier phase than the feedback signal FEB, the positive time-to-digital converter TDC_PS 11 outputs a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB. When the reference signal REF has a later phase than the feedback signal FEB, the negative time-to-digital converter TDC_NS 12 outputs a digital value corresponding to the phase difference between the reference signal REF and the feedback signal FEB.

[0119] Next, the all-digital phase-locked loop can convert the digital value corresponding to the phase difference into a binary number through encoders 13 and 14 respectively (S22).

[0120] Next, in response to the first clock signal CLK1 received after the operation of the time-to-digital converters 11 and 12 and the encoders 13 and 14, the all-digital phase-locked loop can output the binary numbers stored in the first register 15 and the second register 16 as the first data signal IN1 and the second data signal IN2 to the digital loop filter 20 (S23).

[0121] Next, the all-digital phase-locked loop can select one of the first data signal IN1 and the second data signal IN2 as valid data VDATA based on the value of the first data signal IN1 by the selection circuit 21 (S24).

[0122] Next, after the operation of the second operation circuit FAFS2, the all-digital phase-locked loop can respond to the third clock signal CLK3 and output a control signal VCON (S25) to DCO 30 that corresponds to the operation signal of the second operation circuit FAFS2.

[0123] As described above, according to the embodiments, because the digital loop filter can be implemented using digital circuitry without requiring a signal synthesis block for digital encoding, the digital loop filter can be easily and quickly verified as an all-digital phase-locked loop.

Claims

1. Digital loop filters in all-digital phase-locked loops, including: The selection circuit is configured to output one of the first data signal and the second data signal as valid data. The first arithmetic circuit is configured to output a first arithmetic signal by adding or subtracting the valid data and the first register signal; The first register circuit is configured to store the first arithmetic signal and output the first arithmetic signal as the first register signal. The second arithmetic circuit is configured to output a second arithmetic signal by adding or subtracting the value of at least one bit of the valid data from the first register signal. as well as The second register circuit is configured to store the second operation signal and output the second operation signal as a control signal.

2. The digital loop filter according to claim 1, wherein, The selection circuit receives the first data signal and the second data signal obtained by converting the phase difference between the reference signal and the feedback signal into a digital value.

3. The digital loop filter according to claim 2, wherein, When the reference signal has an earlier phase than the feedback signal, the selection circuit receives the first data signal as a digital value corresponding to the phase difference; and when the reference signal has a later phase than the feedback signal, the selection circuit receives the second data signal as a digital value corresponding to the phase difference.

4. The digital loop filter according to claim 1, wherein, The selection circuit selects either the first data signal or the second data signal as the valid data based on the value of the first data signal.

5. The digital loop filter according to claim 4, wherein, The selection circuit includes: A logic circuit configured to perform a logic operation on the first data signal and output a selection signal; and A multiplexer configured to output either the first data signal or the second data signal as the valid data in response to the selection signal.

6. The digital loop filter according to claim 1, wherein, Depending on whether the first data signal or the second data signal is selected as the valid data, the first arithmetic circuit and the second arithmetic circuit each perform operations as adders or subtractors.

7. The digital loop filter according to claim 6, wherein, When the first data signal is selected as the valid data, the first arithmetic circuit and the second arithmetic circuit each act as the adder to perform the operation; and when the second data signal is selected as the valid data, the first arithmetic circuit and the second arithmetic circuit each act as the subtractor to perform the operation.

8. The digital loop filter according to claim 1, wherein, The at least one bit of the valid data includes the least significant bit.

9. The digital loop filter according to claim 1, wherein: The first register circuit responds to the first clock signal by outputting the first register signal to the first arithmetic circuit and the second arithmetic circuit, and When the operation of the first arithmetic circuit terminates, the first clock signal is received.

10. The digital loop filter according to claim 9, wherein: The second register circuit outputs the control signal in response to the second clock signal, and When the operation of the second arithmetic circuit terminates, the second clock signal is received.

11. A digital loop filter in an all-digital phase-locked loop, comprising: The selection circuit is configured to receive a first data signal and a second data signal corresponding to the phase difference between the reference signal and the feedback signal, and output one of the first data signal and the second data signal as valid data. The frequency integration path is configured to store a first operation signal obtained by adding or subtracting the value of the effective data from a first register signal, and to output a first register signal corresponding to the first operation signal; as well as The proportional path is configured to store a second operational signal obtained by adding or subtracting the value of at least one low bit of the valid data from the first register signal, and to output a control signal corresponding to the second operational signal.

12. The digital loop filter according to claim 11, wherein, When the reference signal has an earlier phase than the feedback signal, the selection circuit selects the first data signal.

13. The digital loop filter according to claim 11, wherein, When the reference signal has a later phase than the feedback signal, the selection circuit selects the second data signal.

14. The digital loop filter according to claim 11, wherein, The frequency integration path includes: The first arithmetic circuit is configured to output the first arithmetic signal by adding or subtracting the value of the valid data from the first register signal; and The first register circuit is configured to store the first operational signal and output the first register signal in response to a first clock signal.

15. The digital loop filter according to claim 14, wherein, The proportional path includes: The second arithmetic circuit is configured to output the second arithmetic signal by adding or subtracting the value of at least one bit of the valid data from the first register signal; and The second register circuit is configured to store the second operational signal and output the control signal in response to the second clock signal.

16. The digital loop filter according to claim 15, wherein, When the reference signal has an earlier phase than the feedback signal, the first arithmetic circuit and the second arithmetic circuit each perform operations as adders, and when the reference signal has a later phase than the feedback signal, the first arithmetic circuit and the second arithmetic circuit each perform operations as subtractors.

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