Integrated circuit comprising a composite dielectric layer

Abstract

In some examples, an integrated circuit (100) includes an isolation layer (103) disposed on or over a semiconductor substrate (130). The integrated circuit also includes a first conductive plate (104) located over the isolation layer and a composite dielectric layer (109) located over the first conductive plate. The composite dielectric layer includes a first sub-layer (132) comprising a first chemical composition, a second sub-layer (134) comprising a second, different chemical composition, and a third sub-layer (136) comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate (108) directly on the composite dielectric layer over the first conductive plate.

Description

Summary of the Invention

[0001] According to some embodiments of this disclosure, an integrated circuit includes an isolation layer disposed on or above a semiconductor substrate. The integrated circuit also includes a first conductive plate disposed above the isolation layer and a composite dielectric layer disposed above the first conductive plate. The composite dielectric layer includes: a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate disposed directly above the first conductive plate on the composite dielectric layer.

[0002] According to some examples of this disclosure, a method of manufacturing an integrated circuit includes providing a semiconductor substrate, wherein the semiconductor substrate includes: an isolation layer disposed on or above the semiconductor substrate; and a first conductive plate disposed above the isolation layer. The method further includes forming a composite dielectric layer on the first conductive plate, wherein the composite dielectric layer includes a first sublayer and a second sublayer, each of the first sublayer and the second sublayer having a substantially identical first chemical composition. The method then includes: forming a third sublayer between the first sublayer and the second sublayer, the third sublayer having a second different chemical composition; and forming a second conductive plate directly disposed on the composite dielectric layer. Attached Figure Description

[0003] To describe the various examples in detail, reference will now be made to the accompanying drawings, in which:

[0004] Figure 1 Depicts illustrative integrated circuits including precision capacitors and transistors based on various examples;

[0005] Figure 2 An illustrative method describing how to fabricate integrated circuits based on various examples; and

[0006] Figures 3(a)-3(j) Describes the fabrication of integrated circuits in the continuous fabrication stage based on various examples. Detailed Implementation

[0007] For example, high-precision analog integrated circuits such as analog-to-digital converters typically employ several precision capacitors for proper operation. For instance, in bit converters, some capacitor requirements include: ratio stability less than 0.00075% over 10 years; voltage coefficient less than 10 ppm / V; temperature drift matching less than 0.05% / ℃; dielectric absorption less than 0.00075%; and capacitance greater than 0.5 fF / μm². Precision capacitors are generally formed as part of the fabrication process used to create analog integrated circuits. In some cases, precision capacitors are formed by stacking multiple layers of dielectric material between two conductive plates. The conductive plates can be formed using conductive materials present in the integrated circuit, such as titanium nitride, doped polysilicon, and / or metals. The stack of multiple layers may contain one or more dielectric material layers, such as silicon nitride and silicon dioxide. For example, a stack of multiple dielectric materials may include: a first layer comprising silicon dioxide (SiO2); a second layer comprising silicon nitride (Si3N4); and a third layer comprising silicon dioxide, wherein one silicon dioxide layer contacts a top conductive plate, another silicon dioxide layer contacts a bottom conductive plate, and a silicon nitride layer is disposed between the two silicon dioxide layers. This stack of silicon dioxide, silicon nitride, and silicon dioxide is sometimes referred to as an ONO stack.

[0008] Current fabrication processes employ a silicon nitride (Si3N4) metal-before-dielectric (PMD) liner layer. This liner layer provides tensile strength, protects the underlying transistor from the subsequently formed PMD material, and acts as an etch stop layer during the formation of openings for contacting the transistor and precision capacitors via the PMD material. The PMD liner is typically deposited on an ONO stack, which presents additional challenges to such configurations. During contact opening formation, the contact etching process must vary the etching chemicals under different conditions because different dry / wet etching chemicals are applied to etch the silicon nitride and silicon oxide layers. For example, etching silicon oxide requires a first etching chemical containing tetrafluoromethane / oxygen (CF4 / O2) plasma and a mixture of argon, hydrogen, and perfluorocyclopentene (C5F8). However, etching silicon nitride requires a second etching chemical containing CF4 plasma and a mixture of argon and difluoromethane (CH2F2). From a manufacturing perspective, varying the etching chemicals during the contact etching process under different conditions is undesirable. Therefore, a fabrication method that mitigates these problems is needed.

[0009] Therefore, the systems and methods described in this disclosure mitigate the aforementioned problems. This disclosure describes a dielectric stack comprising an ONO layer that, in addition to performing the intended function of the dielectric, also acts as a PMD liner layer. Specifically, silicon nitride present in the ONO stack functions as an etch stop layer and provides beneficial tensile strength to the underlying transistor. Using this multifunctional ONO stack eliminates the need for a separate liner layer and thus reduces the number of instances requiring changes to the etch chemicals.

[0010] The examples illustrated in the accompanying drawings will now be referred to in detail. Where possible, the same element symbols are used in the figures and description to refer to the same or similar parts. In the figures, the shape and thickness of an example may be enlarged for clarity and convenience. Element not specifically shown or described may take various forms. Furthermore, when a layer is referred to as being "on another layer" or "on a substrate," the layer may be directly on another layer or on a substrate, or an intermediate layer may be present.

[0011] Figure 1 An illustrative integrated circuit 100 is depicted, comprising a precision capacitor 110 and a transistor 120, wherein the transistor 120 is formed in and on a semiconductor substrate 130. The semiconductor substrate 130 may be, for example, a silicon wafer, a gallium arsenide wafer or other alloy compound semiconductor wafer, a silicon-on-insulator (SOI) wafer, or other substrates suitable for forming the integrated circuit 100. The precision capacitor 110 is formed on an isolation layer 103, wherein the isolation layer 103 is a thick silicon oxide layer (e.g., 3500-4500 Å) and serves to prevent current leakage between adjacent semiconductor device components, such as transistors. In some embodiments, the isolation layer 103 is a shallow trench isolation (STI) region, and in other embodiments, the isolation layer 103 (also referred to as a LOCOS layer / region) is formed by locally oxidizing silicon.

[0012] Figure 1 The isolation layer 103 depicted is an STI layer and is formed earlier during the semiconductor device fabrication process and before the formation of the semiconductor device assembly. The STI process includes steps such as: etching trench patterns in a semiconductor substrate; depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trenches; and using techniques such as chemical mechanical planarization to remove excess dielectric. This isolation layer 103, formed before device fabrication, divides the semiconductor substrate 130 into active and isolation regions. Figure 1 (An example of such a region is shown in the figure). The active region 101 is the location in the semiconductor substrate 130 where active devices such as transistors are formed, while the isolation region 102 is the region that isolates the active devices.

[0013] In a transient example, the precision capacitor 110 includes a base plate 104, a top plate 108, and a composite dielectric layer 109 disposed between the base plate 104 and the top plate 108. In some examples, the base plate 104 comprises polycrystalline silicon (commonly referred to as polysilicon) with a thickness of 50 nanometers to 1000 nanometers, and may include a metal silicide layer 113 on the base plate 104. The metal silicide layer 113 may comprise, for example, titanium silicide, tungsten silicide, platinum silicide, cobalt silicide, molybdenum silicide, or nickel silicide. In some examples, dielectric sidewalls 111 and 112 may be present on the lateral surface of the base plate 104.

[0014] The top plate 108 may include one or more layers of titanium, titanium nitride, tantalum, tantalum nitride, tantalum-tungsten, and / or tungsten, having a thickness of, for example, about 20 nanometers to 300 nanometers. The bottom plate 104, the composite dielectric layer 109, and the top plate 108 form a precision capacitor 110. The lateral dimensions of the precision capacitor 110 can be controlled by photolithography and etching processes used to define the lateral dimensions of the top plate 108.

[0015] The composite dielectric layer 109 may comprise multiple sublayers, for example, a first sublayer 132, a second sublayer 134, and a third sublayer 136. The first sublayer 132 comprises a first chemical composition, the second sublayer 134 comprises a second different chemical composition, and the third sublayer 136 comprises a chemical composition substantially similar to the first chemical composition. In one example, the first sublayer 132 comprises silicon oxide, the second sublayer 134 comprises silicon nitride, and the third sublayer 136 comprises silicon oxide. The composite dielectric layer 109 may also be represented as an ONO stack, where O represents silicon oxide and N represents silicon nitride. The integrated circuit 100 also includes another dielectric layer 118 directly located on and laterally extending from the top plate 108. In one example, the dielectric layer 118 comprises a hard mask material, such as silicon nitride, silicon carbide, or amorphous carbon.

[0016] Referring now to transistor 120, the transistor includes a gate dielectric layer 123 of a metal-oxide-semiconductor (MOS) transistor. The gate dielectric layer 123 is formed at the top surface of a semiconductor substrate 130. A source region 121 and a drain region 122 of transistor 120 are formed in the semiconductor substrate 130 below a gate electrode 124. In some embodiments, the gate electrode 124 may comprise polysilicon. Optionally, metal silicide layers 125, 128, and 129 may be formed on the gate electrode 124, the source region 121, and the drain region 122. The metal silicide layers 125, 128, and 129 may comprise, for example, titanium silicide, tungsten silicide, platinum silicide, cobalt silicide, molybdenum silicide, or nickel silicide. In some embodiments, dielectric sidewalls 126 and 127 may be present on the lateral surface of the gate electrode 124.

[0017] A composite dielectric layer 109 is also disposed on the gate electrode 124 and serves as both an etch stop layer and a metal front dielectric liner layer. A second sublayer 134 of the composite dielectric layer 109 is a nitride layer and is configured to provide tensile stress in the transistor 120 to enhance carrier mobility, thereby promoting high-speed, low-power, low-voltage device operation. The second sublayer 134 is a nitride layer and may contain any silicon nitride material. The second sublayer 134 also serves as an etch stop material during the formation of openings for contacting transistor terminals through an overlying dielectric (e.g., a metal front dielectric layer 140 or a PMD layer 140). The PMD layer 140 may contain, for example, borosilicate glass (BPSG). The top surface of the PMD layer 140 may be located, for example, 100 nm to 2000 nm above the top surface of the semiconductor substrate 130.

[0018] The integrated circuit 100 also includes conductive contacts 152, 154, 156, 158, and 160, which are formed through a portion of the PMD layer 140 and the composite dielectric layer 109, and are connected to metal interconnects 144, 145, 146, 147, and 148 present on the top surface of the PMD layer 140, respectively. Conductive contacts 152, 154, and 156 form conductive contacts to transistor terminals (e.g., siliconized transistor gate electrode 124, siliconized source region 121, and siliconized drain region 122, respectively), and conductive contacts 158 and 160 form conductive contacts to capacitor terminals (e.g., siliconized substrate 104 and siliconized top plate 108, respectively).

[0019] Metal interconnects 144-148 exist on the first level. Figure 1 Other metal interconnects present in subsequent layers are not explicitly shown. Metal interconnects 144-148 provide electrical interconnects between various electrical components in integrated circuit 100, wherein each layer includes an inter-layer or inter-layer dielectric (ILD) formed on the previous layer, wherein conductive contacts (also called vias) and / or trenches formed and filled with conductive material (e.g., copper, etc.) are formed and filled.

[0020] For reference Figure 2 This document illustrates an illustrative method 200 for fabricating integrated circuit 100. Although method 200 is illustrated and described below as a series of actions or events, it should be understood that the method for fabricating integrated circuit 100 is not limited to the illustrated order of such actions or events. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those illustrated and / or described herein. Moreover, implementing a method may not require all the illustrated steps.

[0021] Combination Figures 3(a)-3(j) Description method 200, Figures 3(a)-3(j)The fabrication of integrated circuit 100 in a continuous fabrication phase is depicted. Method 200 begins at block 210, the method comprising providing a semiconductor substrate 130, the semiconductor substrate including an isolation layer 103, a substrate 104 and a gate electrode 124 (FIG. 3(e)).

[0022] Several fabrication processes can be performed prior to obtaining the semiconductor substrate 130, as shown in Figure 3(e), and regarding Figure 3(a)-3(e) The steps are described. Various front-end processing steps may be performed prior to method 200, including forming n-wells and p-wells using diffusion, implantation, or other suitable processing steps (Figure 3(a)). The n-wells and p-wells are not explicitly shown in Figure 3(a). Figure 3(a) depicts a semiconductor substrate 130 having a top surface 161. The front-end processing steps may further include forming an isolation structure in the field region of the semiconductor substrate 130 using LOCOS, STI, or any suitable isolation process prior to transistor formation. Figure 3(b) depicts an isolation layer 103 formed using an STI fabrication process. The steps of the STI process include: etching a trench pattern in the semiconductor substrate; depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trenches; and removing excess dielectric material using techniques such as chemical mechanical planarization.

[0023] As described above, isolation layer 103 forms both the active region and the isolation region in semiconductor substrate 130. Isolation region 102 is shown in FIG. 3(b). After the isolation layer 103 is formed, the intended channel region of the semiconductor body may initially be doped to adjust the intended transistor work function, suppress punch-through, etc. Subsequently, the gate dielectric (e.g., gate dielectric layer 123; FIG. 3(c)) can be formed by oxidizing semiconductor substrate 130 (e.g., silicon) to form a thin (e.g., 5-200 nm) insulating layer of gate dielectric layer (e.g., silicon dioxide) on top surface 161, and the conductive gate structure (e.g., gate electrode 124; FIG. 3(d)) together with substrate 104 can then be formed over gate dielectric layer 123 and isolation layer 103, respectively, by deposition and patterning of doped polysilicon or other conductive materials.

[0024] Furthermore, source region 121 and drain region 122 can then be doped with a type of dopant suitable for n-channel or p-channel transistors, for example, by selective implantation (FIG. 3(e)). After the source / drain regions are formed, a silicide process can then be performed to create conductive contacts at the transistor terminals. For example, metal silicide layers 125, 128, and 129 can be formed on source region 121, drain region 122, and gate electrode 124, respectively, using any suitable material (e.g., nickel silicide, cobalt silicide, etc.). A silicide process can also be performed to create conductive contacts at substrate 104. For example, metal silicide layer 113 can be formed during the silicide process step. In some instances, in addition to the silicide process, sidewalls can also be formed on the lateral surfaces of gate electrode 124 and substrate 104. For example, dielectric sidewalls 126 and 127 may be formed on the lateral surface of the gate electrode 124, and dielectric sidewalls 111 and 112 may be formed on the lateral surface of the substrate 104. Figure 3(e) depicts transistor 120.

[0025] Method 200 may now proceed to block 220 (and FIG. 3(f)), wherein the method includes forming a composite dielectric layer 109 over a substrate 104 and a gate electrode 124. The composite dielectric layer 109 comprises a plurality of sublayers (e.g., sublayers 132, 134, and 136), wherein at least one of the sublayers (e.g., sublayer 134) is a nitride layer (block 230; FIG. 3(f)), and sublayers 132 and 136 are oxide layers. In one example, the composite dielectric layer 109 may be formed using plasma-enhanced chemical vapor deposition (PECVD) at a relatively low deposition temperature of about 350°C or lower. The PECVD deposition process may employ a PECVD chamber and begin the deposition of a third sublayer 136 (e.g., silicon oxide). In some instances, the third sublayer 136 is deposited using nominal process parameters, including a deposition temperature of 350°C, a pressure of 8 Torr (approximately 1067 Pa), a high-frequency (HF) RF power of 312 W, a silane (SiH4) flow rate of 42 sccm, a helium (He) flow rate of 8000 sccm, a nitrous oxide (N2O) flow rate of 1420 sccm, and a target thickness of 9 nm. "High-frequency" is defined as a frequency range from approximately 13 MHz to approximately 15 MHz. Optionally, the parameters can be selected from the following corresponding ranges: temperature, 325°C to 425°C; pressure, 6.4 Torr (853 Pa) to 9.6 Torr (1280 Pa); HF RF power, 230 W to 390 W; SiH4 flow rate, 34 sccm to 50 sccm; He flow rate, 6400 sccm to 9600 sccm; N2O flow rate, 1130 sccm to 1700 sccm; and target thickness, 5 nm to 20 nm.

[0026] In some instances, the second sublayer 134 is deposited directly on the third sublayer 136, and preferably this can be done without disrupting the vacuum in the deposition chamber. Deposition conditions may include controlling the PECVD chamber pressure to about 2.5 Torr (about 333 Pa) and providing silane (SiH4) gas at a flow rate of about 175 sccm ± 20%, ammonia (NH3) gas at a flow rate of about 400 sccm, nitrogen gas at a flow rate of about 8000 sccm, and high-frequency RF power at about 230 W. A nominal thickness of about 22 nm can be targeted. This illustrative PECVD process provides chemically stable silicon nitride films (e.g., SiH4) with low hydrogen content. X N Y In one example, X is approximately 3 and Y is approximately 4), where the bonds of hydrogen to silicon (e.g., Si-H bonds) and hydrogen to nitrogen (e.g., NH bonds) are approximately equal. Furthermore, this deposition stabilizes the nitride film, imparting a moderate initial tensile stress to the transistor (0-600 MPa in this example). Optionally, the deposition parameters of the second sublayer 134 can be selected from the following corresponding ranges: temperature, 325°C to 425°C; pressure, 2 Torr (267 Pa) to 3 Torr (400 Pa); HF RF power, 170 W to 290 W; SiH4 flow rate, between 140 sccm and 210 sccm; NH3 flow rate, between 320 sccm and 480 sccm; and N2 flow rate, between 6400 sccm and 9600 sccm. The thickness can be in the range of 15 nm to 50 nm. In some instances, the first sublayer 132 is deposited directly on the second sublayer 134, and this is preferably done without disrupting the vacuum in the deposition chamber.

[0027] Optionally, the first sublayer 132 may be formed using the same process conditions used to form the third sublayer 136, and the process conditions may be selected from the same ranges as those described for the third sublayer 136. The nominal thickness of the third sublayer 136 may be 13 nm, and the thickness may be in the range between 5 nm and 20 nm.

[0028] Method 200 then proceeds to block 240, the method comprising forming a top plate 108 on a composite dielectric layer 109 (FIG. 3(g)). The top plate 108 can be formed by directly depositing a conductive layer, such as TiN (or other metallic material), onto a first sublayer 132 and directly depositing a photoresist layer onto the conductive layer. The photoresist layer is then patterned, and the conductive layer is etched to form the top plate 108. In some instances, a dielectric layer may also be deposited on the conductive layer. In these instances, a photoresist layer is deposited and patterned on the dielectric layer, and the dielectric layer may first be patterned (e.g., as a hard mask), thereby forming a dielectric layer 118. The conductive layer may then be etched to form the top plate 108.

[0029] Figure 3(h) depicts a PMD layer 140, which is formed by depositing, for example, borosilicate glass (BPSG) or silica on the exposed portion of the composite dielectric layer 109, the top surface of the dielectric layer 118, and the sidewalls of the top plate 108 and the dielectric layer 118. The PMD layer 140 can be deposited using a chemical vapor deposition process. In some examples, the PMD layer 140 can be deposited to a thickness of 100 nm to 2000 nm. Figure 3(i) depicts conductive contacts 152, 154, 156, 158, and 160, which are formed through portions of the PMD layer 140 and the composite dielectric layer 109 to form connections between different metal interconnects. Conductive contacts 152, 154, and 156 form conductive connections to transistor terminals (e.g., siliconized transistor gate electrode 124, siliconized source region 121, and siliconized drain region 122, respectively), and conductive contacts 158 and 160 form conductive connections to capacitor terminals (e.g., siliconized substrate 104 and top plate 108, respectively). Conductive contacts 152, 154, 156, 158, and 160 can be formed by first etching a portion of the PMD layer 140 to form an opening, and then depositing conductive material into the opening as described below to form conductive contacts. The openings can be created by first patterning the top side of the PMD layer 140 using a conductive contact mask; and then dry etching the PMD layer 140. The dry etching is performed using a first etching chemical comprising tetrafluoromethane / oxygen (CF4 / O2) plasma ions and a mixture of argon, hydrogen, and perfluorocyclopropene (C5F8). The first etching chemical automatically stops etching at the second sublayer 134, which is a nitride layer and acts as an etch stop. At this point, the dry etching process is performed using a second etching chemical compatible with etching away the second sublayer 134, wherein the second etching chemical contains CF4 plasma with a mixture of argon and difluoromethane (CH2F2). As the second sublayer 134 is etched away, the second chemical automatically stops etching, and the dry etching process reaches the third sublayer 136. At this point, the first etching chemical of the dry etching process is re-established to etch through the third sublayer 136.

[0030] After openings are created in the PMD layer 140, conductive contacts 152, 154, 156, 158, and 160 can be formed using the following steps. First, a thin barrier film of titanium is deposited by a suitable deposition process on the bottom and interior of the trench. Next, a titanium nitride layer is deposited on top of the titanium. Finally, the openings are filled with tungsten using a CVD (chemical vapor deposition) process. Figure 3(j) depicts metal interconnects 144-148 present on the top surface of the PMD layer 140. Metal interconnects 144-148 can be formed by first depositing a stack of titanium, titanium nitride, and an aluminum-copper alloy using a deposition (e.g., CVD) process and then patterning it.

[0031] In the foregoing discussion and in the claims, the terms "comprising" and "including" are used in an open manner and should therefore be interpreted as meaning "including but not limited to...". Furthermore, the term "coupled" is intended to mean either an indirect or direct connection. Therefore, if a first device is coupled to a second device, the connection can be a direct connection or an indirect connection via other devices and connections. Similarly, devices coupled between a first component or location and a second component or location can be a direct connection or an indirect connection via other devices and connections. Elements or features "configured" to perform a task or function can be configured by the manufacturer during manufacturing (e.g., programming or structural design) to perform said function, and / or can be configured (or reconfigured) by the user after manufacturing to perform said function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof. Additionally, the phrase "grounding" or similar terms used in the foregoing discussion are intended to encompass chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings of this disclosure. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of that value.

[0032] The foregoing discussion is intended to illustrate the principles and various embodiments of this disclosure. Once fully understanding the foregoing disclosure, those skilled in the art will recognize numerous variations and modifications. The appended claims are intended to be interpreted as encompassing all such variations and modifications.

Claims

1. An integrated circuit, comprising: isolation layer, It is placed on or on a semiconductor substrate; A first conductive plate is located above the insulating layer; A composite dielectric layer is located above the first conductive plate, the composite dielectric layer comprising: The first sublayer and the second sublayer have a substantially identical first chemical composition; A third sublayer is located between the first sublayer and the second sublayer, the third sublayer having a second chemical composition different from the first chemical composition, the second chemical composition comprising silicon, nitrogen and hydrogen; as well as The second conductive plate is located directly on the composite dielectric layer; A second dielectric layer is disposed on the second conductive plate; A metal-front dielectric (PMD) layer is disposed above the composite dielectric layer and the second dielectric layer, the PMD layer comprising borosilicate glass and having a top side; as well as Multiple contacts are formed through the following steps: A first dry etching process is performed using a first etching chemical compatible with etching through the PMD layer and the second sublayer, wherein the first etching chemical comprises a tetrafluoromethane / oxygen CF4 / O2 plasma and a mixture of argon (Ar), hydrogen (H2), and perfluorocyclopentene (C5F8), and wherein the third sublayer acts as an etch stop layer for the first etching chemical. A second dry etching process is performed using a second etching chemical compatible with etching through the third sublayer, wherein the second etching chemical comprises tetrafluoromethane CF4 plasma with a mixture of argon and difluoromethane CH2F2, and wherein the first sublayer acts as an etch stop layer for the second etching chemical. The first dry etching process is restored using the first etching chemicals that are compatible with etching through the first sublayer to form multiple contact openings; and The plurality of contact openings are filled with a conductive material; The formation of the third sublayer comprises providing silane at a flow rate between 175 sccm and 210 sccm, ammonia at a flow rate between 320 and 480 sccm, and nitrogen at a flow rate between 6400 and 9600 sccm, and providing approximately 230 W of high-frequency radio frequency power during the formation of the first, second, and third sublayers, with a substrate temperature of approximately 350°C, and the third sublayer comprising hydrogen bonded substantially equally to silicon and nitrogen.

2. The integrated circuit according to claim 1, further comprising a silicide layer directly located on the first conductive plate, the first sublayer being directly located on the silicide layer.

3. The integrated circuit according to claim 1, further comprising a gate electrode of a transistor located above an active region of the substrate, wherein the composite dielectric layer is located above the first conductive plate and the gate electrode.

4. The integrated circuit according to claim 3, further comprising a first metal silicide layer on the transistor gate and a second metal silicide layer on the polysilicon substrate.

5. The integrated circuit according to claim 3, further comprising: A first conductive contact extends through the PMD and forms a conductive connection with the first conductive plate; A second conductive contact extends through the PMD and forms a conductive connection with the second conductive plate; and A third conductive contact extends through the PMD and the composite dielectric layer and forms a conductive connection with the gate electrode.

6. The integrated circuit according to claim 3, wherein the first conductive plate and the gate electrode are formed from the same polysilicon layer.

7. The integrated circuit of claim 3, wherein the first conductive plate comprises polysilicon and the second conductive plate comprises titanium nitride.

8. The integrated circuit according to claim 1, wherein The first chemical composition includes silicon oxide; and The second chemical composition includes silicon nitride.

9. The integrated circuit of claim 1, wherein the second conductive plate comprises titanium nitride.

10. The integrated circuit of claim 1, further comprising: A first conductive contact extends through the PMD and forms a conductive connection with the first conductive plate; and A second conductive contact extends through the PMD and forms a conductive connection with the second conductive plate.

11. The integrated circuit of claim 1, wherein the first conductive plate comprises polysilicon.

12. The integrated circuit of claim 1, wherein the first sublayer and the second sublayer each have a thickness ranging from 5 nm to 20 nm, and the third sublayer has a thickness ranging from 15 nm to 50 nm.

13. A method for manufacturing an integrated circuit, comprising the following steps: A semiconductor substrate is provided, the substrate comprising: An isolation layer disposed on or above the semiconductor substrate; and A first conductive plate is located above the insulating layer; A composite dielectric layer is formed on the first conductive plate, the formation comprising: A first sublayer and a second sublayer are formed, the first sublayer and the second sublayer having substantially the same first chemical composition; A third sublayer is formed between the first sublayer and the second sublayer, the third sublayer having a second chemical composition different from the first chemical composition, the second chemical composition comprising silicon, nitrogen and hydrogen; and A second conductive plate is formed, which is directly located on the composite dielectric layer; A second dielectric layer is formed on the second conductive plate; A metal-pre-dielectric PMD layer is deposited on the composite dielectric layer and the second dielectric layer, the PMD layer comprising borosilicate glass and having a top side; as well as Multiple contacts are formed, including: A first dry etching process is performed using a first etching chemical compatible with etching through the PMD layer and the second sublayer, wherein the first etching chemical comprises a tetrafluoromethane / oxygen CF4 / O2 plasma and a mixture of argon (Ar), hydrogen (H2), and perfluorocyclopentene (C5F8), wherein the third sublayer acts as an etch stop layer for the first etching chemical. A second dry etching process is performed using a second etching chemical compatible with etching through the third sublayer, wherein the second etching chemical comprises tetrafluoromethane CF4 plasma with a mixture of argon and difluoromethane CH2F2, and wherein the first sublayer acts as an etch stop layer for the second etching chemical. The first dry etching process is resumed using the first etching chemicals compatible with etching through the first sublayer to form multiple contact openings; and The plurality of contact openings are filled with a conductive material; The formation of the third sublayer comprises providing silane at a flow rate between 175 sccm and 210 sccm, ammonia at a flow rate between 320 and 480 sccm, and nitrogen at a flow rate between 6400 and 9600 sccm, and providing approximately 230 W of high-frequency radio frequency power during the formation of the first, second, and third sublayers, with a substrate temperature of approximately 350°C, and the third sublayer comprising hydrogen bonded substantially in equal amounts to silicon and nitrogen.

14. The method of claim 13, further comprising forming the composite dielectric layer on the gate electrode of the transistor gate electrode, wherein the third sublayer imparts tensile stress to the transistor.

15. The method of claim 14, further comprising: Forming each of the plurality of contacts extending from the top side to the gate electrode, the first conductive plate, and the second conductive plate.

16. The method of claim 14, further comprising forming silicide contacts on the gate electrode and the first conductive plate.

17. The method of claim 13, wherein forming the first sublayer and the second sublayer comprises: providing a high-frequency RF power of about 312 W; and flowing silane gas, helium gas, and nitrous oxide gas at about 42 sccm, about 8000 sccm, and about 1420 sccm, respectively.

18. The method of claim 13, wherein the second dielectric layer comprises silicon nitride.

19. The method of claim 13, wherein the first conductive plate is formed of polycrystalline silicon and the second conductive plate is formed of metal.

20. A method for manufacturing an integrated circuit, comprising: A composite dielectric layer is formed on a first conductive plate and on the gate of a transistor, the first conductive plate and the transistor being located on a semiconductor substrate, the formation comprising: A first sublayer and a second sublayer are formed, the first sublayer and the second sublayer having substantially the same first chemical composition; A third sublayer is formed between the first sublayer and the second sublayer, the third sublayer having a second chemical composition different from the first chemical composition; and A second conductive plate is formed, which is directly located on the composite dielectric layer on the first conductive plate; A second dielectric layer is formed on the second conductive plate; A metal-pre-dielectric PMD layer is deposited on the composite dielectric layer and the second dielectric layer, the PMD layer comprising borosilicate glass and having a top side; as well as Multiple contacts are formed, including: The top side of the PMD layer is patterned using a contact mask; A first dry etching process is performed using a first etching chemical compatible with etching through the PMD layer and the second sublayer, wherein the first etching chemical comprises a tetrafluoromethane / oxygen CF4 / O2 plasma and a mixture of argon (Ar), hydrogen (H2), and perfluorocyclopentene (C5F8), wherein the third sublayer acts as an etch stop layer for the first etching chemical. A second dry etching process is performed using a second etching chemical compatible with etching through the third sublayer, wherein the second etching chemical comprises tetrafluoromethane CF4 plasma with a mixture of argon and difluoromethane CH2F2, and wherein the first sublayer acts as an etch stop layer for the second etching chemical. The first dry etching process is resumed using the first etching chemicals compatible with the etching of the first sublayer to form multiple contact openings; and The plurality of contact openings are filled with a conductive material; The formation of the third sublayer includes providing approximately 230 W of high-frequency radio frequency power, and silane, ammonia, and nitrogen flowing at 175 sccm, 400 sccm, and 8000 sccm, respectively, with a substrate temperature of approximately 350°C, and the third sublayer includes silicon nitride, wherein the silicon nitride contains hydrogen atoms bonded approximately equal to those of silicon and nitrogen.

21. The method of claim 20, wherein the third sublayer comprises nitrogen, and the first and second sublayers do not contain nitrogen.

22. The method of claim 20, further comprising forming an electrical contact among the plurality of contacts that extends through the composite dielectric layer to the first conductive plate.

23. The method of claim 20, wherein the extension of the first conductive plate extends beyond the second conductive plate, and the method further comprises forming a first electrical contact among the plurality of contacts extending through the composite dielectric layer to the extension of the first conductive plate; and forming a second electrical contact among the plurality of contacts to the second conductive plate.

24. The method of claim 23, further comprising forming a third electrical contact and a fourth electrical contact, respectively, to the source and drain of the transistor, and forming a fifth electrical contact, to the gate, wherein the third, fourth, and fifth electrical contacts pass through the composite dielectric layer.

25. The method of claim 20, wherein the first conductive plate and the transistor gate are formed of the same material layer.

26. The method of claim 20, wherein the first sublayer and the second sublayer comprise silicon oxide, and the third sublayer comprises silicon nitride.

27. The method of claim 20, wherein the first sublayer, the second sublayer, and the third sublayer are formed in a plasma reactor, and the vacuum is not broken between the formation of the first sublayer and the third sublayer, and between the formation of the third sublayer and the second sublayer.

28. The method of claim 20, wherein the first conductive plate is formed directly on the semiconductor substrate or on an isolation layer formed within the semiconductor substrate.

29. The method of claim 28, wherein the isolation layer is a shallow trench isolation layer.

30. The method of claim 20, wherein the first conductive plate is formed of polycrystalline silicon and the second conductive plate is formed of metal.

31. The method according to claim 20, wherein the ratio of ammonia to silane is about 2.

3.

32. A method for manufacturing an integrated circuit, comprising: Receive a semiconductor substrate, the substrate comprising: An isolation layer disposed on or above the semiconductor substrate; and A first conductive plate is located above the insulating layer; A composite dielectric layer is formed on the first conductive plate, the formation comprising: A first silicon oxide layer is formed on the first conductive plate; A silicon nitride layer is formed on top of the first silicon oxide layer; A second silicon oxide layer is formed on top of the silicon nitride layer; and The second conductive plate is formed directly on the second silicon oxide layer above the first conductive plate; A second dielectric layer is formed on the second conductive plate; A metal-pre-dielectric PMD layer is deposited on the composite dielectric layer and the second dielectric layer, the PMD layer comprising borosilicate glass and having a top side; as well as Multiple contacts are formed, including: The top side of the PMD layer is patterned using a contact mask; A first dry etching process is performed using a first etching chemical compatible with etching through the PMD layer and the second silicon oxide layer, wherein the first etching chemical comprises a tetrafluoromethane / oxygen CF4 / O2 plasma and a mixture of argon (Ar), hydrogen (H2), and perfluorocyclopentene (C5F8), wherein the silicon nitride layer acts as an etch stop layer for the first etching chemical. A second dry etching process is performed using a second etching chemical compatible with etching through the silicon nitride layer, wherein the second etching chemical comprises tetrafluoromethane CF4 plasma with a mixture of argon and difluoromethane CH2F2, and wherein the first silicon oxide layer acts as an etch stop layer for the second etching chemical. The first dry etching process is resumed using the first etching chemicals compatible with etching through the first silicon oxide layer to form multiple contact openings; and The plurality of contact openings are filled with a conductive material; The silicon nitride layer contains hydrogen atoms bonded to approximately equal amounts of silicon and nitrogen.

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