Integrated assembly and method of forming an integrated assembly

Abstract

Some embodiments include a method of forming an integrated assembly. A first stack is formed over a conductive structure. The first stack includes a second layer between a first layer and a third layer. The first and third layers are electrically conductive. A first opening is formed through the first stack. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. The second stack has alternating first and second levels. A second opening is formed through the second stack and through the sacrificial material. A first semiconductor material is formed within the second opening. A third opening is formed through the second stack, through the third layer to the second layer. The second layer is removed to form a conduit. A second semiconductor material is formed within the conduit. A dopant is diffused outward from the second semiconductor material into the first semiconductor material. Some embodiments include an integrated assembly.

Description

[0001] Relevant patent data

[0002] This application relates to U.S. Patent Application Serial No. 16 / 550,638, filed August 26, 2019, entitled "Integrated Assemblies, and Methods of Forming Integrated Assemblies," the entire contents of which are incorporated herein by reference. Technical Field

[0003] A method for forming an integrated assembly (e.g., an integrated memory device). Integrated assembly. Background Technology

[0004] Memory provides data storage for electronic systems. Flash memory is a type of memory and has numerous uses in modern computers and devices. For example, modern personal computers may have a BIOS stored on flash memory chips. As another example, it is becoming increasingly common for computers and other devices to use flash memory in solid-state drives (SSDs) to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because, as wireless electronic devices become standardized, it enables manufacturers to support new communication protocols and provides the ability to remotely upgrade devices to enhance features.

[0005] NAND can be the basic architecture for flash memory and can be configured to include vertically stacked memory cells.

[0006] Before describing NAND in detail, it may be helpful to describe more generally the relationships of memory arrays within an integrated arrangement. Figure 1 shows a block diagram of a prior art device 1000, which includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns, and access lines 1004 (e.g., word lines WL0 to WLm for conducting signals) and first data lines 1006 (e.g., bit lines BL0 to BLn for conducting signals). The access lines 1004 and the first data lines 1006 are used to transmit information back and forth between the memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells 1003 will be accessed. Sensing amplifier circuitry 1015 operates to determine the value of the information read from the memory cells 1003. I / O circuitry 1017 transmits the value of the information between the memory array 1002 and the input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 can represent values ​​of information read from or written to memory cell 1003. Other devices can communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 controls memory operations performed on memory cell 1003 and utilizes signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuit 1040 and input / output (I / O) circuit 1017. Selection circuit 1040 can respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013 that represent values ​​of information read from or programmed into memory cell 1003. The column decoder 1008 can selectively activate the CSEL1 to CSELn signals based on the address signals A0 to AX on the address lines 1009. During read and program operations, the selection circuit 1040 can select the signals on the first data line 1006 and the second data line 1013 to provide communication between the memory array 1002 and the I / O circuit 1017.

[0007] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, 32 charge storage devices stacked one on top of the other, wherein each charge storage device corresponds to, for example, one of 32 layers (e.g., layers 0 to 31). The charge storage devices of the respective strings may share a common channel region, such as a common channel region formed in a corresponding pillar of a semiconductor material (e.g., polysilicon) surrounding which the charge storage device string is formed. In a second direction (X-X'), each of the multiple strings in, for example, 16 first groups may include, for example, eight strings sharing multiple (e.g., 32) access lines (i.e., “global control gate (CG) lines”, also referred to as word lines WL). Each of the access lines may couple to a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same level) can be logically grouped into (e.g.) two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each of the (e.g.) eight second groups of multiple strings can include 16 strings coupled by corresponding ones of the eight data lines. The size of the memory block can include 1,024 pages and approximately 16 MB in total (e.g., 16 WL × 32 levels × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16 KB / page = 16 MB). The number of strings, levels, access lines, data lines, first groups, second groups, and / or pages can be greater than or less than the number shown in Figure 2.

[0008] Figure 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of Figure 2 along the X-X' direction. The memory block 300 includes 15 strings of charge storage devices from one of 16 first groups of strings described in Figure 2. The multiple strings of the memory block 300 can be divided into multiple subsets 310, 320, 330 (e.g., block columns) (e.g., block column I, block column j, and block column K), where each subset (e.g., block column) includes a “partial block” (sub-block) of the memory block 300. A global drain-side selected gate (SGD) line 340 can be coupled to the SGDs of the multiple strings. For example, the global SGD line 340 can be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding ones of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a corresponding subset (e.g., block column). Each of the sub-SGD drivers 332, 334, and 336 can simultaneously couple or disconnect the SGD of the corresponding sub-block (e.g., block column) string, independent of the SGD of the strings of other sub-blocks. A global source-side select gate (SGS) line 360 ​​can be coupled to the SGS of multiple strings. For example, the global SGS line 360 ​​can be coupled to multiple sub-SGS lines 362, 364, and 366 via corresponding sub-SGS drivers 322, 324, and 326, where each sub-SGS line corresponds to a corresponding subset (e.g., block column). Each of the sub-SGS drivers 322, 324, and 326 can simultaneously couple or disconnect the SGS of the corresponding sub-block (e.g., block column) string, independent of the SGS of the strings of other sub-blocks. A global access line (e.g., a global CG line) 350 can couple to the charge storage device corresponding to the corresponding level of each of the multiple strings. Each global CG line (e.g., global CG line 350) can be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, and 356 via a corresponding of a plurality of sub-string drivers 312, 314, and 316. Each of the sub-string drivers can simultaneously couple or disconnect the charge storage device corresponding to the corresponding partial block and / or layer, independently of the charge storage devices of other partial blocks and / or other layers. The charge storage devices corresponding to the corresponding subset (e.g., partial block) and the corresponding layer may include a “partial layer” (e.g., a single “block”) of charge storage devices. The string corresponding to the corresponding subset (e.g., partial block) can be coupled to a corresponding of sub-sources 372, 374, and 376 (e.g., “block source”), wherein each sub-source is coupled to a corresponding power source.

[0009] Alternatively, the NAND memory device 200 is described with reference to the schematic diagram in FIG4.

[0010] Memory array 200 includes word lines 2021 to 202 N and position lines 2281 to 228 M .

[0011] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. N Charge storage transistors can use floating gate materials (such as polysilicon) to store charge, or they can use charge trapping materials (such as silicon nitride, metal nanodots, etc.) to store charge.

[0012] A charge storage transistor 208 is located at the intersection of word line 202 and string 206. The charge storage transistor 208 represents a non-volatile memory cell used for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side select gate SGS) 210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, and each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device and are generally illustrated in boxes in FIG. 4.

[0013] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 corresponding to the NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 corresponding to the NAND string 2061. The source select device 210 is connected to the source select line 214.

[0014] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 couples its control gate 236 to a word line 202. A row of charge storage transistors 208 are transistors coupled to a given word line 228 within a NAND string 206. A row of charge storage transistors 208 are transistors that are collectively coupled to a given word line 202.

[0016] The vertically stacked memory cells of a three-dimensional NAND architecture can be erased by generating hole carriers underneath them and then sweeping the hole carriers upward along the memory cells using an electric field.

[0017] The gated structure of the transistor can be used to provide gate-induced drain leakage (GIDL), which generates holes for block erasure of the memory cell. The transistor can be a source-side selected (SGS) device as described above. The channel material associated with the serial memory cell can be configured as a channel material pillar, and a region of this pillar can be gate-coupled to the SGS device. The gate-coupled portion of the channel material pillar overlaps with the gate of the SGS device.

[0018] It is expected that at least some gated coupling portions of the channel material pillar are heavily doped. In some applications, it is expected that the gated coupling portions comprise both a heavily doped lower region and a lightly doped upper region, both of which overlap with the gate of the SGS device. Specifically, the overlap with the lightly doped region provides the SGS device with a leak-free “off” characteristic, and the overlap with the heavily doped region provides the SGS device with a leaky GIDL characteristic. The terms “heavily doped” and “lightly doped” are used relative to each other rather than relative to a particular conventional meaning. Thus, a “heavily doped” region is more heavily doped than an adjacent “lightly doped” region and may or may not include heavy doping in the conventional sense. Similarly, a “lightly doped” region is less doped than an adjacent “heavily doped” region and may or may not include light doping in the conventional sense. In some applications, the term “lightly doped” refers to having a density of less than or equal to about 10 18 atoms / cm 3 Semiconductor materials with doped materials, and the term "heavily doped" refers to materials with a dopant concentration greater than or equal to about 10. 22 atoms / cm 3 Semiconductor materials with dopants.

[0019] The channel material can be doped to a light doping level first, and then a heavily doped region can be formed by diffusion from the underlying doped semiconductor material outward.

[0020] The goal is to develop improved methods to achieve the desired heavily doped regions in the channel material pillars. Attached Figure Description

[0021] Figure 1 shows a block diagram of a prior art memory device having a memory array containing memory cells.

[0022] Figure 2 shows a schematic diagram of the prior art memory device of Figure 1 in the form of a 3D NAND memory device.

[0023] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 in the X-X' direction.

[0024] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0025] Figure 5 and 6 This is a schematic cross-sectional side view of a region of an instance integration assembly in an instance sequence process stage of an instance embodiment method for manufacturing an instance memory device.

[0026] Figure 6A and 6B It is replaceable Figure 6 A schematic cross-sectional side view of the integrated assembly in the process stage.

[0027] Figures 7 to 20 yes Figure 6 A schematic cross-sectional side view of an instance assembly in the sequential process stages following the process stages. Figure 20 The example memory device is described in the text.

[0028] Figure 20A It is along Figure 20 A schematic top view of line 20A-20A. Figure 20 The cross-sectional side view is along Figure 20A Line 20-20.

[0029] Figure 21 This is a schematic cross-sectional side view of another example memory device. Detailed Implementation

[0030] Some embodiments include a novel method for forming a memory device with vertically stacked memory cell hierarchies on a conductive electrode structure. The memory device includes at least one select device hierarchy (e.g., at least one SGS device hierarchy) between the memory cell hierarchy and the conductive electrode structure. A channel material extends vertically along both the memory cell hierarchy and the select device hierarchy. First, a sacrificial material is provided in a region of the conductive electrode structure. The sacrificial material is replaced with a conductive-doped semiconductor material, and a dopant diffuses outward from the conductive-doped semiconductor material into a lower region of the channel material. The dopant in the lower region of the channel material can be provided at desired locations and concentrations to form a doped region of the select device hierarchy. References are made below. Figures 5 to 21 Describe an example implementation.

[0031] refer to Figure 5 The integrated assembly 10 includes a conductive structure 14 on the base plate 12.

[0032] The substrate 12 may include semiconductor materials; and may include, for example, monocrystalline silicon (Si), substantially composed of monocrystalline silicon (Si), or composed of monocrystalline silicon (Si). The substrate 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction that includes, but is not limited to, bulk semiconducting materials, such as semiconducting wafers (alone or in a combination including other materials) and layers of semiconducting materials (alone or in a combination including other materials). The term "substrate" refers to any support structure that includes, but is not limited to, the semiconductor substrate described above. In some applications, the substrate 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0033] A gap is provided between the base plate 12 and the conductive structure 14 to indicate that other materials, devices, etc. may exist between the base plate 12 and the conductive structure 14.

[0034] The conductive structure 14 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt), ruthenium (Ru), etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0035] In some embodiments, the conductive structure 14 may include a metal and may be referred to as a metal-containing structure.

[0036] In some embodiments, the conductive structure 14 may include WSi, be substantially composed of WSi, or be composed of WSi, wherein the chemical formula indicates the major component rather than a specific stoichiometry. WSi may alternatively be referred to as WSi. x , where x is the number of values ​​greater than 0.

[0037] A stack 16 is formed on the conductive structure 14. The stack 16 includes a first layer 18, a second layer 20, and a third layer 22. The first layer, the second layer, and the third layer each include a first material 24, a second material 26, and a third material 28, respectively.

[0038] In some embodiments, the first material 24 and the third material 28 may be conductive. In such embodiments, the first and third materials may comprise any suitable conductive composition, such as (e.g.) one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the first and third materials may comprise conductively doped semiconductor materials. Semiconductor materials may comprise any suitable composition, and in some embodiments may comprise one or more of, substantially consist of one or more of, or consist of one or more of the following: silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., wherein the term "group III / V semiconductor material" refers to a semiconductor material comprising elements selected from groups III and V of the periodic table (where groups III and V are older designations and are now referred to as groups 13 and 15). The first material 24 and the third material 28 may comprise compositions identical to each other, or may comprise compositions different from each other. In some embodiments, the first material 24 and the third material 28 may comprise conductive doped silicon. The conductive doped silicon may be doped to at least about 10⁻⁶ with suitable dopants that enhance conductivity (e.g., boron, phosphorus, arsenic, etc.). 22 atoms / cm 3 At least about 10 24 atoms / cm 3 Concentrations such as... In some embodiments, materials 24 and 28 may be n-type silicon doped with phosphorus to a suitable concentration to enhance conductivity.

[0039] The second material 26 may be a sacrificial material, and in particular, a material that can be selectively removed relative to the first material 24 and the third material 28. For the purposes of this invention and the following claims, a material is considered to be selectively removable relative to another material if it can be etched faster than the other material.

[0040] In some embodiments, the second material 26 may include silicon dioxide, silicon nitride, etc., and may be substantially composed of or composed of silicon dioxide, silicon nitride, etc. In some embodiments, the second layer 20 may include multiple materials, rather than the single material described. For example, the second layer 20 may include a stack of two or more stacked materials.

[0041] In some embodiments, stack 16 may be referred to as a first stack to distinguish it from another stack formed in a subsequent process stage. In some embodiments, sacrificial material 26 may be referred to as a first sacrificial material to distinguish it from another sacrificial material formed in a subsequent process stage.

[0042] refer to Figure 6An opening 30 is formed extending through the stack 16 to the conductive structure 14. In the illustrated embodiment, the opening 30 terminates at the upper surface of the conductive structure 14. In other embodiments, the opening 30 may extend into the conductive structure 14. In some embodiments, the opening 30 may be referred to as a first opening to distinguish it from other openings formed in subsequent process stages.

[0043] A liner 32 is formed across the upper surface of stack 16 and extends within opening 30. Liner 32 includes liner material 34. Liner material may alternatively be referred to as protective material. Material 34 may include any suitable composition and in some embodiments may include silicon nitride, silicon, etc., substantially composed of silicon nitride, silicon, etc., or composed of silicon nitride, silicon, etc. As long as liner material 34 is substantially composed of silicon, this silicon may be relatively undoped and may (for example) have a pH less than or equal to about 10. 16 atoms / cm 3 Less than or equal to approximately 10 15 atoms / cm 3 The dopant concentration, etc. Therefore, if the substrate material 34 is essentially composed of silicon, then the amount of dopant present in the substrate (if present) can be approximately the intrinsic concentration.

[0044] In some embodiments, the liner material 34 may be referred to as a protective first material to distinguish it from other protective materials formed in subsequent process stages.

[0045] A sacrificial material 36 is formed across the stack 16 and extends within the lined opening 30. In some embodiments, the sacrificial material 36 may be referred to as a second material to distinguish it from the first material 34.

[0046] In some embodiments, sacrificial materials 26 and 36 may be referred to as the first sacrificial material and the second sacrificial material, respectively.

[0047] Material 36 may comprise any suitable composition that can be selectively removed relative to the protective first material 34. In some embodiments, the protective first material 34 comprises silicon nitride, and the second material 36 comprises silicon dioxide and one or more of boron, phosphorus, and fluorine (e.g., borosilicate glass). In some embodiments, the protective first material 34 is substantially composed of silicon, and the second material 36 comprises tungsten, is substantially composed of tungsten, or is composed of tungsten.

[0048] In some embodiments, the protective liner 32 may include multiple materials, rather than a single material 34. For example, Figure 6AAn embodiment is shown in which the liner 32 includes a second liner material 38 on a first material 34. In some embodiments, the first material 34 may be considered as a region consisting essentially of silicon. In such embodiments, the second material 38 may include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide, and the sacrificial material 36 may include tungsten, consist essentially of tungsten, or consist of tungsten. Figure 6B Another embodiment in which the liner 32 comprises multiple materials is shown. Figure 6B In one embodiment, the liner 32 includes a material 34 that is substantially composed of silicon, a material 38 that includes silicon dioxide, and another material 40 on the material 38. The material 40 may, for example, include a metal nitride (e.g., titanium nitride), be substantially composed of a metal nitride (e.g., titanium nitride), or be composed of a metal nitride (e.g., titanium nitride). Figure 6B The sacrificial material 36 may include tungsten, be substantially composed of tungsten, or be composed of tungsten.

[0049] Figure 7 exhibit Figure 6 The process is a subsequent process stage, and it demonstrates that sacrificial material 36 and liner material 34 have been removed from the upper surface of stack 16 using planarization (e.g., chemical mechanical polishing, CMP). Planarization forms a planarized surface 41 extending across materials 28, 34, and 36. Surface 41 may or may not have the illustrated planar configuration, and in some embodiments may have indentations (concave surfaces) extending into the soft material 36.

[0050] Although the illustrated embodiment uses a planarization process to remove the liner material 34 from the stack 16, in other embodiments, the planarization process may stop at the liner 32 ( Figure 6 The liner is removed from the top surface of the stack 16 instead of from the stack 16.

[0051] refer to Figure 8 A second stack 42 is formed on the first stack 16. The second stack 42 has alternating first levels 44 and second levels 46. The first level 44 includes material 48, and the second level 46 includes material 50. Materials 48 and 50 may include any suitable composition. In some embodiments, material 48 may include silicon nitride, be substantially composed of silicon nitride, or be composed of silicon nitride; and material 50 may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide. In some embodiments, material 48 and material 50 may be referred to as a third material and a fourth material, respectively, to be associated with the material already formed in the opening 30 ( Figure 6 Distinguish between the first material 34 and the second material 36 within the )

[0052] Figure 8 (and Figure 8 The base plate 12 is not shown in the subsequent diagrams. Figure 7 This is to simplify the diagram. However, it should be understood that the base plate will still exist.

[0053] refer to Figure 9 This forms an opening 52 extending through the second stack 42 to the sacrificial material 36. The opening 52 may be referred to as the second opening to connect with... Figure 6 The first opening is 30.

[0054] refer to Figure 10 This causes the opening 52 to extend through the sacrificial material 36. Figure 9 ) to protective materials 34.

[0055] refer to Figure 11 A semiconductor material (channel material) 54 is formed within the opening 52. The semiconductor material 54 may be referred to as the first semiconductor material to distinguish it from other semiconductor materials formed in subsequent process stages. The first semiconductor material (channel material) 54 forms a channel material pillar 56.

[0056] Semiconductor material 54 may include any suitable composition, and in some embodiments may include one or more of, substantially consist of one or more of, or consist of one or more of the following: silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc. In some embodiments, semiconductor material 54 may include suitably doped silicon, substantially consist of suitably doped silicon, or consist of suitably doped silicon.

[0057] In the illustrated embodiment, the channel material column 56 is an annular (e.g., Figure 20A (As shown in the top view), such annulus surrounds insulating material 58. This configuration of the channel material pillar can be considered as corresponding to a “hollow” channel configuration, wherein dielectric material 58 is provided within the hollow of the channel material pillar. In other embodiments, the channel material may be configured as a solid pillar instead of the hollow pillar illustrated.

[0058] The channel material pillar 56 and the materials 48 and 50 of the stack 42 are separated by an intervention region 60. Region 60 includes one or more cell materials (memory cell materials), wherein such cell materials are formed within the opening 52 prior to the channel material 54. The cell materials of region 60 may include tunneling materials, charge storage materials, charge blocking materials, and dielectric barrier materials. The tunneling material (also referred to as the gate dielectric material) may include any suitable composition and, in some embodiments, may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc. The charge storage material may include any suitable composition and, in some embodiments, may include a floating gate material (e.g., polysilicon) or a charge trapping material (e.g., silicon nitride, silicon oxynitride, conductive nanodots, etc.). The charge blocking material may include any suitable composition and, in some embodiments, may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc. The dielectric barrier material may include any suitable composition and, in some embodiments, may include one or more of alumina, hafnium oxide, zirconium oxide, etc.

[0059] refer to Figure 12 This forms an opening 62 that passes through the second stack 42, through the third layer 22, and into the second layer 26. The opening 62 may or may not penetrate the second layer 26. The opening 62 may be referred to as the third opening to connect with... Figure 6 The first opening 30 and Figure 9 The second opening 52 is distinguished. In some embodiments, opening 52 is a cylindrical opening (as can be seen from...). Figure 20A (understand from the top view), and opening 62 is relative to... Figure 12 The cross-section extends into and out of the page groove (see also: Figure 20A (Understanding from a top view).

[0060] Opening 62 has a sidewall surface 63 extending along the materials 48 and 50 of stack 42. In the illustrated embodiment, the sidewall surface 63 is tapered. In other embodiments, the sidewall surface 63 may be substantially vertically straight, wherein the term “substantially vertically straight” means vertically straight until within reasonable manufacturing and measurement tolerances.

[0061] refer to Figure 13 A protective material 64 is formed along the sidewall surface 63 of the opening 62. In some embodiments, the protective material 64 may be considered as a lining for the sidewall surface 63. In some embodiments, the protective material 64 may be referred to as a second protective material to distinguish it from the first protective material 34. In some embodiments, the protective material 64 may be referred to as a fifth material to distinguish it from the first material 34, the second material 36, the third material 48, and the fourth material 50.

[0062] The protective material 64 may comprise any suitable composition. In some embodiments, the protective material 64 may comprise silicon, be substantially composed of silicon, or be composed of silicon, and in particular may comprise virtually undoped (e.g., including intrinsic dopant concentrations, and in some embodiments including less than or equal to about 10). 16 atoms / cm 3 Silicon with (dopant concentration).

[0063] refer to Figure 14 The second layer 20 is selectively removed relative to the materials 24 and 28 of the first layer 18 and the third layer 22, and relative to the protective material 64. Figure 13 The sacrificial material 26. This forms the conduit 66 between the first layer 18 and the third layer 22.

[0064] refer to Figure 15 The conduit 66 extends through the protective material 34 and the unit material within the region 60 to expose the sidewall surface 67 of the semiconductor material (channel material) 54.

[0065] refer to Figure 16 In catheter 66 ( Figure 15 A conductive doped semiconductor material 68 is formed within the semiconductor material 54. The semiconductor material 68 may be referred to as a second semiconductor material to distinguish it from the first semiconductor material 54.

[0066] Semiconductor material 68 may comprise any suitable composition, and in some embodiments may comprise one or more of, substantially comprise one or more of, or comprise one or more of the following: silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc. In some embodiments, semiconductor material 68 may comprise heavy doping with an n-type dopant (e.g., doped to at least about 10⁻⁶). 22 atoms / cm 3 The concentration of silicon is specified. In some embodiments, semiconductor material 68 may include a composition that is the same as one or both of conductive materials 24 and 28, and in other embodiments may include a composition that is different from both conductive materials 24 and 28.

[0067] refer to Figure 17 Materials 64 and 68 are removed from the opening (slit) 62. Materials 64 and 68 can be removed to any suitable level within the slit 62. In the illustrated embodiment, materials 64 and 68 are completely removed from the slit, but it should be understood that in other embodiments, one or both of materials 64 and 68 may remain within a portion of the slit 62.

[0068] Additionally, the dopant is diffused outward from the conductive doped semiconductor material 68 into the semiconductor material (channel material) 54 to form a heavily doped region 74 in the lower portion of the semiconductor material 54. Dots are used to indicate the dopant within the heavily doped region 74.

[0069] The outward diffusion from the doped material 68 to the semiconductor material 54 can be accomplished using any suitable process that includes, for example, a suitable heat treatment (e.g., a heat treatment at a temperature of more than about 300°C for at least about two minutes).

[0070] refer to Figure 18 Remove material 48 from level 44 of the first layer. Figure 16 And it is replaced by conductive material 70. Although conductive material 70 is shown to completely fill the first layer 44, in other embodiments, at least some of the material provided within the first layer 44 may be an insulating material (e.g., a dielectric barrier material). Conductive material 70 may include any suitable composition, and in some embodiments may include a tungsten core at least partially surrounded by titanium nitride.

[0071] Figure 18 The first layer 44 is a conductive layer, and the stack 42 can be considered as including alternating insulating layers 46 and conductive layers 44.

[0072] refer to Figure 19 An insulating material 72 is formed within the slit 62. The insulating material 72 may comprise any suitable composition, and in some embodiments may comprise silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0073] refer to Figure 20 Assembly 10 is shown as a memory device including memory cell 80 and a selection device (SGS device) 78. The lowermost of conductive layers 44 is designated 44a, and a doped region 74 extends into conductive layer 44a. Conductive layer 44a includes the SGS device 78. In the illustrated embodiment, the dopant portion extends across layer 44a to achieve a desired balance between the leak-free "off" characteristics of the SGS device and the leaky GIDL characteristics of the SGS device. Although only one of the conductive layers is shown incorporated into the source selection device, in other embodiments, multiple conductive layers may be incorporated into the source selection device. The conductive layers may be electrically coupled (grouped together) to be incorporated together into a long-channel source selection device. If multiple conductive layers are incorporated into the source selection device, then outwardly diffused dopant may extend upward across two or more of the conductive layers 44 incorporated into the source selection device.

[0074] Memory cells 80 (e.g., NAND memory cells) are stacked vertically on top of each other. The memory cells 80 are stacked along a first layer 44. Each memory cell includes a region of semiconductor material (channel material) 54 and a region of conductive layer 44 (control gate region). Regions of conductive layers not included in the memory cell 80 may be considered as word line regions (or wiring regions) coupling the control gate region to driver circuitry and / or other suitable circuitry. The memory cell 80 also includes cell material (e.g., tunneling material, charge storage material, dielectric barrier material, and charge blocking material) within region 60.

[0075] In some embodiments, the conductive level 44 associated with the memory cell 80 may be referred to as a word line / control gate level (or memory cell level) because it contains word lines and control gates associated with the vertically stacked memory cells of the NAND string. The NAND string may include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, and so on.

[0076] Conductive materials 14, 24, 68, and 28 together form the source structure 76 of the memory device. The source structure may be similar to the source structure 216 described in the "Prior Art" section. The source structure is shown to be coupled to a control circuitry system (e.g., CMOS). The control circuitry system may be located within the source structure 76 (e.g., may be coupled to...). Figure 5 The conductive material 14 can be associated with the base plate 12 (and is located directly under the source structure 76), or in any other suitable location. The conductive material 14 can be coupled to the control circuitry (e.g., CMOS) at any suitable process stage.

[0077] In some embodiments, the channel material pillar 56 may be considered as representing a large number of substantially identical channel material pillars extending across the memory device 10, wherein the term “substantially identical” means identical within reasonable manufacturing and measurement tolerances. Figure 20A The top view shows pillars 56 arranged within a matrix (wherein the illustrated embodiment, pillars 56 are hexagonally stacked), and shows a slit 62 extending through the matrix of channel material pillars. In some embodiments, the slit 62 may divide the pillars into a first block 82 and a second block 84. Thus, memory cells 80 on one side of the slit 62 may be considered as being within the first block 82, and memory cells 80 on the other side of the slit 62 may be considered as being within the second block 84. Blocks 82 and 84 may be similar to the blocks (or sub-blocks) described above in the "Prior Art" section of this invention.

[0078] In some embodiments, the region of the channel material 54 under the SGS layer 44a can be considered as the lower region of the channel material. The liner material 34 along the lower region of the channel material can be considered as a first liner region 90 of a conductive-doped semiconductor material (e.g., silicon) 28 configured along the upper portion 22 of the semiconductor material of the source structure 76, and a second liner region 92 of a conductive-doped semiconductor material (e.g., silicon) 24 configured along the lower portion 18 of the semiconductor material of the source structure 76. The first liner region 90 and the second liner region 92 are perpendicularly spaced from each other by an insertion gap 94. The liner regions 90 and 92 are along the cell material (memory cell material) within region 60.

[0079] Figure 21 The display is similar to Figure 20 The memory device 10 of the memory device, but the liner regions 90 and 92 include the above reference. Figure 6B The three layers described are 34, 38, and 40. In some embodiments, these three layers may be considered together as any of the configurations forming layers. Along Figure 21 20A-20A line Figure 20A The top view remains the same as along Figure 20 Line 20A-20A.

[0080] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" means electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of a wide variety of systems, such as cameras, wireless devices, displays, chipsets, video converters, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, and so on.

[0081] Unless otherwise stated, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including (e.g.) atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0082] The terms "dielectric" and "insulating" can be used to describe materials having insulating electrical properties. In this invention, these terms are considered synonyms. The use of the term "dielectric" in some instances and the term "insulating" (or "electrically insulating") in others provides a linguistic variation within this invention to simplify the pre-basis of the following claims and is not intended to indicate any significant chemical or electrical differences.

[0083] The terms "electrical connection" and "electrical coupling" are both used in this invention. The terms are considered synonyms. Using one term in some instances and another in others provides a linguistic variation within this invention to simplify the pre-basis of the following claims.

[0084] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the following claims relate to any structure having descriptive relationships between various features, whether the structure is presented in the specific orientation of the drawings or rotated relative to that orientation.

[0085] The cross-sectional views in the accompanying drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section (unless otherwise indicated) to simplify the illustration.

[0086] When a structure is referred to above as "on another structure," "adjacent to another structure," or "against another structure," it may be directly on said other structure or there may be intervening structures. In contrast, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate upright alignment.

[0087] A structure (such as a layer, material, etc.) may be described as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (such as a base plate). A vertically extending structure may extend generally orthogonally to the upper surface of the substrate, or it may not extend orthogonally to the upper surface of the substrate.

[0088] Some embodiments include a method of forming an integrated assembly. A first stack is formed on a conductive structure. The first stack includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first layer and the third layer are conductive. The second layer includes a first sacrificial material. A first opening extending through the first stack is formed. A second sacrificial material is formed within the first opening. A second stack is formed on the first stack. The second stack has alternating first and second layers. A second opening is formed through the second stack to the second sacrificial material. The second opening is extended through the second sacrificial material. A first semiconductor material is formed within the extended second opening. A third opening is formed through the second stack, through the third layer, to the second layer. The first sacrificial material of the second layer is removed to form a conduit. A conductively doped second semiconductor material is formed within the conduit. A dopant is diffused outward from the conductively doped second semiconductor material into the first semiconductor material. The outwardly diffused dopant extends upward to at least one of the first layers. A conductive material is formed within the first layer. An insulating material is formed within the third opening.

[0089] Some embodiments include a method of forming an integrated assembly. A first stack is formed on a metal-containing structure. The first stack includes a first layer, a second layer on the first layer, and a third layer on the second layer. A first opening extending through the first stack is formed. The first opening is lined with a protective first material. The lined first opening is filled with a second material. After filling the lined first opening, a second stack is formed on the first stack. The second stack has alternating first and second levels. The first level includes a third material, and the second level includes a fourth material. The fourth material is insulating. A second opening of the second material is formed through the second stack into the first opening. The second opening is extended through the second material into the protective first material. A channel material is formed within the extended second opening. A third opening is formed through the second stack, through the third layer, and into the second layer. The sidewall surface of the third opening is lined with a protective fifth material. The second layer is selectively removed relative to the first and third layers, and selectively removed relative to the protective fifth material. The removal of the second layer forms a conduit. A conductive-doped semiconductor material is formed within the conduit. The dopant diffuses outward from the conductive doped semiconductor material into the channel material. The outwardly diffused dopant migrates upward to at least the lowest first layer of the second stack. At least some of the third material is replaced with a conductive material to form the first layer as a conductive layer.

[0090] Some embodiments include a method of forming an integrated assembly. A first stack is formed on a metal-containing structure. The first stack includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers include conductive doped silicon. The second layer includes silicon dioxide. A first opening extending through the first stack is formed. A liner is formed within the first opening to line the first opening. Tungsten is formed within the lined first opening. A second stack is formed on the first stack. The second stack has alternating first and second layers. A second opening is formed through the second stack to the tungsten. The second opening extends through the tungsten. A first semiconductor material is formed within the extended second opening. A third opening is formed through the second stack, through the third layer, and back to the second layer. The sidewall surfaces of the third opening are lined with a protective material. The silicon dioxide of the second layer is removed to form a conduit. A conductive doped second semiconductor material is formed within the conduit. A dopant is diffused outward from the conductive doped second semiconductor material into the first semiconductor material. The outwardly diffused dopant extends upward to at least one of the first layers. A conductive material is formed within the first layer. An insulating material is formed within the third opening.

[0091] Some embodiments include an integrated structure comprising a source structure comprising a conductive-doped semiconductor material. Vertically stacked conductive layers are located on the source structure. An upper conductive layer of the vertically stacked conductive layers is a memory cell layer, and a lower conductive layer of the vertically stacked conductive layers is a select device layer. A channel material extends vertically along the memory cell layer and the select device layer. A region of the channel material below the select device layer is a lower region of the channel material. One or more memory cell materials are located between the channel material and the vertically stacked conductive layers. The one or more memory cell materials are located along the lower region of the channel material. A first liner region is located between the memory cell material and the conductive-doped semiconductor material of the upper portion of the semiconductor material of the source structure. A second liner region is located between the memory cell material and the conductive-doped semiconductor material of the lower portion of the semiconductor material of the source structure. A gap is located between the first liner region and the second liner region.

[0092] In accordance with regulations, the objectives disclosed herein have been described using language more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims should be given the full scope of the literal wording and should be properly interpreted in accordance with the doctrine of equivalence.

Claims

1. A method for forming an integrated assembly, comprising: A first stack is formed on the conductive structure; The first stack includes a first layer, a second layer on the first layer, and a third layer on the second layer; The first and third layers are conductive; the second layer includes a first sacrificial material; A first opening is formed that extends completely through the first stack to the conductive structure; A liner is formed across the upper surface of the first stack and extending within the first opening; A second sacrificial material is formed across the first stack and extending within the lined first opening; Remove the second sacrificial material and the liner from the upper surface of the first stack; After removing the second sacrificial material and the liner from the upper surface of the first stack, a second stack is formed on the first stack; The second stack has alternating first and second levels; Forming a second opening through the second stack to the second sacrificial material; The second opening extends through the second sacrificial material; A first semiconductor material is formed within the extended second opening; A third opening is formed that passes through the second stack, through the third layer, and into the second layer; Remove the first sacrificial material from the second layer to form a conduit; A conductive-doped second semiconductor material is formed inside the conduit; The dopant diffuses outward from the conductive doped second semiconductor material into the first semiconductor material, and the outwardly diffused dopant extends upward to at least one of the first layers; A conductive material is formed within the first layer; and An insulating material is formed within the third opening.

2. The method of claim 1, further comprising forming a memory cell along the first layer, wherein the memory cell includes a region of the first semiconductor material; wherein the integrated assembly includes a memory device including the memory cell; and wherein the conductive structure, the first layer, the third layer, and the conductive-doped second semiconductor material together form a source structure of the memory device.

3. The method of claim 2, further comprising forming a source selection device to include at least one of the first layers.

4. The method according to claim 1, wherein the second sacrificial material comprises one or more of silicon dioxide, phosphorus, fluorine and boron.

5. The method of claim 1, wherein the second sacrificial material comprises borosilicate glass.

6. The method of claim 1, wherein the second sacrificial material comprises tungsten.

7. The method of claim 1, wherein the first layer and the third layer comprise a doped semiconductor material.

8. The method of claim 1, wherein the first layer and the third layer comprise doped silicon.

9. The method of claim 8, wherein the first sacrificial material comprises silicon dioxide.

10. The method of claim 9, further comprising lining the sidewall surface of the third opening with a protective material before removing the first sacrificial material; and wherein the protective material is substantially composed of silicon.

11. A method of forming an integrated assembly, comprising: A first stack is formed on a metal-containing structure; The first stack includes a first layer, a second layer on the first layer, and a third layer on the second layer; Forming a first opening that extends through the first stack; The first opening is lined with a protective first material, and then the lined first opening is filled with a second material; After filling the lined first opening, a second stack is formed on the first stack; The second stack has alternating first and second levels; The first layer includes a third material and the second layer includes a fourth material; the fourth material is insulating. A second opening is formed through the second material stacked into the first opening; The second opening extends through the second material into the protective first material; Channel material is formed within the extended second opening; A third opening is formed that passes through the second stack, through the third layer, and into the second layer; The sidewall surface of the third opening is lined with a protective fifth material; The second layer is selectively removed relative to the first layer and the third layer, and the second layer is selectively removed relative to the protective fifth material, thereby forming a catheter; A conductive doped semiconductor material is formed inside the conduit; The dopant diffuses outward from the conductive doped semiconductor material into the channel material, and the outwardly diffused dopant migrates upward to at least the lowest first level of the second stack; and At least some of the third material is replaced with a conductive material to form the first layer as a conductive layer.

12. The method of claim 11, wherein the second opening is one of a plurality of substantially identical openings, wherein the channel material is configured as a channel material pillar; wherein the channel material pillar is one of a plurality of substantially identical channel material pillars; and wherein the third opening is a slit extending through a matrix of the channel material pillars.

13. The method of claim 12, wherein the channel material column on the first side of the slit is in a first block area, and wherein the channel material column on the opposite second side of the slit is in a second block area.

14. The method of claim 13, further comprising forming a memory cell along the conductive layer, wherein the memory cell includes a region of the channel material pillar; wherein the integrated assembly includes a memory device including the memory cell; and wherein the metal structure, the first layer, the third layer, and the conductive doped semiconductor material together form the source structure of the memory device.

15. A method of forming an integrated assembly, comprising: A first stack is formed on a metal-containing structure; The first stack includes a first layer, a second layer on the first layer, and a third layer on the second layer; The first layer and the third layer comprise conductive doped silicon; the second layer comprises silicon dioxide; Forming a first opening that extends through the first stack; A liner is formed inside the first opening to line the first opening; Tungsten is formed within the first liner-lined opening; A second stack is formed on the first stack; The second stack has alternating first and second levels; A second opening is formed through the second stack into the tungsten; The second opening extends through the tungsten; A first semiconductor material is formed within the extended second opening; A third opening is formed that passes through the second stack, through the third layer, and into the second layer; The sidewall surface of the third opening is lined with a protective material; Remove the silica from the second layer to form a conduit; A conductive-doped second semiconductor material is formed inside the conduit; The dopant diffuses outward from the conductive doped second semiconductor material into the first semiconductor material, and the outwardly diffused dopant extends upward to at least one of the first layers; A conductive material is formed within the first layer; and An insulating material is formed within the third opening.

16. The method of claim 15, further comprising forming one or more unit materials within the extended second opening prior to forming the first semiconductor material.

17. The method of claim 16, wherein the one or more unit materials comprise tunneling materials, charge storage materials, and charge blocking materials.

18. The method of claim 16, further comprising extending the conduit through the one or more unit materials to the sidewall surface of the first semiconductor material.

19. The method of claim 18, wherein the second opening is one of a plurality of substantially identical openings, wherein the first semiconductor material is configured as a channel material pillar; wherein the channel material pillar is one of a plurality of substantially identical channel material pillars; and wherein the third opening is a slit extending through a matrix of the channel material pillars.

20. An integrated structure comprising: The source structure comprises an upper portion and a lower portion of conductive doped semiconductor material; Vertically stacked conductive layers on the source structure; The upper conductive layer of the vertically stacked conductive layers is a memory cell layer, and the lower conductive layer of the vertically stacked conductive layers is a selection device layer. A channel material extends vertically along the memory cell level and the selection device level, and forms a ring around a dielectric material, wherein the diameter of the lower portion of the dielectric material is larger than the diameter of the upper portion of the dielectric material; The region of the channel material below the selection device level is the lower region of the channel material, and at least a portion of the lower region of the channel material forms the annulus surrounding the lower portion of the dielectric material; One or more memory cell materials are disposed between the channel material and the vertically stacked conductive layers; The one or more memory cell materials are along the lower region of the channel material; A first liner region is located between the memory cell material and the upper portion of the conductive doped semiconductor material of the source structure; The second liner region is located between the memory cell material and the lower portion of the conductive doped semiconductor material of the source structure; and The gap is located between the first liner region and the second liner region.

21. The integrated structure of claim 20, wherein the first liner region and the second liner region comprise titanium nitride.

22. The integrated structure of claim 20, wherein the conductive doped semiconductor material comprises conductive doped silicon.

23. The integrated structure of claim 20, wherein the conductive layer comprises a metal.

24. The integrated structure of claim 20, wherein the conductive layers are spaced apart from each other by silicon dioxide intervening layers.

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