Memory device and method for controlling refresh operations of a memory device

Abstract

Memory devices and methods for controlling refresh operations of memory devices are provided. The methods disclosed herein include receiving, by a refresh controller of a memory device, a refresh command from a host to perform a refresh operation on a plurality of memory rows. The methods also include selecting, by the refresh controller using a refresh row selection circuit, at least one memory row from the plurality of memory rows for the refresh operation. The at least one memory row is selected by performing a digital read or an analog read to at least one row state cell (RCC) and at least one supplemental cell connected to each memory row of the plurality of memory rows. The methods also include performing, by the refresh controller, the refresh operation on the selected at least one memory row.

Description

Technical Field

[0001] The example embodiments relate to the field of memory devices, and more specifically, to a method for controlling refresh operations of a memory device. Background Technology

[0002] Memory devices (such as volatile memory devices, e.g., dynamic random access memory (DRAM)) comprise multiple memory cells. Each memory cell (e.g., each memory cell in a DRAM device) includes a capacitor for storing data bits. The presence of charge on the capacitor determines whether the stored data bit is "0" or "1". The capacitor may lose / leak charge over time, causing the stored data bits to be lost. Therefore, to maintain data integrity in the memory device, the charge in the memory cell is periodically restored via a refresh operation. A refresh operation involves reading charge / data bits from the capacitor of each memory cell and rewriting the data bits (e.g., the read data) back into the capacitor by restoring the charge on the capacitor to its original level. Summary of the Invention

[0003] Some example embodiments herein disclose methods and / or systems for controlling refresh operations of memory devices.

[0004] Some example embodiments herein disclose methods and / or systems for selecting at least one memory row from a plurality of memory rows in a memory device and performing a refresh operation on the selected at least one memory row.

[0005] Some example embodiments herein disclose methods and / or systems for selecting at least one memory row for a refresh operation by determining the state of a plurality of memory cells included in each memory row and the refresh requirements of the plurality of memory cells included in each memory row.

[0006] Some example embodiments herein disclose methods and / or systems for reading at least one data bit of at least one row status cell (RCC) connected to each memory row to determine the state of a plurality of memory cells included in each memory row.

[0007] Some example embodiments herein disclose methods and / or systems for reading at least one data bit connected to at least one supplementary unit in each memory row to determine refresh requirements of a plurality of memory cells included in each memory row.

[0008] Some example embodiments herein disclose methods and / or systems for selecting at least one memory row for a refresh operation by reading a comparison voltage stored in at least one RCC connected to each memory row and a voltage of at least one supplementary cell connected to each memory row.

[0009] Therefore, some example embodiments herein provide methods and / or systems for controlling refresh operations of a memory device. The method includes: receiving from a host by a refresh controller at least one refresh command for a plurality of memory rows in the memory device, wherein each of the plurality of memory rows includes a plurality of memory cells; selecting at least one memory row from the plurality of memory rows by a refresh row selection circuit by reading at least one row status unit (RCC) and at least one supplementary unit, each of the RCC and the supplementary unit being associated with a corresponding memory row in the plurality of memory rows; and performing a refresh operation on the selected at least one memory row by the refresh controller using refresh circuitry.

[0010] Therefore, the embodiments herein provide a memory device comprising: at least one memory array including a plurality of memory cells arranged on each of a plurality of memory rows; a refresh row selection circuit including at least one row status unit (RCC) connected to a memory row in the plurality of memory rows and at least one supplementary unit connected to a memory row in the plurality of memory rows; and a refresh controller coupled to the refresh row selection circuit. The refresh controller is configured to: receive from a host at least one refresh command for the plurality of memory rows in the memory device; enable the refresh row selection circuit to select at least one memory row in the plurality of memory rows by reading the at least one RCC and the at least one supplementary unit associated with a memory row in the plurality of memory rows; and perform a refresh operation on the selected at least one memory row using the refresh circuit.

[0011] These and other aspects of the exemplary embodiments herein will be better appreciated and understood when considered in conjunction with the following description and accompanying drawings. However, it should be understood that while the following description indicates exemplary embodiments and their various specific details, it is given by way of illustration and not limitation. Many changes and modifications can be made within the scope of the exemplary embodiments herein without departing from the spirit of the embodiments herein, and the exemplary embodiments herein encompass all such modifications. Attached Figure Description

[0012] The exemplary embodiments herein are illustrated in the accompanying drawings, in which the same reference numerals indicate corresponding parts in different figures. The exemplary embodiments herein will be better understood through the following description with reference to the accompanying drawings, in which:

[0013] Figure 1A The memory cells of the memory device are described;

[0014] Figure 1B These are example sequence diagrams depicting conventional methods for performing refresh operations on memory devices;

[0015] Figure 1C This is an example diagram depicting the time interval for issuing refresh commands to a memory device to perform a refresh operation;

[0016] Figure 2 A memory system according to some example embodiments disclosed herein is described;

[0017] Figure 3A and Figure 3B This is a block diagram of a memory device for controlling refresh operations based on the state and refresh requirements of memory cells in the memory device, according to some example embodiments disclosed herein.

[0018] Figure 4A and Figure 4B This is a block diagram of a memory device that controls refresh operations using RCC storage voltages and supplementary cell voltages associated with memory cells in the memory device, according to some example embodiments disclosed herein.

[0019] Figure 5 This is an example diagram depicting the refresh of one or more memory banks of at least one memory array according to some example embodiments disclosed herein;

[0020] Figure 6A and Figure 6B This is an example diagram depicting a refresh operation incorporated into one or more memory chips of a host according to some example embodiments disclosed herein;

[0021] Figure 7 This is an example flowchart depicting a method for controlling refresh operations of at least one memory device according to some example embodiments disclosed herein;

[0022] Figure 8 This is an example flowchart depicting a method for controlling refresh operations in a memory device using data bits of RCC and supplementary units, according to some example embodiments disclosed herein.

[0023] Figure 9This is an example flowchart depicting a method for controlling refresh operations in a memory device using the voltage of a supplementary unit and an RCC, according to some example embodiments disclosed herein.

[0024] Figure 10 This is an example diagram depicting the initialization of data bits / voltages connected to one or more RCCs in each memory row according to some example embodiments disclosed herein;

[0025] Figure 11 These are example sequence diagrams depicting methods for performing a self-refresh operation according to some example embodiments disclosed herein; and

[0026] Figure 12 These are example diagrams depicting a conventional self-refresh operation according to some example embodiments disclosed herein, as well as a self-refresh operation performed using RCC and supplementary units. Detailed Implementation

[0027] The exemplary embodiments herein, along with their various features and beneficial details, are explained more fully with reference to the non-limiting embodiments illustrated in the accompanying drawings and detailed in the description below. Descriptions of well-known components and processing techniques have been omitted to avoid unnecessarily obscuring the embodiments herein. The description herein is intended only to facilitate an understanding of how the exemplary embodiments herein can be practiced, and is also intended only to enable those skilled in the art to practice the exemplary embodiments herein. Therefore, this disclosure should not be construed as limiting the scope of the exemplary embodiments herein.

[0028] The embodiments herein disclose methods and systems for controlling refresh operations of memory devices.

[0029] The embodiments herein disclose methods and systems for integrating at least one row state unit (RCC) and at least one supplementary unit into each of a plurality of memory rows in a memory device to control refresh operations of the memory device.

[0030] In conventional methods, refresh operations on memory cells can be performed based on / according to cell retention time. Cell retention time can be a predefined time, where the predefined time is the time a memory cell retains data bits before they are lost / leaked. Furthermore, more data loss / leaking may occur at higher operating temperatures. Cell retention time can be defined by considering the worst / weakest memory cell in the memory device (which is likely to lose charge earliest). In one example, for higher temperatures, cell retention time could be defined as 64 milliseconds (ms) or 32 ms. However, performing refresh operations based on cell retention time leads to performance degradation due to reduced bandwidth and / or increased power consumption.

[0031] Figure 1B This is an example sequence diagram depicting a conventional method for performing refresh operations on a memory device coupled to a host. The host includes a memory controller. The memory device includes multiple memory cells and a refresh controller. The multiple memory cells can be arranged in rows (word lines) and columns (bit lines). Each memory cell includes a capacitor and a transistor; the capacitor is used to store data bits, and the transistor is used to determine / access whether the memory cell is currently being accessed for data bits (e.g., ...). Figure 1A (As depicted in the text). The refresh controller can be configured to refresh at least one row comprising multiple memory cells.

[0032] The memory controller sends a refresh command to the refresh controller to refresh rows of memory cells. The memory controller issues the refresh command based on the capacity and configuration of the memory device. Upon receiving the refresh command from the memory controller, the refresh controller initiates a refresh operation on the rows of memory cells. Simultaneously, the memory controller waits for the refresh cycle time (tRFC). The tRFC time can be the maximum time required to complete the refresh operation initiated on the rows of memory cells. Once tRFC has elapsed, the memory controller issues other commands (e.g., read and / or write commands) to the memory device to perform other operations (e.g., read and / or write operations). The memory controller then waits for the periodic refresh interval time (tREFI) (e.g., 7.8 microseconds (μs)) within the cell retention time (e.g., 64 ms) by tracking the time elapsed since the last refresh command was issued. Once tREFI has elapsed, the memory controller issues another refresh command to the refresh controller to refresh the next row or group of rows.

[0033] In such Figure 1C In the example depicted, the memory controller can issue 8192 refresh commands to the refresh controller within the cell retention time (e.g., 64 ms or 32 ms). Therefore, at higher temperatures, the memory controller can issue a single refresh command at a tREFI of 7.8 microseconds (μs) or 3.9 μs (e.g., tREFI = 64 ms / 8192 = 7.8 μs or tREFI = 32 ms / 8192 = 3.9 μs). However, as the density of memory cells in a memory device increases, the time required to refresh rows of memory cells may increase (e.g., possibly exponentially for a single refresh command). Therefore, refresh operations may consume more bandwidth than is used for read and / or write operations, potentially degrading the performance of the memory device.

[0034] Now refer to Figures 2 to 12 (where similar reference numerals consistently denote corresponding features throughout all figures), some example embodiments are shown.

[0035] Figure 2 A memory system 200 according to some example embodiments disclosed herein is depicted. The memory system 200 includes at least one memory device 202 and a host 204.

[0036] The memory device 202 mentioned herein may be a volatile semiconductor (or volatile semiconductor memory) device configured to store data. The data may be, but is not limited to, files, documents, media (e.g., text, images, audio, video, animation, etc.), applications (e.g., calendar applications, call-related applications, streaming applications, file download-related applications, social networking applications, camera applications, IoT-related applications, data management applications, augmented reality (AR)-related applications, game-related applications, etc.), at least one of the following.

[0037] In some example embodiments, memory device 202 may be, but is not limited to, random access memory (RAM). Examples of random access memory may include, but are not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous graphics random access memory (SGRAM), high-bandwidth memory (HBM), magnetoresistive random access memory (MRAM), etc. In some example embodiments, memory device 202 may be at least one type of DRAM, such as, but not limited to, synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), graphics double data rate DRAM (GDDR DRAM), quadruple data rate DRAM (QDR DRAM), video DRAM (VDRAM), extended data output DRAM (EDO DRAM), multi-bank DRAM (MDRAM), etc. In some example embodiments, memory device 202 may be at least one of monolithic memory circuitry, semiconductor dies, stacks of memory dies, chips, packaged memory circuitry, or any other type of tangible memory circuitry.

[0038] The memory device 202 can communicate with the host 204 via a memory channel / bus. The memory channel can support various protocols that enable the memory device 202 to communicate with the host 204 (such as, but not limited to, memory protocols (e.g., dual in-line memory module (DIMM) interface, LPDDR, LPDRAM, JEDEC, etc.), input / output (I / O) protocols (e.g., PCI, InfiniBand, etc.), networking protocols (e.g., Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), etc.), storage protocols (e.g., Network File System (NFS), Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), etc.), wireless protocols, etc.).

[0039] The memory device 202 includes at least one memory array 206, a refresh controller 208, a refresh row selection circuit 210, and a refresh circuit 212.

[0040] Memory array 206 includes multiple memory cells 302 for storing data (e.g., ... Figures 3A to 4B (As depicted herein). Multiple memory cells 302 may be located on an array having multiple word lines / rows 304a and multiple bit lines 304b. The intersection of bit lines 304b and word lines 304a constitutes the address of the memory cell 302 / corresponds to the address of the memory cell 302. Data being written to or read from the memory cell 302 can be determined based on the bit lines 304b. Word lines / rows can be used to control the reading of data from and / or the writing of data to the memory cell 302. Data can be read from / written to the memory cell 302 by applying a signal to a positioned word line 304a. The exemplary embodiments herein use interchangeably terms such as "word line," "row of memory cell," "memory row," "row," etc., to refer to wiring / physical connections (such as gates) that can be used to control the reading and writing of the memory cell 302.

[0041] Each memory cell 302 includes one or more capacitors (such as capacitor 302a) for storing data as bits '0' or bits '1' (hereinafter referred to as data bits). The charge on capacitor 302a determines the data bits stored in capacitor 302a. To maintain data integrity and prevent data loss, the data bits / charge of memory cell 302 can be recovered using a refresh operation. A refresh operation may include: reading charge / data from capacitor 302a of memory cell 302; and rewriting the read data (e.g., accessible data) into capacitor 302a by restoring the charge on capacitor 302a to its original level.

[0042] The refresh controller 208 can be configured to control refresh operations in the memory device 202. In some example embodiments, the refresh controller 208 controls the refresh operation by selecting one or more memory rows 304a for the refresh operation and (e.g., performing refresh operations sequentially on the selected one or more memory rows 304a in a predetermined (or optionally, variable) order). In some example embodiments, performing a refresh operation on the selected one or more memory rows 304a refers to restoring the charge / data bits of the memory cells 302 located on the selected one or more memory rows 304a. The refresh operation may include reading the data bits of the memory cells 302 and rewriting the data bits into the memory cells 302.

[0043] The refresh controller 208 can also be configured to enable the refresh row selection circuit 210 to select one or more memory rows 304a for a refresh operation, wherein the refresh operation may be performed on only one selected row at a time. In some example embodiments, the refresh row selection circuit 210 may select one or more memory rows 304a for a refresh operation by: determining the state of memory cells 302 located on one or more memory rows 304a, and determining a time period (hereinafter referred to as the refresh period) corresponding to the time of the refresh operation performed on the one or more memory rows 304a. In some example embodiments, the refresh controller 208 may select one or more memory rows 304a for a refresh operation based on a combination of row status cell (RCC) storage voltage and supplementary cell voltage associated with one or more memory rows 304a. After selecting one or more memory rows 304a, the refresh row selection circuit 210 may activate the one or more memory rows 304a selected for the refresh operation.

[0044] The refresh controller 208 can also be configured to enable the refresh circuit 212 to perform refresh operations one by one on the active / selected memory rows 304a, and skip refresh operations on memory rows 304a that have not yet been activated / selected. In some example embodiments, based on the specifications / design of the memory device 202, only one selected memory row 304a can be refreshed at a time. The refresh circuit 212 performs the refresh operation by reading charge / data from the capacitor 302a of the memory cell 302 located on the selected one or more memory rows 304a, and rewriting the read data (e.g., accessible data) into the cell by restoring the charge in the capacitor 302a to its previous level.

[0045] The host 204 referred to herein may be at least one of a processor, system-on-a-chip (SoC), server, integrated chip (IC), chipset, mobile computing device, mobile phone, smartphone, tablet computer, phablet, personal digital assistant (PDA), laptop computer, computer, wearable device, IoT (Internet of Things) device, wearable computing device, vehicle infotainment system, medical device, camera, application processor (AP), multiprocessor system, microprocessor-based programmable consumer electronics, network computer, minicomputer, mainframe computer, and any other device supporting at least one memory device 202.

[0046] Host 204 may include memory controller 214. Host 204 may also include components (not shown) such as, but not limited to, a central processing unit (CPU) / processor, a memory copying accelerator block, input / output (I / O) ports, etc. Memory controller 214 may be configured to control the operation of at least one memory device 202 by maintaining information about at least one memory device 202. Examples of operation may be, but are not limited to, reading data from at least one memory device 202, writing data to at least one memory device 202, initiating a refresh operation for refreshing at least one memory device 202, etc. The information may be at least one of the following: the number of memory devices 202 associated with host 204, the capacity and / or configuration of at least one memory device 202, data stored in at least one memory array 206 of memory device 202, the location / address of data stored within at least one memory array 206, the time defined for performing at least one operation in memory device 202, etc.

[0047] To perform a refresh operation, the memory controller 214 of host 204 may issue a refresh command to the refresh controller 208 of memory device 202, indicating that at least one memory row 304a of memory array 206 will be refreshed. Memory device 202 may indicate the memory row 304a for the refresh operation based on the capacity and / or configuration of at least one memory device 202. Memory controller 214 may issue the refresh command based on cell retention time at periodic refresh intervals (e.g., time interval tREFI). Cell retention time may be the time during which memory cells 302 of memory array 206 can retain data before data loss / charge leakage. Based on the standards / specifications of memory device 202, tREFI and cell retention time may be variable or predefined. In some exemplary embodiments, for higher temperatures, the cell retention time may be 64 milliseconds (ms) or 32 ms. The temperature range may vary based on the type of memory device 202. In some exemplary embodiments, for temperature ranges of 85 degrees Celsius and above, the cell retention time may be 64 ms or 32 ms. In one example, for a cell retention time of 64 ms, tREFI can be 7.8 microseconds (μs), allowing the memory controller 214 to issue a refresh command to the memory device 202 every 7.8 μs. In another example, for a cell retention time of 32 ms, tREFI can be defined as 3.9 μs, allowing the memory controller 214 to issue a refresh command to the memory device 202 every 3.9 μs.

[0048] Upon receiving a refresh command from memory controller 214, refresh controller 208 enables refresh row selection circuit 210 to select one or more memory rows 304a from those memory rows 304a indicated in the refresh command as being used for a refresh operation. In some example embodiments, the one or more memory rows 304a may be selected based on the state and / or refresh requirement of the memory cells 302 included in the memory row 304a and / or based on a combination of RCC storage voltage and supplementary cell voltage associated with the one or more memory rows 304a. Refresh row selection circuit 210 can activate the selected one or more memory rows 304a. Once one or more memory rows 304a are selected for a refresh operation, refresh controller 208 enables refresh circuit 212 to perform a refresh operation on the selected / activated one or more memory rows 304a and skip refresh operations on one or more memory rows 304a that have not yet been selected / activated for a refresh operation. After performing a refresh operation on the selected one or more memory rows 304a, refresh controller 208 issues a skip command / instruction to memory controller 214. The refresh controller 208 sends a skip command to the memory controller 214 as confirmation, indicating the completion of the refresh operation on the indicated memory row 304a.

[0049] Upon receiving a skip command from refresh controller 208, memory controller 214 determines that one or more rows of memory device 202 have been refreshed (i.e., memory device 202 is idle). Memory controller 214 then issues other commands (such as, but not limited to, read commands and / or write commands) to the relevant internal circuitry (not shown) of memory device 202 to perform other operations (such as, but not limited to, read operations and / or write operations). Memory controller 214 also tracks the time associated with tREFI (e.g., the time since the last refresh command was issued). Once tREFI has elapsed, memory controller 214 issues another refresh command to refresh controller 208 to perform refresh operations on other memory rows 304a. Therefore, selective refresh of one or more memory rows 304a can reduce the latency of memory controller 214 as well as the bandwidth and time required for refresh operations.

[0050] In some example embodiments, if the refresh selection circuit 210 selects all memory rows 304a indicated in the refresh command for the refresh operation, the refresh controller 208 enables the refresh circuit 212 to perform the refresh operation on all memory rows 304a. Furthermore, if all indicated memory rows 304a have already been selected for the refresh operation, the refresh controller 208 does not issue a refresh skip command to the memory controller 214. In such a case, the memory controller 214 waits for the refresh cycle time (tRFC), which can be large (e.g., the refresh cycle time (tRFC) is the maximum time required to refresh all memory rows 304a). tRFC can be based on the specifications of the memory device 202; however, the example embodiments are not limited thereto. Once the tRFC time has elapsed, the memory controller 214 determines that the refresh operation is complete and issues one or more commands to the relevant internal circuitry (not shown) of the memory device 202 to perform one or more operations. Then, the memory controller 214 can wait for tREFI, and once tREFI has passed, the memory controller 214 can issue another refresh command to refresh another set of memory rows 304a.

[0051] Figure 2 Example blocks (or “boxes”) of the memory system 200 are shown, but it will be understood that the example embodiments are not limited thereto. In some example embodiments, the memory system 200 may include fewer or more blocks. Furthermore, the labels or names of the blocks are for illustrative purposes only and do not limit the scope of the example embodiments herein. One or more blocks may be combined to perform the same or substantially similar functions in the memory system 200.

[0052] Figure 3A and Figure 3B This is a block diagram of a memory device 202 for controlling refresh operations based on the state and refresh requirements of memory cell 302, according to some example embodiments disclosed herein.

[0053] The memory device 202 includes a memory array 206, at least one sense amplifier (such as sense amplifier 306), a refresh controller 208, a refresh row selection circuit 210, and a refresh circuit 212. In some example embodiments, the refresh row selection circuit 210 includes a row address demultiplexer (row address DEMUX) 318, a row status circuit 308, a supplementary reload circuitry 312, and a digital verification module 320.

[0054] Memory array 206 includes a plurality of memory cells 302, which may be located on a plurality of memory rows / word lines 304a and a plurality of bit lines 304b. In some example embodiments, memory array 206 may include 'm' memory rows 304a and 'n' bit lines 304b (where m and n are both integers greater than 0), such that memory array 206 includes (m×n) memory cells 302. Each memory cell 302 includes a capacitor 302a and a transistor 302b. Capacitor 302a may be configured to store data bits, and the charge level of capacitor 302a determines the data bits stored in capacitor 302a. For example, the presence of charge on capacitor 302a determines that the data bit stored in capacitor 302a may be '1', and the absence of charge on capacitor 302a determines that the data bit stored in capacitor 302a may be '0'. Optionally, the presence of charge on capacitor 302a can indicate that the data bit stored in the capacitor is '0', and the absence of charge on the capacitor can indicate that the data bit stored in the capacitor is '1'. Transistor 302b can determine whether the associated memory cell 302 is currently being accessed for data. Furthermore, data bits / charges can be read from / written to the capacitor 302a of memory cell 302 by activating / enabling the corresponding memory row 304a.

[0055] The sense amplifier 306 can be coupled to at least one memory cell 302 of the memory array 206 using bit lines. The sense amplifier 306 can be enabled (via associated internal circuitry (not shown) of the memory device 202) when data is to be read from the memory array 206. The sense amplifier 306 senses a low-voltage signal representing a data bit ('1' or '0') stored in the memory cell 302 from the bit lines and amplifies the sensed low-voltage signal to a recognizable logic level, allowing the data to be correctly interpreted / read by the host 204.

[0056] Row state circuitry 308 and supplementary overload circuitry 312 can be combined with memory array 206 using logic gates 316. Row state circuitry 308 includes one or more row state cells (RCCs) 310, which can be connected to corresponding memory rows 304a using logic gates 316. In some example embodiments, such as Figure 3A As depicted, the row state circuitry 308 may include a single RCC 310 for each memory row 304a. In some example embodiments, such as Figure 3A As depicted, the logic gate 316 that combines the row state circuit 308 with the memory row 304a of the memory array 206 can involve simple AND gate logic. In some example embodiments, such as Figure 3B As depicted, the row state circuitry 308 may include multiple RCCs 310 for each memory row 304a. In some example embodiments, such as Figure 3B As depicted, the logic gate 316 that combines the row state circuit 308 with the memory row 304a of the memory array 206 can involve complex logic for selecting the memory row 304a. For example, as Figure 3B As depicted, the row state circuitry 308 may include 'N' RCCs 310 for a single memory row 304a (here, N may be an integer greater than 1). In some example embodiments, one or more RCCs 310 may be inherently volatile or non-volatile. If one or more RCCs 310 are inherently volatile, then one or more RCCs 310 may also be refreshed.

[0057] RCC 310 may be the same as memory cell 302 of memory array 206. RCC 310 may include capacitor 310a and transistor 310b. Capacitor 310a of RCC 310 may be configured to store data bits '1' or '0'. The charge / voltage on capacitor 310a of RCC 310 may determine the stored data bits. Transistor 310b may determine / control access to the associated RCC 310. Optionally or additionally, RCC 310 may include or correspond to an openable / closeable fuse and / or antifuse. The fuse / antifuse may be configured (e.g., may be blown) such that RCC 310 is non-volatile.

[0058] In some example embodiments, RCC 310 can be used to classify the respective connected memory rows 304a into one or more states. The charge / data bits present on the capacitors 310a of the RCC 310 can be used to classify their respective connected memory rows 304a into one or more states. The states referred to herein can be, but are not limited to, best row, good row, bad row, average row, etc. The state of a memory row 304a can indicate the memory cells 302 located on the corresponding memory row 304a at their data loss rate and / or time level. In some example embodiments, the number of states can vary based on the number of RCC 310s connected to each memory row 304a. For example, 'N' RCCs 310 can be used to classify the associated memory rows 304a into up to 2 N There are several states.

[0059] In some example embodiments, if a single RCC 310 is connected to memory row 304a (e.g. Figure 3AAs depicted in [the text], RCC 310 can store only '1' or '0' (i.e., 2 data bits), allowing the data bits of RCC 310 to be used to classify the connected memory row 304a into one of two states. For example, consider an example where a single RCC 310 is connected to memory row 304a. In this case, if RCC 310 stores charge / data bit '1', the memory row 304a connected to the corresponding RCC 310 can be classified as a good row. If RCC 310 stores charge / data bit '0', the memory row 304a connected to the corresponding RCC 310 can be classified as a bad row. In some example embodiments, a good row may correspond to a row with better refresh / retention performance than a bad row. For example, each cell in a good row may retain charge for a longer than a predetermined (or optionally, variable) threshold, while each cell in a bad row may not retain charge for a longer than the threshold. In some example embodiments, a good row may correspond to a row in which the average refresh performance and / or average retention performance of all cells on the good row is better than a variable (or alternatively, predetermined) threshold, and a bad row may correspond to a row in which the average refresh performance and / or average retention performance of all cells on the bad row is worse than the threshold.

[0060] In some example embodiments, if two RCCs 310 are connected to a single memory row 304a, the two RCCs 310 can use capacitors 310a and / or fuses / anti-fuse (not shown) to store data bits “00” or “01” or “10” or “11” (i.e., 4 data bits). Therefore, the two RCCs 310 can be used to classify the connected memory row 304a into one of four states. Consider an example case where two RCCs 310 (RCC1 and RCC2) are connected to a single memory row 304a. In this case, if RCC1 and RCC2 store charge / data bits '0', the memory row 304a connected to the corresponding RCC1 and RCC2 can be classified as a bad row. If RCC1 stores charge / data bits '0' and RCC2 stores charge / data bits '1', the memory row 304a connected to the corresponding RCC1 and RCC2 can be classified as an average row. If RCC1 stores charge / data '1' and RCC2 stores charge / data '0', then the memory row 304a connected to the corresponding RCC1 and RCC2 can be classified as a good row. If RCC1 stores charge / data '1' and RCC2 stores charge / data '1', then the memory row 304a connected to the corresponding RCC1 and RCC2 can be classified as a best row. The embodiments herein may interchangeably use terms such as, but not limited to, "RCC," "refresh cell," "voltage storage cell (VCS)," etc., to denote one or more cells that can be connected to each memory row 304a to depict the state of the corresponding memory row 304a.

[0061] In some exemplary embodiments, multiple RCC 310s can be divided into different groups for determining the state at different temperature ranges. For example, the first two (least significant) data bits of RCC 310 can be used to determine the state of the connected memory row 304a at a lower temperature, and the last (most significant) data bit of RCC 310 can be used to determine the state of the connected memory row 304a at a higher temperature; however, the example embodiment is not limited to this, and other bits can correspond to the temperature-based refresh capability / performance of the memory row 304a. In the example here, temperatures below 65 degrees Celsius can be considered to be in the lower temperature range, and temperatures above 65 degrees Celsius can be considered to be in the higher temperature range.

[0062] In some example embodiments, host 204 may pre-initialize the data bits / charge / voltage of one or more RCC 310s based on cell retention criteria / DIMM data. Cell retention criteria may include, but are not limited to, information such as: a retention analysis mechanism suitable for identifying weak memory cells 302 (memory cells 302 that may be the first to lose data / leak charge) in each memory row 304a; the number of rounds of testing required / used to identify weak memory cells 302; retention time tests for determining whether each memory row 304a can be refreshed at a normal rate; etc. Cell retention criteria for memory device 202 can be determined by testing memory device 202 during its production / manufacturing. Cell retention criteria may be maintained / set in memory device 202 after testing (e.g., maintained in the non-volatile portion of memory device 202 (e.g., in fuse / anti-fuse memory)). Once memory device 202 is initialized / started, the host 204's Basic Input / Output System (BIOS) (not shown) accesses the cell reservation criteria held in memory device 202. Thereafter, host 204 performs tests on memory device 202 using the accessed cell reservation criteria. In some example embodiments, host 204 may use a Memory Built-In Self Test (MBIST) module and / or any other module / device with similar capabilities to speed up the testing of memory device 202. During testing, when determining whether a memory cell 302 located on the corresponding memory row 304a has passed the accessed cell reservation criteria, host 204 may initialize the data bits or voltage of one or more RCC 310s connected to memory row 304a. Host 204 may use Mode Register (MR) commands to initialize the data bits (e.g., voltage) of one or more RCC 310s. In some example embodiments, the MR command may be a specialized command similar to a normal MR command, which can be used to operate memory device 202 in Target Row Refresh (TRR) mode, etc. (where normal read and write operations cannot be performed). In some example embodiments, the MR command used to initialize the data bits or voltage of one or more RCC 310s can be implemented using the normal MR command used to operate the memory device in TRR mode, etc.

[0063] The host 204 can also reinitialize the data bits, voltages, or values ​​of one or more RCC 310s. In some example embodiments, the digital verification module 320 can also reinitialize the data bits, voltages, or values ​​of the RCC 310. The data bits or voltages of the RCC 310 can be initialized to mark the memory row 310 connected to the RCC 310 as a bad row that requires a refresh operation in each (refresh) cycle.

[0064] In some example embodiments, when an error correction code (ECC) error is detected by host 204, host 204 / digital verification module 320 can reinitialize one or more data bits of RCC 310. In some example embodiments, digital verification module 320 can reinitialize the data bits of RCC 310 on-board using methods / techniques such as, but not limited to, single-bit correction methods, double-bit error detection methods (SECDED ECC), etc. In one embodiment, digital verification module 320 can use any method / technique defined in the specifications of memory device 202 to initialize the data bits / voltage of RCC 310 on-board.

[0065] When an ECC error occurs in a specific memory row 304a, the host 204 / digital verification module 320 can treat the corresponding memory row 304a as a bad row / worst row and can reinitialize the data bits of one or more RCC 310s connected to the corresponding memory row 304a. For example, when an ECC error occurs in memory row 304a connected to the corresponding RCC 310, the host 204 can reinitialize the data bits of the RCC 310 from '1' to '0', therefore, the corresponding memory row 304a cannot be skipped from the refresh operation.

[0066] In some example embodiments, host 204 can initialize the data bits of one or more RCC 310s by performing a scrub method. For example, host 204 can perform the scrub method when the temperature of memory device 202 exceeds a temperature threshold (which may be variable or optionally predefined based on the specifications of memory device 202). In some example embodiments, host 204 can perform the scrub method at variable (or optionally, predefined) regular intervals. The scrub method includes: reading the ECC from each location of memory device 202, correcting the bit errors if they exist within the ECCs, and backing the corrected data bitwise parallel to each read location of memory device 202. The scrub method can be used to prevent crashes and errors in large-scale server farms (e.g., host 204 according to the inventive concept) where the probability of failure is high due to the presence of a large number of memory devices 202.

[0067] The supplementary overload circuit 312 may include one or more supplementary units 314, which are connected to the corresponding memory row 304a using logic gates 316. In some example embodiments, such as Figure 3A As depicted, the supplementary overload circuitry 312 includes a single supplementary unit 314 for each memory row 304a. In some example embodiments, such as Figure 3A As depicted, logic gate 316 may include simple AND logic. In some example embodiments, such as Figure 3B As depicted, the supplementary overload circuitry 312 includes multiple supplementary units 314 for a single memory row 304a. For example, as... Figure 3B As depicted, the supplementary overload circuitry 312 may include 'M' supplementary units 314 for a single memory row 304a (where M can be an integer greater than 1). In one embodiment, one or more supplementary units 314 may be volatile units. After refreshing the memory row 304a connected to the corresponding one or more supplementary units 314, the one or more supplementary units 314 may also be refreshed.

[0068] One or more supplementary cells 314 may be identical to memory cells 302 of memory array 206; however, the example embodiment is not limited thereto. Supplementary cell 314 may include capacitor 314a and transistor 314b; optionally or additionally, supplementary cell 314 may include fuse / antifuse (not shown). Capacitor 314a of supplementary cell 314 may be configured to store data bits '1' or '0'. The charge / voltage on capacitor 314a of supplementary cell 314 may be used to determine the stored data bits. Hereinafter, the charge / voltage stored on capacitor 314a of supplementary cell 314 may be referred to as supplementary charge / voltage (or supplementary cell charge / voltage). Transistor 314b of supplementary cell 314 controls access to data from the corresponding supplementary cell 314.

[0069] In some example embodiments, one or more supplementary units 314 may be used to determine the refresh requirement of a corresponding memory row 304a. The refresh requirement may determine whether the memory cell 302 located on the corresponding memory row 304a will be refreshed based on the charge / data bits / voltage stored in the capacitors 314a of one or more supplementary units 314. In each refresh cycle, the data bits / voltage / charge of the capacitors 314a of one or more supplementary units 314 may be set by the digital verification module 320 after a refresh operation is performed on the associated memory row 304a. In some example embodiments, the supplementary units 314 included in the supplementary reload circuit 312 may depict the refresh requirement of the row of memory cells 302 for one or more refresh cycles, and the number of supplementary units 314 included in the supplementary reload circuit 312 may correspond to the number of refresh cycles involved in the refresh requirement of the row of memory cells 302. For example, a single supplementary unit 314 connected to the memory row 304a may depict the refresh requirement of the corresponding memory row 304a for only one refresh cycle. The two supplementary units 314 connected to memory line 304a can depict the refresh requirements of the corresponding memory line 304a for a larger number (e.g., up to three) of refresh cycles.

[0070] For example, consider the case where a single supplementary cell 314 is connected to memory row 304a. In this case, if supplementary cell 314 stores supplementary charge / voltage '1', then memory row 304a connected to the corresponding supplementary cell 314 will be refreshed for one refresh cycle. If supplementary cell 314 stores supplementary charge / voltage '0', then memory row 304a connected to the corresponding supplementary cell 314 can (e.g., will) be skipped from the refresh operation for one refresh cycle.

[0071] Optionally, consider the example case where two supplementary units 314 (supplementary unit 1 and supplementary unit 2) are connected to memory row 304a. In this case, if supplementary unit 1 and supplementary unit 2 store supplementary charge / voltage / data bits '0', then the memory row 304a connected to the corresponding supplementary unit 314 will be refreshed for one refresh cycle (i.e., not skipped from the refresh operation for one refresh cycle) (or, for example, will not be skipped from the refresh operation to be performed). If supplementary unit 1 stores supplementary charge / voltage / data bits '0' and supplementary unit 2 stores supplementary charge / voltage / data bits '1', then the memory row 304a connected to the corresponding supplementary unit 1 and supplementary unit 2 can be skipped from the refresh operation for one refresh cycle. If supplementary unit 1 stores supplementary charge / voltage / data bits '1' and supplementary unit 2 stores supplementary charge / voltage / data bits '0', then the memory row 304a connected to the corresponding supplementary unit 1 and supplementary unit 2 can be skipped from the refresh operation for two refresh cycles. If supplementary unit 1 stores supplementary charge / voltage / data bit '1' and supplementary unit 2 stores supplementary charge / voltage / data bit '1', then the memory row 304a connected to the corresponding supplementary units 1 and 2 can skip the refresh operation for three refresh cycles.

[0072] Row address DEMUX 318 can be configured to activate one or more memory rows 304a indicated by the memory controller 214 of host 204 for a refresh operation. Row address DEMUX 318 receives one or more row addresses from memory controller 214 via associated internal circuitry (not shown) of memory device 202, wherein the one or more row addresses may correspond to memory rows 304a that must be refreshed. Row address DEMUX 318 can activate the memory row 304a corresponding to the received one or more row addresses by applying, for example, a signal '1' to the memory row 304a.

[0073] The digital verification module 320 can be combined with the row state circuitry 308 and the supplementary overload circuitry 312 using an OR gate mechanism 322. In some example embodiments, if a single supplementary unit 314 is connected to the memory row 304a, the OR gate mechanism 322 involves simple OR logic. In some example embodiments, if multiple supplementary units 314 are connected to the memory row 304a, the OR gate mechanism 322 involves complex logic.

[0074] The digital verification module 320 can be configured to initialize / set the data bits / values / voltages of the supplementary unit 314 in each refresh cycle by determining whether to perform a refresh operation on the memory row 304a connected to the corresponding supplementary unit 314.

[0075] For example, consider the case where a single supplementary unit 314 is connected to memory row 304a. In this case, the digital verification module 320 determines the data bits to be initialized on supplementary unit 314 by determining whether a refresh operation should be performed on memory row 304a connected to the corresponding supplementary unit 314 based on the associated current data bits. The digital verification module 320 then updates the determined data bits to be initialized on supplementary unit 314 to the logic OR gate mechanism 322. In some example embodiments, if a refresh operation is performed on memory row 304a connected to supplementary unit 314 in the current refresh cycle (e.g., the current data bit of supplementary unit 314 is '1'), the digital verification module 320 can set the data bit of supplementary unit 314 to '0'. Therefore, updating the data bit of supplementary unit 314 from '0' to '1' can indicate that the refresh operation can be skipped for memory row 304a in the next refresh cycle. If no refresh operation is performed on the memory line 304a connected to the supplementary unit 314 (e.g., the current data bit of the supplementary unit 314 is '0'), the digital verification module 320 can set the data bit of the supplementary unit 314 to '1'. Therefore, updating the data bit of the supplementary unit 314 from '1' to '0' indicates that a refresh operation must be performed for memory line 304a in the next refresh cycle. However, the example embodiments are not limited to this; in some example embodiments, the indications for updating the data bits of the supplementary unit 314 from '0' to '1' and from '1' to '0' can be defined as the opposite of those in the foregoing example embodiments. In one embodiment, the digital verification module 320 updates the data bits to be initialized on the supplementary unit 314 to the logic OR gate mechanism 322.

[0076] For example, consider the case where two supplementary units 314 (supplementary unit 1 and supplementary unit 2) are connected to memory row 304a. In this case, the digital verification module 320 determines whether to perform a refresh operation on the memory row 304a connected to the corresponding supplementary unit 314 based on the associated current data bits to determine the data bits that will be initialized on the supplementary unit 314. The digital verification module 320 then provides an output that can be combined with the output of RCC 310 using simple or complex logic using the OR gate mechanism 322. The output provided by the digital verification module 320 can correspond to the data bits determined to be initialized on the supplementary unit 314. In some example embodiments, if a refresh operation is performed on the memory row 304a connected to supplementary units 1 and 2 every three refresh cycles (the current data bits of supplementary units 314 can be '00'), the digital verification module 320 can set the data bits of supplementary units 1 and 2 to correspond to '01', '10', or '11'. Therefore, the indication could be that the refresh operation can be skipped for memory line 304a in the next one, two, or three refresh cycles.

[0077] The digital verification module 320 can also be configured to write data bits / values ​​to supplementary unit 314 if the associated memory line 304a is refreshed and / or if data is read from or written to the associated memory line 304a. For example, if the memory line 304a connected to the corresponding supplementary unit 314 is refreshed, the digital verification module 320 may write data bits (e.g., '0') indicating that the memory line 304a has been refreshed to supplementary unit 314.

[0078] The digital verification module 320 can also be configured to select one or more memory rows 304a for a refresh operation. In some example embodiments, the digital verification module 320 selects one or more memory rows 304a based on their status and refresh requirements. The digital verification module 320 can determine the status of one or more memory rows 304a by examining data bits of one or more RCC 310 connected to the corresponding memory rows 304a. The digital verification module 320 can determine the refresh requirement by examining data bits of one or more supplementary units 314 connected to the corresponding memory rows 304a. Based on the determined status and refresh requirement of each memory row 304a, the digital verification module 320 selects one or more memory rows 304a for the refresh operation.

[0079] In some example embodiments, if memory line 304a is a "bad" line and has not been refreshed for a long time / long refresh cycle, the digital verification module 320 may select memory line 304a for a refresh operation. In some example embodiments, if memory line 304a is a "bad" line, the digital verification module 320 may select memory line 304a for a refresh operation even if it has already been refreshed in a previous refresh cycle. In some example embodiments, if memory line 304a is a "good" line and has already been refreshed in a previous refresh cycle, the digital verification module 320 may not select memory line 304a for a refresh operation. In some example embodiments, if memory line 304a is a "good" line and has not been refreshed for a long time, the digital verification module 320 may select memory line 304a for a refresh operation.

[0080] The refresh controller 208 can be configured to enable the digital verification module 320 to select one or more memory rows 304a for a refresh operation. The refresh controller 208 can also be configured to enable the refresh circuit 212 to perform a refresh operation on the selected one or more memory rows 304a.

[0081] To perform a refresh operation on memory device 202, memory controller 214 issues a refresh command and a row address (corresponding to the group of memory rows 304a to be refreshed) to memory device 202. At memory device 202, refresh controller 208 receives the refresh command and row address from memory controller 214 via relevant internal circuitry (not shown) of memory device 202. Refresh controller 208 provides the received row address to row address DEMUX318. Upon receiving the row address, row address DEMUX318 activates the group of memory rows 304a corresponding to the received row address.

[0082] When activating a group of memory rows 304a, the digital verification module 320 selects one or more memory rows 304a from the group of activated memory rows 304a for a refresh operation. The digital verification module 320 selects one or more memory rows 304a by performing a digital read of one or more data bits of one or more RCC 310 connected to each memory row 304a in the group of identified memory rows 304a, and one or more data bits of one or more supplementary units 314 connected to each memory row 304a in the group of identified memory rows 304a. The digital verification module 320 can determine the state of each memory row 304a based on the read one or more data bits of the one or more RCC 310. The digital verification module 320 can determine the refresh requirement of each memory row 304a based on the read one or more data bits of the supplementary units 314. The digital verification module 320 then uses the determined state and refresh requirement of each memory row 304a to select one or more rows from the group of identified memory rows 304a for a refresh operation. The digital verification module 320 can also enable one or more selected memory rows 304a for refresh operations. The digital verification module 320 can enable row address DEMUX 318 to deactivate one or more memory rows 304a not selected for refresh operations by blocking signal 1 on the corresponding one or more memory rows 304a. If the selected one or more memory rows 304a are not valid, the digital verification module 320 can also enable row address DEMUX 318 to activate the selected one or more memory rows 304a.

[0083] When one or more selected memory rows 304a are activated, refresh controller 208 can enable refresh circuit 212 to perform a refresh operation. Refresh circuit 212 can determine that one or more active memory rows 304a in a group of memory rows 304a are selected for the refresh operation. Refresh circuit 212 can then perform the refresh operation on the selected one or more memory rows 304a and can skip refresh operations on memory rows 304a that have not yet been selected / activated. The refresh operation includes reading charge / data from capacitor 302a of memory cells 302 located on the selected one or more memory rows 304a, and rewriting the read data (e.g., accessible data) into capacitor 302a by restoring the charge / data bits of memory cells 302.

[0084] Once the refresh operation is completed on one or more selected memory rows 304a, the refresh controller 208 sends a refresh skip command to the memory controller 214 as confirmation of the refresh operation's completion. Therefore, the memory controller 214 does not need to wait for the standard tRFC period to issue other commands to the memory device 202 to perform other operations, further reducing the bandwidth and / or time required to perform the refresh operation.

[0085] If the digital verification module 320 selects all memory rows 304a in the group of active memory rows 304a for refresh operation, the refresh controller 208 does not send a refresh skip command to the memory controller 214 of the host 204.

[0086] Figure 4A and Figure 4B This is a block diagram of a memory device 202 that uses RCC storage voltage and supplementary cell voltage to control refresh operations according to some example embodiments disclosed herein. In some example embodiments, such as Figure 4A As depicted, the refresh row selection circuit 210 of the memory device 202 may include a single RCC / VCS 310 and a single supplementary unit 314 for a single memory row 304a. In some example embodiments, such as Figure 4B As depicted, the refresh row selection circuit 210 of memory device 202 may include one or more RCC / VCS 310s and a single supplementary cell 314 for a single memory row 304a. In some example embodiments, host 204 pre-initializes and / or stores the voltage of RCC 310 based on cell reservation criteria.

[0087] In some example embodiments, such as Figure 4A and Figure 4B As depicted, the refresh row selection circuit 210 may include an analog verification module 402. The analog verification module 402 may be configured to select one or more memory rows 304a for refresh operations based on the voltage / charge stored in capacitors 310a of one or more RCCs 310 and the voltage / charge of capacitors 314a of one or more supplementary units 314. Hereinafter, the voltage / charge stored in capacitors 310a of one or more RCCs 310 may always be referred to as the comparison voltage. Hereinafter, the voltage / charge of capacitors 314a of one or more supplementary units 314 may always be referred to as the supplementary voltage.

[0088] The simulation verification module 402 includes a voltage generation circuit 404, a plurality of transistors 406, and a comparator 408. The voltage generation circuit 404 can be configured to generate and maintain a reference voltage based on the number of RCC 310s connected to each memory row 304a. In some example embodiments, the voltage generation circuit 404 may use appropriate circuitry with variable (or alternatively, pre-calculated) resistance values ​​to generate and maintain the reference voltage.

[0089] In some example embodiments, the voltage generation circuit 404 can generate and maintain up to 2 N A reference voltage, where 'N' describes the number of RCC 310s connected to each memory row 304a. For example, if as Figure 4A As depicted, a single RCC 310 is connected to memory row 304a, then voltage generation circuit 404 generates and maintains two reference voltages Vref1 and Vref2 (e.g., 2). 1 (A reference voltage). For example, if such Figure 4B As depicted, three RCC 310s are connected to each memory row 304a, then the voltage generation circuit 404 generates and maintains eight reference voltages Vref1 to Vref8 (e.g., 2...). 3 (Reference voltage). Furthermore, if multiple RCC 310s are connected to a single memory row 304a, the RCC 310 provides more granularity for voltage comparison.

[0090] In some example embodiments, the RCC 310 can also be divided into multiple groups for storing comparison voltages. For example... Figure 4A As depicted, the voltage stored in an RCC 310 connected to memory row 304a can be used to classify memory row 304a as a good row or a bad row. Therefore, only two reference voltages are held / can be held, and one of the two reference voltages can be selected based on the voltage stored in an RCC 310. For example, if the maximum voltage of capacitor 310a of RCC 310 is 1.2V, the voltage generation circuit 404 can hold reference voltages of 1.15V and 1V. In this case, if the voltage of capacitor 310a of RCC 310 is higher than 1.15V, the memory row 304a connected to RCC 310 can be considered a 'bad' row and can be selected for refresh operation. If the voltage of capacitor 310a of RCC 310 is between 1.15V and 1V, the memory row 304a connected to RCC 310 can be considered a 'good' row and can be skipped from refresh operation. Similarly, if multiple RCC 310s are connected to memory row 304a, the reference voltage can be maintained with more granularity. For example, reference voltages of 1.15V, 1.1V, 1.05V, 1.0V, etc., can be maintained.

[0091] Transistor 406 can be connected to voltage generation circuit 404. Transistor 406 can be connected to one or more RCCs 310 connected to memory row 304a. For example, transistor 406 can be connected to one or more RCCs 310 connected to memory row 304a using diode 406a, but the example embodiment is not limited thereto. Transistor 406 can be configured to select 2 based on the initialization and / or stored voltage of the one or more connected RCCs 310. N One of the reference voltages. In some example embodiments, such as Figure 4A As depicted, if a single RCC 310 is connected to memory row 304a, a transistor 406 with a simple selection mechanism can be used to select 2. 1 One of the reference voltages. In some example embodiments, such as Figure 4B As depicted, if multiple RCC 310s are connected to memory row 304a, transistor 406 combined with complex logic (such as DEMUX) can be used to select 2 N One of the reference voltages.

[0092] Comparator 408 can be configured to logically compare the supplementary cell voltage of supplementary cell 314 with a reference voltage selected by transistor 406. Comparator 408 activates and / or deactivates memory rows 304a connected to supplementary cell 314 based on the voltage comparison. For example, if the voltage of supplementary cell 314 is less than the selected reference voltage, comparator 408 activates the memory row 304a connected to the corresponding supplementary cell 314, allowing the memory cells 302 of the activated row to be refreshed. If the voltage of supplementary cell 314 is greater than or equal to the selected reference voltage, comparator 408 deactivates the memory row 304a connected to the corresponding supplementary cell 314, allowing the deactivated row to be skipped from the refresh operation.

[0093] To perform a refresh operation on memory device 202, memory controller 214 can issue a refresh command and a row address (corresponding to the group of memory rows 304a that must be refreshed) to memory device 202. At memory device 202, refresh controller 208 can receive the refresh command and row address from memory controller 214 via relevant internal circuitry (not shown) of memory device 202. Refresh controller 208 provides the received row address to row address DEMUX 318. Upon receiving the row address, row address DEMUX 318 activates the group of memory rows 304a corresponding to the received row address.

[0094] When activating a group of memory rows 304a, at least one transistor 406 of the simulation verification module 402 selects a comparison voltage based on the initialization and / or storage of one or more RCC 310s connected to the identified group of memory rows 304a. N One of several reference voltages. Transistor 406 provides the selected reference voltage to comparator 408. Comparator 408 may also receive supplementary voltages from supplementary cells 314 connected to the group of active memory rows 304a. Comparator 408 then compares the supplementary voltages of supplementary cells 314 with the selected reference voltage. If the supplementary voltage of supplementary cells 314 is less than the selected reference voltage, comparator 408 selects one or more memory rows 304a connected to the corresponding supplementary cell 314 for refresh operation. Comparator 408 enables the selected one or more memory rows 304a. If the supplementary voltage of supplementary cells 314 is greater than or equal to the selected reference voltage, comparator 408 does not select one or more memory rows 304a connected to the corresponding supplementary cell 314 for refresh operation. Comparator 408 also enables row address DEMUX 318 to deactivate one or more memory rows 304a that have not yet been selected for refresh operation by blocking signal 1 on the corresponding one or more rows. If one or more selected memory rows 304a are not valid, comparator 408 also enables row address DEMUX318 to activate one or more selected memory rows 304a for the wipe operation.

[0095] When one or more memory rows 304a are selected for a refresh operation, the refresh controller 208 enables the refresh circuit 212 to perform the refresh operation. The refresh circuit 212 performs the refresh operation on the activated / selected one or more memory rows 304a and skips the refresh operation on one or more memory rows 304a that have not yet been selected / activated. The refresh operation includes reading charge / data from capacitor 302a of memory cells 302 located on the selected one or more memory rows 304a, and rewriting the read data (e.g., accessible data) into capacitor 302a by restoring the charge / data bits of memory cells 302.

[0096] Once a refresh operation on one or more selected memory rows 304a has been completed, the refresh controller 208 sends a refresh skip command to the memory controller 214 as confirmation, indicating the completion of the refresh operation. Therefore, the memory controller 214 does not need to wait for the standard tRFC period to issue other commands to the memory device 202 to perform other operations, further reducing the bandwidth and time required to perform the refresh operation.

[0097] If comparator 408 makes all identified groups of rows in memory cell 302 valid, then refresh controller 208 does not send a refresh skip command to memory controller 214 of host 204.

[0098] In some example embodiments, the refresh controller 208 maintains a refresh counter (not shown) that can be configured to track the count of memory rows 304a that have been refreshed in each refresh cycle. In one embodiment, the refresh controller 208 may increment the refresh counter as a refresh operation on each selected memory row 304a is completed. In one embodiment, the refresh controller 208 may also increment the refresh counter as a refresh operation on each row is skipped. In one embodiment, the refresh controller 208 may also increment the refresh counter in parallel with issuing a refresh skip command to the host 204.

[0099] Figure 3A , Figure 3B , Figure 4A and Figure 4B Exemplary blocks of memory device 202 are shown, but it will be understood that other embodiments are not limited thereto. In other embodiments, memory device 202 may include fewer or more blocks. Furthermore, the labels or names of blocks are for illustrative purposes only and do not limit the scope of the embodiments herein. One or more blocks may be combined together to perform the same or substantially similar functions in memory device 202.

[0100] Figure 5 This is an example diagram depicting the refresh of one or more memory banks of at least one memory array 206 according to some example embodiments disclosed herein. Figure 5 As depicted, the memory array 206 includes a plurality of memory banks 206a, wherein each memory bank 206a may include memory cells 302 located on memory row / word lines and bit lines. The memory banks 206a may be grouped into multiple groups (hereinafter referred to as memory bank groups). For example, as... Figure 5 As depicted, each memory bank group (memory bank group 0, memory bank group 1, etc.) may include two memory banks 206a (memory bank 0 and memory bank 1).

[0101] In some example embodiments, the refresh controller 208 of the memory device 202 may receive a refresh command from the host 204 to refresh a group of memory banks 206a. In this case, the refresh controller 208 uses associated supplementary reload circuitry 312 and row status circuitry 308 to selectively refresh memory rows 304a within each memory bank 206a of the group of memory banks 206a. In some example embodiments, the refresh controller 208 monitors the completion of refresh operations within each memory bank 206a and sends a refresh skip command to the host 204 when a refresh operation has been completed within all groups of memory banks 206a that have been indicated by the host 204 for refresh operations. The refresh skip command may indicate to the host 204 the completion of refresh operations for the indicated group of memory banks 206a.

[0102] Figure 6A and Figure 6B This is an example diagram depicting refresh operations of one or more memory chips 206 incorporated into host 204 according to some example embodiments disclosed herein. In some example embodiments, memory device 202 may include a plurality of memory chips 206 for storing data. In some example embodiments, such as Figure 6A and Figure 6B As depicted, memory device 202 may include seven memory chips 206. The memory chips 206 may also be connected to their associated refresh controller 208.

[0103] In some example embodiments, one or more refresh controllers 208 may receive refresh commands from host 204 to refresh a group of memory chips 206 (e.g., chipset 0, chipset 1, chipset 2, chipset 3, etc.). In this case, refresh controller 208 uses associated supplemental reload circuitry 312 and row status circuitry 308 to selectively refresh memory rows 304a within each memory chip 206 in the group of memory chips 206. In one embodiment, as... Figure 6A As described, the refresh controller 208 can send a refresh skip command to the host 204 when a refresh operation is completed within each memory chip 206 in the group of memory chips 206. The refresh skip command can indicate to the host 204 the completion of a refresh operation for a specific memory chip 206.

[0104] In some example embodiments, such as Figure 6B As depicted, the refresh controller 208 monitors the completion of refresh operations within each memory chip 206 and sends a refresh skip command to the host 204 when the refresh operation has been completed within the group of all memory chips 206 that have been indicated by the host 204 for refresh operations. The refresh skip command can indicate to the host 204 the completion of refresh operations for the indicated group of memory chips 206.

[0105] The example embodiments described herein also enable the refresh controller 208 to include multiple refresh coordination mechanisms for coordinating different types of refresh operations that can be performed on the memory device 202. These different types of refresh operations may be, but are not limited to, refresh operations performed on the memory banks 206a of the memory device 202, refresh operations performed on groups of memory banks, refresh operations performed on the memory chips 206 of the memory device 202, and / or refresh operations performed on any other component of the memory device 202. In some example embodiments, the refresh coordination mechanism may involve: tracking refresh operations being performed in each memory bank 206a and / or memory chip 206, etc.; receiving signals from each memory bank 206a or memory chip 206, etc., when a refresh operation in each memory bank 206a and / or memory chip 206, etc., is completed; and coordinating refresh operations when signals are received from all memory banks 206a and / or memory chips 206, etc. The refresh controller 208 may use AND gate functionality to coordinate refresh operations. For example, refresh controller 208 can coordinate refresh operations by performing AND gate operations on signals received from memory bank 206a and / or memory chip 206, etc.

[0106] Figure 7 This is an example flowchart depicting a method for controlling refresh operations of at least one memory device 202 according to some example embodiments disclosed herein. In step 1, the memory controller 214 of the host 204 issues a refresh command (e.g., a first refresh command (refresh command 1)) to the refresh controller 208 of the memory device 202 to perform a refresh operation on a group of memory rows 304a in at least one memory array 206. In the example herein, consider the memory controller 214 issuing a refresh command to perform a refresh operation on four memory rows 304a (e.g., row 0, row 1, row 2, and row 3).

[0107] In step 2, refresh controller 208 determines one or more memory rows 304a selected by refresh row selection circuit 210 from memory rows 0 to memory rows 4 for a refresh operation, and runs / executes a refresh operation on the selected one or more memory rows 304a. In some example embodiments, refresh row selection circuit 210 selects one or more memory rows 304a for a refresh operation by: (e.g., based on RCC 310 connected to a group of memory rows 304a) tracking the state of memory cells 302 included in the group of memory rows 304a, and determining the refresh requirement by checking whether the group of memory rows has already been refreshed in a previous refresh cycle via (e.g., based on supplementary unit 314 connected to the group of memory rows 304a).

[0108] In some example embodiments, the refresh row selection circuit 210 selects one or more memory rows 304a for a refresh operation based on the supplemental voltage of the supplemental unit 314 connected to each memory row 304a in the group of memory rows 304a and the comparison voltage stored in the RCC 310 of each memory row 304a in the group of memory rows 304a. In some example embodiments, consider that the refresh row selection circuit 210 selects row 1 for a refresh operation. In this case, the refresh controller 208 performs a refresh operation on row 1 and skips refresh operations on the other three memory rows (rows 0, 2, and 3).

[0109] In step 3, refresh controller 208 sends a refresh skip command to memory controller 214 when it completes the refresh operation on row 1 of memory cell 302.

[0110] In step 4.2, when a refresh skip command is received from refresh controller 208, memory controller 214 determines that memory device 202 is idle. Furthermore, the refresh skip command can be used as multiple refresh commands and can be executed together if the refresh operation will be performed earlier (i.e., in the case of an early refresh) or if the refresh operation will be postponed. In step 5.1, memory controller 214 waits for tREFI by tracking the issuance time of a second refresh command (refresh command 2) used to issue another refresh command.

[0111] In step 5.2, when it is determined that the memory device 202 is idle, the memory controller 214 issues other commands (e.g., read commands and / or write commands, etc.) to the relevant internal circuitry (not shown) of the memory device 202 to perform other operations (e.g., read operations and / or write operations, etc.). Therefore, the memory controller 214 can issue other commands to the memory device 202 without waiting for the tRFC period (step 4.1), which can further reduce the bandwidth and time required to perform the refresh operation. tRFC can be a time defined for completing a refresh operation on a group (e.g., four rows) of indicated memory rows.

[0112] In step 6, once tREFI has passed, the memory controller 214 issues another refresh command (e.g., a second refresh command (refresh command 2)) to refresh another group of memory rows 304a (e.g., rows 4 to 7).

[0113] In step 7, refresh controller 208 determines one or more memory rows 304a selected by refresh row selection circuit 210 from rows 4 to 7 for the refresh operation, and performs the refresh operation on the selected one or more memory rows 304a. In this example, consider that refresh row selection circuit 210 selects all rows (i.e., rows 4 to 7) for the refresh operation. In this case, refresh controller 208 performs the refresh operation on rows 4 to 7 without issuing a refresh skip command to memory controller 214 (step 8).

[0114] In step 9.1, since the memory controller 214 has not yet received a refresh skip command from the refresh controller 208, the memory controller 214 waits for the tRFC defined for completing the refresh operation on rows 4 to 7.

[0115] In step 10.1, once tRFC has passed, the memory controller 214 determines that the refresh operation is complete and waits for tREFI by tracking the issuance time of the second refresh command. In step 10.2, once tRFC has passed, the memory controller 214 can issue other commands to the relevant internal circuitry (not shown) of the memory device 202 to perform other operations.

[0116] In step 11, once tREFI has passed, the memory controller 214 issues another refresh command (e.g., a third refresh command (refresh command 3)) to the memory device 202 to refresh another group of memory rows 304a (e.g., rows 8 to 11).

[0117] In step 12, refresh controller 208 determines one or more memory rows selected by refresh row selection circuit 210 from rows 8 to 11 for the refresh operation, and performs the refresh operation on the selected one or more memory rows. In some example embodiments, consider refresh row selection circuit 210 selecting rows 8 and 10 for the refresh operation. In this case, refresh controller 208 performs the refresh operation only on rows 8 and 10, and skips the refresh operation on rows 9 and 11. In step 13, refresh controller 208 issues a refresh skip command to memory controller 214 upon completion of the refresh operation on rows 8 and 10. Furthermore, memory controller 214 can continuously issue refresh commands to refresh controller 208 to refresh the group of memory rows 304a by tracking tREFI until the refresh operation on all (e.g., all selected) memory rows 304a in at least one memory array 206 is completed.

[0118] Figure 8This is an example flowchart depicting a method 800 for controlling a refresh operation in a memory device 202 by performing a digital read of data bits from RCC 310 and supplementary unit 314, according to some example embodiments disclosed herein. In step 802, at memory device 202, refresh controller 208 receives a refresh command from memory controller 214 of host 204 via associated internal circuitry (not shown) of memory device 202 to perform a refresh operation on a group of memory rows 304a. In step 804, refresh controller 208 enables row address DEMUX 318 to activate the group of memory rows 304 indicated in the refresh command for the refresh operation.

[0119] In step 806, refresh controller 208 enables digital verification module 320 to select one or more memory rows 304a from the group of active memory rows 304a for refresh operations. To select one or more memory rows 304a, digital verification module 320 determines the state of each active memory row 304a by reading one or more data bits of one or more RCC 310 connected to each memory row 304a. Digital verification module 320 also determines the refresh requirement of each identified memory row 304a by reading one or more data bits of one or more supplementary units 314 connected to each memory row 304a. Based on the determined state and refresh requirement, digital verification module 320 selects one or more memory rows for refresh operations. Digital verification module 320 also enables the selected one or more memory rows 304a. Digital verification module 320 enables row address DEMUX 318 to deactivate one or more memory rows 304a that were not selected for refresh operations.

[0120] In step 808, refresh controller 208 enables refresh circuit 212 to perform refresh operations on one or more selected rows of memory cells 302, and skip refresh operations on rows that have not yet been selected for refresh operations. Refresh circuit 212 determines one or more memory rows 304a that have been / have not been selected for refresh operations based on the activation of one or more memory rows 304a, and performs refresh operations or skips refresh operations accordingly. The various actions in method 800 can be performed in the presented order, in different orders, or simultaneously. Furthermore, in some example embodiments, Figure 8 Some of the actions listed can be omitted.

[0121] Figure 9This is an example flowchart depicting a method for controlling a refresh operation in a memory device 202 by performing an analog read of the voltages of supplementary unit 314 and RCC 310, according to some example embodiments disclosed herein. In step 902, at memory device 202, refresh controller 208 receives a refresh command from memory controller 214 of host 204 via associated internal circuitry (not shown) of memory device 202 to perform a refresh operation on a group of memory rows 304a. In step 904, refresh controller 208 enables row address DEMUX 318 to activate the group of memory rows 304a that has already been indicated in the refresh command for a refresh operation.

[0122] In step 906, the refresh controller 208 enables the simulation verification module 402 to select one or more memory rows 304a from the group of active memory rows 304a for the refresh operation. To select one or more memory rows 304a, the refresh controller 208 may determine the initialization / storage comparison voltage of one or more RCC 310 connected to each memory row 304a in the group of active memory rows 304a, and select one of the reference / comparison voltages. In step 908, the simulation verification module 402 compares the supplementary voltage of one or more supplementary cells 314 connected to each memory row 304a in the group of active memory rows 304a with the selected reference voltage. In step 910, the simulation verification module 402 checks whether the voltage of one or more supplementary cells connected to each memory row 304a in the group of memory rows 304a is less than the selected reference / comparison voltage.

[0123] In step 912, if the voltage of one or more supplementary units 314 connected to one or more memory rows 304a is less than the selected reference / compare voltage, the simulation verification module 402 activates one or more memory rows 304a in the group of memory rows 304a. The refresh controller 208 enables the refresh circuit 212 to perform a refresh operation on the activated one or more memory rows 304a. The refresh controller 208 also enables the refresh circuit 212 to skip refresh operations on invalid (inactive) one or more memory rows 304a.

[0124] In step 914, the refresh controller 208 increments the refresh counter when performing a refresh operation and / or skipping a refresh operation. The refresh counter can be used to track the number of memory rows 304a for which refresh operations have been performed / skipped. In step 916, the refresh controller 208 checks whether refresh operations have been performed / skipped for all groups of active memory rows 304a.

[0125] In step 918, if the refresh operation has not yet been performed / skipped on all groups of memory rows 304a (already indicated in the refresh command as to be refreshed), steps 904 to 918 can be repeated. In step 920, if the refresh operation has been performed / skipped on all groups of rows of memory cells 302, the refresh controller 208 issues a refresh skip command to the memory controller 214 of the host 204 as confirmation of the completion of the refresh operation.

[0126] Figure 10 This is an example diagram depicting the initialization of data bits / voltages connected to one or more RCC 310s of each memory row 304a according to some example embodiments disclosed herein. The example embodiments herein enable host 204 to pre-initialize and / or store data bits / voltages connected to one or more RCC 310s of each memory row 304a using cell retention criteria. Cell retention criteria may be maintained / set in memory device 202 during manufacturing. Cell retention criteria may include information such as, but not limited to, retention analysis mechanisms suitable for identifying weak memory cells 302, the number of rounds of testing required to identify weak memory cells 302, retention time tests for determining whether each memory row 304a can be refreshed at a normal rate, etc. Once memory device 202 is initialized / started, the BIOS (not shown) of host 204 accesses the cell retention criteria maintained in memory device 202. Thereafter, host 204 performs tests on memory device 202 using the accessed cell retention criteria. In one example embodiment, the Converged Pattern Generator Checker (CPGC) module and the MBIST module can be used to improve the speed of testing the memory device 202. During testing, the host initializes one or more RCCs 310 connected to each memory row 304a when determining whether the memory cells 302 included in the row have passed the access cell retention criteria.

[0127] In one example embodiment, the host 204 / digital authentication module 320 can reinitialize one or more RCC 310s in the event of an ECC error. In one embodiment, the host 204 can reinitialize the RCC 310s by performing a scrubbing method at regular time intervals or by performing a scrubbing method once the memory device 202 exceeds a specific temperature threshold.

[0128] Figure 11This is an example sequence diagram depicting a method for performing a self-refresh operation according to some example embodiments disclosed herein. The embodiments herein enable the memory controller 214 of host 204 to issue a self-refresh command to memory device 202 to perform a refresh operation when memory device 202 is in self-refresh mode. Self-refresh mode is a low-power mode in which memory device 202 internally maintains the refresh of memory line 304a. In one example embodiment, in self-refresh mode, refresh controller 208 receives a self-refresh enter command from memory controller 214 of host 204 and internally recursively performs at least one action until a self-refresh exit command is received from memory controller 214. The at least one action involves performing a refresh operation on a selected memory line 304a by continuously incrementing a counter, and restarting the refresh operation on the selected memory line 304a once the refresh operation on the selected memory line 304a has been completed.

[0129] In step 1, when the memory device 202 is in self-refresh mode, the memory controller 214 of the host 204 issues a deselect command to the memory device 202 to disable all input signals except for the clock signal and the RESET_n signal. The deselect command can be used to initiate a self-refresh operation in the memory device 202.

[0130] In step 2.1, the memory controller 214 sends a self-refresh enter command to the refresh controller 208 of the memory device 202 on the rising edge of the clock signal CKE. In step 2.2, the memory controller 214 waits for tCKESR. tCKESR can be the minimum amount of time during which the clock signal CKE must be low for the period from self-refresh enter to self-refresh exit (i.e., the time period during which the memory device 202 is in self-refresh mode). In step 3, the refresh controller 208 internally performs refresh operations on one or more memory rows 304a that have been selected for refresh operations. In step 4, the refresh controller 208 increments the refresh counter and internally performs multiple refresh operations.

[0131] In step 5, the memory controller 214 sends a self-refresh exit command to the refresh controller 208 to stop the refresh operation. In step 5.1, the memory controller 214 waits for tXS after sending the self-refresh exit command to the refresh controller 208. In step 6, the refresh controller 208 completes the refresh operation that has been started within tXS. The memory device 202 exits the self-refresh mode when it receives the self-refresh exit command from the memory controller 214. When the memory device 202 exits the self-refresh mode, the Vref DQ generator circuit (the built-in circuit of the memory device 202) can be powered on and can be stable during the tXS period.

[0132] In step 7, the memory controller 214 issues other commands to the memory device 202 to perform other operations (e.g., read operations and write operations).

[0133] Figure 12 These are example diagrams depicting a conventional self-refresh operation according to some example embodiments disclosed herein, and a self-refresh operation performed using RCC310 and supplementary unit 314. In one example embodiment, Figure 12 The document describes conventional self-refresh operations and partial array self-refresh operations. However, the granularity of the refresh cannot be guaranteed in such refresh operations. Instead, the embodiments described herein use RCC 310 and supplementary unit 314 to achieve / ensure / improve the granularity of the refresh operation. The granularity level of row operations can be row-by-row. However, the memory rows 304a can be further divided into different levels. In one embodiment, because large row sizes introduce parasitic capacitance (which may be detrimental to reading or writing data), the memory rows 304a can be internally divided into groups comprising different numbers of rows (e.g., 4 rows, 8 rows, or 16 rows), which can further add more granularity. The embodiments described herein also enable supplementary unit 314 to determine refresh operation requirements.

[0134] The embodiments described here also allocate / restore data to memory device 202 without any optimization or computation.

[0135] The embodiments described here control the refresh operation of the memory device by integrating one or more row status units (RCCs) and one or more supplementary units into each memory row.

[0136] The embodiments described herein select one or more memory rows for a refresh operation by performing at least one of digital and analog reads of one or more RCCs and one or more supplementary units, and perform at least one refresh operation on the selected one or more memory rows. Using one or more RCCs and supplementary units to perform the refresh operation reduces the power consumption, bandwidth, and time required for the refresh operation, which further enhances the performance of the memory device.

[0137] The embodiments described here use one or more supplementary units to allow temperature-dependent power enhancement for refresh operations.

[0138] The embodiments disclosed herein can be implemented by at least one software program that runs on at least one hardware device and performs network management functions to control the elements. Figures 2 to 6B The elements shown may be at least one of a hardware device or a combination of a hardware device and a software module.

[0139] The embodiments disclosed herein describe methods and systems for controlling refresh operations of memory devices. Therefore, it should be understood that when the program runs on a server, mobile device, or any suitable programmable device, the scope of protection is extended to such programs, and in addition to computer-readable storage devices containing messages, such computer-readable storage devices include program code means for implementing one or more steps of the method. In preferred embodiments, the method is implemented by or with a software program written in, for example, a Very High Speed ​​Integrated Circuit Hardware Description Language (VHDL), another programming language, or implemented by one or more VHDL or software modules executed on at least one hardware device. The hardware device can be any kind of portable device that can be programmed. The device may also include a device that is, for example, a hardware device (e.g., an ASIC) or a combination of hardware and software devices (e.g., an ASIC and an FPGA in which software modules are arranged, or at least one microprocessor and at least one memory). The method embodiments described herein can be implemented partly in hardware and partly in software. Optionally, the invention can be implemented on different hardware devices, for example, using multiple CPUs.

[0140] The foregoing description of specific embodiments will fully reveal the general nature of the embodiments herein, enabling others to readily modify such specific embodiments and / or adapt them to various applications by applying existing knowledge without departing from the general concepts. Therefore, such adaptations and modifications should and are intended to be understood within the meaning and scope of equivalents of the disclosed embodiments. It will be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes. Thus, although embodiments herein have been described in terms of embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modifications within the spirit and scope of the embodiments described herein.

Claims

1. A method for controlling refresh operations of a memory device, the method comprising: The refresh controller receives from the host at least one refresh command for a plurality of memory rows in the memory device, wherein each of the plurality of memory rows includes a plurality of memory cells; The refresh row selection circuit selects at least one memory row from the plurality of memory rows by reading at least one row status unit and at least one supplementary unit, each of the at least one row status unit and each of the at least one supplementary unit being associated with a corresponding memory row among the plurality of memory rows; and The refresh controller uses the refresh circuitry to perform a refresh operation on at least one selected memory line. Each of the at least one row status unit is used to indicate the status of the corresponding memory row, and the status of the memory row indicates the time rate and / or time level at which memory cells on the corresponding memory row lose data. Each of the at least one supplementary unit is used to indicate the refresh requirement of the associated memory row.

2. The method according to claim 1, wherein, The step of selecting at least one memory row includes at least one of the following: Perform digital readings of the at least one row status unit and the at least one supplementary unit; and Perform a simulated read of the at least one row status unit and the at least one supplementary unit.

3. A method for controlling refresh operations of a memory device, the method comprising: The refresh controller receives from the host at least one refresh command for multiple memory lines in the memory device, wherein multiple memory cells are located on each memory line; The refresh row selection circuit selects at least one memory row from the plurality of memory rows based on the refresh rules of the plurality of memory cells and at least one state. The refresh rules and at least one state are determined by reading at least one supplementary unit and at least one row state unit, each of the at least one row state unit and each of the at least one supplementary unit being associated with a corresponding memory row in the plurality of memory rows. The refresh controller uses the refresh circuitry to perform a refresh operation on at least one selected memory row. The refresh controller skips refresh operations on at least one unselected memory line among the plurality of memory lines; and Upon completion of a refresh operation on at least one selected memory row, the refresh controller sends a refresh skip instruction to the host. Each of the at least one row status unit is used to indicate the status of the corresponding memory row, and the status of the memory row indicates the time rate and / or time level at which memory cells on the corresponding memory row lose data. Each of the at least one supplementary unit is used to indicate the refresh requirement of the associated memory row.

4. A memory device, comprising: At least one memory array includes a plurality of memory cells, wherein the plurality of memory cells are arranged on each of a plurality of memory rows; A refresh row selection circuit includes at least one row status unit and at least one supplementary unit, each of the at least one row status unit and each of the at least one supplementary unit being connected to a corresponding memory row among the plurality of memory rows; and The refresh controller is integrated with the refresh row selection circuit; and Refresh circuit, The refresh controller is configured as follows: Receive at least one refresh command from the host for the plurality of memory rows in the memory device; Enable the refresh row selection circuitry to select at least one memory row from the plurality of memory rows by reading at least one row status unit and at least one supplementary unit associated with the memory row from the plurality of memory rows; and A refresh circuit is used to perform a refresh operation on at least one selected memory row. Each of the at least one row status unit is used to indicate the status of the connected memory row, and the status of the memory row indicates the time rate and / or time level at which memory cells on the corresponding memory row lose data. Each of the at least one supplementary unit is used to indicate the refresh requirements of the associated memory rows.

5. The memory device according to claim 4, wherein, The memory device includes a volatile semiconductor memory device.

6. The memory device according to claim 4, wherein, The at least one row state unit is at least one of a volatile memory unit and a non-volatile memory unit, and the at least one supplementary unit is a volatile memory unit.

7. The memory device according to any one of claims 4 to 6, wherein, The refresh row selection circuit includes at least one of the following: The digital verification module is configured to perform digital readings of the at least one row status unit and the at least one supplementary unit; as well as The simulation verification module is configured to perform a simulated read of the at least one row status unit and the at least one supplementary unit.

8. The memory device according to claim 7, wherein, The digital verification module is also configured as follows: At least one data bit of the at least one row status unit is read to classify each memory row into at least one state, wherein the at least one state includes at least one good state and at least one bad state, and the at least one bad state indicates that the memory row has poor refresh performance compared to the at least one good state; Read at least one data bit of the at least one supplementary unit to determine whether a refresh operation was performed on each memory row in at least one previous refresh cycle; and If the at least one memory row is classified as at least one bad state, and if no refresh operation was performed on the at least one memory row in the at least one previous refresh cycle, then the at least one memory row is selected from the plurality of memory rows for the refresh operation.

9. The memory device according to claim 8, wherein, The host computer integrated into the memory device is configured to initialize the at least one data bit of the at least one row status unit by: Access to cell retention criteria held in the memory device during the boot process of the memory device, wherein the cell retention criteria include information on at least one of (a) a cell retention analysis mechanism associated with identifying bad memory cells in each memory row, (b) the number of tests required to identify bad memory cells and (c) a retention time test for determining whether each memory row is refreshed at a normal rate; Use cell retention criteria to initiate testing of memory devices; and The at least one data bit of the at least one row state unit is initialized based on whether the access cell retention criterion is met during the test.

10. The memory device according to claim 9, wherein, At least one of the host and the digital verification module is also configured to reinitialize the at least one data bit of the at least one row status unit by at least one of the following operations: At least one error correction code error was detected in the at least one row status unit; Perform the scrubbing method at regular time intervals; and The scrubbing method is executed when the temperature of the memory device exceeds the temperature threshold.

11. The memory device according to claim 8, wherein, The digital verification module is also configured to initialize at least one data bit of the at least one supplementary unit based on whether a refresh operation is performed on the corresponding memory row in the current refresh cycle.

12. The memory device according to claim 11, wherein, The digital verification module is also configured to refresh the supplementary units connected to the at least one memory row when refreshing the at least one memory row.

13. The memory device according to claim 7, wherein, The simulation verification module is also configured as follows: Read at least one comparison voltage stored in the at least one row state unit; Based on at least one comparison voltage read, select at least one reference voltage from a plurality of reference power supplies held by the voltage generation circuit; Read the voltage of the at least one supplementary unit; A comparator is used to compare the voltage of the at least one supplementary unit read with at least one selected reference voltage; as well as If the voltage of the at least one supplementary unit read is less than the selected at least one reference voltage, then the at least one memory row is selected from the plurality of memory rows.

14. The memory device according to claim 13, wherein, The at least one row state unit is configured to store a comparison voltage based on whether the at least one row state unit meets a cell retention criterion during testing of the memory device.

15. The memory device according to claim 13, wherein, The at least one row state unit is classified into at least one group for storing the at least one comparison voltage.

16. The memory device according to any one of claims 4 to 6, in, The refresh line selection circuit is also configured as follows: Enable the refresh row selection circuit to activate at least one selected memory row among the plurality of memory rows, and The refresh circuit is also configured as follows: A refresh operation is performed on at least one active memory row by restoring the data bits of multiple memory cells on at least one active memory row and rewriting the restored data bits into multiple memory cells on at least one active memory row.

17. The memory device according to claim 16, wherein, The refresh controller is also configured as follows: This enables the refresh circuit to skip refresh operations on at least one memory row that was not selected for a refresh operation among the plurality of memory rows. as well as Upon completion of a refresh operation on at least one selected memory row, a refresh skip instruction is sent to the host.

18. The memory device according to claim 17, wherein, The refresh controller is also configured as follows: Maintain a refresh counter to track refresh operations performed on at least one selected memory line and refresh operations skipped on at least one memory line not selected for refresh operations; The refresh counter is updated when the refresh operation on at least one selected memory row is completed and when the refresh operation on at least one memory row not selected for the refresh operation is skipped. as well as Use an updated refresh counter to determine the completion of a refresh operation performed on at least one selected memory line.

19. The memory device according to any one of claims 4 to 6, wherein, The refresh controller is also configured as follows: A refresh coordination mechanism is used to perform a refresh operation on at least one selected memory row of at least one of a plurality of memory banks, a plurality of memory bank groups, and a plurality of memory chips in at least one memory array in a memory device.

20. The memory device according to any one of claims 4 to 6, wherein, The refresh controller is also configured as follows: In response to the memory device being in self-refresh mode, at least one self-refresh enter command for the plurality of memory rows is received from the host; Multiple refresh operations are performed internally and recursively by selecting at least one memory row to be refreshed from the plurality of memory rows. as well as Upon receiving a self-refresh exit command from the host, the multiple refresh operations are completed.

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