First-in first-out memory and storage device

Abstract

The application relates to a first-in first-out memory and a storage device, the first-in first-out memory comprising: storage units, the outputs of a plurality of the storage units being connected to the same node; the storage unit comprising a storage subunit, a selector and a driver, the input of the selector being connected to the outputs of a plurality of the storage subunits, the input of the driver being connected to the output of the selector, the storage subunit receiving storage data under the driving of a first pointer signal, and the driver outputting the storage data under the driving of a second pointer signal. In the application, the length of the data line to which the outputs of a plurality of the storage units are connected is shortened, the data transmission delay of the first-in first-out memory is reduced while the data transmission capacity of the first-in first-out memory is ensured, and thus the data transmission efficiency of the first-in first-out memory is effectively improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to a first-in-first-out memory and storage device. Background Technology

[0002] Register file structure is a commonly used data structure in computer architecture, primarily used for data transfer between two different architectures. Data transfer techniques using register file structure include First-In-First-Out (FIFO) register queue structures. In a FIFO register queue, data can be entered and exited simultaneously during data transfer.

[0003] In the circuit design of storage devices, since data write operations generally have a long latency, FIFO queues are typically used to store the addresses of write operations to improve the efficiency of writing data in storage devices. As the data storage capacity and performance of storage devices continue to increase, the requirements for data read and write speeds are becoming increasingly stringent. However, the larger the number of bits of data transmitted using the FIFO queue in a storage device, the longer the latency of data write operations, thus affecting data transmission efficiency and reducing the efficiency of data writing in the storage device. How to further reduce the latency of output data in the FIFO queue has become one of the key issues that urgently need to be addressed to improve data transmission efficiency and the data writing efficiency of storage devices. Summary of the Invention

[0004] Therefore, it is necessary to provide a first-in-first-out memory and storage device that can improve data transmission efficiency in response to the technical problems mentioned above.

[0005] To achieve the above and other objectives, a first aspect of this application provides a first-in-first-out (FIFO) memory, comprising:

[0006] The outputs of multiple storage units are all connected to the same node;

[0007] The storage unit includes a storage sub-unit, a selector, and a driver. The input of the selector is connected to the output of multiple storage sub-units, and the input of the driver is connected to the output of the selector. The storage sub-unit receives stored data under the drive of a first pointer signal, and the driver outputs the stored data under the drive of a second pointer signal.

[0008] In the FIFO memory of the above embodiments, by setting the input of a selector to be connected to the output of multiple storage sub-units and setting the input of a driver to be connected to the output of the selector, the storage sub-units receive stored data under the drive of a first pointer signal, and the driver outputs the stored data under the drive of a second pointer signal. This shortens the length of the data lines connected to the outputs of multiple storage units, thereby reducing the data transmission delay of the FIFO memory while ensuring its data transmission capability, and thus effectively improving the data transmission efficiency of the FIFO memory.

[0009] In one embodiment, the data input terminals of the plurality of storage sub-units are all connected to the same data signal line, which facilitates inputting data to the plurality of storage sub-units through a single data signal line, thereby simplifying the circuit structure and improving the efficiency of data transmission.

[0010] In one embodiment, the control terminals of the selectors are all connected to the same selection clock line, which facilitates inputting control signals to the control terminals of different selectors through a single selection clock line, thereby simplifying the circuit structure and improving the efficiency of signal transmission.

[0011] In one embodiment, the first pointer signal is generated by a first counter circuit, and the second pointer signal is generated by a second counter circuit. The first counter circuit and the second counter circuit have the same driving clock frequency so as to set the input data and output data of the first-in-first-out memory to maintain a consistent transmission rate, so as to realize the simultaneous input and output of data.

[0012] In one embodiment, the first counter circuit and the second counter circuit have the same counting period value, which facilitates setting the number of bits of the bytes transmitted for the input data and output data of the first-in-first-out memory to be consistent, so that the data output by the first-in-first-out memory is consistent with the input data, thereby ensuring the accuracy of data transmission.

[0013] In one embodiment, the first counter circuit includes:

[0014] A first counter is used to count the clock cycles of a reference clock signal, and the counting cycle value of the first counter is equal to the total number of the storage sub-units.

[0015] A first pointer signal generator is connected to the first counter and is used to generate a first pointer signal.

[0016] In the FIFO memory of the above embodiments, by setting a first counter to count the clock cycles of the reference clock signal, and setting the counting cycle value of the first counter to be equal to the total number of the storage sub-units, a first pointer signal generator can sequentially generate a first pointer signal based on the count value of the first counter, thereby sequentially driving different storage sub-units to receive stored data and realizing serial data input. By setting the first counter to count the clock cycles of the reference clock signal, it is convenient to subsequently configure the FIFO memory to drive data output with the same reference, so that the transmission rate of input data and output data is consistent.

[0017] In one embodiment, the first pointer signal includes a number of sub-input clock signals equal to the number of the counting period; wherein each sub-input clock signal is an asynchronous clock signal, so that each sub-input clock signal can sequentially drive different storage sub-units to receive stored data, thereby realizing serial input of data.

[0018] In one embodiment, the second counter circuit includes:

[0019] The second counter is used to count the clock cycles of the reference clock signal, and the counting cycle value of the second counter is equal to the total number of the storage sub-units;

[0020] A second pointer signal generator, connected to the second counter, is used to generate a second pointer signal.

[0021] In the FIFO memory of the above embodiments, by setting a second counter to count the clock cycles of the reference clock signal, and setting the counting cycle value of the second counter to be equal to the total number of the storage sub-cells, the second pointer signal generator can sequentially generate second pointer signals based on the count value of the second counter, thereby sequentially driving different drivers to output data and realizing serial data output. By setting the second counter to count the clock cycles of the reference clock signal, it is convenient to set the FIFO memory to drive data output with the same reference clock signal as the first pointer signal, so that the transmission rate of output data is consistent with that of input data.

[0022] In one embodiment, the second pointer signal includes an output clock trigger signal of equal quantity to the count cycle value, the output clock trigger signal being used to drive a driver to output stored data.

[0023] In one embodiment, the first-in-first-out memory further includes node storage units whose inputs are connected to the same node, enabling the node storage units to store or cache data output by the driver.

[0024] In one embodiment, the storage sub-unit and / or the node storage unit includes one or more of triggers, latches, and registers.

[0025] A second aspect of this application provides a storage device including a first-in-first-out memory as described in any embodiment of this application, for storing addresses for write operations.

[0026] In the storage device described in the above embodiments, by setting the input of a selector to be connected to the output of multiple storage sub-units and setting the input of a driver to be connected to the output of the selector, the storage sub-units receive stored data under the drive of a first pointer signal, and the driver outputs the stored data under the drive of a second pointer signal. This reduces the length of the data lines connected to the outputs of multiple storage units, thereby ensuring the data transmission capability of the first-in-first-out memory in the storage device while reducing the data transmission latency of the first-in-first-out memory in the storage device, thus effectively improving the data transmission efficiency of the storage device. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a structural block diagram of a first-in-first-out memory provided in the first embodiment of this application.

[0029] Figure 2 This is a structural block diagram of a first-in-first-out (FIFO) memory provided in the second embodiment of this application.

[0030] Figure 3 This is a structural block diagram of a first-in-first-out (FIFO) memory provided in the third embodiment of this application.

[0031] Figure 4 This is a structural block diagram of a first-in-first-out (FIFO) memory provided in the fourth embodiment of this application.

[0032] Figure 5 This is a structural block diagram of a first counter circuit in a first-in-first-out memory provided in the fifth embodiment of this application.

[0033] Figure 6 This is a block diagram of a second counter circuit in a first-in-first-out memory provided in the sixth embodiment of this application.

[0034] Figure 7This is a structural block diagram of a first-in-first-out (FIFO) memory provided in the seventh embodiment of this application.

[0035] Figure 8 This is a circuit diagram of a first-in-first-out (FIFO) memory provided in the eighth embodiment of this application.

[0036] Figure 9 This is a circuit diagram of a first-in-first-out (FIFO) memory provided in the ninth embodiment of this application.

[0037] Figure 10 This is a circuit schematic diagram of a first-in-first-out (FIFO) memory.

[0038] Figure 11 This is a timing diagram of the first pointer signal of a first-in-first-out memory provided in the tenth embodiment of this application.

[0039] Figure 12 This is a timing diagram of the second pointer signal of a first-in-first-out memory provided in the eleventh embodiment of this application.

[0040] Explanation of reference numerals in the attached figures:

[0041] 100, Storage unit; 10, Storage sub-unit; 20, Selector; 30, Driver; 40, First counter circuit; 41, First counter; 42, First pointer signal generator; 50, Second counter circuit; 51, Second counter; 52, Second pointer signal generator; 60, Node storage unit; 61, Latch; 101, First storage unit; 102, Second storage unit. Detailed Implementation

[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0044] Additionally, certain terms used throughout the specification and following claims refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to elements. This document does not intend to distinguish between elements with different names but the same function. In the following description and embodiments, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". Similarly, the term "connection" is intended to express either indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection may be accomplished through a direct electrical connection or through an indirect electrical connection with other devices and connectors.

[0045] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0046] Please refer to Figure 1 In one embodiment of this application, a first-in-first-out (FIFO) memory is provided, which includes multiple storage units 100, and the outputs of each storage unit 100 are connected to the same node O. Each storage unit 100 includes a storage sub-unit 10, a selector 20, and a driver 30. The input of the selector 20 is connected to the outputs of the multiple storage sub-units 10, and the input of the driver 30 is connected to the output of the selector 20. The storage sub-unit 10 receives stored data Data under the drive of a first pointer signal Fifo_in, and the driver 30 outputs the stored data under the drive of a second pointer signal Fifo_out.

[0047] As an example, please continue to refer to Figure 1 The first-in-first-out (FIFO) memory comprises n storage units 100, and the outputs of each storage unit 100 are connected to the same node O. Each storage unit 100 comprises m storage sub-units 10, a selector 20, and a driver 30. The outputs of each storage sub-unit 10 in a storage unit 100 are connected to the inputs of the selector 20, and the inputs of the driver 30 are connected to the outputs of the selector 20. Here, m is an integer, greater than or equal to 1, and n is an integer, greater than or equal to 1. Each storage sub-unit 10 receives stored data Data under the first pointer signal Fifo_in, and each driver 30 outputs the stored data under the second pointer signal Fifo_out.

[0048] Specifically, in the FIFO memory of the above embodiment, by setting the input of selector 20 to be connected to the output of multiple storage sub-units 10, and setting the input of driver 30 to be connected to the output of selector 20, the storage sub-units 10 receive stored data Data under the first pointer signal Fifo_in, and the driver 30 outputs the stored data under the second pointer signal Fifo_out. This shortens the length of the data line Data_Lout to which the outputs of multiple storage units 100 are connected, thereby reducing the data transmission delay of the FIFO memory while ensuring its data transmission capability, thus effectively improving the data transmission efficiency of the FIFO memory.

[0049] Furthermore, in one embodiment of this application, please refer to Figure 2 The data input terminals of multiple storage sub-units 10 are all connected to the same data signal line Data_Lin, which facilitates the input of data Data to multiple storage sub-units 10 through the data signal line Data_Lin, thereby simplifying the circuit structure and improving the efficiency of data transmission.

[0050] Furthermore, in one embodiment of this application, please refer to Figure 3 The control terminals of selector 20 are all connected to the same selection clock line Out_pre, which makes it easy to input control signals to the control terminals of different selectors 20 through the selection clock line Out_pre, thereby simplifying the circuit structure and improving the efficiency of signal transmission.

[0051] Furthermore, in one embodiment of this application, please refer to Figure 4 The first pointer signal Fifo_in is generated by the first counter circuit 40, and the second pointer signal Fifo_out is generated by the second counter circuit 50. The first counter circuit 40 and the second counter circuit 50 have the same driving clock frequency so as to set the input data and output data of the first-in-first-out memory to maintain a consistent transmission rate, so as to realize the simultaneous input and output of data.

[0052] Furthermore, in one embodiment of this application, please continue to refer to... Figure 4 The first counter circuit 40 and the second counter circuit 50 have the same counting period value, which makes it easy to set the number of bits of the input data and output data transmitted by the first-in-first-out memory to be consistent, so that the data output by the first-in-first-out memory is consistent with the input data, thus ensuring the accuracy of data transmission.

[0053] Furthermore, in one embodiment of this application, please refer to Figure 5The first counter circuit 40 includes a first counter 41 and a first pointer signal generator 42. The first counter 41 is used to count the clock cycles of the reference clock signal, and the counting cycle value of the first counter 41 is equal to the total number of the storage sub-units. The first pointer signal generator 42 is connected to the first counter 41 and is used to generate the first pointer signal Fifo_in.

[0054] Specifically, in the FIFO memory of the above embodiment, by setting a first counter 41 to count the clock cycles of the reference clock signal, and setting the counting cycle value of the first counter 41 to be equal to the total number of the storage sub-units, the first pointer signal generator 42 can sequentially generate a first pointer signal Fifo_in based on the counting value of the first counter 41, thereby sequentially driving different storage sub-units to receive stored data and realizing serial data input. By setting the first counter to count the clock cycles of the reference clock signal, it is convenient to subsequently set the FIFO memory to drive data output with the same reference, so that the transmission rate of input data and output data is consistent.

[0055] Furthermore, in one embodiment of this application, the first pointer signal includes a number of sub-input clock signals equal to the number of the counting period; wherein each of the sub-input clock signals is an asynchronous clock signal, so that each sub-input clock signal can sequentially drive different storage sub-units to receive stored data, thereby realizing serial input of data.

[0056] Furthermore, in one embodiment of this application, please refer to Figure 6 The second counter circuit 50 includes a second counter 51 and a second pointer signal generator 52. The second counter 51 is used to count the clock cycles of the reference clock signal, and the counting cycle value of the second counter 51 is equal to the total number of the storage sub-units. The second pointer signal generator 52 is connected to the second counter 51 and is used to generate the second pointer signal Fifo_out.

[0057] Specifically, in the FIFO memory of the above embodiment, by setting a second counter 51 to count the clock cycles of the reference clock signal, and setting the counting cycle value of the second counter 51 to be equal to the total number of the storage sub-units, the second pointer signal generator 52 can sequentially generate the second pointer signal Fifo_out based on the counting value of the second counter 51, thereby sequentially driving different drivers to output data and realizing serial data output. By setting the second counter 51 to count the clock cycles of the reference clock signal, it is convenient to set the FIFO memory to drive data output with the same reference clock signal as the first pointer signal, so that the transmission rate of output data is consistent with that of input data.

[0058] Furthermore, in one embodiment of this application, the second pointer signal includes an output clock trigger signal in an amount equal to the count cycle value, the output clock trigger signal being used to drive a driver to output stored data.

[0059] Furthermore, in one embodiment of this application, please refer to Figure 7 The first-in-first-out memory also includes a node storage unit 60, the input of which is connected to the same node O, so that the node storage unit 60 can store or cache data output by the driver 30.

[0060] Furthermore, in one embodiment of this application, the storage sub-unit and / or the node storage unit includes one or more of triggers, latches, and registers.

[0061] As an example, in one embodiment of this application, please refer to Figure 8 The first-in-first-out (FIFO) memory includes four first storage units 101, and the outputs of each first storage unit 101 are all connected to the same node O. Each first storage unit 101 includes two storage sub-units 10, a selector 20, and a driver 30. The outputs of each storage sub-unit 10 in a first storage unit 101 are all connected to the inputs of the selector 20, and the inputs of the driver 30 are connected to the outputs of the selector 20. Each storage sub-unit 10 receives stored data Data_in_new under the first pointer signal Fifo_in, and each driver 30 outputs the stored data under the second pointer signal Fifo_out. The outputs of the driver 30 are all connected to the first data output signal line Data_out_new1.

[0062] Furthermore, in one embodiment of this application, please continue to refer to... Figure 8 The node storage unit includes a latch 61, the input of which is connected to node O. The latch 61 is used to store or cache data output by each driver 30.

[0063] As an example, in one embodiment of this application, please refer to Figure 9 ,and Figure 8 The difference in the embodiment shown is that the first-in-first-out memory includes not only four first storage units 101, but also a second storage unit 102. The second storage unit 102 includes one storage sub-unit 10 and a driver 30. The input of the driver 30 is connected to the output of the storage sub-unit 10. The driver 30 outputs stored data under the drive of the second pointer signal Fifo_out. The outputs of the driver 30 are all connected to the second data output signal line Data_out_new2.

[0064] Figure 10This is a schematic diagram of a FIFO register queue structure, where the outputs of each driver 30 are connected to the data output signal line Data_out. (Comparison) Figure 9 and Figure 10 It is evident that, when transmitting the same number of bytes, Figure 9 The length of the second data output signal line Data_out_new2 is significantly shorter than Figure 10 The length of the data output signal line Data_out in the input signal. Therefore, under the same input signal transmission rate and the same transmission byte length, Figure 9 The data transfer latency of the register device in the middle is significantly less than Figure 10 Data transmission delay in the FIFO register queue.

[0065] For example, please refer to Figure 9 , Figure 11 and Figure 12 The working principle of this application will be briefly described with reference to specific timing diagrams. The first counter 41 counts the clock cycles of the reference clock signal Fifo_in_clk, and the count cycle value of the first counter 41 is equal to the total number of storage sub-units 10, which is 9. The first pointer signal generator 42 is connected to the first counter 41 and is used to generate the first pointer signal Fifo_in. The first pointer signal Fifo_in includes a number of sub-input clock signals equal to the count cycle value, such as... Figure 11As shown, the first pointer signal Fifo_in includes Fifo_in <0> Fifo_in <1> Fifo_in <2> Fifo_in <3> Fifo_in <4> Fifo_in <5> Fifo_in <6> Fifo_in <7> and Fifo_in <8> There are a total of 9 asynchronous sub-input clock signals. The first pointer signal generator 42 generates the first sub-input clock signal Fifo_in when the count value of the first counter 41 is 0. <0> The first pointer signal generator 42 generates the second sub-input clock signal Fifo_in when the count value of the first counter 41 is 1. <1> The first pointer signal generator 42 generates the third sub-input clock signal Fifo_in when the count value of the first counter 41 is 2. <2> The first pointer signal generator 42 generates the fourth sub-input clock signal Fifo_in when the count value of the first counter 41 is 3. <3> The first pointer signal generator 42 generates the fifth sub-input clock signal Fifo_in when the count value of the first counter 41 is 4. <4> The first pointer signal generator 42 generates the sixth sub-input clock signal Fifo_in when the count value of the first counter 41 is 5. <5> The first pointer signal generator 42 generates the seventh sub-input clock signal Fifo_in when the count value of the first counter 41 is 6. <6> The first pointer signal generator 42 generates the eighth sub-input clock signal Fifo_in when the count value of the first counter 41 is 7. <7> The first pointer signal generator 42 generates the ninth sub-input clock signal Fifo_in when the count value of the first counter 41 is 8. <8> This allows each sub-input clock signal to sequentially drive different storage sub-units to receive and store data, thus achieving serial data input.The second counter 51 counts the clock cycles of the reference clock signal Fifo_out_clk, and the counting cycle value of the second counter 51 is equal to the total number of storage sub-units 10, which is 9. The second pointer signal generator 52 is connected to the second counter 51 and is used to generate the second pointer signal Fifo_out, which includes the first sub-output clock signal Fifo_out. <0> The second sub-output clock signal Fifo_out <1> The third sub-output clock signal Fifo_out <2> The fourth sub-output clock signal Fifo_out <3> and the eighth sub-output clock signal Fifo_out <8> Among them, the first sub-output clock signal Fifo_out <0> The second sub-output clock signal Fifo_out <1> The third sub-output clock signal Fifo_out <2> and the fourth sub-output clock signal Fifo_out <3> Each counting cycle of the second counter 51 includes two synchronous output clock trigger signals, and the eighth sub-output clock signal Fifo_out <8> One output clock trigger signal is included in one counting cycle of the second counter 51; that is, the second pointer signal Fifo_out includes 9 output clock trigger signals. Figure 12 The output clock trigger signal can be a rising edge waveform or a pulse waveform. During one counting cycle of the second counter 51, when the clock selection signal Out_pre input to the control terminal of the selector 20 is low, Figure 9 The middle driver 30 sequentially sends Fifo_in <0> Fifo_in <2> Fifo_in <4> and Fifo_in <6> The stored data is output to the drive input; during one counting cycle of the second counter 51, when the clock selection signal Out_pre input to the control terminal of the selector 20 is high, Figure 9 The middle driver 30 sequentially sends Fifo_in <1> Fifo_in <3> Fifo_in <5> Fifo_in <7> and Fifo_in <8> The stored data is driven to output, thus enabling asynchronous data output.

[0066] Furthermore, in one embodiment of this application, a storage device is provided, including a first-in-first-out (FIFO) memory as described in any embodiment of this application, for storing the address of a write operation. By setting the input of a selector connected to the output of multiple storage sub-cells, and setting the input of a driver connected to the output of the selector, the storage sub-cells receive stored data under the drive of a first pointer signal, and the driver outputs the stored data under the drive of a second pointer signal. This shortens the length of the data lines connected to the outputs of multiple storage cells, thereby reducing the data transmission latency of the FIFO memory while ensuring its data transmission capability, thus effectively improving the data transmission efficiency of the storage device.

[0067] For specific limitations on the storage device in the above embodiments, please refer to the limitations on the first-in-first-out memory mentioned above, which will not be repeated here.

[0068] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.

[0069] The storage devices provided in the above embodiments include, but are not limited to, DRAM, SDRAM, SRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, LPDDR4 SDRAM, DDR5 SDRAM, LPDDR5 SDRAM, GDDR5 SDRAM, GDDR6 SDRAM, PRAM, MRAM, and RRAM.

[0070] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A first-in-first-out (FIFO) memory, characterized in that, include: Multiple storage units, the outputs of which are all connected to the same node; The storage unit includes multiple storage sub-units, a selector, and a driver. The input of the selector is connected to the output of the multiple storage sub-units, and the input of the driver is connected to the output of the selector. The storage sub-units receive stored data under the drive of a first pointer signal, and the driver outputs the stored data under the drive of a second pointer signal. All the data input terminals of the storage sub-units are connected to the same data signal line, and all the control terminals of the selectors are connected to the same selection clock line.

2. The first-in-first-out memory according to claim 1, characterized in that, The first pointer signal is generated by the first counter circuit, and the second pointer signal is generated by the second counter circuit. The first counter circuit and the second counter circuit have the same driving clock frequency.

3. The first-in-first-out memory according to claim 2, characterized in that, The first counter circuit and the second counter circuit have the same counting period value.

4. The first-in-first-out memory according to claim 3, characterized in that, The first counter circuit includes: A first counter is used to count the clock cycles of a reference clock signal, and the counting cycle value of the first counter is equal to the total number of the storage sub-units. A first pointer signal generator is connected to the first counter and is used to generate a first pointer signal.

5. The first-in-first-out memory according to claim 4, characterized in that, The first pointer signal includes a number of sub-input clock signals equal to the number of the counting period values; Among them, each of the sub-input clock signals is an asynchronous clock signal.

6. The first-in-first-out memory according to claim 3, characterized in that, The second counter circuit includes: The second counter is used to count the clock cycles of the reference clock signal, and the counting cycle value of the second counter is equal to the total number of the storage sub-units; A second pointer signal generator, connected to the second counter, is used to generate a second pointer signal.

7. The first-in-first-out memory according to claim 6, characterized in that, The second pointer signal includes an output clock trigger signal whose quantity is equal to the count cycle value, and the output clock trigger signal is used to drive a driver to output stored data.

8. The first-in-first-out memory according to claim 1, characterized in that, Also includes: A node storage unit, wherein the input of the node storage unit is connected to the same node.

9. The first-in-first-out memory according to claim 8, characterized in that, The storage sub-unit and / or the node storage unit includes one or more of triggers, latches, and registers.

10. A storage device, characterized in that, include: The first-in-first-out memory as described in any one of claims 1-9 is used to store the address of a write operation.

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