Method and system for processing floating point numbers

Abstract

The present invention relates to methods and systems for processing floating point numbers. A method and system for processing a set of 'k' floating point numbers to perform addition and / or subtraction is disclosed. Each floating point number includes a mantissa (m i ) and an exponent (e i ). The method includes receiving the set of 'k' floating point numbers in a first format, each floating point number in the first format including a mantissa (m i ) having a bit length of 'b' bits. The method further includes generating a set of 'k' numbers (y i ) based on the mantissas of the 'k' floating point numbers, the numbers having a bit length of 'n' bits obtained by adding an extra most significant bit and an extra least significant bit to the bit length 'b' of the mantissas (m i ). The method includes identifying a maximum exponent (e i ) among the exponents (e max ), aligning the magnitudes of the numbers (y i ) based on the maximum exponent (e max ), and simultaneously processing the set of 'k' numbers.

Description

Technical Field

[0001] This application involves processing floating-point numbers. Background Technology

[0002] Most computing systems use number formats, typically binary or radix-2, for various calculations. These number formats include fixed-point or floating-point formats. Fixed-point formats can provide additional precision but are only used to represent a finite range of values. Therefore, most modern computing systems use floating-point formats to provide a trade-off between range and precision.

[0003] Floating-point numbers consist of a mantissa (m) of length 'b' bits, an exponent (e) of length 'a' bits, and an optional sign bit (s) to represent a binary number. In some widely used formats, the exponent is biased (i.e., offset) by a value (c) to represent numbers less than 1 and is used to encode outliers at its endpoints. For non-extreme values ​​e, the floating-point number x is said to be normalized, and the number x is represented as (-1). s 2 e-c (1+2 -b When e = 0, the floating-point number x is called a nonnormal number, and the number is represented as (-1). s 2 1-c 2 -b m. This includes the value 0 obtained by setting m = 0. Therefore, floating-point numbers can be used to precisely represent very small or very large numbers using scientific notation, binary, or other bases. Using floating-point numbers in arithmetic calculations provides varying degrees of precision, depending on the bit length or type of the floating-point format used.

[0004] The calculation of sums involving large arrays of real numbers frequently appears in solutions to various numerical problems. For example, such sums may appear as part of a dot product calculation. Therefore, it is advantageous to have dedicated hardware for performing summations in high-performance computing systems, graphics processing systems, neural network accelerators, and so on. Traditionally, different methods exist for achieving this, each with its own advantages and disadvantages.

[0005] One known method for performing addition on a set of floating-point numbers in a computing system is accumulation. This form of continuous summation uses a floating-point adder, adding each input number sequentially to the floating-point accumulator. Figure 1 shows an adder unit 100 using this principle. Adder unit 100 includes a multiplexer 102 and an adder 104. The floating-point array x1, x2...x... nThe floating-point numbers are provided as input to multiplexer 102. In each cycle, multiplexer 102 provides the floating-point numbers as the first input to adder 104. Adder 104 accumulates or adds each floating-point number to a second input. The output (sum) generated by adder 104 is fed back to adder 104 as the second input. The output of adder 104 is rounded in each step, which results in rounding errors in the output generated in each loop. Rounding errors are characteristic of floating-point computation.

[0006] Therefore, each floating-point number is added to the previously calculated output (summation) to generate a new or cumulative output. In other words, the summation is performed as a sequence of separate sums of two numbers. The final output (y) generated after adding all the floating-point numbers in the array is provided as the output of adder unit 100. Therefore, in the case of n input numbers, performing sequential summation will produce a processing power of 1 / (n-1). Furthermore, when adding very small numbers to very large values, rounding can lead to large offsetting errors.

[0007] By using multiple floating-point adders, an architecture that provides more processing power can be obtained. For example, using n-1 floating-point adders can pipeline the sum of n floating-point numbers with a processing power of 1. Furthermore, using a sequential chain of floating-point adders will provide a delay of (n-1) cycles for the accumulation.

[0008] Therefore, existing methods and architectures for handling floating-point numbers have shortcomings. Summary of the Invention

[0009] This summary is provided to introduce, in a simplified form, a series of concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0010] This paper discloses a method and system for processing a set of 'k' floating-point numbers to perform addition and / or subtraction. Each floating-point number includes a mantissa (m i ) and index (e i The method includes receiving the set of 'k' floating-point numbers in a first format. The method also includes generating a set of 'k' numbers (y) based on the mantissa of the 'k' floating-point numbers. i This method includes identifying the index e. i The largest exponent (e) in max ), based on the maximum exponent (e) max Align the number (y) i The value of the 'k' number is processed simultaneously.

[0011] According to the first aspect, a method is provided for processing a set of 'k' floating-point numbers to perform addition and / or subtraction, k≥3, using a hardware implementation, wherein each floating-point number includes a mantissa (m i ) and index (e i The method includes: receiving the group of 'k' floating-point numbers in a first format, each floating-point number in the first format including a mantissa of length 'b' bits (m i ); Generate a set of 'k' numbers (y) based on the mantissa of the 'k' floating-point number. i This number has the property of adding extra most significant bits and extra least significant bits to the mantissa (m). i The bit length of 'n' bits is obtained by using the bit length 'b' of 'n' bits, where 'n' bits include multiple value bits, and 'n' is a value of 'b'. The index e is a digit where x is an integer and x ≥ 1; i The largest exponent (e) in max Based on the maximum exponent (e) max Align the numbers (y) with the numbers (y) i The value of the digit; and simultaneously process the group of 'k' digits.

[0012] Optionally, this set of 'k' floating-point numbers includes unsigned floating-point numbers that explicitly include a leading bit.

[0013] Optionally, the group of 'k' floating-point numbers includes unsigned floating-point numbers that implicitly include a leading bit and x ≥ 2.

[0014] Optionally, the group of 'k' floating-point numbers includes signed floating-point numbers that explicitly include a leading bit and x ≥ 2.

[0015] Optionally, the group of 'k' floating-point numbers includes signed floating-point numbers that implicitly include a leading bit and x ≥ 3.

[0016] Optionally, x ≤ 3, and optionally, x ≤ b.

[0017] Optionally, adding additional most significant bits includes adding at least The most significant bit.

[0018] Optionally, adding additional least significant bits includes adding at least The least significant bit.

[0019] Optionally, if the received first format of the group of 'k' floating-point numbers implicitly includes a leading bit, then adding an additional most significant bit includes adding a leading bit.

[0020] Optionally, the method includes forming the number (y) by adding a leading bit before the mantissa mi of the floating-point number. i The value of ).

[0021] Optionally, the method further includes: processing the 'k' digit (y i The function calculates the output value; renormalizes the output value; and rounds the output value to represent it as a floating-point number.

[0022] Optionally, the number (y) i The magnitude alignment is based on the maximum exponent (e) max The steps include: For each floating-point number (i): Calculate the maximum exponent (e). max ) and index (e i The difference between (e) d ); and based on the calculated difference (e d ) will correspond to the number (y) i The magnitude of the displacement is shifted to the LSB side.

[0023] Optionally, in addition to shifting the magnitude bits of the number, the method also includes truncating the bits shifted beyond the bit length of the number.

[0024] Optionally, the method further includes, if the set of 'k' floating-point numbers includes signed floating-point numbers, then based on the sign bit (s) of each corresponding number... i The complement of a number is used to determine its value.

[0025] Optionally, the maximum exponent is identified by determining the maximum value among the exponents ei in the set of 'k' floating-point numbers.

[0026] Optionally, processing the 'k' number involves calculating the sum by performing an 'n'-bit carry-back addition.

[0027] Optionally, processing the group of 'k' floating-point numbers produces the same output value, regardless of the order in which the group of 'k' floating-point numbers are provided as input.

[0028] According to the second aspect, a hardware implementation is provided for processing a set of k floating-point numbers to perform addition and / or subtraction, where k ≥ 3, and each floating-point number includes a mantissa m. i and index (e i The hardware implementation includes a format conversion unit, a maximum exponent detection unit, an alignment unit, and a processing unit. The format conversion unit is configured to receive a group of 'k' floating-point numbers in a first format, each floating-point number in the first format including a mantissa (m) of length 'b' bits. i ); and the mantissa (m) of the group of 'k' floating-point numbers i Convert ) into a set of 'k' numbers (y i ), number (y) i ) has the ability to add extra most significant bits and extra least significant bits to the mantissa (m iThe bit length 'b' is used to generate an 'n' bit length, where 'n' bits include value bits, and where 'n' is... The maximum exponent detection unit is configured to identify the exponent e, where x is an integer and x ≥ 1. i The largest exponent (e) in max The alignment unit is configured based on the maximum exponent (e). max Align the value bits of the digits. The processing unit is configured to process this group of 'k' digits simultaneously to generate an output value.

[0029] Optionally, the format conversion unit receives the set of 'k' floating-point numbers in a first format, including unsigned floating-point numbers that explicitly include a leading bit.

[0030] Optionally, the format conversion unit receives the set of 'k' floating-point numbers in a first format, including unsigned floating-point numbers that implicitly include a leading bit and x ≥ 2.

[0031] Optionally, the format conversion unit receives the set of 'k' floating-point numbers in a first format, which explicitly includes a leading bit and x ≥ 2.

[0032] Optionally, the format conversion unit receives the set of 'k' floating-point numbers in a first format including signed floating-point numbers, wherein a leading bit is implicitly included and x ≥ 3.

[0033] Optionally, it also includes a renormalization unit configured to: renormalize the output value; and round the output value to represent the output value as a floating-point number.

[0034] Optionally, if the received 'k' floating-point number in the first format implicitly includes a leading bit, the format conversion unit converts the mantissa (m) by adding the leading bit. i ).

[0035] Optionally, the format conversion unit generates a number by converting each mantissa (m) i Add a leading bit before it.

[0036] Optionally, the alignment unit aligns the magnitude bits of the digits based on the maximum exponent (e). max The alignment unit includes: a plurality of subtraction units, wherein each subtraction unit is configured to calculate the maximum exponent (e) of each floating-point number (i). max ) and index (e i The difference between (e) d ); and multiple shifter units, each shifter unit being configured based on the calculated difference (e d The corresponding numerical value is shifted to the LSB side.

[0037] Optionally, the alignment unit may further truncate bits of the number shifted to a number beyond its bit length.

[0038] Optionally, the alignment unit further includes a plurality of two's complement units, which are configured to, if the set of 'k' floating-point numbers includes signed floating-point numbers, base the alignment on the sign bit (s) of the corresponding number. i To determine the complement of each number's value, we use the two's complement of the two's complement.

[0039] Optionally, the format conversion unit converts the format by sending the format to the mantissa (m) i Add at least The additional most significant bit is used to convert the mantissa (mi) of the 'k' floating-point number into the 'k' number.

[0040] Optionally, the format conversion unit converts the format by sending the format to the mantissa (m) i Add at least The number of additional least significant bits in the mantissa (m) of this group of 'k' floating-point numbers. i Convert ) to the 'k' number in this group.

[0041] Optionally, multiple shifter units perform the shifting of magnitude bits in parallel, thereby greatly reducing latency.

[0042] Optionally, the multiple shifter units and multiple complement units may be implemented sequentially in any order.

[0043] Optionally, the processing unit is a carry-store adder circuit capable of adding 'k' numbers to generate a sum value as the output value.

[0044] According to a third aspect, there is provided computer-readable code configured to cause the method of the first aspect to be executed when the code is run.

[0045] According to the fourth aspect, a computer-readable storage medium is provided, on which computer-readable code of the third aspect is encoded.

[0046] The hardware implementation of the adder according to the first aspect described above can be embodied in the hardware of an integrated circuit. A method for manufacturing an adder at an integrated circuit manufacturing system is provided. An integrated circuit definition dataset may be provided, which, when processed in the integrated circuit manufacturing system, configures the system to manufacture an adder. A non-transitory computer-readable storage medium may be provided, on which a computer-readable description of an adder is stored, which, when processed in the integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the adder.

[0047] An integrated circuit manufacturing system may be provided, comprising: a non-transitory computer-readable storage medium storing a computer-readable description of a hardware implementation of an adder according to the first aspect described above; a layout processing system configured to process the computer-readable description to generate a circuit layout description of an integrated circuit embodying the adder; and an integrated circuit generation system configured to manufacture the adder according to the circuit layout description.

[0048] Computer program code for performing any of the methods described herein may be provided. A non-transitory computer-readable storage medium may be provided having computer-readable instructions stored thereon, which, when executed at a computer system, cause the computer system to perform any of the methods described herein.

[0049] As will be apparent to those skilled in the art, the above features can be appropriately combined, and can be combined with any aspect of the examples described herein. Attached Figure Description

[0050] The example will now be described in detail with reference to the accompanying drawings, in which:

[0051] Figure 1 This is a block diagram showing a conventional floating-point accumulator;

[0052] Figure 2 This is a schematic block diagram illustrating a floating-point adder network designed to minimize latency;

[0053] Figure 3 This is a block diagram illustrating an example of a hardware implementation of an adder;

[0054] Figure 4a This is a block diagram showing the mantissa of a floating-point number in the first format representation;

[0055] Figure 4b This is a block diagram illustrating the second format representation of signed numbers;

[0056] Figure 5 It is shown Figure 3 Block diagrams of different units in the hardware implementation of the adder;

[0057] Figures 6a to 6d An example of converting a floating-point number from a first format representation to a second format representation is shown;

[0058] Figure 7a This is a flowchart illustrating a method for processing a set of k floating-point numbers;

[0059] Figure 7b This is a flowchart illustrating a method for converting the mantissa of this set of floating-point numbers into a set of signed or unsigned numbers;

[0060] Figure 8 It is a graph showing the area versus delay comparison of three different architectures of floating-point adders;

[0061] Figure 9 A computer system in which an adder is implemented is shown; and

[0062] Figure 10 An integrated circuit manufacturing system for generating integrated circuits embodying adders is shown; and

[0063] Figure 11 The architecture 300, implemented as an accumulator, is shown.

[0064] The accompanying drawings illustrate various examples. Those skilled in the art will understand that the element boundaries (e.g., boxes, groups of boxes, or other shapes) shown in the drawings represent one example of a boundary. In some examples, it may be that one element can be designed as multiple elements, or multiple elements can be designed as one element. Where appropriate, common reference numerals are used throughout the drawings to indicate similar features. Detailed Implementation

[0065] The following description is given by way of example to enable those skilled in the art to make and use the invention. The invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be readily apparent to those skilled in the art.

[0066] The implementation scheme will now be described using examples only.

[0067] When improving the performance of floating-point number processing, such as performing addition or subtraction, the accuracy of the generated output and the speed of calculation are two main criteria to consider.

[0068] Some arrangements that provide faster computation for floating-point adders include arrangements for performing parallel summations. These can also be used to reduce network latency. For example, specific implementations of floating-point adder networks for performing parallel summations and designed to reduce latency include... Figure 2 As shown. Figure 2 The tree adder 200 includes multiple adders 202a, 202b…202g arranged in a balanced structure. Each adder is configured to receive two inputs and generate an output (sum) of the two inputs. Using the tree adder 200, one can use… The stage implements the addition of 'n' floating-point numbers.

[0069] exist Figure 2In the example given, an array of eight floating-point numbers (x1, x2…x8) is provided as input to a tree adder 200. In the first stage, two (different) inputs to the array are provided to each of the four adders (primary adders) among a plurality of adders. Thus, eight floating-point numbers are provided as input to the four primary adders (202a, 202b, 202c, and 202d). Each adder generates a first output value y, resulting in four first output values ​​(y1, y2, y3, and y4). During the second stage, two (different) values ​​of the first output values ​​are provided as input to each of the two adders (secondary adders) among a plurality of adders. Thus, four first outputs are provided as input to the two secondary adders (202e and 202f). Each secondary adder (202e and 202f) generates a secondary output, resulting in two secondary output values ​​(y5 and y6). Furthermore, in the third stage, the two secondary output values ​​are provided as inputs to the three-stage adder 202g. The three-stage adder 202g generates the final output y7, which is the sum of eight floating-point arrays. Therefore, it is possible to... The addition is performed on 8 floating-point numbers in the three phases (i.e., the three phases).

[0070] Furthermore, in general examples, tree adders do not necessarily have to be as follows: Figure 2 The balanced structure is shown. A tree adder can use a single adder to add floating-point numbers at each different stage. For example, in the first stage, any two floating-point numbers are added to generate a first sum. Then, in the second stage, a second adder is used to add the first sum to another floating-point number to generate a second sum, and so on. Compared to a balanced tree adder, the layout latency in this example is increased.

[0071] However, in all these examples and the examples provided in the background art, at each stage, the output value is rounded or truncated to fit the output value to its finite representation. Multiple roundings can lead to significant cancellation. Different outputs are produced for different orders of feeding each input to the tree adder. Significant cancellation can occur when very small numbers are added to very large numbers, and important bits of the result can be lost due to rounding. For example, when summing a large positive number P, its corresponding negative number -P, and two small positive numbers Q and R, the exact value of the sum is (Q+R). A floating-point addition arrangement of summing P and -P in the first main adder and Q and R in the second main adder should give the final result (Q+R). However, if the order of the inputs is different and the main adder performs summations of (P+Q) and (-P+R), and P is much larger than Q and R, the output of the main adder can be rounded to P and -P, resulting in a total output of 0. A similar effect can be observed in accumulator architectures.

[0072] As mentioned above, existing methods for processing floating-point numbers, such as performing addition using accumulators or binary tree adders, generate output values ​​of varying precision based on the order in which the numbers are provided as input. That is, a specific order of providing the input produces the best result that is closest to the actual sum of the numbers. Other orders of providing the input may produce results that are less close to the actual sum of the numbers. Therefore, a range of results can be obtained around the actual sum of the floating-point numbers based on the order in which the inputs are provided.

[0073] The varying precision of the results is due to truncation or rounding errors, as well as the significant cancellation discussed earlier. Furthermore, performing addition on a large number of numbers using an accumulator incurs substantial latency because the additions are performed sequentially. While methods using binary tree adders can perform additions in parallel, additions still need to be performed at various stages to generate the final output value. Additionally, renormalization and rounding are performed at each stage, further increasing the latency in generating the output value. Therefore, a more accurate method for processing a set of floating-point numbers with less latency is needed.

[0074] This document describes a hardware implementation and method for simultaneously processing a set of k floating-point numbers. The method includes converting each floating-point number received in a first format into a number in a second format for processing. Furthermore, the method includes simultaneously processing the numbers in the second format (e.g., obtaining a sum by performing a single summation on all numbers in the set, as opposed to performing multiple summations across the set) to generate an output value.

[0075] Figure 3 This is a block diagram illustrating an example implementation of an architecture for processing a set of k floating-point numbers. Architecture 300 is an adder that performs operations on k floating-point numbers (x0, x1, x2…x…). k-1 The architecture performs addition or subtraction on a set of numbers to generate an output value. It is particularly well-suited for large arrays of numbers, but can also be used to add two or more numbers as needed. Architecture 300 includes a format conversion unit 302, a maximum exponent detection unit 304, an alignment unit 306, a processing unit 308, and a renormalization unit 310. Each number in the set of 'k' floating-point numbers includes a mantissa m of length 'b' bits. i The exponent e with a length of 'a' bits i The 'k' floating-point numbers can be signed or unsigned. In the case of signed numbers, each number will also include a sign bit s. i Including the mantissa and exponent. However, some floating-point formats (e.g., unsigned formats) may not include the sign bit.

[0076] The set of 'k' floating-point numbers (x0, x1, x2…x) can be received in input unit 301. k-1Input unit 301 can be a storage device or memory unit capable of storing the received input. This group of 'k' floating-point numbers (x0, x1, x2…x…) k-1 The numbers are stored in the first format received, and are referred to below as the first format numbers. The format conversion unit 302 receives the mantissas (m0, m1, m2…m) of the group of 'k' floating-point numbers from the input unit 301. k-1 The format conversion unit 302 converts the mantissas (m0, m1, m2…m…m…) into a single string. k-1 ) can be converted into different second formats (y0, y1, y2...y k-1 The 'k' number in ) is described in more detail below.

[0077] The bit length of the mantissa and exponent of a number in a first format is identified based on the type of the floating-point format. The first format can be a predefined format that the architecture 300 is designed to receive, or it can be identified on a task-by-task basis (e.g., by a controller, not shown). Examples of various types of floating-point formats include, but are not limited to, IEEE formats, including half-precision floating-point numbers (16-bit floating-point numbers), single-precision floating-point numbers (float16), and double-precision floating-point numbers (double), or other formats such as brain-float numbers (bfloat16). In some of the examples below, the IEEE single-precision floating-point format is considered as having a mantissa m with a bit length of 23 bits. i The exponent e with a bit length of 8 bits i The first format. In some other examples given below, the brain floating-point format is considered as having a mantissa m with a bit length of 7 bits. i The exponent e with a bit length of 8 bits i The first format is used to explain the method. However, it should be understood that the invention is not limited to these formats, and those skilled in the art will understand that architecture 300 can be implemented to perform the methods described herein using numbers of any type of floating-point format.

[0078] The format conversion unit 302 converts floating-point numbers in the first format to numbers in the second format. This includes removing the mantissa 'm' from each of the 'k' floating-point numbers in the set. i 'Convert to number'y i Upon receiving a set of 'k' floating-point numbers where all digits are unsigned floating-point numbers, the format conversion unit converts the mantissa to produce a set of k unsigned numbers. Similarly, upon receiving a set of 'k' floating-point numbers that are signed floating-point numbers, the format conversion unit converts the mantissa to produce a set of k signed numbers. Format conversion unit 302 converts the mantissa m, which has a bit length of 'b' bits (first format). i To generate a number 'y' with a bit length of 'n' bits i'(To indicate the second format). This is achieved by adding one or more additional most significant bits (MSB) and one or more additional least significant bits (LSB) to the mantissa (m) of the first format, which is 'b' bits long. i We can obtain the bit length of 'n' bits using 'b'. Therefore, the bit length 'n' is always greater than the bit length 'b' of the original mantissa.

[0079] If the group of 'k' floating-point numbers is an unsigned floating-point number, the resulting representation of an unsigned number with a bit length of 'n' bits includes n magnitude bits. If the group of 'k' floating-point numbers is a signed floating-point number, the additional MSB added to the mantissa of the first format may include bits representing the sign bit. Therefore, the resulting representation of a signed number with a bit length of 'n' bits includes a sign bit and (n-1) magnitude bits. Typically, floating-point formats do not explicitly encode leading bits (i.e., bits representing digits appearing before the decimal point), as they can be assumed to be 1s in a binary floating-point number and are therefore implicitly encoded (and are thus also called 'hidden bits'). Therefore, in the case where the leading bits are 'hidden bits' in the first format, the second format adds bits to account for the second format number 'y'. i The leading bit of the '' length. The format conversion unit forms the number 'y' by adding a leading bit with a value based on the encoded floating-point number before the mantissa of the floating-point number. i The specific value of ' (i.e., whether it is a normal or non-normal number). In this second format, as the output of the format conversion unit, each number can be considered as a combination of a valid sign bit (if it has been added) and a floating-point mantissa with an extended bit width, the position of which the decimal point appears in the same position as the bits representing the mantissa value in the first format—the second format only includes extra bits before and after the position of the decimal point.

[0080] The number in the first format is converted to the number in the second format based on the number of floating-point numbers (k) in the set. That is, the mantissa (m) added to the first format is... i The number of additional MSBs and LSBs is determined based on the number 'k'. (The last part, "m", appears to be a typo and can be left as is.) i At least the logarithmic number of the number 'k' ( (bits) extended to the MSB side and at least in logarithmic order of the number 'k-1'. Bit extension to the LSB side to obtain the number 'y' i Preferably, assuming the first format is a signed floating-point number with an implicit leading bit and treating any sign bit as separate from the mantissa, then... Additional MSB and LSB is added to the mantissa m i The bit length 'b' on either side. That is, in the additional MSB added (except for...) Two additional bits (besides the first bit) are allocated to the implicit leading bit (or hidden bit) and the sign bit. i The additional LSBs added (excluding) The additional bits (beyond the standard bit) are precision bits, used to obtain extra precision. The added extra MSB and LSB prevent bit overflow or underflow while processing this group of 'k' numbers, which will be explained in detail later. In different examples, the number of extra MSB and LSB added to each side can be the same or different. Generally speaking, the second format of the number 'y'... i The bit length 'n' can be obtained as:

[0081]

[0082] Where x is an integer and preferably x≥1, the value of x depends on the number of extra bits added to represent the leading bit, sign bit, and precision bit (if any).

[0083] Figure 4a The mantissa (m) of the first format is shown. i The representation of ) and Figure 4b The second format of the signed number 'y' is shown. i The expression '. In Figure 4a In the first format, it is shown as a brain floating-point number with a mantissa length of 7 bits, b. Figure 4b The signed number represented in the second format is shown. Figure 4b The representation in the figure shows the signed number 'y' i ', bit length is This is achieved by adding log2(k) + 2 extra MSBs and log2(k-1) + 1 extra LSBs to the bit length 'b' of the mantissa. Therefore, in one example, when having... Figure 4a When a set of eight floating-point numbers of length 7 are added together (i.e., k = 8), the signed number in the second format will have a bit length of n = 16 bits.

[0084] from Figure 4b The examples clearly demonstrate that, as defined in this article, the number 'y' represented in the second format... i 'Including the bits allocated to represent the sign bit (s)' i The bits allocated to represent the leading bit (LB) (i.e., hidden bits, which are not explicitly encoded in the first format for efficiency), and additional bits as extra MSBs. Position, and Additional LSBs. Therefore, the second format number 'y iA ' is a signed number, consisting of a sign bit and a magnitude bit (i.e., bits indicating the absolute magnitude of the value being represented). The sign bit is assigned either '0' or '1' based on whether the number is positive or negative. As mentioned above, if all floating-point numbers in this set of 'k' floating-point numbers in the example were unsigned, it could be achieved by adding... An additional MSB is used to represent the second format, which includes bits representing the leading bit and... Bits. Furthermore, if all floating-point numbers in the group of 'k' floating-point numbers represented in the first format in the example are unsigned and contain explicit leading bits, then the signed number 'y'... i 'It can be done by...' Additional MSB added to the mantissa m i The bit length b is used to represent

[0085] exist Figure 4b In the example shown, the number 'y' i 'include Additional LSBs, added to the mantissa m i Number 'y' i 'May include Extra LSBs, added to the mantissa (m i ), where r is any integer, r≥1. Preferably, the number 'y' i 'include Extra LSBs, added to the mantissa (m i Add to the mantissa m. i The additional LSB improves the accuracy of the results and reduces underflow of the mantissa, while also aligning the digits 'y'. i This will be explained in detail below.

[0086] Therefore, in the examples described in the above paragraphs, where the first format is a signed floating-point number with an implicit leading bit and the number of additional bits x ≥ 3. Furthermore, in another example, it is assumed that the first format is a signed floating-point number with an explicit leading bit. Additional MSB and LSB is added to the mantissa m i The bit length 'b' is taken from either side to produce the number 'y'. i This results in the number of additional bits x ≥ 2.

[0087] Similarly, in another exemplary case, suppose the first format is an unsigned floating-point number with an implicit leading bit. Additional MSB and The extra LSB is added to the mantissa m i The bit length 'b' is taken from either side to produce the number 'y'. iThis results in the number of additional bits x ≥ 2. Furthermore, in another exemplary case, suppose the first format is an unsigned floating-point number with an explicit leading bit. Additional MSB and The extra LSB is added to the mantissa m i The bit length 'b' is taken from either side to produce the number 'y'. i This results in the number of additional bits x ≥ 1.

[0088] Therefore, although it is expected that more than b additional bits are needed to maintain the required precision, in practice (as the mathematical proof presented later confirms) it is possible to achieve the required precision with fewer or equal to b additional bits, and in the example above, the required precision can be achieved with a number x of fewer or equal to three additional bits.

[0089] Therefore, in the general example, x ≥ 1 and x ≤ 'b' bits, such that the number 'y' i The bit length of ' is the largest.

[0090]

[0091] In addition to the sign bit and leading bit, the extra MSB and LSB added to the mantissa are initially assigned '0' bits in the second format. The sign bit is assigned either '0' or '1' bits based on whether the number is positive or negative. The leading bit is assigned either '1' or '0' bits based on the type of the floating-point format. In one example, a '1' bit is added as a leading bit when the floating-point number is a normalized non-zero number, and a '0' bit is added as a leading bit when the floating-point number is zero or a denormalized number.

[0092] In addition, the exponent 'e' of each number in the first format i '(e0, e1, e2, e3...e k-1 This is provided as input to the maximum exponential detection unit 304. For example... Figure 3 As shown, the input 'e' provided from input unit 301 to the maximum detection unit i In some other arrangements, the index can be passed to the maximum index detection unit 304 via the format conversion unit.

[0093] The maximum exponent detection unit 304 identifies the maximum exponent (e) from the exponents of the group of k numbers. max The maximum exponent detection unit 304 uses various methods or functions to detect the maximum exponent. One example of a method for identifying the maximum exponent is using a binary tree structure. See below for reference. Figure 5 Detailed description of the maximum index (e) maxHowever, which option is better may depend on available resources (e.g., parallel processing is generally faster, but computationally more intensive).

[0094] In addition to providing the maximum exponent detection unit 304, the exponent value e is also provided from the input unit 301. i As input to alignment unit 306. Alignment unit 306 receives the exponent 'e' of each floating-point number in the first format. i As the first input, alignment unit 306 also receives the maximum exponent (e) from maximum exponent detection unit 304. max As the second input, it receives the number 'y' from the format conversion unit 302. i As the third input, alignment unit 306 aligns each number 'y'. i’ The magnitude of the value is determined based on the maximum exponent, thus assigning the number 'y' to the digit. i Convert to a distinct number (or integer p) with a bit length of n bits. i ). refer to Figure 5 The alignment of the number 'y' was explained in detail. i The method, but in general, the numbers in the second format are adjusted based on the maximum exponent, and for convenience, the adjusted numbers (p0, p1, p2...p...) are... k-1 The integer is processed in the processing unit 308 for further processing.

[0095] Subsequently, the k integers (p0, p1, p2...p) generated in this way will be... k-1 The input is provided to processing unit 308. Processing unit 308 is an adder unit. Processing unit 308 processes k integers simultaneously (i.e., k is an aligner number). That is, the processing unit processes all integers in the set simultaneously, rather than processing the elements in the set sequentially, for example. Processing unit 308 performs addition and / or subtraction of k integers to generate an output value q. Note that adding a positive number to a negative number is equivalent to performing subtraction, therefore the term processing is used herein to encompass the individual or combined effects of addition and subtraction.

[0096] The output value q of processing unit 308 and the maximum exponent of maximum exponent detection unit 304 are further provided to renormalization unit 310. Renormalization unit 310 converts the output value from processing unit into a floating-point number, for example, in a first format (but optionally in a different format, for example, a third format if desired), having a mantissa m. i and index 'e i Output unit 312 stores the converted output value (i.e., the output floating-point number).

[0097] Figure 5 It is shown Figure 3The block diagram illustrates the different units in an implementation of architecture 300. Consider a scenario where the set of k floating-point numbers in the first format comprises four numbers, i.e., k = 4. Format conversion unit 302 receives the set of four floating-point numbers x. i (x0, x1, x2, x3) are taken as input. The format conversion unit 302 converts the set of four numbers in the first format into four numbers y in the second format. i For reference Figure 3 As described above. In this example, the group of k floating-point numbers in the first format are considered to be four signed floating-point numbers with implicit leading bits. Therefore, the group of k floating-point numbers is converted into four signed numbers with a bit length of n bits, including the sign bit s. i and (n-1) magnitude position f i In other exemplary cases, the set of k floating-point numbers in the first format can be unsigned floating-point numbers.

[0098] The exponent 'e' of each number (e0, e1, e2, and e3) from input unit 301 i It is provided to the maximum index detection unit 304.

[0099] Figure 5 The maximum exponent detection unit 304 includes three maximum function logics 504a, 504b, and 504c. This is only an example, and other implementations may have different or similar structures for finding the maximum exponent, but with different numbers of logics to account for different numbers of inputs.

[0100] In the illustrated example, the maximum function logic (max1) 504a receives exponents e0 and e1. The maximum function logic (max2) 504b receives exponents e2 and e3. The maximum function logic 504a identifies the maximum exponent value among e0 and e1. The maximum function logic 504b identifies the maximum exponent value among e2 and e3. Furthermore, the outputs of the maximum function logics 504a and 504b are provided to the maximum function logic (max3) 504c. The maximum function logic 504c identifies the maximum exponent value in the outputs of the maximum function logics 504a and 504b to detect e. max That is, the largest of the input exponents e0, e1, e2 and e3.

[0101] As described above, the maximum value detection unit 304 can be implemented in different other ways. For example, the maximum value detection unit 304 can be implemented using a binary search tree.

[0102] Returning to the illustrated example, the maximum exponent identified by the maximum detection unit 304 is provided as input to the alignment unit 306. Furthermore, the exponents of the four numbers in the first format are provided as input to the alignment unit 306. Additionally, the exponents of the four signed numbers 'y' in the second format...i ' is provided as input to alignment unit 306. Alignment unit 306 aligns each signed number 'y' based on the maximum exponent and the corresponding exponent of the number corresponding to the first format of the signed number. i The value of f i In other words, the magnitude bits of the corresponding floating-point number that does not yet have the maximum exponent of the signed number are shifted to account for the difference between the exponent of the number in the first format and the maximum exponent (effectively adding zeros before the first (or at least the first non-zero) magnitude bits and removing trailing bits as needed to realign the magnitude bits as required). Therefore, alignment unit 306 converts each signed number ('yi') into another integer (p) output by alignment unit 306. i Integer p i It is considered a fixed-point number format. Similarly, in the case of unsigned numbers, the alignment unit shifts the magnitude bits of the unsigned number based on the maximum exponent and the corresponding exponent of the number in the first format corresponding to the unsigned number.

[0103] use Figures 6a to 6d The example shown illustrates the signed number 'y' i 'to integer p i The conversion. It should be understood that when describing this series of diagrams, the starting point is the signed number 'y' of the second format number output by the format conversion unit 302. i ', and the endpoint is the converted signed number pi (integer p) mentioned above. i However, for ease of reference, in the following description, the intermediate stage may also be referred to as the signed number.

[0104] Consider an example of a floating-point number in first format with an implicit leading bit and a sign bit separate from the mantissa. Each number has a 7-bit mantissa m in first format. i (such as bfloat16). Therefore, in this example, when converted to the second format, each of the four numbers in the set includes a signed number y with a bit length 'n'. i (including the signed bit s) i ),in

[0105]

[0106] Figure 6a This shows a signed number 'y' in a second format with a bit length of 14 bits. i '. In one example, consider Figure 6a The numbers shown represent signed numbers y0 provided as input to alignment unit 306. Alignment unit 306 includes multiple subtraction modules 505. Alignment unit 306 also includes multiple shifter units 506 and multiple two's complement units 507.

[0107] Each subtraction module in the subtraction module receives the exponent e from the input unit 301. i As the first input, the maximum exponent is received from the maximum exponent detection unit 304 as the second input, and the signed number 'y' is received from the format conversion unit 302. i As the third input, input unit 301 takes the raw exponents 'e' of the four numbers. i Provided to each subtraction module. Each subtraction module calculates the maximum exponent of the number. max 'and index'e i The difference between 'e' di '.exist Figure 5 In the first subtraction module, the exponent e0 of the first number is received from the input unit 301, and the maximum exponent e is received from the maximum exponent detection unit 304. max The first subtraction module calculates in Figure 5 The Chinese term is e d0 The first difference. Similarly, the remaining subtraction modules calculate the difference e. d1 e d2 e d3 ,like Figure 5 As shown in the figure, multiple subtraction modules calculate the difference e of each number in parallel. di However, other arrangements are also possible—for example, a single subtraction module that performs each subtraction sequentially. Returning to the depicted example, the calculated difference e from each of the multiple subtraction modules 505... d0 e d1 e d2 and e d3 It is further provided to the corresponding shifter unit in the plurality of shifter units 506.

[0108] Each of the multiple shifter units 506 receives the calculated difference e of the numbers. d As the first input, and receiving the corresponding signed number 'y' i The value of f i As a second input. Furthermore, each of the plurality of shifter units 506 adjusts the signed number 'y' based on the corresponding calculated exponent difference. i The value of f i Perform a shift. Value f i (Except for the sign bit) Shift to the least significant bit side (i.e., the right side of the depicted format) by a number of positions equal to the calculated exponent difference. Figure 6a The value f of the signed number 'y0' of the first input is shown. iThe 'b bit', which includes the bit corresponding to the mantissa of the number in the first format, is preceded by an explicit leading bit '1'. The remaining extra bits of the signed number 'y0' are filled with '0' bits. The original 'b bit' and the explicit leading bit are shifted by a shifter unit. Furthermore, in Figure 6a In this context, the sign bit of the signed number y0 is assigned a '1' bit, indicating that the signed number y0 is negative. The shifter unit does not shift the sign bit.

[0109] In this example, the first shifter of the plurality of shifters 506 receives a first input (the magnitude bit f0 of the signed number y0) from the format conversion unit 302. Furthermore, the first shifter receives the calculated difference e from the first subtraction module. d0 (In one example, for) Figure 6a The first digit shown has a mantissa (f0), considering the calculated difference e. d0 (difference e) max And e0) equals 5) as the second input. Therefore, the first shifter unit shifts the value of the signed number y0 by 5 positions to the right. Figure 6b The shifted numbers are shown. The calculated difference e d It will never be a negative number. Therefore, based on the difference e calculated for each number... d Quantity position f i Always shift to the least significant bit side (i.e., shift to the right in the example), possibly shifting zero bits.

[0110] Similarly, other shifter units in the plurality of shifter units 506 are based on the corresponding calculated difference e d1 e d2 and e d3 The magnitude bits (f1, f2, and f3) of the remaining three numbers are shifted. Therefore, all shifter units in the plurality of shifter units 506 execute the magnitude bit shifting in parallel. i The shifting of the mantissa is significantly increased in most existing architectures for processing floating-point numbers, where shifters sequentially shift or align the mantissa as needed, which greatly increases latency. Because in the disclosed architecture, the shifting or aligning of all numbers occurs in parallel, the processing latency can be significantly reduced as the number of floating-point numbers to be processed increases. In another implementation, despite the increased latency due to limitations in available resources, multiple shifter units 506 may sequentially perform the shifting of the mantissa f. i The shifting (e.g., parallel processing can be faster overall, but is more computationally intensive).

[0111] exist Figure 6bAs can be seen, shifting the magnitude bits results in shifting 5 bits out of the signed number's bit width (and thus, shifting out the stored representation of the number). The shifter unit truncates the bits of the signed number beyond the bit length shifted to n bits. When the calculated exponent difference of the corresponding numbers is greater than the mantissa m of the number in the first format when converted to the second format... i When an additional number of LSBs is added, the bits corresponding to the mantissa of the original number in the first format are shifted out by 'n' bits. When the calculated difference is greater than the number of additional LSBs, it causes an underflow of bits in the original (first format) mantissa. When the calculated difference is less than the number of additional LSBs, it only causes an underflow of 'zero' bits added by the format conversion unit 302. As described above, Figure 6b This shows the 5 bits shifted out from a bit length of n bits when the bit is shifted by 5 bits. Figure 6c The diagram shows the signed number after truncation. It's clear from the figure that although the bits were shifted by 5 bits, in this case, only 2 bits of the actual number (i.e., the two mantissa bits of the number in the first format) are lost due to the extra LSB added during the conversion to the second format. Therefore, the extra LSB is used to reduce precision loss, which would occur if all numbers were shifted to the same maximum exponent using the first format.

[0112] The output from each shifter unit 506 is also provided to the corresponding two's complement unit among the plurality of two's complement units 507. The two's complement unit receives the aligned magnitude bits from the shifter unit as its first input and converts the signed number 'y'... i The sign bit is used as the second input. However, in other arrangements, the function of the two's complement unit can be performed before the function of the shift unit or as part of the adder unit (processing unit 308). In any case, the two's complement unit performs the magnitude bit f on those numbers with the sign bit indicating a negative number. i The two's complement. In this case, the shifted positive sign number in the set is provided to the processing unit 308 ( Figure 5 The adder 508 in the set is used without performing two's complement operations. Furthermore, the two's complement of the negative numbers in the set is provided to the processing unit. The processing unit 308 receives the outputs of multiple two's complement units 507 and simultaneously processes the aligned signed number p. i To generate the output. The output obtained from each two's complement unit is the aligned number p. i . Figure 6d Indicates to Figure 6c The number p0 is obtained by performing two's complement on the mantissa shown.

[0113] Therefore, alignment unit 306 performs alignment of the number 'y' i The value of f i The steps of shifting and truncation are performed to align the number 'y'.i The value of ' is used to generate a set of numbers (or integers) p i The alignment unit also converts any number with a sign bit indicating that the number is negative into its two's complement representation. In unsigned numbers 'y'... i In the case of ', the alignment unit performs alignment on the number 'y'. i The value of f i The process involves shifting and truncating the bits. The only difference is that in the case of unsigned numbers, the two's complement step is not required. Alignment unit 306 can process each number in parallel for the shifting, truncating, and two's complement steps of the mantissa bits. The resulting number p... i It is an integer. The number pi is represented as...

[0114]

[0115] For simplicity, assume the exponential deviation is 0.

[0116] like Figure 5 As shown, the converted numbers, namely integers p0, p1, p2, and p3, are further provided to adder 508, which is the processing unit 308. The signed integer p0 is generated by performing shift, truncation, and complement operations on the magnitude bits f0 of the signed number y0 in the example. Figure 6d As shown. In one example, adder 508 is a carry-store adder capable of performing addition on 4 'n'-bit integers. The value of integer pi is between and Between. The carry-store adder performs the addition of four signed integers pi to generate a sum value q (output).

[0117]

[0118] The value of the added term (i.e., 4 integers p) i Less than And therefore the sum will be less than And it will not overflow by 'n' bits. That is, the maximum integer p. i The position corresponding to the hidden bit will be 1-, that is, from the MSB end. The value is assigned a sign bit, and the sum of the k digits (i.e., considering the extreme case where all digits have the maximum exponent) must not overflow the additional MSB provided after the sign bit. The adder 508 processes the group of 'k' floating-point numbers to produce the same output value, regardless of the order in which the group of 'k' floating-point numbers are provided as input.

[0119] The sum q is further provided to the renormalization unit 310. Note that in this example, the value q, like the value pi, will be a signed integer in two's complement format. The normalization unit 310 includes a shifter 510a and a subtractor 510b. The shifter 510a shifts the bits of the sum q to generate a normalized value (general format). The shifter 510a represents the sum q in normalized format by calculating the number of consecutive leading '0' or '1' bits (denoted as 'd') in the MSB (i.e., including the sign bit). The number of leading '0' bits is calculated when the obtained sum is non-negative, and the number of leading '1' bits is calculated when the obtained sum is negative. The shifter shifts the bits of the number to generate a normalized number (n) in normalized format. k Number (n) k The number is further rounded to represent a normalized number (n) with the required bit length. k For example, if the output has the same format as the input, the bit length is 'b' bits. Normalized number (n) k This is represented as (assuming that an addition was made when converting to the second format). MSB):

[0120]

[0121] The subtractor 510b receives the maximum exponent as the first input and d (the number of leading '0's or '1's) and the number of extra LSBs added to the mantissa (in the first format) as input. Furthermore, the subtractor calculates the exponent of the normalized number based on the input, and represents the exponent in bits of length 'a'. The final output exponent is calculated as (again assuming that extra LSBs were added during conversion to the second format). MSB)

[0122]

[0123] This is an example, and those skilled in the art will not be limited to it; in other examples, different and other known methods can be used to calculate the exponent e. k Therefore, the final output or sum obtained is calculated using the normalized mantissa (n). k ) and index (e k )express.

[0124] The adder architecture 300 can be used to perform addition on any number of floating-point numbers. Figure 5 The example shown is a concrete example of an adder 300 used to add a set of four floating-point numbers. Furthermore, an additional number of elements can be added to each unit of adder 500 in a similar manner, thereby extending it to perform addition on any number of floating-point numbers simultaneously (e.g., 20 or 50 floating-point numbers).

[0125] In addition, the architecture 300 can also be used as an accumulator, such as Figure 11 As shown, it is used to perform addition on multiple sets of floating-point numbers, even if the number of floating-point numbers exceeds the input of the adder. Figure 11 An architecture 300 implemented as an accumulator design is shown. The accumulator design 1100 includes receiving a large array of floating-point numbers (x0, x1…x…). n The gate control unit 1102, as such Figure 3 The adder (300) shown includes accumulator 1104 and register 1106. Consider accumulator 1104 as an adder with an architecture 300 capable of simultaneously adding a set of 33 floating-point numbers. If there are 128 floating-point numbers (x0, x1…x…) 127 If an array is to be added, the accumulator 1104 performs the addition on the 128 floating-point numbers in the array in four separate batches at different clock cycles.

[0126] During the first loop, array gating unit 1102 provides the first 32 floating-point numbers in the array to accumulator 1104. Accumulator 1104 then stores the array (x0, x1…x…) into accumulators. 31 The first 32 floating-point numbers in the array are added to the accumulated value (c), where c is initially 0, to generate the first output and store the first output as the accumulated value (c) in register 1106. The first output is then processed by adding the first 32 floating-point numbers to the accumulated value (c). Figure 3 or Figure 5 The addition is performed in the same manner as described above to generate the value. In the second loop, the accumulator 1104 will perform addition on the next 32 floating-point numbers (x... 32 x 33 …x 63 The second output is generated by adding the accumulated value (c) to the accumulated value and passed to the second output to be stored as the accumulated value. Similarly, the remaining numbers in the array are added to the updated accumulated value in batches of 32 numbers each clock cycle. Therefore, in a pipelined design, adding an array of 128 numbers requires only three additional addition cycles.

[0127] Figure 7a This is a flowchart illustrating a method for processing a set of 'k' floating-point numbers. The method includes performing addition and / or subtraction using a hardware implementation of the architecture. Each floating-point number in the set of 'k' includes a mantissa (m... i ) and index (e i ).

[0128] In step 702, the method includes receiving the group of 'k' floating-point numbers in a first format. Each floating-point number in the first format includes a mantissa (m) of length 'b' bits. i ) and an exponent of length 'a' bits (e i The mantissa (m) of the first format is identified based on the floating-point format type.i The bit length 'b' bits and the exponent (e) i The number of bits is 'a' bits. Furthermore, floating-point numbers can be signed or unsigned numbers with implicit or explicit leading bits. For example, a single-precision (32-bit) floating-point number in the first format is typically a signed number with implicit leading bits, consisting of a 23-bit mantissa (excluding the leading bit), an 8-bit exponent, and an additional sign bit (s). i In other examples, a single-precision (32-bit) floating-point number in the first format can be a signed number with an explicit leading bit, and then the mantissa has a bit length of 23 bits, including the explicit leading bit.

[0129] When a single-precision (32-bit) floating-point number in the first format is an unsigned number with an implicit leading bit, there will be no extra sign bit, and the mantissa can be represented by a 24-bit length (excluding the leading bit). Furthermore, when a single-precision (32-bit) floating-point number in the first format is an unsigned number with an explicit leading bit, the 24-bit length of the mantissa includes the explicit leading bit.

[0130] Upon receiving the group of 'k' floating-point numbers in the first format, at step 704, the method includes retrieving the mantissa (m) of each floating-point number in the group of 'k' floating-point numbers. i Convert y to numbers i By adding extra MSB and extra LSB to the mantissa of the first format (m i The number (y) is obtained from the bit length 'b' of the given number. i The bit length of b is extended based on the number 'k' (the number of floating-point numbers in the set). In the example of the set of 'k' floating-point numbers as signed numbers in the first format, adding extra MBS and LSB includes preferably adding The most significant bit of the quantity The least significant bits of the number. The number of extra MSBs and extra LSBs added to the bit length b of the mantissa can be the same or different. In this example, the added extra MSBs include the bits representing the sign bit and another bit representing the leading bit. Therefore, signed numbers are represented by the bit s. i The bit length is represented by the 'n' bits of the leading bit (LB). The bit length 'n' is represented as...

[0131]

[0132] Where x is an integer and x≥1.

[0133] Furthermore, the method at step 706 includes identifying the exponent (e) of the set of 'k' floating-point numbers. i The largest exponent (e) in ) maxMaximum exponent (e) max The maximum exponent detection unit 304 identifies a set of values ​​(exponent, e). The maximum exponent detection unit 304 implements algorithms, such as those used to identify a set of values ​​(exponent, e). i The maximum value function in ). Step 706 can be executed before or after step 704, or even in parallel with step 706.

[0134] The method also includes, at step 708, setting the number 'y' i The value of ' is aligned based on the maximum exponent (e) max ). Number 'y i ' is an integer represented as a fixed-point number with a bit length of n bits. Relative to Figure 7b The method for determining the magnitude bits of an aligned number is discussed. Alignment unit 306 is based on the magnitude bits of the aligned number with the maximum exponent. Alignment unit 306 thus generates an aligned number that is an integer p. i .

[0135] The method also includes, at step 710, simultaneously processing the group of 'k' aligned numbers p i To generate the output value q. Integer p i The processing includes performing addition and / or subtraction on the k numbers. It should be noted that adding a positive number to a negative number is equivalent to performing subtraction; therefore, the term "processing" is used herein to encompass the individual or combined effects of addition and subtraction. The processing of the k numbers is performed simultaneously. That is, the processing unit processes all integers in the set at the same time, rather than processing elements in the set sequentially or in pairs, for example. Processing unit 308 performs addition and / or subtraction on the k integers to generate an output value.

[0136] Furthermore, at step 712, the method includes renormalizing and rounding the output value q, representing the output value as a first format or any other format with a normalized mantissa n. k and index e k The method involves renormalizing the output value to represent the output value q as a standard normalized number. Furthermore, the method applies this normalized number n... kRounding is performed to represent the number with a mantissa of a specific bit length. In one example, the normalized number is rounded to a bit length of 'b' bits so that the number in the first format is represented as the received input with a mantissa of bit length 'b'. In other examples, the output value is represented in a different floating-point format compared to the received input. Normalization is performed by initially counting the number of repeating '0' or '1' bits on the MSB side. When the output value 'q' is non-negative (i.e., positive), repeating '0' bits are counted. When the output value 'q' is negative, repeating '1' bits are counted. Furthermore, normalization is performed by shifting the output value q to the LSB side around the decimal point to represent the signed number as a normalized number. Additionally, the method calculates the exponent value based on the maximum exponent and the count of repeating bits. The exponent value thus calculated is represented with a bit length of 'a' bits, as referenced above. Figure 5 As explained. Therefore, the output 'q' is normalized to a floating-point number represented in the first format.

[0137] Figure 7b This shows the alignment of the numbers based on the maximum exponent (y). i The flowchart of the method.

[0138] The method includes, at the first step 714, calculating the maximum exponent (e) for each floating-point number in the set of 'k' floating-point numbers. max ) and index (e i The difference between (e) d The subtractor unit in alignment unit 306 calculates the difference e for each input floating-point number. d Alignment unit 306 includes a function for calculating difference e. d Multiple subtractor units.

[0139] The method includes, at step 716, shifting the magnitude of the corresponding digital number to the LSB side based on the calculated difference between the corresponding floating-point numbers. If the calculated difference e d Greater than the mantissa m in the first format i The number of extra LSBs added when converting to a number, by shifting the position of the bits to align the value bits, causes the original 'b bits' to underflow from the mantissa of the first format number.

[0140] Furthermore, to shift the magnitude bits of a number, the method at step 718 includes truncating the bits of the number shifted beyond the bit length. That is, all bits shifted beyond the bit length 'n' are truncated. This method truncates only the bits corresponding to the mantissa of the original first format number when the calculated difference is greater than the number of additional LSBs added. Any reasonable fair rounding scheme can be used to truncate the bits. The error caused by truncation when processing floating-point numbers is minimal because the mantissa (m... i It has been extended by adding an extra number of LSBs to mitigate the effects of underflow when performing shift or truncation steps.

[0141] The method at (optional step 720) also includes a sign bit (s) based on each corresponding digit. i This step determines the two's complement of the number. This step is optional if the received 'k' floating-point number in the first format is a signed number. When the sign bit (si) of the number indicates a negative number, the signed number is two's complemented. Positive numbers remain unchanged, and then all numbers are processed simultaneously. In one example, processing a 'k' number involves calculating the sum by performing an 'n' carry-saving addition. The sum is further normalized and rounded to represent the output in floating-point format.

[0142] Figure 8 This is a diagram illustrating an implementation of architecture 300 and comparing it with other standard architectures used for processing a set of floating-point numbers. Figure 8 In the middle, it is shown that Figure 3 The diagram presents a graphical representation of the results of a first experiment comparing the implementation of architecture 300 as explained in the diagram with other standard architectures. The first experiment includes a comparison of the area versus latency tradeoffs of the different architectures. Figure 8 As shown, in the first experiment, three architectures (Arch 1, Arch 2, and Arch 3) were used for comparison. Arch 1 is a balanced tree architecture for the floating-point adder implementation (pairwise rounding to the nearest position and associated with even-numbered implementations). The results obtained for Arch 1 are... Figure 8 The cross (+) symbol on the first curve in the diagram represents this. Arch 2 is another architecture of the balanced tree implementation of the floating-point adder (with paired, rational rounding implementation). The results obtained for Arch 2 are obtained by... Figure 8 The circle (o) symbol on the second curve shown represents the arch. Arch 3 is an implementation of architecture 300 disclosed in this document (with reasonable rounding). The results obtained for arch 3 are... Figure 8 The square symbol on the third curve in the diagram represents the architecture. In the first experiment, the three architectures were implemented in software using VHDL.

[0143] In the first experiment, a set of floating-point numbers in the first format of single-precision (32-bit) floating-point numbers was used as input. Each floating-point number included a mantissa mi of 23 bits (b = 23 bits) and an exponent 'e of 8 bits (a = 8 bits). i 'and sign bit. The first experiment involved synthesizing three architectures for various timing objectives to observe the area-delay tradeoff. From Figure 8 The figures show that Arch 3 (Architecture 300) has the smallest delay and the smallest area. In particular, the fastest circuit synthesized according to Architecture 300 uses less than 50% of the area of ​​the fastest circuit synthesized from other architectures under consideration, and its delay is also less than 50% of the latter.

[0144] Furthermore, the complexity of hardware implementations of different architectures was compared. The complexity of hardware implementations, such as the critical path, was represented using Big O notation. For architecture 300, the maximum exponent detection unit 304 is implemented with O(log(k)log(a)) gates on the critical path. Additionally, the alignment unit 306 is implemented with O(log(b)) gates on the critical path. The processing unit (308), i.e., the adder 508, is implemented with O(log(k)+log(b)) gates on the critical path. The normalization unit 310 is implemented with O(log(a)) gates on the critical path. Therefore, the overall hardware implementation can be implemented with O(log(k)log(a)+log(b)) logic gates on its critical path. To increase the array size k and mantissa width b, the critical path is asymptotically shorter than the balanced tree architecture of the floating-point adder.

[0145] For the same input of the set of k floating-point numbers in the first format, the direct implementation of a multi-input adder consisting of a binary tree of floating-point adders (with a fixed rounding mode, such as rounding to zero) is explained below. By construction, the implementation produces a sum of pairs of reasonable rounding. The critical path in the balanced tree of floating-point adders passes through O(log(k)) adders, each with O(log(ab)) gates on its critical path. In summary, the architecture of the balanced tree of floating-point adders therefore has O(log(k)log(ab)) logic gates on its critical path.

[0146] Furthermore, the output generated by the implementation of architecture 300 has an accuracy no less than the worst-case precision of pairwise addition performed using a binary tree adder or an accumulator adder with reasonable rounding. A mathematical proof of the accuracy of architecture 300 is provided later. This shows that the accuracy of the result is no less than the worst-case precision of pairwise floating-point addition with a reasonable rounding scheme. This means that, for any given input array, performing pairwise addition by iteratively replacing two terms in the array with the sum of their rounded values ​​to the nearest larger or smaller representable values ​​will always produce a result that is less precise than or equal to the result produced by addition using the disclosed architecture 300. In known architectures, an imprecise choice for sorting the input and performing rounding steps is to add the incrementing numbers to the largest number and always round in the same direction. The output accuracy obtained by architecture 300 is no less than the accuracy of the result obtained by making these choices.

[0147] Compared to a floating-point adder tree, the architecture 300 significantly improves latency and area performance by removing the intermediate normalization step and replacing the intermediate carry propagation step with a single carry-store addition, such as... Figure 8 As shown, as measured on a zero-centered Gaussian distributed input, the empirical accuracy of the architecture 300, as described above, shows a significant advantage over the floating-point adder tree.

[0148] Finally, the architecture 300 used to perform addition is commutative. Any input order produces the same output. This leads to better result reproducibility because the order in which floating-point numbers in the set are bound to the inputs of architecture 300 does not affect the result.

[0149] The mathematical proof of the accuracy of the architecture 300 is provided below. In the following section, it is proven that the accuracy of the algorithm is no less than that of the worst-case iterative pairwise addition with reasonable rounding.

[0150] First, we define and prove some fundamental properties of rational rounding schemes. Let F1, Let F be two number formats, and r∈R∪{±∞} be a number. When q is the minimum upper bound or maximum lower bound of r in F, q is a reasonable rounding of r in format F, written as q≈ F r.

[0151] When the minimum upper bound and maximum lower bound of r in F2 belong to F1, F1 is more accurate than F2 in the neighborhood of r. Therefore, the following proposition is given directly.

[0152] Proposition 1: If F1 is more accurate than F2 in the neighborhood of r, then for all values ​​q1 and q2, there exists a value such that q1 ≈ F2. F1 r and q2≈ F2 q1, obtain q2≈ F2 r。 .

[0153] Now let F be in floating-point format, using 'a' for the exponent, 'b' for the mantissa, and 'c' for the exponent bias in the input and output of the calculation. Additionally, a set of 'k' floating-point numbers in format F is taken as input. The algorithm converts these numbers to the largest exponent e in the array. max Perform the fixed-point format G with the alignment above.

[0154] Let l be the exponent, such that e l =e max For the largest exponent. The number in format G is obtained via... Given a signed integer, its value is in Within the range and representing real numbers Each input floating-point number x i Converted to fixed-point values The rounding option will be implemented later.

[0155] Then the fixed-point values ​​are added together, and their sum is converted back to its original format to produce the result. The rounding option will also be implemented later.

[0156] For the purposes of this analysis, the numbers in the input array are divided into two categories: small numbers, whose exponents are less than 10 ... And large numbers, whose index is between and e l之间 The input array is divided into smaller numbers x′. ０ ,...,x′ k′-1 Arrays and large numbers x′ k′ ,...,x′ k-z , x′ k-1 =x l An array. The count of small numbers k′ is verified to be 0 ≤ k′ ≤ k-1. For all i = 0, ..., k-1, ..., n′ i and e′ i They represent x′ respectively i The significant numbers and exponents, and p′ i Represents x′ i Convert to fixed-point format G, so that It should be noted that while small numbers may be subject to rounding errors, large numbers are represented precisely.

[0157] sequence w i By making To construct, where i = 0, ..., k-2, and w k-1 =y. Think back. therefore In this decomposition, two lemmas concerning the magnitude of the intermediate sum are proved.

[0158] First, it was proven that no underflow occurs in format G when adding a small number to a number with the largest exponent.

[0159] Lemma 1: If x l If normalized, then

[0160]

[0161] This is true for all i = 1, ..., k′-1.

[0162] Proof: Proved by induction This is true for all i = 1, ..., k′-1. Let i be an integer between 1 and k′-1. First, by using the triangle inequality... Then, since i≤k′-1, we obtain the following by assumption. also, It can be represented by G, therefore after rounding, we get

[0163] If i = 1, then Because x l It can be represented by G elements, and then... Because x l It has been normalized.

[0164] If i > 1, then by inductive hypothesis

[0165] In either case, obtain This concludes the induction. As a direct result, we obtain... Make This holds true for all i = 1, ..., k′-1, since k′ ≤ k-1.

[0166] Next, we will prove that no overflow occurs in format G when all other numbers are added to the number with the largest exponent.

[0167] Lemma 2: If x l If normalized, then This is true for all i = 1, ..., k-1.

[0168] Proof: Point out This is true for all i = 0, ..., k-1, because x l It is the largest input index, and then Because of value It can be represented by G elements. Therefore This holds true for all i = 1, ..., k-1, obtained through direct induction on i. Then...

[0169] The worst-case accuracy of architecture 300 is stated and proved in the following theorem.

[0170] Theorem 1: For any array x0, ..., x... k-1 There will exist x0, ..., x k-1 The sum of pairwise average rounding z is such that a set of inputs x0, ..., x... k-1 Applying this to architecture 300 will produce output y, making

[0171] Proof: Focus on x l In the case of normalization, other cases pose no difficulty. Consider the sequence u0, ..., u k-1 , such that u0 = x l and u i It is u in F i-1 +x′ i-1 The maximum lower bound holds for all i = 1, ..., k-1, and for sequences v0, ..., v k-1 , such that v0 = x l and v i It is v in F i-1 +x′ i-1 The minimum lower bound holds for all i = 1, ..., k-1. These sequences define the sum u of paired reasonable rounding. k-1 and v k-1 This is obtained by systematically rounding the intermediate sums in the same direction. It is obvious. Claim u i ≤w i ≤v i This holds true for all i = 0, ..., k-1, such that u k-1 ≤y≤v k-1 This way you can get it immediately. Where z = u k-1 Or z = v k-1 ...

[0172] By inductive proof, u i ≤w i ≤v i This holds true for all i = 0, ..., k-1.

[0173] i = 0: By definition, u0 = v0 = x l And w0 = x lBecause w0≈ G x l And x l It can be represented by G.

[0174] i = 1, ..., k′-1: Obtain u by inductive hypothesis. i-1 ≤w i-1 ≤v i-1 Then u i-1 +x′ i-1 ≤w i-1 +x′ i-1 ≤v i-1 +x′ i-1 Furthermore, by means of Lemma 1 and Lemma 2, we obtain This makes G, compared to F, in w i-1 +x′ i-1 The neighborhood is more precise because for the exponent range G, it accommodates at least the same number of mantissa bits as F. Since G is a fixed-point format and the sum does not overflow or underflow, x′ i舍入 Then add the result to w i-1 Equivalent to x′ i-1 Add to w i-1 Then round the result. To obtain u... i It is u in F i-1 +x′ i-1 The maximum lower bound of , and less than or equal to u in G. i-1 +x′ i-1 The maximum lower bound of v. Similarly, v i It is u in F i-1 +x′ i-1 The minimum upper limit of, and greater than or equal to u+i-1′ in G. u i-1. Therefore, according to the definition of proper rounding, we obtain u. i ≤w i ≤v i . ·

[0175] i = k′, k′+1, ..., k-2: u is obtained through inductive hypothesis. i-1 ≤w i-1 ≤v i-1 Then u i-1 +x′ i-1 ≤w i-1 +x′ i-1 ≤v i-1 +x′ i-1 Because x′ i It is a large number, so it can be represented by G, and after Lemma 2, we obtain w. i =w i-1 +x′ i-1Because u i ≤u i-1 +x′ i-1 and v i ≥v i-1 +x′ i-1 , obtain u i ≤w i ≤v i , ·

[0176] i = k-1: According to the inductive hypothesis, u k-2 +x′ k-2 ≤w k-2 +x′ k-2 ≤v k-2 +x′ k-2 Using similar parameters as before, we can obtain... Compared to any of G, w k-2 +x′ k-2 and The F in the neighborhood is more accurate. Then, by the definition of average rounding, w is obtained according to Proposition 1. k-1 ≈ F w k-2 +x′ k-2 Then u k-1 ≤w k-1 ≤v k-1 .

[0177] Similar reasoning applies to x l The non-normal value. In this case, all intermediate sums can be represented by G, so only the final rounding results in a loss of precision. As before, the final rounding preserves the order. l An infinite OR NaN input value results in an infinite OR NaN output value, which does not involve rounding.

[0178] Figure 9 A computer system is shown in which the graphics processing system described herein can be implemented. The computer system includes a CPU 902, a GPU 904, memory 906, and other devices 914, such as a display 916, a speaker 918, and a camera 908. A processing block 910 (corresponding to processing block 110) is implemented on the GPU 904. In other examples, processing block 910 may be implemented on the CPU 902. Components of the computer system can communicate with each other via a communication bus 920. A memory repository 912 (corresponding to memory repository 112) is implemented as part of memory 906.

[0179] Although Figure 9An implementation of the graphics processing system is shown, but it should be understood that a similar block diagram can be drawn for an artificial intelligence accelerator system—for example, by replacing the GPU 904 with a neural network accelerator (NNA), or by adding an NNA as an additional unit. In such a case, an adder architecture 300 can be implemented in the NNA.

[0180] The adder described herein can be embodied in hardware on an integrated circuit. Generally, any of the functions, methods, techniques, or components described above can be implemented in software, firmware, hardware (e.g., a fixed logic circuit system), or any combination thereof. The terms “module,” “function,” “component,” “element,” “cell,” “block,” and “logic” are used herein to generally denote software, firmware, hardware, or any combination thereof. In the case of a software implementation, a module, function, component, element, cell, block, or logic represents program code that, when executed on a processor, performs a specified task. The algorithms and methods described herein can be executed by one or more processors that execute code that causes the processor to perform the algorithm / method. Examples of computer-readable storage media include random access memory (RAM), read-only memory (ROM), optical disk, flash memory, hard disk storage, and other memory devices that can use magnetic, optical, and other techniques to store instructions or other data and can be accessed by a machine.

[0181] As used herein, the terms computer program code and computer-readable instructions refer to any kind of executable code for a processor, including code expressed in machine language, interpreted language, or scripting language. Executable code includes binary code, machine code, bytecode, code defining integrated circuits (such as hardware description languages ​​or netlists), and code expressed in programming languages ​​such as C, Java, or OpenCL. Executable code can be, for example, any kind of software, firmware, script, module, or library that, when properly executed, processed, interpreted, compiled, or run in a virtual machine or other software environment, causes the processor of a computer system that supports the executable code to perform the tasks specified by that code.

[0182] A processor, computer, or computer system can be any kind of device, machine, or special-purpose circuit, or a collection or part thereof, that has the processing power to execute instructions. A processor can be any kind of general-purpose or special-purpose processor, such as a CPU, GPU, NNA, system-on-a-chip, state machine, media processor, application-specific integrated circuit (ASIC), programmable logic array, field-programmable gate array (FPGA), etc. A computer or computer system may include one or more processors.

[0183] This invention also intends to cover software that defines the configuration of hardware as described herein, such as hardware description language (HDL) software, for designing integrated circuits or for configuring programmable chips to perform desired functions. Specifically, a computer-readable storage medium may be provided on which computer-readable program code in the form of an integrated circuit definition dataset (also referred to as a hardware design) is encoded, which, when processed (i.e., run) in an integrated circuit manufacturing system, configures the system to manufacture a computing device including any of the devices described herein. The integrated circuit definition dataset may, for example, be an integrated circuit description.

[0184] Therefore, a method for manufacturing an adder architecture as described herein can be provided at an integrated circuit manufacturing system. Furthermore, an integrated circuit definition dataset can be provided, which, when processed in the integrated circuit manufacturing system, enables the method for manufacturing the adder to be executed.

[0185] Integrated circuit definition datasets can be in the form of computer code, such as netlists, code for configuring programmable chips, or hardware description languages ​​suitable for manufacturing at any level in integrated circuits, including register-transfer level (RTL) code, high-level circuit representations (such as Verilog or VHDL), and low-level circuit representations (such as OASIS(RTM) and GDSII). Higher-level representations (such as RTL) that logically define hardware suitable for manufacturing in integrated circuits can be processed on a computer system configured to generate manufacturing definitions of integrated circuits within the context of a software environment that includes definitions of circuit elements and rules for combining these elements to generate the manufacturing definitions of the integrated circuits defined by that representation. As is typically the case where software executes at a computer system to define a machine, one or more intermediate user steps (e.g., providing commands, variables, etc.) may be required to configure the computer system to generate the manufacturing definitions of the integrated circuits, executing code that defines the integrated circuits to generate the manufacturing definitions of said integrated circuits.

[0186] Now regarding Figure 10 Describe an example of processing integrated circuit definition datasets (e.g., hardware designs) on an integrated circuit manufacturing system in order to configure the system for manufacturing adders.

[0187] Figure 10An example of an integrated circuit (IC) manufacturing system 1002 configured to manufacture an adder as described in any of the examples herein is shown. Specifically, the IC manufacturing system 1002 includes a layout processing system 1004 and an integrated circuit generation system 1006. The IC manufacturing system 1002 is configured to receive an IC definition dataset / hardware design (e.g., defining an adder as described in any of the examples herein), process the IC definition dataset, and generate an IC (e.g., embodying an adder as described in any of the examples herein) based on the IC definition dataset. The processing of the IC definition dataset configures the IC manufacturing system 1002 to manufacture an integrated circuit embodying an adder as described in any of the examples herein.

[0188] The layout processing system 1004 is configured to receive and process an IC definition dataset / hardware design to determine a circuit layout. Methods for determining a circuit layout based on an IC definition dataset are known in the art and may involve, for example, synthesizing RTL code to determine the gate-level representation of the circuit to be generated, for example, in relation to logic components (e.g., NAND, NOR, AND, OR, MUX, and FLIP-FLOP components). By determining the location information of the logic components, the circuit layout can be determined based on the gate-level representation of the circuit. This can be done automatically or with user intervention to optimize the circuit layout. Once the layout processing system 1004 has determined the circuit layout, it can output the circuit layout definition to the IC generation system 1006. The circuit layout definition may be, for example, a circuit layout description.

[0189] As is known in the art, IC generation system 1006 generates ICs according to a circuit layout definition. For example, IC generation system 1006 may implement a semiconductor device manufacturing process for generating ICs, which may involve a multi-step sequence of photolithography and chemical processing steps, during which electronic circuits are gradually formed on a wafer made of semiconductor material. The circuit layout definition may be in the form of a mask, which can be used in the photolithography process to generate ICs according to the circuit definition. Alternatively, the circuit layout definition provided to IC generation system 1006 may be in the form of computer-readable code, which IC generation system 1006 can use to form a suitable mask for generating ICs.

[0190] The various processes performed by the IC manufacturing system 1002 can all be implemented in one location, for example, by one party. Alternatively, the IC manufacturing system 1002 can be a distributed system, allowing some processes to be performed at different locations and by different parties. For example, some of the following stages can be performed at different locations and / or by different parties: (i) synthesizing RTL code representing an IC definition dataset to form a gate-level representation of the circuit to be generated; (ii) generating a circuit layout based on the gate-level representation; (iii) forming a mask based on the circuit layout; and (iv) using the mask to manufacture the integrated circuit.

[0191] In other examples, processing an integrated circuit definition dataset at an integrated circuit manufacturing system can configure the system to manufacture adders without processing the IC definition dataset to determine circuit layout. For example, an integrated circuit definition dataset can define the configuration of a reconfigurable processor such as an FPGA, and processing the dataset can configure the IC manufacturing system (e.g., by loading the configuration data into the FPGA) to generate a reconfigurable processor with the defined configuration.

[0192] In some implementations, when an integrated circuit manufacturing definition dataset / hardware design is processed in an integrated circuit manufacturing system, the integrated circuit manufacturing system can generate an apparatus as described herein. For example, using an integrated circuit manufacturing definition dataset, as referenced above... Figure 10 The described method allows for the configuration of an integrated circuit manufacturing system to produce devices as described herein.

[0193] In some examples, an integrated circuit definition dataset may include software running on hardware defined at the dataset, or software running in combination with hardware defined at the dataset. Figure 10 In the example shown, the IC generation system can be further configured by the integrated circuit definition dataset / hardware design to load firmware onto the integrated circuit according to the program code defined at the integrated circuit definition dataset during the manufacturing of the integrated circuit, or otherwise provide program code to the integrated circuit for use with the integrated circuit.

[0194] Compared to known implementations, the concepts set forth in this application, when implemented in devices, apparatuses, modules, and / or systems (and the methods practiced herein), can lead to performance improvements. Performance improvements may include one or more of increased computational performance, reduced latency, increased throughput, and / or reduced power consumption. During the manufacture of such devices, apparatuses, modules, and systems (e.g., in integrated circuits), trade-offs can be made between performance improvements and physical implementation methods, thereby improving manufacturing processes. For example, a trade-off can be made between performance improvements and layout area, thereby matching the performance of known implementations but using less silicon. This can be accomplished, for example, by reusing functional blocks serially or sharing functional blocks among elements of a device, apparatus, module, and / or system. Conversely, the concepts set forth in this application that lead to improvements in the physical implementation of devices, apparatuses, modules, and systems (such as reduced silicon area) can be traded off for performance improvements. This can be accomplished, for example, by manufacturing multiple instances of a module within a predefined area budget.

[0195] The applicant has independently disclosed each individual feature described herein, as well as any combination of two or more such features, to the extent that such features or combinations can be implemented based on the specification as a whole, in accordance with the common knowledge of those skilled in the art, regardless of whether such features or combinations of features solve any problem disclosed herein. In view of the foregoing description, those skilled in the art will understand that various modifications can be made within the scope of this invention.

Claims

1. A method for processing a set of 'k' floating-point numbers using a hardware implementation to perform addition and / or subtraction, where k ≥ 3, each floating-point number including a mantissa (m i ) and index (e i The method includes: Receive the group of 'k' floating-point numbers in a first format, each of the first format including a mantissa of length 'b' bits (m i ); A set of 'k' numbers (y) is generated based on the mantissa of the 'k' floating-point number. i The number is formed by adding an extra most significant bit and an extra least significant bit to the mantissa (m). i The bit length of 'n' bits is obtained by using the bit length 'b' of the given bit length, wherein the 'n' bits include multiple value bits, where 'n' is... The number of bits is denoted by x, where x is an integer and x ≥ 1 and x ≤ 3. Identify the index e i The largest exponent (e) in max ); Based on the maximum index (e) max Align the number (y) i The value of the quantity; and Simultaneously process the group 'k' numbers.

2. The method of claim 1, wherein the group 'k' floating-point number received in a first format comprises: Unsigned floating-point numbers that explicitly include a leading bit; or An unsigned floating-point number that implicitly includes a leading bit and x ≥ 2.

3. The method of claim 1, wherein the group 'k' floating-point number received in a first format comprises: A signed floating-point number that explicitly includes a leading bit and x ≥ 2; or A signed floating-point number that implicitly includes a leading bit and x=3.

4. The method of claim 1, wherein adding additional most significant bits comprises adding at least The number of the most significant bits, and / or where adding additional least significant bits includes adding at least The number of least significant bits.

5. The method of claim 2, wherein adding additional most significant bits comprises adding a leading bit in the case that the received group 'k' floating-point number of the first format implicitly includes a leading bit, wherein the method comprises adding a leading bit by means of the mantissa m of the floating-point number. i The number (y) is formed by adding the leading bit before the digit. i The value of the quantity is ).

6. The method of claim 1, wherein the method further comprises: By processing the 'k' number (y i Use this to calculate the output value; Renormalize the output value; as well as The output value is rounded to represent it as a floating-point number.

7. The method of claim 1, wherein the number (y) i The magnitude alignment of the value is based on the maximum exponent (e). max This includes the following steps: For each floating-point number (i): Calculate the maximum exponent (e) max ) and index (e i The difference between (e) d );as well as Based on the calculated difference (e) d ), and the corresponding number (y) i The value of the displacement is shifted to the LSB side.

8. The method of claim 7, wherein: To further shift the value bits of the number, the method further includes truncating the bits of the number that have been shifted beyond the bit length of the number; or The method further includes, if the group 'k' floating-point numbers include signed floating-point numbers, then based on the sign bit (s) of each corresponding number... i The complement of the value of the number is determined by the two's complement of the two's complement.

9. A hardware implementation for processing a set of k floating-point numbers to perform addition and / or subtraction, k ≥ 3, each floating-point number including a mantissa (mi) and an exponent (e). i The hardware implementation includes: Format conversion unit, the format conversion unit being configured to: Receive the group of 'k' floating-point numbers in a first format, each of the first format including the mantissa (m) of length 'b' bits. i );and The mantissa (m) of the group of 'k' floating-point numbers i Convert ) into a set of 'k' numbers (y i The number (y) i ) has the ability to add an extra most significant bit and an extra least significant bit to the mantissa (m) i The bit length of 'n' bits is obtained by using the bit length 'b' of the given bit length, wherein the 'n' bits include a plurality of value bits, and wherein 'n' is a... The number of bits is denoted by x, where x is an integer and x ≥ 1 and x ≤ 3. Maximum exponent detection unit, the maximum exponent detection unit being configured to identify the exponent e i The largest exponent (e) in max ); Alignment unit, the alignment unit being configured based on the maximum exponent (e) max Align the value bit of the number; as well as A processing unit configured to simultaneously process the group of 'k' numbers to generate an output value.

10. The hardware embodiment of claim 9, wherein the format conversion unit receives the group 'k' floating-point number in a first format, the group 'k' floating-point number in the first format comprising: Unsigned floating-point numbers that explicitly include a leading bit; or An unsigned floating-point number that implicitly includes a leading bit and x ≥ 2.

11. The hardware embodiment of claim 9, wherein the format conversion unit receives the group 'k' floating-point number in a first format, the group 'k' floating-point number in the first format comprising: A signed floating-point number that explicitly includes a leading bit and x ≥ 2; or A signed floating-point number that implicitly includes a leading bit and x=3.

12. The hardware implementation of claim 9, further comprising a renormalization unit, the renormalization unit being configured to: The output value is renormalized; and The output value is rounded to represent it as a floating-point number.

13. The hardware implementation of claim 9, wherein if the received group 'k' floating-point number in the first format implicitly includes a leading bit, the format conversion unit converts the mantissa (m) by adding a leading bit. i ).

14. The hardware embodiment of claim 9, wherein the format conversion unit, when generating the number, performs a conversion on each mantissa (m) i Add the added leading bit before it.

15. The hardware embodiment of claim 9, wherein the alignment unit aligns the magnitude bits of the digit based on the maximum exponent (e). max The alignment unit includes: Multiple subtraction units, wherein each subtraction unit is configured to calculate the maximum exponent (e) max ) and the exponent (e) of each floating-point number (i) i The difference between (e) d ); as well as Multiple shifter units, each configured based on the calculated difference (e d The corresponding numerical value is shifted to the LSB side.

16. The hardware embodiment of claim 15, wherein the alignment unit further truncates the bits of the number shifted to outside the bit length of the number.

17. The hardware implementation of claim 15, wherein the alignment unit further comprises a plurality of two's complement units, the plurality of two's complement units being configured to, if the group 'k' floating-point number includes a signed floating-point number, base the alignment on the sign bit (s) of the corresponding number. i To determine the complement of each number's value, we use the two's complement of the two's complement.

18. A computer-readable code configured to cause the method of any one of claims 1 to 8 to be performed when the code is executed.

19. A computer-readable storage medium having encoded thereon the computer-readable code as claimed in claim 18.

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