Source driving circuit and operation method thereof

Abstract

The present invention provides a source driving circuit, which is applicable to a display panel. The source driving circuit includes a data channel and a control circuit. The data channel is configured to be coupled to a data line of a display panel, and sequentially drive the data line of the display panel according to first display data and second display data. The first display data corresponds to a first scan line of the display panel, and the second display data corresponds to a second scan line of the display panel next to the first scan line of the display panel. The control circuit is coupled to the data channel, and is used to control the time point at which the data channel outputs the second display data according to the similarity between the first display data and the second display data.

Description

Technical Field

[0001] The present invention relates to a source driving circuit, and in particular to a source driving circuit capable of controlling the output time point of display data. Background Art

[0002] In the driver IC of the display panel, the switching of the output grayscale data may cause the gamma reference voltage in the driver IC to be disturbed, which requires recovery time. However, during this recovery time, the interference still exists, so crosstalk interference occurs in the grayscale data that does not need to be switched.

[0003] Figure 1A is a schematic diagram illustrating a display screen having a crosstalk interference phenomenon. Figure 1B Schematic diagram showing the waveform of grayscale data during switching. Figure 1A , the background color of the display screen 100 is black ( Figure 1A A uniform black dot in the region R1 is schematically represented), and the corresponding grayscale data is, for example, +255 (or -255). An area close to white is provided in the middle of the black background color, and the corresponding grayscale data is, for example, +5 (or -5). When the scan line scans region R1, the grayscale data transmitted through channel Ch1 changes from +255 to +5. Similarly, the grayscale data transmitted through channel Ch2 in region R1 changes from -255 to -5. Simply put, the grayscale data transmitted through channels Ch1 to Ch640 in region R1 is transmitted (i.e., the grayscale data is switched), and the grayscale data transmitted through all channels after channel Ch640 (including channel Ch960) should remain black. However, due to the influence of the transition from channel Ch1 to Ch640, the grayscale voltages transmitted through all channels after channel Ch640 are affected accordingly. Therefore, in region R2, unwanted light that is easily recognized by the human eye appears, which is a crosstalk interference phenomenon. In fact, the transition of the channel Ch1 to Ch640 in the region R3 may also affect the grayscale voltage transmitted through all channels after the channel Ch640. Therefore, a dark line that is difficult for the human eye to recognize appears in the region R4.

[0004] Reference together Figure 1A and Figure 1B , channels Ch1, Ch2 and Ch960 send grayscale data S respectively Ch1 , S Ch2 and S Ch960 In region R, the grayscale data S Ch1 From +255 to +5, the grayscale data S Ch2 From -255 to -5, and the grayscale data S Ch960Ideally, it is kept at -5. However, in reality, due to the influence of instantaneous current loading, the source voltage that generates grayscale data may be disturbed. Grayscale data S Ch960 The voltage value of is decreased (see region 101). Note that for ease of description and presentation of a concise diagram, Figure 1B Only the changes of the signal curves of channels Ch1, Ch2 and Ch960 over time are shown. In fact, except for the grayscale voltage transmitted by channel Ch960, the grayscale voltages transmitted by all channels after channel Ch640 will be affected.

[0005] In order to solve the above problem, the recovery speed of the gamma reference voltage can be accelerated (i.e., the recovery time can be reduced) by increasing the combination point of the gamma reference voltage or increasing the current of the gamma reference resistor string. However, in the above manner, the analog current is increased, thereby increasing the analog power consumption. Therefore, it is necessary to provide a solution that can prevent the grayscale data that does not need to be switched from being affected and the analog power consumption from increasing. Summary of the invention

[0006] The invention provides a source driving circuit capable of preventing grayscale data from being disturbed.

[0007] According to an embodiment of the present invention, a source driving circuit includes a data channel and a control circuit. The data channel is configured to be coupled to a data line of a display panel and sequentially drive the data line of the display panel according to first display data and second display data. The first display data corresponds to a first scan line of the display panel, and the second display data corresponds to a second scan line of the display panel next to the first scan line of the display panel. The control circuit is coupled to the data channel to control the time point at which the data channel outputs the second display data according to the similarity between the first display data and the second display data.

[0008] According to an embodiment of the present invention, a source driving circuit includes a data channel and a control circuit. The data channel is configured to be coupled to a data line of a display panel and sequentially drive the data line of the display panel according to first display data and second data. The first display data corresponds to a first scan line of the display panel, and the second display data corresponds to a second scan line next to the first scan line of the display panel. The control circuit is coupled to the data channel and configured to determine whether to generate a delay time at a time point when the data channel outputs the second display data according to a similarity between the second display data and the first display data.

[0009] According to an embodiment of the present invention, an operating method of a source driving circuit comprises the following steps: sequentially driving data lines of a display panel according to first display data and second display data; and determining whether to generate a delay time for delaying the time point of outputting the second display data according to the similarity between the second display data and the first display data.

[0010] In summary, in the present invention, the first display data and the second display data are compared to determine whether to delay the output time point of the second display data. In this way, the time point of outputting the second display data can avoid the time period during which the source voltage may be disturbed.

[0011] In order to make the foregoing content more easily understood, several embodiments of the drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0013] Figure 1A is a schematic diagram illustrating a display screen having a crosstalk interference phenomenon.

[0014] Figure 1B is a schematic diagram illustrating the waveform of grayscale data during switching.

[0015] Figure 2 is a schematic diagram of a block diagram of a source driving circuit provided by the present disclosure.

[0016] Figure 3 is a flow chart illustrating steps of an operating method of a source driver circuit according to an embodiment of the present invention.

[0017] Figure 4 is a flow chart illustrating steps of an operating method of a source driver circuit according to an embodiment of the present invention.

[0018] Figure 5 is a flow chart illustrating steps of an operating method of a source driver circuit according to an embodiment of the present invention.

[0019] Figure 6 is a flow chart illustrating steps of an operating method of a source driver circuit according to an embodiment of the present invention.

[0020] Figure 7 is a schematic diagram showing a block diagram of a control circuit according to an embodiment of the present disclosure.

[0021] Figure 8 FIG. 4 is a schematic diagram illustrating signal waveforms of a source driving circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0023] Figure 2Schematic diagram of a source driver circuit provided by the present disclosure. Figure 2 , the source driving circuit 200 includes a bidirectional shift register 210, a data receiver 220, a first register 230, a second register 240, a level shifter 250, a digital-to-analog converter 260, a control circuit 270, and an output buffer 280. In the above circuits, except for the control circuit 270, the remaining circuits belong to the relevant field, and those skilled in the art should be familiar with their functions. Therefore, except for the control circuit 270, the remaining circuits are briefly described as follows.

[0024] Reference Figure 2 , clock signal S CLOCK is provided to both the bidirectional shift register 210 and the data receiver 220. The data receiver 220 receives the grayscale data S at a first time point. DATA (hereinafter referred to as the first display data, including grayscale data of red R, green G and blue B, for example). The first register 230 is configured to store the first display data. Next, the first display data is moved from the first register 230 to the second register 240 for storage. At this time, the first register 230 stores the grayscale data S received by the data receiver 220 at the second time point. DATA (hereinafter referred to as the second display data). The second time point is just after the first time point in the time sequence. In terms of the structure of the pixel circuit of the panel, the first display data is equivalent to the data channel corresponding to the first scanning time sequence (for example, Figure 1A The second display data is equal to the grayscale data sent by the same data channel corresponding to the second scanning time sequence. The second scanning time sequence is just after the first scanning time sequence.

[0025] In the related art, the first display data is sequentially transmitted by the second register 240, the level shifter 250 and the digital-to-analog converter (also called D / A converter or DAC) 260, and the data output is performed by the output buffer 280 (i.e., the data Y1 to Y384 are output to the corresponding data lines of the panel through the data channel). GAMMA is provided to the digital-to-analog converter 260. The polarity data S POLis provided to the digital-to-analog converter 260 and the output buffer 280. In the present invention, the control circuit 270 can be configured to control the output time of the output buffer 280 to control the time point at which the data channel outputs the second display data according to the similarity between the first display data and the second display data. More specifically, the control circuit 270 can determine whether to delay the output time point of the second display data according to the polarity identity and data similarity between the first display data and the second display data. In this way, the time point at which the second display data is output can avoid a time period during which the source voltage may be interfered. The implementation of the control circuit 270 is described in detail below through an operation flow chart.

[0026] In some embodiments, when the second display data is similar to the first display data, the duration of the delay time is fixed. For example, even when the second display data is more similar to the first display data, the duration of the delay time is the same.

[0027] In some other embodiments, the length of the delay time depends on the similarity between the second display data and the first display data. For example, when the second display data is more similar to the first display data, the length of the delay time is longer.

[0028] Figure 3 1 is a flow chart illustrating the steps of the operating method of the source driving circuit according to an embodiment of the present invention. Figure 3 In step S310, the data channel drives the data line of the display panel according to the first display data and the second display data in sequence. Here, the first display data corresponds to the first scan line of the display panel, and the second display data corresponds to the second scan line of the display panel next to the first scan line of the display panel. This means that in the transmission sequence, the second display data follows the first display data. In step S320, the control circuit 270 determines whether to generate a delay time to delay the time point of outputting the second display data according to the data similarity between the second display data and the first display data.

[0029] Specifically, in step S320, the control circuit 270 may compare the polarity and the bit value between the first display data and the second display data. When the polarity of the first display data is the same as the polarity of the second display data and the amount of the same bit value of the first display data and the second display data is equal to or greater than the threshold value, the control circuit 270 determines that the first display data and the second display data are similar. In one embodiment, when the polarity of the first display data is the same as the polarity of the second display data (for example, both are +) and the bit value of the first display data is exactly the same as the bit value of the second display data (both are "11111111", for example, meaning that the grayscale data is 255), the control circuit determines that the first display data and the second display data are similar. In another embodiment, when 5 identical bit values ​​are provided between the first display data and the second display data (for example, the first display data is "11111111", and the second display data is "11111000"), the control circuit determines that the first display data and the second display data are similar. In another embodiment, when 6 identical bit values ​​are provided between the first display data and the second display data (for example, the first display data is "11111111", and the second display data is "11111100"), the control circuit determines that the first display data and the second display data are similar. The designer can determine the degree of similarity between the first display data and the second display data according to actual needs (requiring all bit values ​​to be the same or only requiring part of the bit values ​​to be the same) to determine that the first display data and the second display data are similar. In addition, when it is determined that the first display data and the second display data have the same polarity and show data similarity, the control circuit 270 delays the time point of outputting the second display time.

[0030] In short, Figure 1A For example, in the present disclosure, the control circuit 270 learns by comparison that the grayscale data of the black background and the grayscale data of the white frame do not change with the scanning sequence. Therefore, the control circuit 270 can delay the output time point of the grayscale data except for the regions R1 and R3 by a delay time, so that the output time point can avoid the time period when the source voltage may be disturbed. In this way, the crosstalk interference phenomenon that may occur is reduced or eliminated. During the delay time, the output end of the data channel is in a floating state. Various exemplary implementations of the output time point of delayed grayscale data are provided below.

[0031] Figure 4 1 is a flow chart illustrating the steps of the operating method of the source driving circuit according to an embodiment of the present invention. Figure 1A , Figure 1B and Figure 4First, the source driving circuit 200 receives the grayscale data corresponding to the Nth scanning sequence (which can be regarded as the first display data), where N is a positive integer (step S410). Next, the first display data is stored in the first register 230 (step S420). The first display data is then moved from the first register 230 to the second register 240 for storage, and the source driving circuit 200 receives the grayscale data corresponding to the N+1th scanning sequence (which can be regarded as the second display data), and stores the grayscale data corresponding to the N+1th scanning sequence (equivalent to the second display data) in the first register 230 (step S430). The first display data in the second register 240 is sent to the digital-to-analog converter 260 (step S440).

[0032] Then, the control circuit 270 determines whether the first display data and the second display data are similar, for example, by comparing to determine whether the polarity of the first display data and the polarity of the second display data are the same, and determines whether the data of the first display data and the data of the second display data are the same (step S450). When the first display data and the second display data have the same polarity and have similar data, the control circuit 270 sets the first display data to be output at a predetermined output time point (for example, output at the rising edge of the load (LD) signal), and sets the second display data to be output at a delay time later than the predetermined output time point (for example, delayed to output at the falling edge of the LD signal) (step S460). On the contrary, when the first display data and the second display data are not similar, for example, have different polarities and / or have different data, the control circuit 270 sets the first display data and the second display data to be output at a predetermined output time point (for example, output at the rising edge of the LD signal) (step S470). Finally, the value of N+1 is designated as a new N value (expressed as N=N+1), and step S410 is performed again (step S480). Note that the LD signal may be a control signal configured to control a point in time at which display data is loaded or output to a data line. In other words, the LD signal may be a control signal for indicating a point in time at which a data channel sends or loads or outputs display data to be displayed on each row of a display panel, which is known to those of ordinary skill in the art.

[0033] by Figure 1AFor example, for the display data sent by the channel after channel 640, the control circuit 270 provided by the present invention can set the display data corresponding to the first scan sequence to be output at the rising edge of the LD signal to be output at the rising edge of the LD signal, and set the display data corresponding to the second scan sequence to be delayed to be output at the falling edge of the LD signal (because the polarity and data of the display data of the first scan sequence are the same as the polarity and data of the display data of the second scan sequence). In addition, the control circuit 270 can control the delay of the display data corresponding to the third scan sequence to be output at the falling edge of the LD signal (because the polarity and data of the display data corresponding to the second scan sequence and the polarity and data of the display data corresponding to the third scan sequence are the same). That is, all output time points of similar or identical display data corresponding to a scan sequence later than the first scan sequence can be delayed.

[0034] In the above embodiment, when the first display data and the second display data have the same polarity and have similar data, the control circuit 270 sets the first display data and the second display data to be output at different types of edges of the same control signal (e.g., LD signal). In more other embodiments, when the first display data and the second display data have the same polarity and have similar data, the control circuit 270 sets the first display data and the second display data to be output based on different control signals that can be generated based on the LD signal. In such an embodiment, the same or different types of edges of different control signals can be used to trigger the display data to be output or loaded to the corresponding data line.

[0035] Figure 5 is a flow chart illustrating the steps of the operating method of the source driving circuit according to an embodiment of the present invention. Here, steps S510 to S550 and S580 are similar to Figure 4 Steps S410 to S450 and S480 in FIG. 4 are described in detail, and therefore will not be described again here. Figure 1A , Figure 1B and Figure 5 When the first display data and the second display data have the same polarity and similar data, the control circuit 270 sets the first display data to be output at a predetermined rising edge of the LD signal, and sets the second display data to be output at a falling edge of the mask LD signal (step S560). When the first display data and the second display data have different polarities and / or different data, the control circuit 270 sets both the first display data and the second display data to be output at a rising edge of the LD signal (step S570).

[0036] It should be noted that the mask LD signal is generated by the control circuit 270. The mask LD signal may be a signal generated by masking the LD signal. Due to the masking operation, the time point of the rising edge of the mask LD signal may coincide with the time point of the rising edge of the LD signal, but the time point of the falling edge of the mask LD signal may be after the time point of the falling edge of the LD signal. That is, the rising starting point of the mask LD signal and the LD signal is the same, but the holding time of the high voltage level of the mask LD signal (i.e., the pulse width) is longer than the holding time of the high voltage level of the LD signal (i.e., the pulse width). Since the pulse width of the LD signal is determined by the designer, in the case where the pulse end of the LD signal is too short to completely prevent the source voltage from being disturbed, it can be used. Figure 5 The operation shown is to prevent the source voltage from being disturbed.

[0037] Figure 6 is a flow chart illustrating the steps of the operating method of the source driving circuit according to an embodiment of the present invention. Here, steps S610 to S650 and S680 are similar to Figure 4 Steps S410 to S450 and S480 in FIG. 4 are described in detail, and therefore will not be described again here. Figure 1A , Figure 1B and Figure 6 When the first display data and the second display data have the same polarity and similar data, the control circuit 270 sets the first display data to be output at a predetermined falling edge of the LD signal, and sets the second display data to be output at a falling edge of the mask LD signal (step S660). When the first display data and the second display data have different polarities and / or different data, the control circuit 270 sets both the first display data and the second display data to be output at a falling edge of the LD signal (step S670). In the case where the pulse width of the mask LD signal is long enough (determined by the designer), it is also possible to use Figure 6 The operation shown is to prevent the source voltage from being disturbed.

[0038] It should be noted that in more other embodiments, the time point of the rising edge of the mask LD signal may be after the time point of the rising edge of the LD signal. When the first display data and the second display data have the same polarity and have similar data, the control circuit 270 sets the first display data to be output at the rising edge of the LD signal, and sets the second display data to be output at the rising edge of the mask LD signal. When the first display data and the second display data have different polarities and / or different data, the control circuit 270 sets both the first display data and the second display data to be output at the rising edge of the LD signal.

[0039] In some embodiments, the control circuit is configured to, when the second display data is similar to the first display data, control the second display data to be output to the data line at a first transition edge of the data output control signal; and when the second display data is not similar to the first display data, control the second display data to be output to the data line at a second transition edge of the data output control signal, wherein the first transition edge of the data output control signal appears after the second transition edge of the data output control signal.

[0040] The data output control signal may be a load (LD) signal for indicating a time point at which the data channel transmits display data to be displayed on each row of the display panel.

[0041] In some embodiments, different types of edges of the same data output control signal can be used to trigger the display data to be output. More specifically, the first transition edge of the data output control signal can be the falling / rising edge of the data output control signal, and the second transition edge of the data output control signal can be the rising / falling edge of the same data output control signal.

[0042] In some embodiments, the same or different types of edges of different data output control signals may be used to trigger the display data to be output. More specifically, the data output control signal may include a first data output control signal and a second data output control signal.

[0043] The first data output control signal may be a load (LD) signal for instructing a time interval at which a data channel transmits display data to be displayed on each line of the display panel, and the second data output control signal may be a mask LD signal generated by causing the LD signal to be displayed.

[0044] The control circuit can also be configured to, when the second display data is similar to the first display data, control the second display data to be output to the data line at the rising / falling edge of the first data output control signal, and when the second display data is not similar to the first display data, control the second display data to be output to the data line at the rising / falling edge of the second data output control signal, wherein the rising / falling edge of the first data output control signal occurs after the rising / falling edge of the second data output control signal.

[0045] Figure 7 is a schematic diagram showing a block diagram of a control circuit according to an embodiment of the present disclosure. Figure 7 The control circuit 270 includes a multiplexer 271, a level shifter 272, an amplifier 273, and a switch M. The multiplexer 271 can be configured to control the level of the signal S SEL (Indicates that Figure 5 Step S550 or Figure 6The result determined in step S650 in the step S650) selects between the LD signal LD ​​to be output and the mask LD signal MLD to be used as the output signal. The multiplexer 271 belongs to a digital circuit, and the switch M belongs to an analog circuit, so the level shifter 272 is required to convert the first (e.g., low) voltage into a second (e.g., high) voltage so that the switch M can be turned on due to the increase in voltage. The non-inverting input terminal of the amplifier 273 receives the input signal S1 indicating the display data, and the output signal of the output terminal of the amplifier 273 is fed back to the inverting input terminal of the amplifier 273 to serve as the input signal of the non-inverting input terminal. The output signal of the amplifier 273 is transmitted to the first end of the switch M, and the output signal of the amplifier 273 is transmitted to the second end of the switch M to serve as the output signal S2 (i.e., determined according to the output signal of the level shifter 272). Figure 2 Therefore, the control circuit 270 can be used according to Figure 4 Step S450, Figure 5 Step S550 or Figure 6 The result determined in step S650 of step S650 determines whether to delay the output time point of the second display data. It should be noted that various implementations can be performed according to the switch control signal to open or close the output path of the data channel. For example, by using the switch control signal to control the switch and delaying the starting point of the on state of the switch by a delay time, the switch control signal can be generated to cause the delay time.

[0046] Figure 8 Schematic diagram of the signal waveform of the source driving circuit according to the embodiment of the present invention. Figure 8 , ChX represents the actual output signal of the Xth data channel, ChX+1 represents the actual output signal of the X+1th data channel, where X is a positive integer. D_ChX represents a voltage signal to be transmitted through the X-th data channel, LD represents an LD signal, MLD represents a mask LD signal, and S MUX Represents the output signal of the multiplexer. Figure 8 As shown, the output signal ChX+1 corresponding to the second display data is transmitted in the period between time points t2 and t3, and the output signal ChX of the adjacent X-th data channel does not change in the period between time points t2 and t3. Therefore, in the present invention, the source driver circuit can control the data voltage at point 801 to be output at the falling edge of the mask LD signal MLD by comparing the display data (second display data) at point 801 with the previous display data (i.e., the first display data). The LD signal LD ​​and the mask LD signal MLD are selectively provided to trigger the display data to be loaded or output to the corresponding data line. As shown in FIG. Figure 6 As shown in step S660, the multiplexer Figure 6 The control signal of the result determined in step S650 (see output signal S MUX ) selects the mask LD signal MLD to be output at time point t2 (see output signal S MUX ), so that the output signal ChX can avoid the period when the source voltage may be disturbed. By the way, since the data voltages at points 802 and 803 are transitional, the multiplexer such as Figure 6 As in step S670 of step S670, according to Figure 6 The LD signal LD ​​to be output at time points t1 and t4 is selected based on the control signal of the result determined in step S650, so that the source driving circuit does not delay the output time point of the output data voltage.

[0047] In view of this, in the present invention, the first display data and the second display data are compared, so that when the first display data and the second display data are similar according to the difference between them, the output time point of the second display data can be delayed. In this way, the time point of outputting the second display data can avoid the time period during which the source voltage may be interfered. In addition, with respect to the crosstalk problem in the display screen, in the present invention, since the binding point method used in the prior art to increase the gamma reference voltage is not adopted, the problem of increased analog power consumption is avoided.

[0048] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations as long as they fall within the scope of the following claims and their equivalents.

Claims

1. A source driving circuit, suitable for a display panel, characterized in that: The source driving circuit comprises: a data channel, for coupling to a data line of the display panel, and sequentially driving the data line of the display panel according to first display data and second display data, wherein the first display data corresponds to a first scan line of the display panel, and the second display data corresponds to a second scan line of the display panel next to the first scan line of the display panel; a control circuit coupled to the data channel and configured to control a time point at which the data channel outputs the second display data according to a similarity between the first display data and the second display data, The control circuit is configured to: When the second display data is similar to the first display data, controlling the second display data to be output to the data line at a first transition edge of a data output control signal; and When the second display data is not similar to the first display data, the second display data is controlled to be output to the data line at a second transition edge of the data output control signal, The first transition edge of the data output control signal appears after the second transition edge of the data output control signal.

2. The source driving circuit according to claim 1, characterized in that: The control circuit is configured to delay the time point by a delay time when the second display data is identical to or similar to the first display data.

3. The source driving circuit according to claim 2, characterized in that: During the delay time, the control circuit is configured to place the output terminal of the data channel in a floating state.

4. The source driving circuit according to claim 2, characterized in that: When the first display data and the second display data are similar, the time length of the delay time is fixed.

5. The source driving circuit according to claim 2, characterized in that: The length of the delay time depends on the similarity between the second display data and the first display data.

6. A source driving circuit, suitable for a display panel, characterized in that: The source driving circuit comprises: a data channel, for coupling to a data line of the display panel, and sequentially driving the data line of the display panel according to first display data and second display data, wherein the first display data corresponds to a first scan line of the display panel, and the second display data corresponds to a second scan line of the display panel next to the first scan line of the display panel; and a control circuit coupled to the data channel and configured to determine whether to generate a delay time according to the similarity between the second display data and the first display data, so as to delay a time point at which the data channel outputs the second display data, The control circuit is configured to: When the second display data is similar to the first display data, controlling the second display data to be output to the data line at a first transition edge of a data output control signal; and When the second display data is not similar to the first display data, the second display data is controlled to be output to the data line at a second transition edge of the data output control signal, The first transition edge of the data output control signal appears after the second transition edge of the data output control signal.

7. The source driving circuit according to claim 6, characterized in that: Each of the first display data and the second display data includes a polarity and a bit value, respectively, and the control circuit is configured to determine the similarity between the second display data and the first display data based on the polarity identity of the second display data and the first display data, and the bit value similarity between the second display data and the first display data.

8. The source driving circuit according to claim 7, characterized in that: The control circuit is configured to determine that the second display data is similar to the first display data when an amount of identical bit values ​​of the first display data and the second display data is equal to or greater than a threshold and the polarity of the second display data is the same as the polarity of the first display data.

9. The source driving circuit according to claim 6, characterized in that: The control circuit is further configured to cause a delay when the second display data is similar to the first display data, and the control circuit is further configured to not generate the delay time when the second display data is not similar to the first display data.

10. The source driving circuit according to claim 6, characterized in that: The data output control signal is a load signal for instructing a time point at which the data channel transmits display data to be displayed on each row of the display panel.

11. The source driving circuit according to claim 6, characterized in that: The first transition edge of the data output control signal is a falling / rising edge of the data output control signal, and the second transition edge of the data output control signal is a rising / falling edge of the data output control signal.

12. The source driving circuit according to claim 6, characterized in that: The data output control signal includes a first data output control signal and a second data output control signal.

13. The source driving circuit according to claim 12, characterized in that: The first data output control signal is a load signal for indicating a time interval for the data channel to transmit display data for display on each line of the display panel, and the second data output control signal is a mask load signal generated by making the load signal.

14. The source driving circuit according to claim 12, characterized in that: The control circuit is further configured to: When the second display data is similar to the first display data, controlling the second display data to be output to the data line at a rising edge / falling edge of the first data output control signal; and When the second display data is not similar to the first display data, controlling the second display data to be output to the data line at the rising / falling edge of the second data output control signal, The rising / falling edge of the first data output control signal is later than the rising / falling edge of the second data output control signal.

15. The source driving circuit according to claim 12, characterized in that: During the delay time, the control circuit is configured to place the output terminal of the data channel in a floating state.

16. The source driving circuit according to claim 15, characterized in that: The data channel includes: an amplifier for sequentially outputting a first driving voltage indicated by the first display data and a second driving voltage indicated by the second display data; and A switch is coupled between the amplifier and the output end of the data channel to be opened or closed according to a switch control signal, wherein the control circuit is configured to generate the switch control signal and perform an operation of generating the delay time by delaying the starting point of the switch conduction state by the delay time using the switch control signal.

17. The source driving circuit according to claim 16, characterized in that: The control circuit includes a multiplexer configured to select one of the first data output control signal and the second data output control signal as the switch control signal according to similarity between the second display data and the first display data, wherein a rising / falling edge of the first data output control signal occurs later than a rising / falling edge of the second data output control signal.

18. A source driving circuit operating method, applicable to a display panel, characterized in that: The operation method comprises: sequentially driving the data lines of the display panel according to first display data and second display data, wherein the first display data corresponds to a first scan line of the display panel, and the second display data corresponds to a second scan line of the display panel next to the first scan line of the display panel; Determining whether to generate a delay time for delaying the time point of outputting the second display data according to the similarity between the second display data and the first display data; When the second display data is similar to the first display data, controlling the second display data to be output to the data line at a first transition edge of a data output control signal; and When the second display data is different from the first display data, the second display data is controlled to be output to the data line at the second transition edge of the data output control signal, The first transition edge of the data output control signal is later than the second transition edge of the pulse of the data output control signal.

19. The source driving circuit operating method according to claim 18, characterized in that: Each of the first display data and the second display data includes a polarity and a bit value, respectively, and the operation method further includes: The similarity between the second display data and the first display data is determined according to polarity identity between the second display data and the first display data, and bit value similarity between the second display data and the first display data.

20. The source driving circuit operating method according to claim 19, wherein: Also includes: When the amount of the same bit values ​​of the first display data and the second display data is equal to or greater than a threshold and the polarity of the second display data is the same as the polarity of the first display data, it is determined that the second display data is similar to the first display data.

21. The source driving circuit operating method according to claim 18, wherein: Also includes: The operation of generating the delay time is performed when the second display data is similar to the first display data, and the operation of generating the delay time is not performed when the second display data is not similar to the first display data.

22. The source driving circuit operating method according to claim 18, wherein: The data output control signal is a load signal for instructing a time point at which a data channel sends display data to be displayed on each row of the display panel.

23. The source driving circuit operating method according to claim 18, wherein: The first transition edge of the data output control signal is a falling / rising edge of the data output control signal, and the second transition edge of the data output control signal is a rising / falling edge of the data output control signal.

24. The source driving circuit operating method according to claim 18, wherein: The data output control signal includes a first data output control signal and a second data output control signal.

25. The source driving circuit operating method according to claim 24, characterized in that: The first data output control signal is a load signal for instructing a data channel to send a time interval of display data to be displayed on each line of the display panel, and the second data output control signal is a mask load signal generated by fabricating the load signal.

26. The source driving circuit operating method according to claim 24, characterized in that: Also includes: When the second display data is similar to the first display data, controlling the second display data to be output to the data line at a rising / falling edge of the first data output control signal; and When the second display data is not similar to the first display data, controlling the second display data to be output to the data line at the rising / falling edge of the second data output control signal, The rising / falling edge of the first data output control signal is later than the rising / falling edge of the second data output control signal.

27. The source driving circuit operating method according to claim 18, characterized in that: Also includes: The output end of the data channel is placed in a floating state during the delay time.

28. The source driving circuit operating method according to claim 27, characterized in that: Also includes: sequentially outputting a first driving voltage indicated by the first display data and a second driving voltage indicated by the second display data; as well as The output path of the data channel is turned on or off according to a switch control signal, wherein the switch control signal is generated so as to generate the delay time by delaying a start point of a conduction state of the switch by the delay time using the switch control signal.

29. The source driving circuit operating method according to claim 28, characterized in that: Also includes: According to the similarity between the second display data and the first display data, one of the first data output control signal and the second data output control signal is selected as the switch control signal, wherein the rising / falling edge of the first data output control signal appears after the rising / falling edge of the second data output control signal.

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