Semiconductor device and memory system

Abstract

A semiconductor device includes a multi-level receiver including N sense amplifiers and a decoder decoding outputs of the N sense amplifiers, each of the N sense amplifiers receiving a multi-level signal having M levels and a reference signal (where M is a natural number greater than 2, and where N is a natural number smaller than M), a clock buffer receiving a reference clock signal, and a clock controller generating N clock signals using the reference clock signal, inputting the N clock signals to the N sense amplifiers, respectively, and determining a phase of each of the N clock signals using outputs of the N sense amplifiers, respectively.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0105421, filed on August 21, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a memory system. Background Technology

[0004] Memory devices can provide the ability to write and erase data or read recorded data in response to control signals received from an external controller. Memory devices can receive data from the controller and store it in memory cells, and can send data as non-return-to-zero (NRZ) signals and other multi-level signals to improve data transfer speeds between the memory device and the controller. Summary of the Invention

[0005] One aspect of the present invention is to provide a semiconductor device and a memory system that can accurately recover information sent by a controller into a multi-level signal by adjusting the phase of each of the clock signals input to a sense amplifier that receives a multi-level signal.

[0006] According to one aspect of the present invention, a semiconductor device includes: a multilevel receiver comprising N sense amplifiers and a decoder for decoding the outputs of the N sense amplifiers, each of the N sense amplifiers receiving a multilevel signal having M levels and a reference signal, wherein M is a natural number greater than 2 and N is a natural number less than M; a clock buffer configured to receive a reference clock signal; and a clock controller configured to: generate N clock signals using the reference clock signal, input the N clock signals to the N sense amplifiers respectively, and determine the phase of each of the N clock signals using the outputs of the N sense amplifiers respectively.

[0007] According to one aspect of the present invention, a semiconductor device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a word line driver connected to the plurality of word lines; read / write circuitry connected to the plurality of bit lines; a multilevel receiver including a plurality of sense amplifiers receiving multilevel signals having M levels (where M is a natural number greater than 2) from an external controller and a decoder decoding the outputs of the plurality of sense amplifiers; and a clock controller configured to: generate a plurality of clock signals when the multilevel receiver receives a test data pattern from the external controller during a refresh operation of the memory cells, and input the plurality of clock signals to the plurality of sense amplifiers respectively, and adjust the phase of each of the plurality of clock signals using the outputs of the plurality of sense amplifiers respectively.

[0008] According to one aspect of the present invention, a memory system includes: a memory device having a plurality of memory cells; and a controller connected to the memory device via a plurality of pins and configured to control the memory device, wherein the controller sends at least one of a data signal, a data strobe signal, and a command / address signal to the memory device via the plurality of pins, the controller sends a refresh command to the memory device, and when the memory device performs a refresh operation in response to the refresh command, the controller sends a test data pattern as a multi-level signal to the memory device via at least one of the plurality of pins. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following specific embodiments, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a schematic diagram of a system including a semiconductor device according to an exemplary embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram illustrating a semiconductor device according to an example embodiment of the concept of the present invention;

[0012] Figures 3 to 5 This is a diagram illustrating a multi-level signal received by a semiconductor device according to an exemplary embodiment of the concept of the present invention;

[0013] Figure 6 and Figure 7 These are diagrams provided to illustrate the operation of a semiconductor device according to an exemplary embodiment of the concept of the present invention;

[0014] Figures 8 to 13 These are diagrams provided to illustrate the operation of a semiconductor device according to an exemplary embodiment of the concept of the present invention;

[0015] Figure 14This is a schematic diagram illustrating a memory system according to an exemplary embodiment of the present invention;

[0016] Figure 15 This is a schematic diagram illustrating a semiconductor device included in a memory system according to an exemplary embodiment of the present invention;

[0017] Figure 16 and Figure 17 This is a schematic diagram illustrating a semiconductor device according to an example embodiment of the concept of the present invention;

[0018] Figures 18 to 22 These are diagrams provided to illustrate the operation of a semiconductor device according to an exemplary embodiment of the concept of the present invention;

[0019] Figure 23 These are diagrams provided to illustrate the operation of a memory system according to an exemplary embodiment of the concept of the present invention;

[0020] Figure 24 A diagram schematically illustrates a memory system according to an exemplary embodiment of the concept of the present invention; and

[0021] Figure 25 This is a schematic diagram illustrating a mobile system including a semiconductor device according to an example embodiment of the present invention. Detailed Implementation

[0022] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram of a system including a semiconductor device according to an exemplary embodiment of the present invention.

[0024] refer to Figure 1 System 1, according to an exemplary embodiment of the present invention, may include a first semiconductor device 10 and a second semiconductor device 20 for transmitting and receiving data. Figure 1 In the example embodiment of system 1 shown, the first semiconductor device 10 can send data to the second semiconductor device 20.

[0025] For example, the first semiconductor device 10 can send data signals and clock signals to the second semiconductor device 20. The first semiconductor device 10 may include a first output circuit 11 and a second output circuit 12 for sending data signals, a clock generator 13 for sending clock signals, a core circuit 14 for controlling the overall operation of the first semiconductor device 10, etc.

[0026] The second semiconductor device 20 may include a first multilevel receiver 21 and a second multilevel receiver 22 for receiving data signals, a clock receiver 23 for receiving clock signals, and a core circuit 24 for controlling the overall operation of the second semiconductor device 20.

[0027] Each of the first output circuit 11 and the second output circuit 12 can transmit data signals as multi-level signals. Therefore, each of the data signals transmitted via the first data channel DCH1 and the second data channel DCH2 can be a multi-level signal with M levels, where M can be a natural number greater than 2. For example, M can be a power of 2 and can be determined based on the amount of data to be transmitted via each of the first data channel DCH1 and the second data channel DCH2.

[0028] Clock generator 13 can send a reference clock signal to second semiconductor device 20 via clock channel CCH. The reference clock signal can be a signal that repeatedly increases and decreases between two levels. However, according to an example embodiment, the reference clock signal can also be generated as a multi-level signal (similar to a data signal) and sent to the second semiconductor device 20. In the example embodiment, the number of levels that the reference clock signal can have and the number of levels that the data signal can have can be the same or different from each other.

[0029] The first multilevel receiver 21 and the second multilevel receiver 22 can be recovered by receiving data signals. For example, the first multilevel receiver 21 may include N sense amplifiers that receive a multilevel signal with M levels and a reference signal. N may be a natural number less than M, which defines the multilevel signal, and the first multilevel receiver 21 may also include a decoder for decoding the outputs of the N sense amplifiers. The configuration and operation of the second multilevel receiver 22 may be similar to the configuration and operation of the first multilevel receiver 21.

[0030] Each of the N sensing amplifiers included in the first multi-level receiver 21 can compare a data signal received through the first data channel DCH1 with a reference signal and output the comparison result to the decoder. In an example embodiment, the operating timing of each of the sensing amplifiers can be determined based on a clock signal sent from the clock receiver 23 to the first multi-level receiver 21. For example, each of the sensing amplifiers can compare the data signal and the reference signal at the rising and falling edges of the clock signal and output the comparison result to the decoder. Therefore, when the phase of the clock signal is not properly controlled, errors may occur in the output of the sensing amplifiers and / or in the data recovered by the first multi-level receiver 21.

[0031] Due to parasitic capacitance and resistance components present in the routing wiring and / or the characteristic differences of the components included in the sensing amplifier, the data signals and / or clock signals input to each of the sensing amplifiers included in the first multilevel receiver 21 and the second multilevel receiver 22 may have different timings. In an exemplary embodiment of the inventive concept, by controlling the phase of the clock signal input to each of the sensing amplifiers respectively, the timing differences caused by parasitic capacitance, resistance components, and component characteristics can be compensated, and the performance of the first multilevel receiver 21 and the second multilevel receiver 22 can be improved.

[0032] Figure 2 This is a schematic diagram illustrating a semiconductor device according to an example embodiment of the concept of the present invention.

[0033] refer to Figure 2 The semiconductor device 100, according to an exemplary embodiment of the present invention, may include a multilevel receiver 110, a clock buffer 120, a clock controller 130, etc. The multilevel receiver 110 may include a plurality of sense amplifiers 111 to 113 that receive a data signal transmitted as a multilevel signal, and a decoder 114 that decodes the outputs of the sense amplifiers 111 to 113. In the exemplary embodiment, the data signal may be a multilevel signal having M levels (where M is a natural number greater than 2), and the number of sense amplifiers 111 to 113 may be N (where N is a natural number less than M). For example, depending on the transmission speed of the data signal, M may be defined as a power of 2, and N may be defined as M-1. The clock buffer 120 may receive a reference clock signal (CLK). REF The clock controller 130 can use a reference clock signal (CLK). REF The system generates clock signals CLK1 to CLK3. The N clock signals CLK1 to CLK3 can be input to N sense amplifiers 111 to 113 respectively.

[0034] The first sensing amplifier 111 can operate according to the first clock signal CLK1, and the data signal is compared with the first reference signal V. REF1 The comparison is performed, and the second sensing amplifier 112 can operate according to the second clock signal CLK2, and compare the data signal with the second reference signal V. REF2 The third sensing amplifier 113 can operate according to the third clock signal CLK3 and compare the data signal with the third reference signal V. REF3 Compare them.

[0035] Due to the difference in the length of the path along which the data signal DATA is transmitted, the data signals input to the sensing amplifiers 111 to 113 may have different phases, and therefore differences in resistance and parasitic capacitance will occur.

[0036] Since clock signals CLK1 to CLK3 are respectively input to sensing amplifiers 111 to 113, when the phases of clock signals CLK1 to CLK3 are adjusted together, it may not be possible to accurately recover the data signal in at least one of sensing amplifiers 111 to 113.

[0037] In an exemplary embodiment of the present invention, clock controller 130 can control the phase of each of clock signals CLK1 to CLK3 respectively by using the output of each of sense amplifiers 111 to 113.

[0038] The clock controller 130 may include a clock generator 131 that determines the phase of each of the clock signals CLK1 to CLK3, an error detector 132 that detects the output of each of the sensing amplifiers 111 to 113, etc.

[0039] The clock generator 131 may include a plurality of delay units that determine the delay time of each of the clock signals CLK1 to CLK3, such that the phase of each of the clock signals CLK1 to CLK3 can be controlled individually.

[0040] According to an example embodiment, the clock controller 130 can adjust the phase of each of the clock signals CLK1 to CLK3 simultaneously or sequentially.

[0041] Figures 3 to 5 This is a diagram illustrating a multi-level signal received by a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0042] First, refer to Figure 3 and Figure 4 In an exemplary embodiment of the present invention, the multilevel signal received by the semiconductor device can have four levels, LV1 to LV4. Figure 3 and Figure 4 In the example embodiment shown, the semiconductor device can generate a multilevel signal based on 4-level pulse amplitude modulation-4 (PAM-4). Using a multilevel signal generated based on 4-level pulse width modulation, two data bits can be received during one data transmission cycle (PR).

[0043] For example, each of the four levels LV1 to LV4 can correspond to data 00, 01, 10, and 11. Therefore, a semiconductor device can receive two bits, for example, one of 00, 10, 01, and 11, during a data transmission cycle PR. The semiconductor device may include a multilevel receiver that receives multilevel signals and recovers data, and the multilevel receiver may include multiple sense amplifiers.

[0044] For example, when Figure 3 and Figure 4 As shown, when generating a multilevel signal based on 4-level pulse amplitude modulation, the multilevel receiver can include three sensing amplifiers. When n bits of data are received via the multilevel signal during one data transmission cycle PR, the multilevel signal can have 2 n A level, and a multi-level receiver may include (2) n -1) sensing amplifiers.

[0045] The sense amplifier can combine a multi-level signal with a reference signal V. REF1 To V REF3 Comparison. For example, the first sensing amplifier can compare the multi-level signal with a first reference signal V. REF1 The comparison is performed. For example, the first sensing amplifier compares the multi-level signal with a first reference signal V. REF1 The comparison is performed, and if the multi-level signal is less than the first reference signal V... REF1 This allows us to determine that the multi-level signal corresponds to the

[00] data bit. Similarly, the second sensing amplifier can correlate the multi-level signal with the second reference signal V. REF2 The comparison is performed, and the third sensing amplifier can compare the multi-level signal with the third reference signal V. REF3 Compare them.

[0046] Reference signal V REF1 To V REF3 Each of these can be an intermediate value of at least some of the levels LV1 to LV4 that a multi-level signal can have. For example, the first reference signal V REF1 It can be an intermediate value between the first level LV1 and the second level LV2, and the second reference signal V REF2 It can be an intermediate value between the second level LV2 and the third level LV3. The third reference signal V REF3 It can be an intermediate value between the third level LV3 and the fourth level LV4.

[0047] When distortion occurs in a multi-level signal, the differences between the first level LV1 and the fourth level LV4 can be different from each other. For example, the difference between the first level LV1 and the second level LV2 can be the smallest, and the difference between the third level LV3 and the fourth level LV4 can be the largest. When distortion occurs in a multi-level signal, the reference signal V can be adjusted together to account for the distortion of the multi-level signal. REF1 To V REF3 .

[0048] exist Figure 5In the example embodiment shown, three bits of data can be received during a data transmission cycle PR using a multi-level signal. Therefore, a multi-level signal is generated based on 8-level pulse amplitude modulation, and this multi-level signal can have eight different levels LV1 to LV8. The eight different levels LV1 to LV8 can correspond to data 000, 001, 010, 011, 100, 101, 110, and 111, respectively.

[0049] For example, according to Figure 3 The multilevel signal in the example embodiment shown can be a signal input to a first sensing amplifier, and according to... Figure 4 The multilevel signal in the illustrated example embodiment can be a signal input to a second sense amplifier. The first and second sense amplifiers can be included in a single multilevel receiver. During transition periods TP1 and TP2, the multilevel signal can increase or decrease between levels LV1 and LV4. For example, due to the difference between the routing path from the receive pad receiving the multilevel signal to the input terminal of the first sense amplifier and the routing path from the receive pad to the input terminal of the second sense amplifier, the multilevel signal input to the first sense amplifier can have a first transition period TP1, and the multilevel signal input to the second sense amplifier can have a second transition period TP2, different from the first transition period TP1.

[0050] Therefore, when clock signals with the same phase are input to the sense amplifier, errors may occur in the output of the sense amplifier. Ideally, each of the sense amplifiers can combine the multi-level signal and the reference signal V at the midpoint of the data transmission cycle PR. REF1 To V REF3 A comparison is made. When the clock signals input to the sensing amplifiers are in phase, an error may occur in the output of at least one of the sensing amplifiers due to the difference between the transition periods TP1 and TP2.

[0051] To address this issue, in an exemplary embodiment of the present invention, the phase of the clock signal input to each of the sensing amplifiers can be controlled separately. For example, taking into account the difference between the first transition period TP1 of the multi-level signal input to the first sensing amplifier and the second transition period TP2 of the multi-level signal input to the second sensing amplifier, the first clock signal input to the first sensing amplifier and the second clock signal input to the second sensing amplifier can have different phases.

[0052] Figure 6 and Figure 7 These are diagrams provided to illustrate the operation of a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0053] First, refer to Figure 6 Operation of the semiconductor device according to an exemplary embodiment of the present invention can be initiated by receiving a reference clock signal (S10). For example, the reference clock signal can be received from another semiconductor device connected to communicate with each other. After receiving the reference clock signal, a clock adjustment mode can be initiated (S11). The clock adjustment mode can be an operating mode for adjusting the phase of each of the clock signals input to a sensing amplifier that receives multi-level signals. When the clock adjustment mode is initiated, a test data pattern can be received from another semiconductor device that has already transmitted the reference clock signal (S12). For example, the test data pattern can be a pseudo-random binary sequence (PRBS) pattern.

[0054] A clock controller included in a semiconductor device can generate multiple clock signals using a reference clock signal (S13). For example, the clock controller can generate multiple clock signals by delaying the reference clock signal by a predetermined or (alternatively) desired initial delay time. In operation S13, the multiple clock signals can have the same phase and can be input to a sensing amplifier. The clock controller can compare the output of each of the sensing amplifiers with a test data pattern (S14). The test data pattern can be data input to each of the sensing amplifiers as a multi-level signal. Based on the comparison result of operation S14, the clock controller can determine whether there is an error in the output of each of the sensing amplifiers and adjust the phase of each of the clock signals accordingly (S15).

[0055] In an exemplary embodiment of the present invention, the output of the sensing amplifier can be compared with a test data pattern, and if no error is found, the delay time of the clock signal input to the sensing amplifier can be intentionally increased or decreased, and the output of the sensing amplifier can be compared with the test data pattern. A threshold delay time for the clock signal can be found by increasing or decreasing the delay time until the output of the sensing amplifier does not match the test data pattern, and this threshold delay time can be used to find a delay time for the clock signal that is being improved or optimized for the sensing amplifier, and the phase can be adjusted. Reference will be made below to... Figure 7 To describe in more detail.

[0056] refer to Figure 7 In an exemplary embodiment of the present invention, phase adjustment of the clock signal can begin by setting an initial delay time for the clock signal (S20). As described above, the initial delay time can be set together with the clock signal input to a sensing amplifier included in a multi-level receiver. The clock signal with the initial delay time set can then be input to the sensing amplifier (S21).

[0057] The sensing amplifier can operate synchronously with a clock signal and can compare a multi-level signal with a reference signal, outputting the comparison result. The clock controller can compare the output of the sensing amplifier with a test data pattern (S22) and determine whether an error has occurred (S23). As described above, the test data pattern can be data input to the sensing amplifier as a multi-level signal. Therefore, by comparing the test data pattern with the output of the sensing amplifier, it can be determined whether the sensing amplifier, which operates synchronously with the clock signal, accurately receives the multi-level signal.

[0058] If no error is determined in operation S23, the clock controller may intentionally increase the delay time of the clock signal (S24). Understandably, the phase of the clock signal is delayed. The clock signal with the increased delay time can be input to the sensing amplifier, and the output of the sensing amplifier can be compared with the test data pattern again. The delay time of the clock signal may be increased until an error is determined in operation S23 due to a mismatch between the output of the sensing amplifier and the test data pattern.

[0059] If an error is determined to have occurred in operation S23, the clock controller may determine the delay time of the clock signal as a first threshold delay time (S25). The clock controller may reduce the delay time of the clock signal (S26). In an example embodiment, the clock controller may reduce the delay time of the clock signal after resetting the delay time of the clock signal to the initial delay time.

[0060] The clock controller can input a clock signal with reduced delay time to the sensing amplifier (S27), compare the output of the sensing amplifier with the test data pattern (S28), and determine whether an error has occurred (S29). If it is determined in operation S29 that no error has occurred, the clock controller can further reduce the delay time of the clock signal (S30) and input the clock signal to the sensing amplifier.

[0061] For example, the clock controller can reduce the clock signal delay time until an error is determined in operation S29 due to a mismatch between the output of the sensing amplifier and the test data pattern. If an error is determined in operation S29, the clock controller can determine the clock signal delay time as a second threshold delay time (S31). The clock controller can use the first threshold delay time and the second threshold delay time to determine the phase of the clock signal for improvement or optimization of the sensing amplifier (S32).

[0062] The difference between the first threshold delay time and the second threshold delay time can be calculated, and the result can be added to the initial delay time to determine the final delay time and the phase of the clock signal. For example, if the first threshold delay time is greater than the second threshold delay time, the final delay time of the clock signal can be further increased compared to the initial delay time, and if the first threshold delay time is less than the second threshold delay time, the final delay time of the clock signal can be further reduced compared to the initial delay time.

[0063] Figures 8 to 13 These are diagrams provided to illustrate the operation of a semiconductor device according to an example embodiment of the concept of the present invention.

[0064] The semiconductor device according to an example embodiment may include a multilevel receiver that receives a multilevel signal (MLS), and as described above, the multilevel receiver may include a plurality of sense amplifiers that collectively receive the multilevel signal (MLS). Each of the sense amplifiers may compare the multilevel signal (MLS) with a reference signal in synchronization with a clock signal, and in an example embodiment of the inventive concept, the phase of the clock signal input to each of the sense amplifiers may be adjusted individually to reduce or prevent malfunctions of the multilevel receiver.

[0065] In the following text, reference will be made to Figures 8 to 13 The clock signal adjustment operation of a semiconductor device according to an example embodiment of the present invention is described.

[0066] First, refer to Figure 8 The multilevel signal MLS can have one of the first level LV1 to the fourth level LV4, and can transmit 2 bits of data during one data transmission cycle PR. The multilevel signal MLS can be input to a first sensing amplifier that operates synchronously with a first clock signal CLK1, and the first clock signal CLK1 can be set to have an initial delay time.

[0067] The multilevel signal MLS can be a signal used to send a test data pattern to a semiconductor device while adjusting the phase of the first clock signal CLK1.

[0068] When the first sensing amplifier operates synchronously with the first clock signal CLK1 and the multi-level signal MLS and reference signal V are used... REF1 To V REF3 When performing a comparison, the clock controller can compare the output of the first sensing amplifier with the test data pattern. When the first sensing amplifier operates via a first clock signal CLK1 with an initial delay time set, the output of the first sensing amplifier can be matched with the test data pattern.

[0069] The clock controller can increase the delay time of the first clock signal CLK by a first delay amount ΔD1 and input it to the first sensing amplifier.

[0070] exist Figure 8 In the illustrated example embodiment, even when the delay time is increased by a first delay amount ΔD1, the output of the first sensing amplifier can still match the test data pattern. The clock controller can also delay the delay time of the first clock signal CLK1 by a second delay amount ΔD2 and input it to the first sensing amplifier. Even with the increase of the second delay amount ΔD2, the rising and falling edges of the first clock signal CLK1 will not overlap with the first transition period of the multi-level signal. Therefore, the output of the first sensing amplifier can match the test data pattern.

[0071] When the clock controller further delays the delay time of the first clock signal CLK1 by a third delay amount ΔD3, the rising and falling edges of the first clock signal CLK1 can overlap with the first transition period of the multi-level signal MLS. Therefore, the output of the first sensing amplifier may not match the test data pattern.

[0072] When the output of the first sensing amplifier does not match the test data pattern, the clock controller can set the delay time of the first clock signal CLK1 to a first threshold delay time ΔTHD1. For example, the first threshold delay time ΔTHD1 can be determined as the sum of a first delay amount ΔD1 to a third delay amount ΔD3. According to an example embodiment, the first delay amount ΔD1 to the third delay amount ΔD3 used to find the first threshold delay time ΔTHD1 can be different from each other, or at least a portion of them can be the same.

[0073] When the first threshold delay time ΔTHD1 is determined, the clock controller can reset the delay time of the first clock signal CLK1 to the initial delay time, and the clock controller can reduce the delay time of the first clock signal CLK1 until the output of the first sensing amplifier does not match the test data pattern.

[0074] refer to Figure 9 The delay time of the first clock signal CLK1 can be reduced by a fourth delay amount ΔD4 based on the initial delay time, and the output of the first sensing amplifier can be compared with the test data pattern.

[0075] In an example embodiment, the output of the first sensing amplifier can be matched with a test data pattern. The clock controller can compare the output of the first sensing amplifier with the test data pattern while sequentially reducing the delay time of the first clock signal CLK1 by a fifth delay amount ΔD5 and a sixth delay amount ΔD6.

[0076] When the delay time of the first clock signal CLK1 is reduced by the sum of the fourth delay amount ΔD4 to the sixth delay amount ΔD6, the rising and falling edges of the first clock signal CLK1 can overlap with the first transition period TP1 of the multi-level signal MLS, and the output of the first sensing amplifier can mismatch with the test data pattern.

[0077] The clock controller can use the sum of the fourth delay amount ΔD4 to the sixth delay amount ΔD6 to determine the second threshold delay time ΔTHD2.

[0078] The clock controller can use the first threshold delay time ΔTHD1 and the second threshold delay time ΔTHD2 to determine the first final delay time ΔFD1.

[0079] For example, the first final delay time ΔFD1 can be determined by the sum of the first threshold delay time ΔTHD1 and the second threshold delay time ΔTHD2, and the phase of the first clock signal CLK1, which is improved or optimized for the first sense amplifier, can be determined by adding the first final delay time ΔFD1 to the initial delay time of the first clock signal CLK1.

[0080] Figures 11 to 13 It can be shown as in the reference Figures 8 to 10 A diagram illustrating the clock signal adjustment operation of the second sensing amplifier that receives the multi-level signal MLS as described in the example embodiment.

[0081] For example, the second sensing amplifier can operate synchronously with a second clock signal CLK2, which is different from the first clock signal CLK1. Additionally, the multi-level signal MLS input to both the first and second sensing amplifiers can be the same signal transmitting the same data.

[0082] On the other hand, due to differences in routing, parasitic capacitance, etc., between each of the first and second sensing amplifiers, the multilevel signal MLS input to the second sensing amplifier may have a different second transition period TP2 than the multilevel signal MLS input to the first sensing amplifier.

[0083] First, refer to Figure 11 The clock controller can compare the output of the second sensing amplifier with the test data pattern when the delay time of the second clock signal CLK2 is increased.

[0084] When the delay time of the second clock signal CLK2 is increased by the first delay amount ΔD1, the rising edge and falling edge of the second clock signal CLK2 may not overlap with the second transition period TP2 of the multi-level signal MLS.

[0085] Therefore, the output of the second sensing amplifier can be matched with the test data pattern, and the clock controller can further delay the delay time of the second clock signal CLK2 by a second delay amount (ΔD2).

[0086] When the delay time of the second clock signal CLK2 is further delayed by a second delay amount ΔD2, the rising and falling edges of the second clock signal CLK2 can overlap with the second transition period TP2 of the multi-level signal MLS. Therefore, the output of the second sensing amplifier may not match the test data pattern.

[0087] The clock controller can determine the sum of the first delay ΔD1 and the second delay ΔD2 as the first threshold delay time ΔTHD1.

[0088] Next, refer to Figure 12 The clock controller can compare the output of the second sensing amplifier with the test data pattern while reducing the delay time of the second clock signal CLK2.

[0089] When the delay time of the second clock signal CLK2 is reduced by the third delay amount ΔD3, the rising edge and falling edge of the second clock signal CLK2 may not overlap with the second transition period TP2 of the multi-level signal MLS.

[0090] Therefore, the output of the second sensing amplifier can be matched with the test data pattern, and the clock controller can further reduce the delay time of the second clock signal CLK2 by a fourth delay amount ΔD4.

[0091] When the delay time of the second clock signal CLK2 is further reduced by a fourth delay amount ΔD4, the rising and falling edges of the second clock signal CLK2 can overlap with the second transition period TP2 of the multi-level signal MLS. Therefore, the output of the second sensing amplifier can mismatch with the test data pattern. The clock controller can determine the sum of the third delay amount ΔD3 and the fourth delay amount ΔD4 as the second threshold delay time ΔTHD2.

[0092] The clock controller can determine the second final delay time ΔFD2 using a first threshold delay time ΔTHD1 and a second threshold delay time ΔTHD2. For example, the second final delay time ΔFD2 can be determined by the sum of the first threshold delay time ΔTHD1 and the second threshold delay time ΔTHD2, and the phase of the second clock signal CLK2, which is improved or optimized for the second sense amplifier, can be determined by adding the second final delay time ΔFD2 to the initial delay time of the second clock signal CLK2.

[0093] Reference Figures 11 to 13In the described example embodiments, the delay amounts ΔD1 to ΔD4 and the threshold delay times ΔTHD1 and ΔTHD2 may differ from the reference values. Figures 8 to 10 Those described in the example embodiments.

[0094] Therefore, the first final delay time ΔFD1 applied to the first clock signal CLK1 and the second final delay time ΔFD2 applied to the second clock signal CLK2 can be different from each other. The first clock signal CLK1, improved or optimized for the first sense amplifier, and the second clock signal CLK2, improved or optimized for the second sense amplifier, can have different phases. In an exemplary embodiment of the inventive concept, by adjusting the phase of the clock signals separately, taking into account the electrical characteristics of each of the sense amplifiers and the electrical characteristics of the routing path through which the multilevel signal MLS is input to each of the sense amplifiers, the operational performance of the multilevel receiver can be improved.

[0095] Figure 14 This is a schematic diagram illustrating a memory system according to an example embodiment of the concept of the present invention.

[0096] refer to Figure 14 A memory system 200 according to an exemplary embodiment of the present invention may include a controller 210 and a memory device 220 for exchanging data. The controller 210 may send clock signals and command / address signals required for the operation of the memory device 220, data signals to be stored in the memory device 220, etc. The memory device 220 may write / delete or read data in response to the control of the controller 210, and may send the read data to the controller 210 in the form of data signals.

[0097] The controller 210 may include a data input / output circuit 211 for sending and receiving data signals, a command / address signal generator 212 for sending command / address signals to the memory device 220, a clock generator 213 for sending clock signals to the memory device 220, and a core circuit 214 for controlling the overall operation of the controller 210. The memory device 220 may include a data transceiver 221 for inputting and outputting data signals, a command / address signal receiver 222 for receiving command / address signals, a clock receiver 223 for receiving clock signals, and a memory circuit 224. The memory circuit 224 may include a memory bank with memory cells.

[0098] At least one of the signals transmitted between the controller 210 and the memory device 220 can be a multi-level signal. In the following description, for ease of description, it is assumed that the data signal is a multi-level signal, but the clock signal and / or command / address signal can also be multi-level signals. When the data signal is a multi-level signal, N bits of data (where N is a natural number greater than 2) can be transmitted between the controller 210 and the memory device 220 at a time per data transmission cycle.

[0099] Data transceiver 221 can generate data by recovering the data signal received from controller 210. The data recovered by data transceiver 221 can be stored in memory circuit 224. For example, data transceiver 221 can be synchronized with a clock signal provided by clock receiver 223 to recover the data signal sent by controller 210 into data. Therefore, if the phase of the clock signal provided by clock receiver is not accurately determined, errors may occur during the data recovery process.

[0100] When the data signal is transmitted as a multi-level signal, the data transceiver 221 can compare the multi-level signal with multiple reference signals. The data transceiver 221 may include multiple sense amplifiers for comparing the multi-level signal with the multiple reference signals. However, the electrical characteristics of each sense amplifier, the length of the routing path through which the data signal is transmitted to the sense amplifier, etc., may differ for each of the sense amplifiers. Therefore, when the phase of the clock signal is determined collectively, an error may occur in at least one sense amplifier. In an exemplary embodiment of the inventive concept, by controlling the phase of the clock signal input to each of the sense amplifiers separately, operational errors of the data transceiver 221 can be reduced or prevented.

[0101] Figure 15 This is a schematic diagram illustrating a semiconductor device included in a memory system according to an example embodiment of the present invention.

[0102] refer to Figure 15 According to an exemplary embodiment of the present invention, the semiconductor device may be a memory device 300. The memory device 300 may include a memory bank 301 having memory cells, a row decoder 302, a column decoder 303, an input / output circuit 304, etc. The row decoder 302 and column decoder 303 may select at least one of the memory cells included in the memory bank 301, and the input / output circuit 304 may write data to or read data stored in the selected memory cell.

[0103] Additionally, the memory device 300 may include multiple circuits connected to pins P1 through P3. For example, a receiver 305 and a transmitter 306 may be connected to data pin P1, and the receiver 305 may send data signals to an external controller. A clock buffer 307 and a clock controller 308 may be connected to clock pin P2. The clock buffer 307 and the clock controller 308 can generate the clock signals required for the operation of the memory device 300 by using a reference clock received from an external controller. A command / address signal receiver 309 may be connected to command / address pin P3.

[0104] For example, at least one of the signals received from an external controller can be a multilevel signal. For example, the data signal sent and received via data pin P1 can be a multilevel signal. Receiver 305 can be synchronized with a clock signal provided by clock controller 308 to recover the data received as a multilevel signal. For example, receiver 305 can recover the data by comparing the multilevel signal with a predetermined or (alternatively) desired reference signal for each rising and falling edge of the clock signal.

[0105] Figure 16 and Figure 17 This is a schematic diagram illustrating a semiconductor device according to an example embodiment of the concept of the present invention.

[0106] refer to Figure 16 The semiconductor device 400, according to an exemplary embodiment of the present invention, may include a multilevel receiver 410, a clock buffer 420, a clock controller 430, etc. The multilevel receiver 410 may include a plurality of sense amplifiers 411 to 413 for receiving a data signal DQ transmitted as a multilevel signal, and a decoder 414 for decoding the outputs of the sense amplifiers 411 to 413. In the exemplary embodiment, the data signal DQ may be a multilevel signal having M levels (where M is a natural number greater than 2), and the number of sense amplifiers 411 to 413 may be N (where N is a natural number less than M). For example, depending on the transmission rate of the data signal DQ, M may be defined as a power of 2, and N may be defined as M-1.

[0107] Clock buffer 420 can receive reference clock signal CLK REF and the reference clock signal CLK REF Phase shifts of 90, 180, and 270 degrees are applied to provide four sub-clock signals CLK to clock controller 430. However, according to an example embodiment, clock buffer 420 may receive multiple reference clock signals. For example, clock buffer 420 may receive a first reference clock signal and a second reference clock signal as differential signals, where the second reference clock signal is complementary to the first reference clock signal.

[0108] Clock controller 430 can generate N clock signals CLK1 to CLK3 that are input to N sense amplifiers 411 to 413. For example, each of the N clock signals CLK1 to CLK3 may include a first sub-clock signal to a fourth sub-clock signal, and the second to fourth sub-clock signals may be clock signals based on phase shifts of 90 degrees, 180 degrees, and 270 degrees from the first sub-clock signal. However, according to an example embodiment, clock buffer 420 may send a reference clock signal CLK to clock controller 430. REF Furthermore, the clock controller 430 can phase-shift the reference clock signal CLK. REF To generate multiple sub-clock signals.

[0109] The first sensing amplifier 411 can operate according to the first clock signal CLK1 to connect the data signal DQ with the first reference signal V. REF1 The comparison is performed, and the second sensing amplifier 412 can operate according to the second clock signal CLK2 to compare the data signal DQ with the second reference signal V. REF2 The third sensing amplifier 413 can operate according to the third clock signal CLK3 to compare the data signal DQ with the third reference signal V. REF3 Compare them.

[0110] Due to the differences in the path through which the data signal DQ is transmitted and the electrical characteristics of each of the sense amplifiers 411 to 413, the data signal DQ input to the sense amplifiers 411 to 413 can have different phases or different transition periods. In an exemplary embodiment of the inventive concept, the clock controller 130 can use the output of each of the sense amplifiers 411 to 413 to control the phase of each of the clock signals CLK1 to CLK3 respectively. The clock controller 430 may include a clock generator 431 for determining the phase of each of the clock signals CLK1 to CLK3, an error detector 432 for detecting the output of each of the sense amplifiers 411 to 413, etc. In an exemplary embodiment, the clock generator 431 may include a plurality of delay units for determining the delay time of each of the clock signals CLK1 to CLK3 so that the phase of each of the clock signals CLK1 to CLK3 can be controlled separately. The clock generator 431 may be a multiphase clock generator.

[0111] refer to Figure 17 The semiconductor device 500 may include multiple unit sense amplifiers 501 to 504, a decoder that generates data using the output of the unit sense amplifiers 501 to 504, a clock buffer 506, a clock generator 507, an error detector 508, etc. The clock buffer 506 can receive a reference clock signal CLK from an external controller, etc. REFand sends the phase-shifted reference clock signal CLK to the clock generator 507. REF Multiple sub-clock signals CLK are generated.

[0112] Clock generator 507 can adjust the phase of multiple sub-clock signals CLK received from clock buffer 506 to generate sub-clock signals CLK that are input to unit sense amplifiers 501 to 504. S1 To CLK S4 Referring to the outputs of each of the unit sense amplifiers 501 to 504 detected by the error detector 508, the clock generator 507 can improve or optimize the sub-clock signal CLK. S1 To CLK S4 The phase of each of them is adapted to the unit sense amplifiers 501 to 504.

[0113] Error detector 508 can detect the presence of an error in the output of each of the unit sense amplifiers 501 to 504. For example, when the sub-clock signal CLK... S1 To CLK S4 An error may occur in at least one of the unit sense amplifiers 501 to 504 when at least one rising edge and one falling edge overlap with the transition period of the data signal DQ. When an error is detected, the sub-clock signal CLK can be adjusted. S1 To CLK S4 Phase operations.

[0114] In the example embodiment, the adjustment sub-clock signal CLK may also be executed once at each predetermined or (alternatively) desired cycle or in a specific operating mode of the semiconductor device 500. S1 To CLK S4 The phase operation. For example, when the semiconductor device 500 is a dynamic random access memory (DRAM), while performing a refresh operation on the memory cell in the semiconductor device 500, the sub-clock signal CLK can be adjusted. S1 To CLK S4 The phase operation. Therefore, without a separate operation time, the sub-clock signal CLK can be adjusted during continuous operation of the semiconductor device 500. S1 To CLK S4 The phase is determined to accurately receive the data signal DQ.

[0115] Figures 18 to 22 These are diagrams provided to illustrate the operation of a semiconductor device according to an exemplary embodiment of the concept of the present invention. In the following description, reference will be made to... Figure 17 Describe the operation of semiconductor device 500.

[0116] In a semiconductor device 500 according to an exemplary embodiment of the present invention, unit sense amplifiers 501 to 504 that receive multi-level signals (e.g., data signals DQ) can be synchronized with a sub-clock signal CLK. S1 To CLK S4 Synchronous operation.

[0117] First, refer to Figure 18 Second sub-clock signal CLK S2 Up to the fourth sub-clock signal CLK S4 This can be achieved by using the first sub-clock signal CLK. S1 Signals generated by phase shifts of 90 degrees, 180 degrees, and 270 degrees. Therefore, in the sub-clock signal CLK... S1 To CLK S4 There may be a predetermined or (alternatively) expected delay time td between them.

[0118] refer to Figure 19 The data signal DQ can be a signal with a total of four levels LV1 to LV4 generated by a 4-level pulse amplitude modulation method. Therefore, the semiconductor device 500 can receive 2 data bits during one data transmission cycle PR. To determine the first sub-clock signal CLK input to the unit sense amplifiers 501 to 504... S1 Up to the fourth sub-clock signal CLK S4 The phase of the clock signal CLK is set to have a predetermined or (alternatively) desired initial delay time. S1 To CLK S4 It can be input to unit sense amplifiers 501 to 504. For example, by using the first sub-clock signal CLK. S1 Phase shifts of 90 degrees, 180 degrees, and 270 degrees can generate the sub-clock signal CLK. S1 To CLK S4 In the example embodiment, the sub-clock signal CLK S1 To CLK S4 The period can be twice the period of the data signal DQ.

[0119] Next, refer to Figure 20 This can be achieved by delaying the sub-clock signal CLK. S1 To CLK S4 The phase is used to find the first threshold delay time ΔTHD1. For example, clock generator 507 can generate a sub-clock signal CLK. S1 To CLK S4 Each delay is a predetermined or (optionally) desired delay amount, and error detector 508 can detect the outputs of unit sense amplifiers 501 to 504. Clock generator 507 can increase the sub-clock signal CLK. S1 To CLKS4 The delay time is until the error detector 508 determines the first threshold delay time ΔTHD1 at the same time as it determines that an error exists in the output of the unit sense amplifiers 501 to 504.

[0120] Once the first threshold delay time ΔTHD1 is determined, the second threshold delay time ΔTHD2 can be found. For example, ... Figure 21 As shown, clock generator 507 can generate the sub-clock signal CLK. S1 To CLK S4 Each of the predetermined or (optionally) desired delay amounts, and error detector 508 can detect the outputs of unit sense amplifiers 501 to 504. Clock generator 507 can advance the sub-clock signal CLK. S1 To CLK S4 The phase is determined until the error detector 508 determines that there is an error in the output of the unit sensing amplifiers 501 to 504, and determines the second threshold delay time ΔTHD2.

[0121] Clock generator 507 can determine the final delay time ΔFD using a first threshold delay time ΔTHD1 and a second threshold delay time ΔTHD2. The final delay time ΔFD can be determined as the difference between the first threshold delay time ΔTHD1 and the second threshold delay time ΔTHD2. Clock generator 507 will then generate the sub-clock signal CLK. S1 To CLK S4 The phase of each of them is advanced or delayed by the final delay time ΔFD, which allows for improvement or optimization of the operating timing of the unit sense amplifiers 501 to 504.

[0122] like Figure 22 As shown, when the first threshold delay time ΔTHD1 is greater than the second threshold delay time ΔTHD2, the sub-clock signal CLK... S1 To CLK S4 Each phase in the sequence can be delayed by a final delay time ΔFD. Conversely, when the first threshold delay time ΔTHD1 is less than the second threshold delay time ΔTHD2, the sub-clock signal CLK... S1 To CLK S4 Each of the phases can be advanced by the final delay time ΔFD.

[0123] Clock generator 507 can adjust the sub-clock signal CLK individually. S1 To CLK S4 The final delay time ΔFD for each of them. According to the example embodiment, this can be compared with the sub-clock signal CLK. S1 To CLK S4 The final delay time ΔFD is determined differently in several ways. Alternatively, the sub-clock signal CLK is calculated. S1To CLK S4 One of them (e.g., the first sub-clock signal CLK) S1 The final delay time ΔFD, and the first sub-clock signal CLK on which the final delay time ΔFD can be reflected. S1 Delays of 90 degrees, 180 degrees, and 270 degrees are used to generate the second sub-clock signal CLK. S2 Up to the fourth sub-clock signal CLK S4 .like Figure 22 As shown, by using the first sub-clock signal CLK S1 Up to the fourth sub-clock signal CLK S4 Receiving the data signal DQ can shorten the sampling time and increase the data transmission rate.

[0124] Figure 23 The diagram is provided to illustrate the operation of a memory system according to an exemplary embodiment of the concept of the present invention.

[0125] refer to Figure 23 The memory system according to an exemplary embodiment of the present invention may include a controller 600 and a memory device 700, and the controller 600 and the memory device 700 may send and receive signals to each other via multiple pins. For example, the controller 600 may send command / address signals, data signals, data strobe signals, clock signals, etc. to the memory device 700, and the memory device 700 may output data signals read in response to the control of the controller 600 to the controller 600.

[0126] In the operation of the memory system according to an exemplary embodiment of the present invention, the controller 600 can generate a refresh command (S40) and can initiate operation by sending a refresh command to the memory device 700 (S41). For example, the memory device 700 can be a volatile dynamic random access memory and can perform a refresh operation to refresh the data of the memory cells in response to the refresh command (S42).

[0127] The controller 600, having already sent a refresh command to the memory device 700, can generate a test data pattern (S43). The test data pattern can be a pseudo-random binary sequence (PRBS) pattern and can be sent to the memory device 700 (S44). While performing a refresh operation on the memory cell, the memory device 700 can perform a clock adjustment operation to optimize the operating timing of the receiver receiving signals from the controller 600.

[0128] For example, in clock adjustment operations, a multilevel receiver connected to a pin that receives multilevel signals from controller 600 can receive test data patterns. In an example embodiment, the multilevel receiver can be connected to at least one of a data signal (DQ) pin, a data strobe signal (DQS) pin, and a command / address signal (CA) pin to receive multilevel signals. In an example embodiment, the multilevel signal can be a signal generated by a pulse amplitude modulation method.

[0129] The operating timing of the multilevel receiver can be determined by a clock controller that inputs a clock signal to the multilevel receiver. While the multilevel receiver receives the test data pattern, the clock controller can increase the delay time of the clock signal input to the multilevel receiver (S45). When the delay time of the clock signal increases and the output of the multilevel receiver does not match the test data pattern, the clock controller can set the corresponding delay time to a first threshold delay time (S46).

[0130] Next, the clock controller can reduce the delay time of the clock signal input to the multilevel receiver (S47). When the delay time of the clock signal is reduced and the output of the multilevel receiver does not match the test data pattern, the clock controller can set the corresponding delay time to a second threshold delay time (S48). The clock controller can use the first threshold delay time and the second threshold delay time to determine the phase of the clock signal (S49), and then can terminate the refresh operation (S50). However, according to the example embodiment, the refresh operation can be terminated first.

[0131] When the refresh operation is terminated, the multilevel receiver of memory device 700 can operate synchronously with a clock signal having adjusted phase. For example, by receiving a test data pattern pin during the refresh operation, after the refresh operation is terminated, the multilevel receiver can receive at least one of a data signal (DQ), a data strobe signal (DQS), and a command / address signal (CA) as a multilevel signal. The multilevel signal can be decoded into data according to the timing provided by the clock signal having adjusted phase.

[0132] Figure 24 This is a schematic diagram illustrating a memory system according to an example embodiment of the concept of the present invention.

[0133] according to Figure 24 The memory system 1000 of the example embodiment shown may be a solid-state drive (SSD). The memory system 1000 may have a form factor according to the M.2 standard and may communicate with external central processing units, systems-on-a-chip, application processors, etc., according to the Peripheral Component Interconnect Fast (PCI) protocol.

[0134] The memory system 1000 may include a system substrate 1001, connector pins 1002 and component elements 1003 formed on the system substrate 1001, a controller 1010 mounted on the system substrate 1001, a NAND memory 1020, a DRAM 1030, a PMIC 1040, etc. The connector pins 1002 may contact pins of computer equipment and / or server equipment to which the memory system 1000 is mounted. The component elements 1003 may include passive components, such as resistors and capacitors required for the operation of the memory system 1000.

[0135] The controller 1010 can control the memory system 1000 according to control commands from computer devices and / or server devices. The controller 1010 can store data received via connector pin 1002 in NAND memory 1020 and / or DRAM 1030, or read data stored in NAND memory 1020 and / or DRAM 1030 for output to computer devices and / or server devices. The PMIC 1040 can distribute power supplied via connector pin 1002 to the controller 1010, NAND memory 1020, DRAM 1030, etc.

[0136] The controller 1010 can be connected to the NAND memory 1020 and DRAM 1030 via wiring formed on the system substrate 1001. For example, the controller 1010 can generate data signals, etc., using a pulse amplitude modulation method and send them to the NAND memory 1020 and / or DRAM 1030. The multi-level receivers of the NAND memory 1020 and / or DRAM 1030, which receive data signals, such as pulse amplitude modulation type data signals, can operate synchronously with a clock signal received from the controller 1010. As previously referenced... Figures 1 to 23 As described, the NAND memory 1020 and / or DRAM 1030 may include a clock controller that adjusts the phase of each of the clock signals input to the sense amplifier included in the multilevel receiver.

[0137] Figure 25 This is a schematic diagram illustrating a mobile system including a semiconductor device according to an example embodiment of the present invention.

[0138] refer to Figure 25The mobile system 2000 may include a camera 2100, a display 2200, an audio processing unit 2300, a modem 2400, DRAM 2500a and 2500b, flash memory devices 2600a and 2600b, and an application processor (hereinafter referred to as "AP") 2800. The mobile system 2000 can be implemented as a laptop computer, portable terminal, smartphone, desktop PC, wearable device, healthcare device, or Internet of Things (IoT) device. Alternatively, the mobile system 2000 can be implemented as a server or personal computer.

[0139] Camera 2100 can capture still images or videos under user control. Mobile system 2000 can obtain specific information using the still images / videos captured by camera 2100, or it can convert the still images / videos into other types of data such as text and store them. Alternatively, mobile system 2000 can recognize strings included in the still images / videos captured by camera 2100 and can also provide text or audio translations corresponding to those strings. As mentioned above, the application areas of camera 2100 in mobile system 2000 are becoming increasingly diversified. In an example embodiment, camera 2100 can send data such as still images / videos to AP 2800 via a D-Phy or C-Phy interface according to the MIPI standard.

[0140] The display 2200 can be implemented in various forms, such as a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AM-OLED), a plasma display panel (PDP), a field emission display (FED), electronic paper, etc. In an example embodiment, the display 2200 can be used as an input device for the mobile system 2000 by providing touch screen functionality. Additionally, the display 2200 can be integrated with a fingerprint sensor, etc., to provide security features for the mobile system 2000. In an example embodiment, the AP 2800 can send image data to be displayed on the display 2200 via a D-Phy or C-Phy interface according to the MIPI standard.

[0141] The audio processing unit 2300 can process audio data stored in flash memory devices 2600a and 2600b or audio data included in content received from external devices such as modem 2400, input / output devices 2700a and 2700b. For example, the audio processing unit 2300 can perform various processes on the audio data, such as encoding / decoding, amplification, noise filtering, etc.

[0142] The modem 2400 can modulate and transmit signals to send / receive wired / wireless data, while simultaneously recovering the original signal by demodulating signals received from external sources. Input / output devices 2700a and 2700b are devices that provide digital input / output and may include ports for connecting to external recording media, input devices (e.g., touchscreens, mechanical buttons, etc.), and output devices capable of outputting vibrations via methods such as haptics. In some examples, input / output devices 2700a and 2700b can connect to external recording media via ports such as USB, Lightning cable, SD card, micro SD card, DVD, and network adapter.

[0143] AP 2800 can control the overall operation of mobile system 2000. Specifically, AP 2800 can control display 2200, causing a portion of the content stored in flash memory devices 2600a and 2600b to be displayed on the screen. Additionally, when receiving user input via input / output devices 2700a and 2700b, AP 2800 can perform control operations corresponding to the user input.

[0144] The AP 2800 can be provided as a System-on-Chip (SoC) driving applications, an operating system (OS), etc. Additionally, the AP 2800 can be included in a semiconductor package along with other devices included in the mobile system 2000 (e.g., DRAM 2500a, flash memory 2620, and / or memory controller 2610). For example, at least one device different from the AP 2800 can be provided in the form of a package such as a PoP, ball grid array (BGA), chip-scale package (CSP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), wafer-level processing stacked package (WSP), etc. An input / output scheduler or device driver for controlling the flash memory devices 2600a and 2600b can be included in the kernel of the operating system driving the AP 2800. The device driver can control the access performance of the flash memory devices 2600a and 2600b by referencing the number of synchronization queues managed by the input / output scheduler, or it can control CPU modes, dynamic voltage and frequency scaling (DVFS), etc., within the SoC.

[0145] In an example embodiment, the AP 2800 may include a processor block that performs operations or drives applications and / or an operating system, as well as various other peripheral components connected to the processor block via a system bus. Peripheral components may include a memory controller, internal memory, a power management block, an error detection block, a monitoring block, etc. The processor block may include one or more cores, and when multiple cores are included in the processor block, each of these cores may include a cache memory, and a common cache memory shared by these cores may be included in the processor block.

[0146] In the example embodiment, AP 2800 may also include accelerator block 2820, which is dedicated circuitry for AI data manipulation. Alternatively, according to the example embodiment, a separate accelerator chip may be provided separately from AP 2800, and DRAM 2500b may be additionally connected to accelerator block 2820 or the accelerator chip. Accelerator block 2820 is a functional block dedicated to performing specific functions of AP 2800 and may include a graphics processing unit (GPU) (which is a functional block dedicated to performing graphics data processing), a neural processing unit (NPU) (which is a block dedicated to performing AI computation and inference), a data processing unit (DPU) (which is a block dedicated to performing data transmission), etc.

[0147] According to an example embodiment, the mobile system 2000 may include multiple DRAMs 2500a and 2500b. In an example embodiment, the AP 2800 may include a controller 2810 for controlling the DRAMs 2500a and 2500b, and the DRAM 2500a may be directly connected to the AP 2800.

[0148] The AP 2800 can control the DRAM by setting a JEDEC-compliant Command and Mode Register (MRS) configuration, or by setting the specifications and functions required by the Mobile System 2000 (e.g., low voltage / high speed / reliability, and DRAM interface protocols for CRC / ECC). For example, the AP 2800 can communicate with the DRAM 2500a via a JEDEC-compliant interface such as LPDDR4 or LPDDR5. Alternatively, the AP 2800 can also communicate to control the DRAM 2500b used in an accelerator, in which the accelerator block 2820 or an accelerator chip provided separately from the AP 2800 has a higher bandwidth than the DRAM 2500a.

[0149] although Figure 25Only DRAMs 2500a and 2500b are shown, but the configuration of the mobile system 2000 is not necessarily limited to this type, and depending on the bandwidth, response speed, and voltage conditions of the AP 2800 or accelerator block 2820, other memories besides DRAMs 2500a and 2500b can be included in the mobile system 2000. For example, the controller 2810 and / or the accelerator block 2820 can control various memories such as PRAM, SRAM, MRAM, RRAM, FRAM, and hybrid RAM. DRAMs 2500a and 2500b have relatively lower latency and higher bandwidth compared to input / output devices 2700a and 2700b or flash memory devices 2600a and 2600b. DRAM 2500a and 2500b can be initialized when the mobile system 2000 is powered on, and if the operating system and application data are loaded, DRAM 2500a and 2500b can be used as temporary storage locations for application data or execution space for various software codes.

[0150] In DRAMs 2500a and 2500b, data for four arithmetic operations (addition / subtraction / multiplication / division), vector operations, address operations, or FFT operations can be stored. In other example embodiments, DRAMs 2500a and 2500b can be provided as processing-in-memory (PIM) equipped with arithmetic functions. For example, functions used in DRAMs 2500a and 2500b for performing inference can be executed. Here, inference can be performed using a deep learning algorithm employing an artificial neural network. The deep learning algorithm can include a training step of learning a model from various data and an inference step of recognizing data using the trained model. For example, functions for inference can include the hyperbolic tangent function, the sigmoid function, the corrected linear unit (ReLU) function, etc.

[0151] In some example embodiments, images captured by the user through camera 2100 can be signal processed and stored in DRAM 2500b, and accelerator block 2820 or accelerator chip can perform AI data manipulation recognition by using the data stored in DRAM 2500b and functions for inference.

[0152] In some example embodiments, the mobile system 2000 may include multiple memory devices or multiple flash memory devices 2600a and 2600b with a capacity greater than that of DRAMs 2500a and 2500b. Flash memory devices 2600a and 2600b may include a controller 2610 and flash memory 2620. The controller 2610 may receive control command data from the AP 2800 and, in response to the control commands, write data to the flash memory 2620 or read data stored in the flash memory 2620 to send it to the AP 2800.

[0153] According to an example embodiment, the accelerator block 2820 or accelerator chip can use flash memory devices 2600a and 2600b to perform training steps and AI data operations. In the example embodiment, the operational logic capable of performing predetermined or (alternatively) desired operations within the flash memory devices 2600a and 2600b can be implemented in the controller 2610, and the operational logic can also alternatively use data stored in the flash memory 2620 to perform at least a portion of the training steps and inference AI data operations performed by the AP 2800 and / or the accelerator block 2820.

[0154] In an example embodiment, AP 2800 may include interface 2830, and therefore, flash memory devices 2600a and 2600b can be directly connected to AP 2800. For example, AP 2800 may be implemented as a SoC, flash memory device 2600a may be implemented as a separate chip different from AP 2800, and AP 2800 and flash memory device 2600a may be mounted in a single package. However, the example embodiment of the inventive concept is not limited thereto, and multiple flash memory devices 2600a and 2600b may be electrically connected to mobile system 2000 via interconnection.

[0155] Flash memory devices 2600a and 2600b can store data such as still images / videos captured by camera 2100, or data received via a communication network and / or ports included in input / output devices 2700a and 2700b. For example, flash memory devices 2600a and 2600b can store augmented reality / virtual reality, high-definition (HD), or ultra-high-definition (UHD) content.

[0156] refer to Figure 25The described mobile system 2000 includes at least some of the following devices: camera 2100, display 2200, audio processing unit 2300, modem 2400, DRAM 2500a and 2500b, flash memory devices 2600a and 2600b, input / output devices 2700a and 2700b, and AP 2800. These devices can exchange multilevel signals with each other. For example, AP 2800 can exchange data with at least one of the other components via multilevel signals. (This is based on the above reference.) Figures 1 to 23 In at least one of the described example embodiments, the device for transmitting and receiving signals via multilevel signals can improve or optimize the operational timing of the multilevel receiver receiving multilevel signals.

[0157] One or more of the elements disclosed above may include or be implemented therein processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0158] As described above, according to an exemplary embodiment of the present invention, the phase of each of the clock signals input to a plurality of sense amplifiers receiving multi-level signals from another external semiconductor device can be adjusted individually. Therefore, the phase of each of the clock signals can be improved or optimized by taking into account the characteristic differences of each of the sense amplifiers, and the information received as a multi-level signal can be accurately recovered to improve the operating performance of the semiconductor device.

[0159] The various advantages and effects of the present invention are not limited to those described above, and can be more readily understood in the process of describing specific exemplary embodiments of the present invention.

[0160] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A multilevel receiver includes N sensing amplifiers and a decoder that decodes the outputs of the N sensing amplifiers. Each of the N sensing amplifiers receives a multilevel signal with M levels and a reference signal, where M is a natural number greater than 2 and N is a natural number less than M. A clock buffer is configured to receive a reference clock signal; as well as A clock controller is configured to: generate N clock signals using the reference clock signal, input the N clock signals to the N sense amplifiers respectively, and determine the phase of each of the N clock signals using the outputs of the N sense amplifiers respectively. The clock controller is further configured to: When the multi-level receiver receives a test data pattern as the multi-level signal from an external controller, a first threshold delay time for each of the N clock signals is determined by increasing the delay time of each of the N clock signals until the outputs of the N sense amplifiers differ from the test data pattern; and a second threshold delay time for each of the N clock signals is determined by decreasing the delay time of each of the N clock signals until the outputs of the N sense amplifiers differ from the test data pattern. Specifically, for each of the N clock signals, the phase is determined based on the first threshold delay time and the second threshold delay time.

2. The semiconductor device according to claim 1, wherein, The N sensing amplifiers include a first sensing amplifier and a second sensing amplifier, wherein the first sensing amplifier receives a first reference signal, and the second sensing amplifier receives a second reference signal different from the first reference signal. The N clock signals include a first clock signal input to the first sensing amplifier and a second clock signal input to the second sensing amplifier, wherein the phase of the first clock signal is different from the phase of the second clock signal.

3. The semiconductor device according to claim 1, wherein, The first threshold delay time has a positive sign, and the second threshold delay time has a negative sign. The delay time is determined based on the sum of the first threshold delay time and the second threshold delay time.

4. The semiconductor device according to claim 1, wherein, M is a power of 2, and N equals M-1.

5. The semiconductor device according to claim 1, wherein, The reference signal received by each of the N sensing amplifiers has a level different from the M levels.

6. The semiconductor device according to claim 1, wherein, The clock controller sequentially determines the phase of each of the N clock signals.

7. A semiconductor device, comprising: A memory cell array comprising multiple memory cells connected to multiple word lines and multiple bit lines; A word line driver, connected to the plurality of word lines; Read / write circuitry is connected to the plurality of bit lines; A multi-level receiver includes multiple sensing amplifiers that receive multi-level signals with M levels from an external controller, and a decoder that decodes the outputs of the multiple sensing amplifiers, where M is a natural number greater than 2; and A clock controller is configured to: generate multiple clock signals when the multi-level receiver receives a test data pattern from the external controller during a refresh operation of the memory cell, and input the multiple clock signals to the multiple sense amplifiers respectively, and adjust the phase of each of the multiple clock signals using the outputs of the multiple sense amplifiers respectively. Specifically, the clock controller determines a first threshold delay time for each of the plurality of clock signals by increasing the delay time of each clock signal until the output of the plurality of sense amplifiers differs from the test data pattern, and determines a second threshold delay time for each of the plurality of clock signals by decreasing the delay time of each clock signal until the output of the plurality of sense amplifiers differs from the test data pattern. Specifically, for each of the plurality of clock signals, the phase is determined based on the first threshold delay time and the second threshold delay time.

8. The semiconductor device according to claim 7, wherein, During the refresh operation, the multilevel receiver receives a pseudo-random binary sequence pattern "PRBS" as the test data pattern.

9. The semiconductor device according to claim 7, wherein, The multilevel signal is at least one of the data signal "DQ", the data strobe signal "DQS", and the command / address signal "CA".

10. The semiconductor device according to claim 7, wherein, Each of the plurality of sensing amplifiers includes a plurality of unit sensing amplifiers. Each of the plurality of clock signals includes a plurality of sub-clock signals with different phases, and Each of the plurality of unit sense amplifiers receives a corresponding sub-clock signal.

11. The semiconductor device according to claim 10, wherein, Each of the plurality of clock signals includes a first sub-clock signal and second to fourth sub-clock signals that are phase-shifted by 90 degrees, 180 degrees, and 270 degrees relative to the first sub-clock signal.

12. The semiconductor device according to claim 7, wherein, At least a portion of the multiple clock signals have different phases.

13. A memory system, comprising: A memory device having multiple memory cells; as well as The controller, connected to the memory device via multiple pins, is configured to control the memory device. The controller sends at least one of a data signal, a data strobe signal, and a command / address signal to the memory device through the plurality of pins. The controller sends a refresh command to the memory device. When the memory device performs a refresh operation in response to the refresh command, the controller sends a test data pattern as a multi-level signal to the memory device through at least one of the plurality of pins. The memory device is further configured to: When the test data pattern is received during the refresh operation, multiple clock signals are generated; and A first threshold delay time for each of the plurality of clock signals is determined by increasing the delay time of each clock signal until the outputs of the plurality of sense amplifiers in the memory device differ from the test data pattern; a second threshold delay time for each of the plurality of clock signals is determined by decreasing the delay time of each clock signal until the outputs of the plurality of sense amplifiers differ from the test data pattern. For each of the plurality of clock signals, the phase is determined based on the first threshold delay time and the second threshold delay time.

14. The memory system according to claim 13, wherein, The memory device receives the test data pattern via a pin that receives at least one of the plurality of pins: the data signal, the data strobe signal, and the command / address signal.

15. The memory system according to claim 14, wherein, The memory device receives, after the refresh operation, at least one of the data signal, the data strobe signal, and the command / address signal as the multi-level signal via the pin that received the test data pattern during the refresh operation.

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