Semiconductor memory device and method of operating a semiconductor memory device

Abstract

A semiconductor memory device includes an array of memory cells, an error correction code (ECC) engine, a scrub control circuit, and a control logic circuit. The array of memory cells includes rows of memory cells, each of the rows of memory cells including volatile memory cells. The scrub control circuit generates a scrub address for performing a normal scrub operation on a row of memory cells in a first cycle based on a refresh row address for refreshing the row of memory cells. The control logic circuit controls the ECC engine and the scrub control circuit to dynamically assign a scrub operation to a weak codeword within a refresh operation such that a dynamically assigned scrub (DAS) operation is performed in a second cycle that is less than the first cycle. An error bit is detected in each of the weak codewords during a normal scrub operation or a normal read operation on at least one of the rows of memory cells.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0101480, filed on August 3, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to memory, and more specifically, to semiconductor memory devices and methods of operating semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can be categorized into non-volatile memory devices, such as flash memory, and volatile memory devices, such as DRAM. The high-speed operation and cost-effectiveness of DRAM make it suitable for system memory. However, due to the continuous shrinking of DRAM manufacturing design rules, bit errors in memory cells within DRAM may increase and / or DRAM yields may decrease. Summary of the Invention

[0005] The example embodiments can provide more reliable semiconductor memory devices.

[0006] According to an example embodiment, a semiconductor memory device includes a memory cell array, an error-correcting code (ECC) engine, a cleanup control circuit, and control logic circuitry. The memory cell array includes a plurality of memory cell rows, and each of the plurality of memory cell rows includes a volatile memory cell. The cleanup control circuitry generates a cleanup address for performing a normal cleanup operation on the plurality of memory cell rows in a first cycle, based on a refresh row address used to refresh the plurality of memory cell rows. The control logic circuitry controls the ECC engine and the cleanup control circuitry to dynamically allocate cleanup operations to weak codewords within a refresh operation, such that a dynamic allocation cleanup (DAS) operation is performed in a second cycle less than the first cycle. An error bit is detected in each of the weak codewords during a normal cleanup operation or a normal read operation on at least one of the plurality of memory cell rows.

[0007] According to an example embodiment, in a method of operating a semiconductor memory device including a memory cell array, the memory cell array comprising a plurality of memory cell rows, each of the plurality of memory cell rows comprising a plurality of volatile memory cells, a cleanup control circuit generates a cleanup address for performing a normal cleanup operation on the plurality of memory cell rows based on a refresh row address for refreshing the plurality of memory cell rows. While an ECC engine performs a normal cleanup operation on the memory cell rows based on the cleanup address in a first cycle, an error correction code (ECC) engine stores the address of a weak codeword in an address storage table of the cleanup control circuit, and the cleanup operation on the weak codeword is dynamically performed during refresh operations. The ECC engine performs a dynamic allocation cleanup (DAS) operation on the weak codeword in a second cycle smaller than the first cycle. During a normal cleanup operation or a normal read operation on at least one of the plurality of memory cell rows, an error bit is detected in each of the weak codewords.

[0008] According to an example embodiment, a semiconductor memory device includes a memory cell array, an error-correcting code (ECC) engine, a refresh control circuit, a cleanup control circuit, and control logic circuitry. The memory cell array includes a plurality of memory cell rows, each of the plurality of memory cell rows including a volatile memory cell. The refresh control circuit generates refresh row addresses for refreshing the plurality of memory cell rows. The cleanup control circuit generates cleanup addresses based on the refresh row addresses for performing a normal cleanup operation on the plurality of memory cell rows in a first cycle. The control logic circuitry controls the ECC engine and the cleanup control circuitry to dynamically allocate cleanup operations to weak codewords within a refresh operation, such that a dynamic allocation cleanup (DAS) operation is performed in a second cycle less than the first cycle. During a normal cleanup operation or a normal read operation on at least one of the memory cell rows, an error bit is detected in each of the weak codewords. The control logic circuitry stores the address of the weak codeword as a weak codeword address in an address storage table of the cleanup control circuitry and provides a flag signal to the cleanup control circuitry to trigger the DAS operation.

[0009] Therefore, the semiconductor memory device includes an ECC engine and a cleanup control circuit. The ECC engine and cleanup control circuit perform a normal cleanup operation within a first cycle based on the refresh address. The ECC engine and cleanup control circuit dynamically allocate cleanup operations to weak codewords, wherein, during a normal cleanup operation or a normal read operation, an error bit is detected in a weak codeword within a refresh operation, and a DAS operation is performed in a second cycle shorter than the first cycle. Therefore, the semiconductor memory device can enhance reliability and / or performance by reducing or preventing the accumulation of error bits. Attached Figure Description

[0010] The exemplary embodiments will now be described in more detail with reference to the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating a memory system according to an example embodiment.

[0012] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of a semiconductor memory device.

[0013] Figure 3 Show Figure 2 An example of a first memory bank array in a semiconductor memory device.

[0014] Figure 4 This illustrates an example embodiment. Figure 2 A block diagram of the refresh control circuit in a semiconductor memory device.

[0015] Figure 5 This illustrates an example embodiment. Figure 4 The circuit diagram of an example refresh clock generator is shown.

[0016] Figure 6 This illustrates an example embodiment. Figure 4 A circuit diagram of another example of a refresh clock generator.

[0017] Figure 7 This is a circuit diagram illustrating interference between memory cells in a semiconductor memory device.

[0018] Figure 8 This illustrates an example embodiment. Figure 2 A block diagram of an example of a victim address detector in a semiconductor memory device.

[0019] Figure 9 It is shown Figure 8 A block diagram of the interference detector in the victim address detector.

[0020] Figure 10 This illustrates an example embodiment. Figure 2 A block diagram of an example of a cleanup control circuit in a semiconductor memory device.

[0021] Figure 11 This illustrates an example embodiment. Figure 10 Block diagram of the cleanup address generator in the cleanup control circuit.

[0022] Figure 12 Showing according to an example embodiment Figure 10 The weak codeword address generator in the cleanup control circuit.

[0023] Figure 13 Showing in the write operation Figure 2 It is part of a semiconductor memory device.

[0024] Figure 14 This is shown in the refresh operation or normal read operation. Figure 2 It is part of a semiconductor memory device.

[0025] Figure 15 This illustrates an example embodiment. Figure 2 A block diagram of an example ECC engine in a semiconductor memory device.

[0026] Figure 16 Showing according to an example embodiment Figure 15 An example of an ECC encoder in an ECC engine.

[0027] Figure 17 Showing according to an example embodiment Figure 15 An example of an ECC decoder in an ECC engine.

[0028] Figure 18 Showing according to an example embodiment Figure 17 The operation of the ECC decoder.

[0029] Figure 19 Shown in Figure 2 Normal refresh and cleanup operations performed in semiconductor memory devices.

[0030] Figure 20 Shown in Figure 2 Normal refresh and cleanup operations are performed in semiconductor memory devices.

[0031] Figure 21 Show Figure 19 or Figure 20 The timing of the cleanup operations.

[0032] Figure 22A The refresh and cleanup operations performed by a semiconductor memory device according to an example embodiment are shown.

[0033] Figure 22B This illustrates operation on a row of memory cells in a semiconductor memory device according to an example embodiment.

[0034] Figure 23 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0035] Figure 24 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0036] Figure 25 This is a flowchart illustrating a method of a semiconductor memory device according to an example embodiment.

[0037] Figure 26This is a diagram illustrating a semiconductor package including stacked memory devices according to an example embodiment. Specific Implementation

[0038] Various exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are illustrated.

[0039] Figure 1 This is a block diagram illustrating a memory system according to an example embodiment.

[0040] Reference Figure 1 The memory system 20 may include a memory controller 100 and / or a semiconductor memory device 200.

[0041] The memory controller 100 controls the overall operation of the memory system 20. The memory controller 100 controls the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 can write data to or read data from the semiconductor memory device 200 in response to a request from the host.

[0042] In addition, the memory controller 100 can issue operation commands to the semiconductor memory device 200 for controlling the semiconductor memory device 200.

[0043] In some example embodiments, the semiconductor memory device 200 is a memory device that includes dynamic memory cells, such as dynamic random access memory (DRAM), dual data rate 4 (DDR4) synchronous DRAM (SDRAM), low power DDR4 (LPDDR4) SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM.

[0044] The memory controller 100 can send a clock signal CLK, a command CMD, and / or an address (signal) ADDR to the semiconductor memory device 200, and exchange master data MD with the semiconductor memory device 200. The memory controller 100 sends write data to the semiconductor memory device 200 and receives read data from the semiconductor memory device 200.

[0045] The semiconductor memory device 200 may include a memory cell array 300 that stores master data MD and parity bits generated based on the master data MD, an error correction code (ECC) engine 400, control logic circuitry 210, and cleanup control circuitry 500.

[0046] The ECC engine 400, under the control of the control logic circuit 210, can perform ECC encoding on write data to be stored in the target page of the memory cell array 300, and can perform ECC decoding on codewords read from the target page.

[0047] The cleanup control circuit 500 generates cleanup addresses such that when a refresh operation is performed on multiple rows of memory cells included in the memory cell array 300, a cleanup operation is performed on a selected row of memory cells in the multiple rows of memory cells in a first cycle whenever a refresh operation is performed on N rows of memory cells. Here, N is a natural number greater than 2.

[0048] The control logic circuit 210 can control the ECC engine 400 to perform a normal cleanup operation, such that the ECC engine 400 reads data corresponding to the first codeword from at least one subpage specified by the cleanup address in the selected memory cell row, corrects at least one erroneous bit in the first codeword, and writes the corrected first codeword back to the memory location storing the at least one subpage.

[0049] The ECC engine 400 can store the address of the weak codeword in which an error bit is detected during normal cleanup operations in an address storage table in the cleanup control circuit 500.

[0050] The control logic circuit 210 can control the ECC engine 400 to dynamically distribute cleanup operations on weak codewords within a refresh operation, so that the Dynamic Allocation Cleanup (DAS) operation is performed in a second cycle less than the first cycle.

[0051] In some example embodiments, the memory controller 100 may include a central processing unit (CPU) 110. The CPU 110 may control the overall operation of the memory controller 100. The memory controller 100 may also include an ECC engine 130 that detects and corrects erroneous bits in data read from the semiconductor memory device 200.

[0052] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of a semiconductor memory device.

[0053] Reference Figure 2 The semiconductor memory device 200 may include control logic circuitry 210, address register 220, memory bank control logic 230, refresh control circuitry 385, row address multiplexer 240, column address latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, input / output (I / O) gate circuitry 290, ECC engine 400, cleanup control circuitry 500, victim address detector 560, and / or data I / O buffer 295.

[0054] The memory cell array 300 may include first memory cell arrays 310a to sixteenth memory cell arrays 310s. The row decoder 260 may include first memory cell row decoders 260a to sixteenth memory cell row decoders 260s respectively coupled to the first memory cell arrays 310a to sixteenth memory cell arrays 310s. The column decoder 270 may include first memory cell column decoders 270a to sixteenth memory cell column decoders 270s respectively coupled to the first memory cell arrays 310a to sixteenth memory cell arrays 310s. The sense amplifier unit 285 may include first memory cell sense amplifiers 285a to sixteenth memory cell sense amplifiers 285s respectively coupled to the first memory cell arrays 310a to sixteenth memory cell arrays 310s.

[0055] The first memory bank arrays 310a to 16th memory bank arrays 310s, the first memory bank row decoders 260a to 16th memory bank row decoders 260s, the first memory bank column decoders 270a to 16th memory bank column decoders 270s, and the first memory bank sense amplifiers 285a to 16th memory bank sense amplifiers 285s can form the first to sixteenth memory banks. Each of the first memory bank arrays 310a to 16th memory bank arrays 310s may include multiple memory cells MC formed at the intersection of multiple word lines WL and multiple bit lines BTL.

[0056] Address register 220 receives address ADDR from memory controller 100, which includes bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR. Address register 220 provides the received bank address BANK_ADDR to bank control logic 230, the received row address ROW_ADDR to row address multiplexer 240, and the received column address COL_ADDR to column address latch 250.

[0057] The memory bank control logic 230 generates a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, one of the first memory bank row decoders 260a to the sixteenth memory bank row decoder 260s corresponding to the memory bank address BANK_ADDR is activated, and in response to the memory bank control signal, one of the first memory bank column decoders 270a to the sixteenth memory bank column decoder 270s corresponding to the memory bank address BANK_ADDR is activated.

[0058] Row address multiplexer 240 receives row address ROW_ADDR from address register 220 and refresh row address REF_ADDR from refresh control circuit 385. Row address multiplexer 240 selectively outputs row address ROW_ADDR or refresh row address REF_ADDR as row address RA. Row address RA output from row address multiplexer 240 is applied to first memory bank row decoders 260a to sixteenth memory bank row decoders 260s.

[0059] The refresh control circuit 385 can sequentially output the refresh row address REF_ADDR in response to the first refresh control signal IREF1 or the second refresh control signal IREF2 from the control logic circuit 210.

[0060] When the command CMD from the memory controller 100 corresponds to an automatic refresh command, the control logic circuit 210 can apply the first refresh control signal IREF1 to the refresh control circuit 385 whenever it receives the automatic refresh command. When the command CMD from the memory controller 100 corresponds to a self-refresh enter command, the control logic circuit 210 can apply the second refresh control signal IREF2 to the refresh control circuit 385, and the second refresh control signal IREF2 is activated from the time the control logic circuit 210 receives the self-refresh enter command to the time the control logic circuit 210 receives the self-refresh exit command.

[0061] The refresh control circuit 385 can sequentially increment or decrement the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or during the activation of the second refresh control signal IREF2.

[0062] One of the sixteenth bank row decoders 260a to 260s is activated via the bank control logic 230 to decode the row address RA or target cleanup row address TSRA output from the row address multiplexer 240, and activates the word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line drive voltage to the word line corresponding to the row address RA.

[0063] Column address latch 250 receives column address COL_ADDR from address register 220 and temporarily stores the received column address COL_ADDR. In some example embodiments, in burst mode, column address latch 250 generates a column address incremented from the received column address COL_ADDR. Column address latch 250 applies the temporarily stored or generated column address to the first bank column decoders 270a through the sixteenth bank column decoders 270s.

[0064] One of the sixteenth bank column decoders 270a to 270s is activated via I / O gate 290, which activates the sense amplifier corresponding to the bank address BANK_ADDR and column address COL_ADDR or the target cleanup column address TSCA.

[0065] I / O gate circuit 290 may include circuitry for gating input / output data, and may also include input data masking logic, read data latches for storing data output from the first memory array 310a to the sixteenth memory array 310s, and / or write drivers for writing data to the first memory array 310a to the sixteenth memory array 310s.

[0066] A codeword CW read from one of the memory arrays 310a to 310s is coupled to the readout amplifier of the memory array from which it is read and stored in a read data latch. After ECC decoding of the codeword CW by the ECC engine 400, the codeword CW stored in the read data latch can be provided to the memory controller 100 via the data I / O buffer 295.

[0067] The master data MD to be written to one of the memory arrays 310a to 310s can be provided from the memory controller 100 to the data I / O buffer 295, and from the data I / O buffer 295 to the ECC engine 400. The ECC engine 400 can perform ECC encoding on the master data MD to generate parity bits. The ECC engine 400 can provide the master data MD and the parity bits to the I / O gate 290, and the I / O gate 290 can write the master data MD and the parity bits to a subpage in a memory array via a write driver.

[0068] The data I / O buffer 295 can provide the master data MD from the memory controller 100 to the ECC engine 400 during write operations of the semiconductor memory device 200 based on the clock signal CLK, and can also provide the master data MD from the ECC engine 400 to the memory controller 100 during read operations of the semiconductor memory device 200.

[0069] The cleanup control circuit 500 can count the sequentially changing refresh row addresses REF_ADDR, and output a normal cleanup address SCADDR whenever the cleanup control circuit 500 counts N refresh row addresses. Here, N is an integer greater than 2. The normal cleanup address SCADDR may include the cleanup row address SRA and the cleanup column address SCA.

[0070] In the first cleanup mode, the cleanup control circuit 500 can provide the cleanup row address SRA and the cleanup column address SCA to the row decoder 260 and column decoder 270, respectively. The ECC engine 400 can store the addresses of these weak codewords and detect error bits in each of these weak codewords during normal cleanup operations.

[0071] The ECC engine 400 performs ECC decoding on codewords read from subpages of the target page during normal cleanup or read operations. When at least one error bit is detected in the main data of the codeword, it provides an error generation signal EGS to the control logic circuit 210 to correct the error bit. The control logic circuit 210 stores the row and column addresses of the codeword containing at least one error bit as an error address EADDR in an address storage table within the cleanup control circuit 500.

[0072] In some embodiments, instead of the control logic circuit 210, the ECC engine 400 can directly store the error address EADDR in the address storage table.

[0073] During DAS operation, the ECC engine 400 performs ECC decoding on the weak codeword from the weak subpage, corrects at least one erroneous bit in the weak codeword, and writes the corrected weak codeword back to the memory location corresponding to the weak subpage.

[0074] Victim address detector 560 can count the number of accesses to a first memory region in memory cell array 300, and generate at least one victim address VCT_ADDR specifying at least one adjacent memory region adjacent to the first memory region when the counted number of accesses reaches a reference value during a reference interval.

[0075] Victim address detector 560 may provide at least one victim address VCT_ADDR to row decoder 260, causing a target refresh operation to be performed on at least one adjacent memory region. In some example embodiments, victim address detector 560 may store at least one victim address VCT_ADDR in an address storage table in cleanup control circuitry 500.

[0076] In the second cleanup mode, the cleanup control circuit 500 may, in response to the flag signal DASFG from the control logic circuit, output the address of the codeword associated with the error address EADDR or the victim address VCT_ADDR stored in the address storage table as the weak codeword address WCADDR. The weak codeword address WCADDR may include the weak codeword row address WCRA and the weak codeword column address WCCA. In the second cleanup mode, the cleanup control circuit 500 may provide the weak codeword row address WCRA and the weak codeword column address WCCA to the row decoder 260 and the column decoder 270, respectively.

[0077] Control logic circuitry 210 can control the operation of semiconductor memory device 200. For example, control logic circuitry 210 can generate control signals for semiconductor memory device 200 to perform write or read operations. Control logic circuitry 210 may include command decoder 211 for decoding commands CMD received from memory controller 100 and mode register 212 for setting the operating mode of semiconductor memory device 200. Control logic circuitry 210 may include counter 214 for counting error generation signals EGS.

[0078] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding write enable signals, row address strobe signals, column address strobe signals, chip select signals, etc. The control logic circuit 210 can generate a first control signal CTL1 for controlling I / O gate circuit 290, a second control signal CTL2 for controlling ECC engine 400, a third control signal CTL3 for controlling cleanup control circuit 500, and a fourth control signal CTL4 for controlling victim address detector 560.

[0079] Furthermore, control logic circuit 210 can provide refresh control circuit 385 with a mode signal MS associated with the refresh cycle. Control logic circuit 210 can generate mode signal MS based on a temperature signal representing the operating temperature of semiconductor memory device 200. Additionally, control logic circuit 210 can provide cleanup control circuit 500 with error address EADDR and flag signal DASFG.

[0080] Figure 3 Show Figure 2 An example of a first memory bank array in a semiconductor memory device.

[0081] Reference Figure 3 The first memory bank array 310 may include multiple word lines WL1 to WLm (m is a natural number greater than 2), multiple bit lines BTL1 to BTLn (n is a natural number greater than 2), and multiple volatile memory cells MC disposed at the intersections between the word lines WL1 to WLm and the bit lines BTL1 to BTLn. Each of the memory cells MC may include a cell transistor coupled to each of the word lines WL1 to WLm and each of the bit lines BTL1 to BTLn, and a cell capacitor coupled to the cell transistor.

[0082] Figure 4 This illustrates an example embodiment. Figure 2 A block diagram of an example refresh control circuit in a semiconductor memory device.

[0083] Reference Figure 4The refresh control circuit 385 may include a refresh clock generator 390 and / or a refresh counter 397.

[0084] The refresh clock generator 390 can generate a refresh clock signal RCK in response to a first refresh control signal IREF1, a second refresh control signal IREF2, and a mode signal MS. The mode signal MS determines the refresh period of the refresh operation. As described above, the refresh clock generator 390 generates the refresh clock signal RCK whenever it receives the first refresh control signal IREF1 or during the activation of the second refresh control signal IREF2.

[0085] The refresh counter 397 can generate the refresh row address REF_ADDR that sequentially specifies the rows of memory cells by performing a counting operation during the refresh clock signal RCK.

[0086] Figure 5 This illustrates an example embodiment. Figure 4 The circuit diagram shown is an example of a refresh clock generator.

[0087] Reference Figure 5 The refresh clock generator 390a may include multiple oscillators 391, 392, and 393, a multiplexer 394, and / or a decoder 395a. The decoder 395a decodes a first refresh control signal IREF1, a second refresh control signal IREF2, and a mode signal MS to output a clock control signal RCS1. The oscillators 391, 392, and 393 generate refresh clock signals RCK1, RCK2, and RCK3 with different periods. The multiplexer 394, in response to the clock control signal RCS1, selects one of the refresh clock signals RCK1, RCK2, and RCK3 to provide the refresh clock signal RCK.

[0088] Figure 6 This illustrates an example embodiment. Figure 4 A circuit diagram of another example of a refresh clock generator.

[0089] Reference Figure 6 The refresh clock generator 390b may include a decoder 395b, a bias unit 396a, and / or an oscillator 396b. The decoder 395b decodes a first refresh control signal IREF1, a second refresh control signal IREF2, and a mode signal MS to output a clock control signal RCS2. The bias unit 396a generates a control voltage VCON in response to the clock control signal RCS2. The oscillator 396b generates a refresh pulse signal RCK with a variable period based on the control voltage VCON.

[0090] Figure 7This is a circuit diagram illustrating interference between memory cells in a semiconductor memory device.

[0091] Reference Figure 7 A portion of the semiconductor memory device 200 may include memory cells 51, 52 and 53 and / or bit line sense amplifier 60.

[0092] Assume that each of memory cells 51, 52, and 53 is connected to the same bit line BTL. Furthermore, memory cell 51 is connected to the word line WL. <g-1>Memory cell 52 is connected to word line WL <g>Memory cell 53 is connected to word line WL<g+1> .like Figure 7 As shown, the word line WL <g-1>and WL<g+1> Located near the word line WL <g>Memory cell 51 may include access transistor CT1 and cell capacitor CC1. The gate terminal of access transistor CT1 is connected to word line WL. <g-1>Furthermore, one terminal of access transistor CT1 is connected to bit line BTL. Memory cell 52 may include access transistor CT2 and cell capacitor CC2. The gate terminal of access transistor CT2 is connected to word line WL. <g>Furthermore, one terminal of access transistor CT2 is connected to bit line BTL. Additionally, memory cell 53 may include access transistor CT3 and cell capacitor CC3. The gate terminal of access transistor CT3 is connected to word line WL.<g+1> Furthermore, one terminal of the access transistor CT3 is connected to the bit line BTL.

[0093] Bit line sense amplifier 60 may include an N sense amplifier and a P sense amplifier, wherein the N sense amplifier discharges low-level bit lines in bit lines BTL and BTLB, and the P sense amplifier charges high-level bit lines in bit lines BTL and BTLB.

[0094] During a refresh operation, the bit line sense amplifier 60 rewrites the data stored in the selected memory cell via the N sense amplifier or P sense amplifier. During a read or write operation, a selection voltage (e.g., Vpp) is provided to the word line WL. <g>Then, due to capacitive coupling, even when no selection voltage is applied, adjacent word lines WL... <g-1>and WL<g+1> The voltage also rises. This capacitive coupling is represented by parasitic capacitances Ccl1 and Cc2l.

[0095] During the no-refresh operation, when the word line WL <g>When accessed repeatedly, the data is stored in the word line WL. <g-1>and WL<g+1> The charge in the cell capacitors CC1 and CC3 of memory cells 51 and 53 may gradually leak. In some example embodiments, the reliability of logic "0" stored in cell capacitor CC1 and logic "1" stored in cell capacitor CC3 may not be guaranteed. Therefore, it is necessary to perform cleanup operations on the memory cells at appropriate times.

[0096] Figure 8 This illustrates an example embodiment. Figure 2 A block diagram of an example of a victim address detector in a semiconductor memory device.

[0097] Reference Figure 8 The victim address detector 560 may include an interference detector 570 and / or a victim address generator 577.

[0098] Interference detector 570 can count the number of accesses to a first memory region (e.g., at least one memory cell row) based on row address ROW_ADDR, and generate a first detection signal DET1 when the counted number of accesses reaches a reference value during a reference (or predetermined, or alternatively, desired) interval.

[0099] Victim address generator 577 can generate at least one victim address VCT_ADDR1 and VCT_ADDR2 in response to the first detection signal DET1. The at least one victim address VCT_ADDR1 and VCT_ADDR2 can be a row address specifying a second memory region and a third memory region adjacent to the first memory region. Victim address generator 577 can provide at least one victim address VCT_ADDR1 and VCT_ADDR2 to the address storage table in the cleanup control circuit 500.

[0100] Figure 9 It is shown Figure 8 A block diagram of the interference detector in the victim address detector.

[0101] Reference Figure 9 The interference detector 570 may include an access counter 571, a threshold register 573, and / or a comparator 575.

[0102] Access counter 571 can count the number of accesses to a specified address (or a specified memory region) based on the row address ROW_ADDR. For example, access counter 571 can count the number of accesses to a specified word line. It can count the number of accesses to a specific word line or a group of word lines comprising at least two word lines. Furthermore, the counting of accesses can be performed by a specific block cell, memory cell, or chip cell.

[0103] Threshold register 573 can store a maximum interference generation count that guarantees the reliability of data in a specific word line or memory cell. For example, a threshold (or reference value) on a word line can be stored in threshold register 573. Alternatively, a threshold on a group of word lines, a block, a memory cell, or a chip cell can be stored in threshold register 573.

[0104] Comparator 575 compares a reference value stored in threshold register 573 with the number of accesses to a specific memory region counted by access counter 571. If a memory region exists whose counted accesses reach the reference value, comparator 575 generates a first detection signal DET1. Comparator 575 provides the first detection signal DET1 to victim address generator 577.

[0105] The victim address generator 577 receives the row address ROW_ADDR and generates at least one victim address VCT_ADDR1 and VCT_ADDR2 in response to the first detection signal DET1.

[0106] Figure 10 This illustrates an example embodiment. Figure 2 A block diagram of an example of a cleanup control circuit in a semiconductor memory device.

[0107] Reference Figure 10 The cleanup control circuit 500 may include a counter 505, a cleanup address generator 510, and / or a weak codeword address generator 520.

[0108] Counter 505 counts the refresh row address REF_ADDR and generates an internal cleanup signal ISRB, which is active during a first interval during which the counter 505 counts the refresh row address REF_ADDR to the number specified by the count control signal CCS. The first interval may correspond to the time interval used to refresh one memory cell row.

[0109] The cleanup address generator 510, in response to the internal cleanup signal ISRB and the cleanup mode signal SMS, generates a normal cleanup address SCADDR associated with the normal cleanup operation of the codeword for each of the memory cell rows, the normal cleanup address SCADDR being gradually changed in the first cleanup mode.

[0110] A normal cleanup address SCADDR may include a cleanup row address (SRA) and a cleanup column address (SCA). The cleanup row address (SRA) specifies a page in a memory array, and the cleanup column address (SCA) specifies a codeword in that page. The cleanup address generator 510 provides the cleanup row address (SRA) to the corresponding row decoder and the cleanup column address (SCA) to the corresponding column decoder.

[0111] The cleanup operation performed based on the normal cleanup address SCADDR can be called a normal cleanup operation because the cleanup operation performed based on the normal cleanup address SCADDR is performed on all codewords included in the memory cell array 300.

[0112] The weak codeword address generator 520 generates a weak codeword address WCADDR associated with a weak cleanup operation in a second cleanup mode, in response to an internal cleanup signal ISRB and a cleanup mode signal SMS. The weak cleanup operation is associated with weak codewords in the memory array. The weak codeword address WCADDR may include a weak codeword row address WCRA and a weak codeword column address WCCA. When the cleanup mode signal SMS has a first logic level, it indicates a first cleanup mode; and when it has a second logic level, it indicates a second cleanup mode. The cleanup mode signal SMS may be included in a third control signal CTL3. The weak codeword address generator 520 provides the weak codeword row address WCRA to the corresponding row decoder and the weak codeword column address WCCA to the corresponding column decoder.

[0113] The weak codeword address generator 520 may include an address storage table, which may store the addresses of codewords associated with the victim address VCT_ADDR and the fault address EADDR.

[0114] The cleanup operation performed based on the weak codeword address WCADDR can be called a weak cleanup operation because the cleanup operation performed based on the weak codeword address WCADDR is performed on the weak codewords included in the memory cell array 300.

[0115] Figure 11 This illustrates an example embodiment. Figure 10 Block diagram of the cleanup address generator in the cleanup control circuit.

[0116] Reference Figure 11 The cleanup address generator 510 may include a page segment counter 511 and a row counter 513.

[0117] Page segment counter 511 increments the cleanup column address SCA by 1 during the activation of the internal cleanup signal ISRB in the first cleanup mode, and activates the maximum address detection signal MADT in response to the internal cleanup signal ISRB and the cleanup mode signal SMS, resetting it whenever the cleanup column address SCA reaches its maximum value. Page segment counter 511 provides the maximum address detection signal MADT to row counter 513.

[0118] Row counter 513 begins counting operation one, which initially receives the internal cleanup signal ISRB and increments the cleanup row address SRA by 1 each time the maximum address detection signal MADT is activated in response to the internal cleanup signal ISRB and the cleanup mode signal SMS. Since the internal cleanup signal ISRB is activated during the first interval while a refresh operation is performed on a memory cell row, page segment counter 511 can generate the cleanup column address SCA associated with the codeword in a page during the first interval.

[0119] Figure 12 Showing according to an example embodiment Figure 10 The weak codeword address generator in the cleanup control circuit.

[0120] Reference Figure 12 The weak codeword address generator 520 may include a pointer signal (TPS) generator 521, an address storage table 530, and / or a readout unit 540.

[0121] Address storage table 530 stores address information WCRA1 to WCRAu and WCCA1 to WCCAv (v is a positive integer greater than u) of weak codewords included in memory cell array 300.

[0122] A weak codeword can be a codeword in which erroneous bits are detected in each of its pages during a normal cleanup or read operation. A weak codeword can be all or some of the pages in each memory bank array of memory cell array 300 that comprise a weak page with an erroneous bit count greater than a reference value. Furthermore, a weak codeword can be the codeword of an adjacent page adjacent to a densely accessed memory region.

[0123] During the refresh cycle, the TPS generator 521 can generate a pointer signal TPS that provides location information for the address storage table 530 in response to the flag signal DASFG and the cleanup mode signal SMS, and provide the pointer signal TPS to the address storage table 530 in the second cycle. The flag signal DASFG can trigger DAS operation.

[0124] Address storage table 530 may include non-volatile memory. From Figure 8 At least one victim address, VCT_ADDR1, and VCT_ADDR2, provided by the victim address generator 577 can be stored in the address storage table 530.

[0125] During the refresh cycle, the pointer signal TPS gradually increases with the second cycle, and each time the pointer signal TPS is applied, the address storage table 530 can output the weak codeword address stored in the position (indicated by the pointer signal TPS) through the read unit 540 as the weak codeword row address WCRA and the weak codeword column address WCCA. The read unit 540 provides the weak codeword row address WCRA to the corresponding row decoder and the weak codeword column address WCCA to the corresponding column decoder.

[0126] As described above, control logic circuit 210 can provide the error address EADDR to cleanup control circuit 500. When cleanup control circuit 500 performs K cleanup operations on a specific memory cell row and ECC engine 400 detects an error bit while reading the specific memory cell row, it determines that the specific memory cell row has a permanent fault. When the specific memory cell row with a permanent fault is not replaced, the error bit can accumulate. Therefore, control logic circuit 210 or memory controller 10 can replace the specific memory cell row with a permanent fault with a redundant memory cell row through a redundancy repair operation.

[0127] Furthermore, the control logic circuit 210 can apply different refresh cycles to some memory cell rows based on the number of error bits detected in each memory cell row by the cleanup operation.

[0128] Figure 13 Showing in the write operation Figure 2 It is part of a semiconductor memory device.

[0129] exist Figure 13 The diagram shows a control logic circuit 210, a first memory array 310, an I / O gate circuit 290, and an ECC engine 400.

[0130] Reference Figure 13 The first storage array 310 may include a normal cell array (NCA) and / or a redundant cell array (RCA).

[0131] The normal cell array (NCA) may include multiple first memory blocks MB0 to MB15, such as 311 to 313, and the redundant cell array (RCA) may include at least a second memory block 314. The first memory blocks 311 to 313 are memory blocks that determine the memory capacity of the semiconductor memory device 200. The second memory block 314 is used for ECC and / or redundancy repair. Because the second memory block 314 used for ECC and / or redundancy repair is used for ECC, data line repair, and block repair to repair "faulty" cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block.

[0132] In each of the first memory blocks 311 to 313, a plurality of first memory cells are arranged in a multi-row, multi-column configuration. In the second memory block 314, a plurality of second memory cells are arranged in a multi-row, multi-column configuration. A first memory cell connected to the intersection of the word line WL and the bit line BTL can be a dynamic memory cell. A second memory cell connected to the intersection of the word line WL and the bit line BTL can also be a dynamic memory cell.

[0133] I / O gate circuit 290 may include a plurality of switching circuits 291a to 291d respectively connected to the first memory blocks 311 to 313 and the second memory block 314. In the semiconductor memory device 200, bit lines corresponding to burst length (BL) data can be accessed simultaneously to support a maximum number of BLs indicating the maximum number of accessible column positions.

[0134] The ECC engine 400 can be connected to the switching circuits 291a to 291d via the first data line GIO and the second data line EDBIO. The control logic circuit 210 can receive the command CMD and the address ADDR, and can decode the command CMD to generate a first control signal CTL1 for controlling the switching circuits 291a to 291d and a second control signal CTL2 for controlling the ECC engine 400.

[0135] When the command CMD is a write command, the control logic circuit 210 provides a second control signal CTL2 to the ECC engine 400, and the ECC engine 400 performs ECC encoding on the master data MD to generate parity bits associated with the master data MD, and provides the codeword CW, which includes the master data MD and the parity bits, to the I / O gate circuit 290. The control logic circuit 210 provides a first control signal CTL1 to the I / O gate circuit 290, causing the codeword CW to be stored in a subpage of the target page in the first memory array 310.

[0136] Figure 14 This is shown in the refresh operation or normal read operation. Figure 2 It is part of a semiconductor memory device.

[0137] exist Figure 14 The diagram shows a control logic circuit 210, a first memory array 310, an I / O gate circuit 290, an ECC engine 400, and a cleanup control circuit 500.

[0138] Reference Figure 14 When the command CMD is a refresh command (first command) specifying a refresh operation, the control logic circuit 210 provides the I / O gate circuit 290 with the first control signal CTL1, so that the first (read) codeword RCW in each subpage of the target page stored in the first memory array 310 is provided to the ECC engine 400.

[0139] During the refresh operation, the ECC engine 400 performs ECC decoding on the codeword RCW. When the codeword RCW contains erroneous bits, the ECC engine 400 performs a normal cleanup operation to correct the erroneous bits and writes the corrected master data back to the child page.

[0140] When an error bit is detected during normal cleanup operations, the ECC engine 400 provides an error generation signal EGS to the control logic circuit 210 in response to the detection of the error bit. The control logic circuit 210 can count the error generation signals EGS for a page and store the address of the codeword including the error bit as the error address EADDR in the address storage table, and can apply a flag signal DASFG to the cleanup control circuit 500.

[0141] The cleanup control circuit 500 can respond to the flag signal DASFG by providing the row address WCRA and column address WCCA of the weak code word stored in the address storage table 530 to the row decoder 260 and column decoder 270, respectively.

[0142] When the command CMD corresponds to a read command, the ECC engine 400 can provide the corrected master data C_MD to the data I / O buffer 295.

[0143] Therefore, in the cleanup operation performed in response to a refresh command or read command, the ECC engine 400 performs error detection (operation) on the codewords in the selected memory cell row, and in response to the error information, writes the respective codewords, including the correctable error bits, back to the corresponding memory location. Thus, the ECC engine 400 can reduce the time interval for performing cleanup operations and reduce the cleanup cycle.

[0144] Figure 15 This illustrates an example embodiment. Figure 2 A block diagram of an example ECC engine in a semiconductor memory device.

[0145] Reference Figure 15 The ECC engine 400 may include an ECC encoder 410, an ECC decoder 430, and / or an ECC memory 420. The ECC memory 420 may store ECC 425.

[0146] ECC encoder 410 is coupled to ECC memory 420 and can generate parity bit PRT associated with write data WMD to be stored in the normal cell array NCA of the first memory array 310. Parity bit PRT can be stored in the redundant cell array RCA of the first memory array 310.

[0147] ECC decoder 430 is coupled to ECC memory 420. ECC decoder 430 can perform ECC decoding on read data RMD based on read data RMD and parity bit PRT read from first memory array 310. When the read data RMD includes at least one error bit as a result of ECC decoding, ECC decoder 430 provides error generation signal EGS to control logic circuit 210 and corrects the error bit in read data RMD to output corrected master data C_MD.

[0148] Figure 16 Showing according to an example embodiment Figure 15 An example of an ECC encoder in an ECC engine.

[0149] Reference Figure 16 The ECC encoder 410 may include a parity generator 415. The parity generator 415 receives write data WMD and a basic bit BB, and generates a parity bit PRT by performing, for example, an XOR array operation. The basic bit BB is the bit used to generate the parity bit PRT for the write data WMD, and may include b'0000000. The basic bit BB may include other specific bits besides b'0000000.

[0150] Figure 17 Showing according to an example embodiment Figure 15 An example of an ECC decoder in an ECC engine.

[0151] Reference Figure 17 The ECC decoder 430 may include a corrector generation circuit 440, an error locator 460, and / or a data corrector 470. The corrector generation circuit 440 may include a check bit generator 441 and / or a corrector generator 443.

[0152] The check bit generator 441 generates the check bit CHB based on the read data RMD by performing an XOR array operation, and the corrector generator 443 generates the corrector SDR by comparing the corresponding bits of the check bit CHB and the parity bit PRT.

[0153] Error locator 460 generates an error bit position signal EPS indicating the location of an error bit in the read data RMD, providing the error bit position signal EPS to data corrector 470 when all bits of the corrector SDR are not "0". Additionally, when the read data RMD includes an error bit, error locator 460 provides an error generation signal EGS to control logic circuitry 210.

[0154] The data corrector 470 receives read data RMD. When the read data RMD includes error bits, it corrects the error bits in the read data RMD based on the error bit position signal EPS and outputs the corrected master data C_MD.

[0155] Figure 18 Showing according to an example embodiment Figure 17 The operation of the ECC decoder.

[0156] Reference Figure 17 and Figure 18 In a cleanup operation in response to a refresh command, the codeword CW may include at least one error bit EB1. The codeword CW is read from the first page and provided to the ECC engine 400, as indicated by reference numeral 581. The ECC engine 400 performs ECC decoding on the codeword CW to correct at least one error bit EB1, as indicated by reference numeral 582, and writes the corrected master data C_MD back to a subpage of the first page, as indicated by reference numeral 583.

[0157] Figure 19 Shown in Figure 2 Normal refresh and cleanup operations performed in semiconductor memory devices.

[0158] exist Figure 19 In this context, tRFC represents the refresh cycle and the time used to refresh one row, while tREI represents the refresh interval and the interval between two consecutive refresh commands.

[0159] Reference Figure 19 Note that the cleanup control circuit 500 specifies the memory cell row M times. Whenever the memory cell row is processed N times using a normal refresh operation REF in response to a refresh command, the ECC engine performs a cleanup operation SCRB on the memory cell row. Here, M is an integer greater than 1 and less than N.

[0160] Figure 20 Shown in Figure 2 Normal refresh and cleanup operations performed in semiconductor memory devices.

[0161] Reference Figure 20 Note that the cleanup control circuit 500 specifies memory cell rows to be cleaned S times. During the first interval INT1, whenever N normal refresh operations NREF are performed on the memory cell row in response to a refresh command, the ECC engine 400 performs a cleanup operation SCRB on the memory cell row and performs L refresh operations FREF on the adjacent memory region corresponding to the victim address VCT_ADDR. Here, L is a natural number less than N, and S is a natural number less than L.

[0162] During the second interval INT2, L refresh operations FREF are performed on the adjacent memory region corresponding to the victim address VCT_ADDR, and during the first interval INT1, whenever N normal refresh operations NREF are performed on the memory cell row in response to a refresh command, T DAS operations DAS are performed on the weak codeword. Here, T is a natural number less than N and L.

[0163] Figure 21 Show Figure 19 or Figure 20 The timing of the cleanup operations.

[0164] Reference Figure 21 During the refresh cycle tRFC, when a memory cell row is refreshed, the internal cleanup signal ISRB is activated to a logic high level. After the refresh command is applied and the boundary MG has passed, the word line WL coupled to the memory cell row specified by the cleanup row address is activated.

[0165] After word line WL is activated and the RAS-to-CAS delay time tRCD has elapsed, the M codewords in the memory cell row specified by the cleanup row address are sequentially subjected to the normal cleanup operation NSCLB_OP. A cleanup operation is performed on a codeword during the time interval tCCDscrb. During the write time tWR, the corrected codeword is written back to the corresponding memory location, and word line WL is deactivated after the corrected codeword is written back.

[0166] After the word line WL is deactivated and the row precharge time tRP has elapsed, the internal cleanup signal ISRB is deactivated.

[0167] When at least one weak codeword is detected during the normal cleanup operation NSCLRB_OP, the word line WL is activated during an interval in the refresh operation, and a DAS operation on the at least one weak codeword can be performed.

[0168] Figure 22A The refresh and cleanup operations performed by a semiconductor memory device according to an example embodiment are shown.

[0169] exist Figure 22A In this context, reference numeral 591 represents the normal refresh operation NREF on the sacrificial memory region, and reference numeral 593 represents the target refresh operation FREF on the sacrificial memory region. Reference numeral 595 represents the normal cleanup operation NSCRB, and reference numeral 597 represents the DAS operation DAS.

[0170] Reference Figure 22A Note that the DAS operation is performed on weak codewords more frequently than the normal cleanup operation NSCLRB, and the target refresh operation FREF is performed more frequently than the normal refresh operation NREF.

[0171] In other words, when Figure 14 When the control logic circuit 210 receives an error generation signal EGS during a normal cleanup operation or normal read operation, it ensures an additional refresh time interval within a predetermined or alternatively desired refresh cycle, and may perform a DAS operation or a target refresh operation FREF during the additional refresh time interval.

[0172] Figure 22B This illustrates operation on a row of memory cells in a semiconductor memory device according to an example embodiment.

[0173] Reference Figure 22B Determine whether the corresponding memory cell row has been used sequentially for the target refresh operation FREF (operation S210). When the corresponding memory cell row has been used sequentially for the target refresh operation FREF (yes in S210), perform the target refresh operation FREF on the corresponding memory cell row (operation S215).

[0174] If the corresponding memory cell row is not used sequentially for the target refresh operation FREF (No in S210), determine whether the corresponding memory cell row is used sequentially for the DAS operation DAS (Operation S220). If the corresponding memory cell row is used sequentially for the DAS operation DAS (Yes in S220), perform the DAS operation DAS on the corresponding memory cell row (Operation S225).

[0175] If the corresponding memory cell row is not used sequentially for DAS operation (No in S220), determine whether the corresponding memory cell row is used sequentially for normal cleanup operation NSCLRB (operation S230). If the corresponding memory cell row is used sequentially for normal cleanup operation NSCLRB (Yes in S230), perform normal cleanup operation NSCRB on the corresponding memory cell row (operation S235).

[0176] If the corresponding memory cell row is not used sequentially in the normal cleanup operation NSCLRB (No in S230), determine whether the corresponding memory cell row has been used sequentially in the normal refresh operation NREF (Operation S240). If the corresponding memory cell row has been used sequentially in the normal refresh operation NREF (Yes in S240), perform the normal refresh operation NREF on the corresponding memory cell row (Operation S245). If the corresponding memory cell row is not used sequentially in the normal refresh operation NREF (No in S240), the process terminates.

[0177] Figure 23 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0178] Reference Figure 23 The image shows a semiconductor memory device 200a. The semiconductor memory device 200a may include multiple memory arrays 310a to 310s, multiple memory ECC engines 400a to 400s corresponding to the multiple memory arrays 310a to 310s, and multiple memory cleanup control circuits 500a to 500s corresponding to the multiple memory arrays 310a to 310s. Figure 2 The ECC engine 400 and multiple memory cleanup control circuits 500a to 500s can correspond to Figure 2 The cleaning control circuit 500 in the middle.

[0179] In response to the cleanup mode signal SMS1, the cleanup address generator 510a in the memory bank cleanup control circuit 500a corresponding to the first memory bank array 310a is enabled, and the cleanup address generator 510a generates a cleanup address SCADDR, and the memory bank ECC engine 400a performs a normal cleanup operation NS0 on all codewords in the first memory bank array 310a.

[0180] In response to the cleanup mode signal SMS2, the weak codeword address generator 520b in the memory bank cleanup control circuit 500b corresponding to the memory bank array 310b is enabled, and the weak codeword address generator 520b generates a weak codeword address WCADDRa, and the memory bank ECC engine 400b performs DAS operation on the weak codeword WCW in the memory bank array 310b.

[0181] In response to the cleanup mode signal SMS16, the weak codeword address generator 520s in the memory bank cleanup control circuit 500s corresponding to the memory bank array 310s is enabled, and the weak codeword address generator 520s generates weak codeword addresses WCADDRs, and the memory bank ECC engine 400s performs DAS operation on the weak codewords WCW in the memory bank array 310s.

[0182] Each of the multiple memory bank ECC engines 400a to 400s and each of the multiple memory bank cleanup control circuits 500a to 500s independently performs normal cleanup operations and DAS operations on a corresponding one of the multiple memory bank arrays 310a to 310s. Each of the multiple memory bank ECC engines 400a to 400s and each of the multiple memory bank cleanup control circuits 500a to 500s can selectively perform DAS operations based on whether weak codewords are detected during normal cleanup operations.

[0183] Figure 24 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0184] Referring to FIG22, the semiconductor memory device 600 may include a first set of dies 610 and / or a second set of dies 620 that provide soft error analysis and correction functions in a stacked chip structure.

[0185] The first set of dies 610 may include at least one buffer die 611. The second set of dies 620 may include a plurality of memory dies 620-1 to 620-p stacked on the at least one buffer die 611 and transmitting data through a plurality of through-silicon vias (TSVs).

[0186] Each of the memory dies 620-1 to 620-p may include a cell core ECC engine (e.g., a first-type ECC engine) 622 that generates transmission parity bits (e.g., transmission parity data) based on the transmission data to be sent to the first set of dies 610, a refresh control circuit 624, and a cleanup control circuit 623. The cell core ECC engine 622 may employ... Figure 15 The ECC engine 400. The refresh control circuit 624 can be used. Figure 4 The refresh control circuit 385. The cleaning control circuit 623 can be adopted. Figure 10 The cleaning control circuit 500.

[0187] The cell core ECC engine 622 and the cleanup control circuit 623 can perform a normal cleanup operation on the codeword in a first cycle to detect error bits during a refresh operation on the memory cell row in the memory die, can store the address of weak codewords (in which error bits are detected) and can perform a DAS operation in a second cycle to reduce or prevent the accumulation of error bits.

[0188] The buffer die 611 may include a through-hole ECC engine 612, which uses transmission parity bits to correct transmission errors when a transmission error is detected from transmitted data received through the TSV line, and generates error-corrected data.

[0189] The semiconductor memory device 600 can be a stacked chip-type memory device or a stacked memory device that transmits data and control signals via TSV lines. TSV lines can also be called "through electrodes".

[0190] The core ECC engine 622 can perform error correction on the data output from the memory die 620-p before the data is sent.

[0191] Transmission errors occurring at the data transmission point may be due to noise occurring at the TSV line. Data failures caused by noise at the TSV line can be distinguished from data failures caused by erroneous operation of the memory die, so noise at the TSV line can be considered a soft data failure (or soft error). Soft data failures may be generated due to transmission failures on the transmission path and can be detected and remedied by ECC operation.

[0192] A data TSV line group 632 formed at a memory die 620-p may include TSV lines L1 to Lp, and a parity TSV line group 634 may include TSV lines L10 to Lq. The TSV lines L1 to Lp of the data TSV line group 632 and the parity TSV lines L10 to Lq of the parity TSV line group 634 may be connected to a microbump MCB correspondingly formed between memory dies 620-1 and 620-p.

[0193] Each of the memory dies 620-1 to 620-p may include a DRAM cell, each DRAM cell including at least one access transistor and a storage capacitor.

[0194] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host via the data bus B10. The buffer die 611 may be connected to the memory controller via the data bus B10.

[0195] The unit core ECC engine 622 can output parity bits and data via parity TSV line group 634 and data TSV line group 632, respectively. The output data can be error-corrected data by the unit core ECC engine 622.

[0196] The through-hole ECC engine 612 can determine whether a transmission error has occurred in the transmitted data received via the data TSV line group 632 based on the transmission parity bits received via the parity TSV line group 634. When a transmission error is detected, the through-hole ECC engine 612 can use the transmission parity bits to correct the transmission error in the transmitted data. When the transmission error is uncorrectable, the through-hole ECC engine 612 can output information indicating the occurrence of an uncorrectable data error.

[0197] When an error is detected when reading data from a high-bandwidth memory (HBM) or stacked memory structure, the error is an error that occurs due to noise while the data is being transmitted via TSV.

[0198] According to the example embodiment, such as Figure 23 As shown, the cell core ECC engine 622 can be included in the memory die, and the through-hole ECC engine 612 can be included in the buffer die 611. Therefore, soft data faults can be detected and corrected. Soft data faults may include transmission errors caused by noise when data is transmitted via the TSV line.

[0199] Figure 25 This is a flowchart illustrating a method of a semiconductor memory device according to an example embodiment.

[0200] Reference Figures 2 to 25 In a method of operating a semiconductor memory device 200 including a memory cell array 300, a cleanup control circuit 500 generates a cleanup address for performing a normal cleanup operation on the memory cell rows based on a refresh row address for refreshing the memory cell rows, wherein the memory cell array 300 may include a plurality of memory cell rows, and each of the plurality of memory cell rows may include a plurality of volatile memory cells (operation S110).

[0201] The ECC engine 400 stores the addresses of weak codewords in the address storage table of the cleanup control circuit 500, while the ECC engine performs a normal cleanup operation on the memory cell rows in the first cycle based on the cleanup addresses (operation S120). During the normal cleanup operation or normal read operation on at least one of the memory cell rows, error bits are detected in each of the weak codewords.

[0202] The ECC engine 400 performs DAS operations (operation S130) on weak codewords in a second cycle (less than the first cycle) based on dynamically cleaning up weak codewords within the refresh operation.

[0203] Figure 26 This is a diagram illustrating a semiconductor package including stacked memory devices according to an example embodiment.

[0204] Reference Figure 26 The semiconductor package 900 may include one or more stacked memory devices 910 and / or graphics processing units (GPUs) 920. The GPU 920 may include a memory controller 925.

[0205] The stacked memory device 910 and GPU 920 can be mounted on an inserter 930, and the inserter on which the stacked memory device 910 and GPU 920 are mounted can be mounted on a package substrate 940. The package substrate 940 can be mounted on solder balls 950. The memory controller 925 can be... Figure 1 The memory controller 100 in the middle.

[0206] Each of the stacked memory devices 910 can be implemented in various forms and can be a high-bandwidth memory (HBM) memory device in which multiple layers are stacked. Therefore, each of the stacked memory devices 910 may include a buffer die and multiple memory dies. Each memory die may include a memory cell array, an ECC engine, and / or cleanup control circuitry.

[0207] Multiple stacked memory devices 910 may be mounted on the inserter 930, and the GPU 920 may communicate with the multiple stacked memory devices 910. For example, each of the stacked memory devices 910 and the GPU 920 may include a physical region, and communication between the stacked memory devices 910 and the GPU 920 may be performed via the physical region.

[0208] As mentioned above, according to the example embodiment, the semiconductor memory device may include an ECC engine and a cleanup control circuit. Whenever the refresh control circuit performs N refresh operations on a row of memory cells, the ECC engine and the cleanup control circuit perform a normal cleanup operation on the codewords in the row of memory cells specified by the cleanup address provided by the cleanup control circuit within a first cycle.

[0209] During normal cleanup operations, the ECC engine corrects erroneous bits in the codewords and writes the corrected codewords back to the corresponding memory locations. The ECC engine also stores the addresses of weak codewords, detecting erroneous bits in each of these weak codewords. The ECC engine and cleanup control circuitry perform DAS operations on the weak codewords in a second cycle, less than the first cycle. Therefore, semiconductor memory devices can enhance reliability and / or performance by reducing or preventing the accumulation of erroneous bits.

[0210] The one or more elements disclosed above may include or be implemented in one or more processing circuits, such as hardware including logic circuits, hardware / software combinations (such as processors executing software), or combinations thereof. For example, processing circuits may more specifically include, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0211] Several aspects of the present invention can be applied to systems using semiconductor memory devices employing ECC engines. For example, several aspects of the present invention can be applied to systems such as smartphones, navigation systems, laptop computers, desktop computers, and game consoles that use semiconductor memory devices as working memory.

[0212] The above description is of exemplary embodiments and should not be construed as limiting the exemplary embodiments. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. < / g> < / g> < / g> < / g> < / g>

Claims

1. A semiconductor memory device, comprising: A memory cell array comprising a plurality of memory cell rows, each of the plurality of memory cell rows comprising a volatile memory cell; Error correction code engine; A cleanup control circuit is configured to generate a cleanup address for performing a normal cleanup operation on the plurality of memory cell rows in a first cycle, based on a refresh row address used to refresh the plurality of memory cell rows. as well as A control logic circuit is configured to control the error correction code engine and the cleanup control circuit to dynamically allocate cleanup operations to weak codewords within a refresh operation, such that the dynamic allocation cleanup operation is performed in a second period less than the first period. During a normal cleanup or normal read operation on at least one of the plurality of memory cell rows, an error bit is detected in each of the weak codewords. The control logic circuit is configured to store the address of the weak codeword as a weak codeword address in the address storage table of the cleanup control circuit, and is configured to provide a flag signal to the cleanup control circuit to trigger the dynamic allocation cleanup operation.

2. The semiconductor memory device according to claim 1, wherein, The cleaning control circuit includes: A counter is configured to count the refresh row addresses to generate an internal cleanup signal, wherein the counter activates the internal cleanup signal whenever the counter counts M refresh row addresses, where M is an integer greater than 1. A cleanup address generator, configured to generate, in a first cleanup mode, a normal cleanup address associated with the normal cleanup operation on a first memory cell row selected from the memory cell rows, in response to the internal cleanup signal and a cleanup mode signal; and A weak codeword address generator is configured to generate a weak codeword address associated with a weak cleanup operation in a second cleanup mode in response to the internal cleanup signal and the cleanup mode signal, the weak cleanup operation being associated with a weak codeword in the first memory cell row.

3. The semiconductor memory device according to claim 2, in, The normal cleanup address includes a cleanup row address specifying a memory cell row and a cleanup column address specifying one of the codewords included in the memory cell row, and The cleanup address generator includes: A page segment counter, configured to increment the cleanup column address by 1 during the activation of the internal cleanup signal; and A row counter is configured to increment the cleanup column address by 1 whenever the cleanup column address reaches its maximum value.

4. The semiconductor memory device according to claim 2, wherein, The weak codeword address generator includes: An address storage table, configured to store the address information of the weak codewords; and A table pointer is configured to generate a pointer signal in a second cycle, the pointer signal responding to a flag signal providing location information of the address storage table.

5. The semiconductor memory device according to claim 4, wherein, The address storage table is configured to output the row address and column address of the weak codeword as the weak codeword row address and weak codeword column address whenever the pointer signal is applied to the address storage table, and the weak codeword row address and weak codeword column address are stored in the corresponding positions of the address storage table.

6. The semiconductor memory device according to claim 1, wherein, The control logic circuit is configured to control the error correction code engine such that, during the normal cleanup operation, the error correction code engine reads data corresponding to a first codeword from at least one subpage in the first memory cell row from the memory cell row, corrects at least one erroneous bit in the first codeword, and writes the corrected first codeword back to the memory location corresponding to the at least one subpage. The control logic circuit is configured to control the error correction code engine such that, during the dynamic allocation cleanup operation, the error correction code engine reads the weak codeword from the weak subpage, corrects at least one erroneous bit in the weak codeword, and writes the corrected weak codeword back to the memory location corresponding to the weak subpage.

7. The semiconductor memory device according to claim 6, further comprising: A refresh control circuit is configured to generate the refresh row address in response to a first command received externally. The cleanup control circuit is configured to generate the cleanup address whenever the cleanup control circuit counts N refresh row addresses, where N is an integer greater than 3. The cleanup control circuit is configured to sequentially generate cleanup addresses for M codewords included in the first memory cell row while performing a refresh operation on the first memory cell row of the memory cell row, where M is an integer greater than 1 and less than N.

8. The semiconductor memory device according to claim 7, wherein, The first command is a refresh command.

9. The semiconductor memory device according to claim 6, wherein: The error correction code engine is configured to provide an error generation signal to the control logic circuit when the error correction code engine detects at least one error bit in the first codeword; The control logic circuit is configured to provide the address of the first codeword as an error address to the cleanup control circuit; as well as The cleanup control circuit is configured to store the erroneous address as a weak codeword address in an address storage table therein.

10. The semiconductor memory device according to claim 9, wherein, The control logic circuit is configured to provide the address of the memory cell row as the error address to the cleanup control circuit when the error correction code engine generates an error generation signal greater than a reference value for the memory cell row.

11. The semiconductor memory device of claim 1, further comprising: A victim address detector is configured to count the number of accesses to a first memory region in the memory cell array, and to generate at least one victim address specifying at least one adjacent memory region adjacent to the first memory region when the number of accesses counted during a reference interval reaches a threshold.

12. The semiconductor memory device of claim 11, wherein: The victim address generator is configured to provide the at least one victim address to the cleanup control circuit; and The cleanup control circuit is configured to store the at least one victim address as a weak codeword address in an address storage table therein.

13. The semiconductor memory device of claim 11, wherein: The victim address generator is configured to provide the at least one victim address to a row decoder coupled to the memory cell array; and The row decoder is configured to refresh the at least one adjacent memory region at least twice, in response to the refresh row address and the at least one victim address, while the row decoder refreshes the memory cell row once.

14. The semiconductor memory device according to claim 1, wherein: The memory cell array includes multiple memory bank arrays; The error correction code engine includes multiple memory bank error correction code engines corresponding to the multiple memory bank arrays; The cleaning control circuit includes multiple memory cell cleaning control circuits corresponding to the multiple memory cell arrays; and Each of the plurality of memory bank error correction code engines and each of the plurality of memory bank cleanup control circuits is configured to independently perform the normal cleanup operation and the dynamic allocation cleanup operation on a corresponding one of the plurality of memory bank arrays.

15. The semiconductor memory device according to claim 14, in, Each of the plurality of memory bank error correction code engines and each of the plurality of memory bank cleanup control circuits is configured to selectively perform a dynamic allocation cleanup operation based on whether the weak codeword is detected during the normal cleanup operation.

16. The semiconductor memory device of claim 1, comprising: At least one buffer die; as well as Multiple memory dies, stacked on the at least one buffer die, transmit data through multiple through-silicon via (TSV) lines. Each of the plurality of memory dies includes the memory cell array and the cleanup control circuit.

17. The semiconductor memory device of claim 16, wherein, The semiconductor memory device is a high-bandwidth memory.

18. A method of operating a semiconductor memory device including an array of memory cells, the array of memory cells including a plurality of rows of memory cells, each of the plurality of rows of memory cells including a plurality of volatile memory cells, the method comprising: The cleanup control circuit generates a cleanup address for performing normal cleanup operations on the plurality of memory cell rows based on the refresh row address used to refresh the plurality of memory cell rows; While the error correction code engine performs a normal cleanup operation on the plurality of memory cell rows based on the cleanup address in the first cycle, the error correction code engine stores the address of the weak codeword in the address storage table of the cleanup control circuit. During a normal cleanup operation or normal read operation on at least one of the plurality of memory cell rows, an error bit is detected in each of the weak codewords. and The error correction engine dynamically performs the cleanup operation on the weak codewords during the refresh operation based on the cleanup operation, and performs the dynamic allocation and cleanup operation on the weak codewords in a second cycle that is shorter than the first cycle. The method further includes providing a flag signal to the cleaning control circuit to trigger the dynamic allocation cleaning operation.

19. A semiconductor memory device, comprising: A memory cell array comprising a plurality of memory cell rows, each of the plurality of memory cell rows comprising a volatile memory cell; Error correction code engine; A refresh control circuit is configured to generate refresh row addresses for refreshing the plurality of memory cell rows; A cleanup control circuit is configured to generate a cleanup address based on the refresh row address for performing a normal cleanup operation on the plurality of memory cell rows in a first cycle; and A control logic circuit is configured to control the error correction code engine and the cleanup control circuit to dynamically allocate cleanup operations to weak codewords within a refresh operation, such that the dynamic allocation cleanup operation is performed in a second period less than the first period. During a normal cleanup or normal read operation on at least one of the plurality of memory cell rows, an error bit is detected in each of the weak codewords, and The control logic circuit is configured to store the address of the weak codeword as a weak codeword address in the address storage table of the cleanup control circuit, and is configured to provide a flag signal to the cleanup control circuit to trigger the dynamic allocation cleanup operation.

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