Memory device, memory controller, and storage system including the same

Abstract

Memory devices, memory controllers, and memory systems including the same are provided. The memory system includes a first memory device including a plurality of first memory blocks each including a plurality of first memory cells stacked in a direction perpendicular to a substrate, and a memory controller configured to control a memory operation of the first memory device. The memory controller is configured to select and run a respective control scheme among different control schemes for each of the first memory blocks based on a number of first not-opened (N / O) strings included in each of the first memory blocks.

Description

[0001] Cross-reference to related applications

[0002] This application relates to and claims priority to Korean Patent Application No. 10-2020-0101395, filed on August 12, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to storage devices, and more specifically, to storage devices comprising at least one not-open string, controllers for controlling the storage device, and storage systems including the same. Background Technology

[0004] With the latest developments in data technology, there is a need for highly integrated 3D storage devices to store large amounts of data with high reliability. However, in 3D storage devices, "off-strings" (or "closed strings") are storage defects where channels are not formed in the storage string. N / O strings (sometimes referred to as storage hole faults) can be formed during manufacturing due to process errors. It has been found that even with error correction coding (ECC) applied to the data, it is difficult to write data into storage cells of off-strings. Furthermore, storage cells of off-strings can adversely affect storage cells of adjacent "open" (normal) strings. Therefore, a technique is needed to address the problems caused by N / O strings. Summary of the Invention

[0005] Embodiments of the present invention provide a storage device, a memory controller, and a storage system including the same, to minimize the adverse effects caused by unopened strings and optimize storage operations by applying different control schemes to storage blocks having unopened strings and storage blocks not having any unopened strings.

[0006] According to one aspect of the present invention, a storage system is provided, comprising: a first storage device including a plurality of first storage blocks, each first storage block including a plurality of first storage cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control storage operations of the first storage device. The memory controller is further configured to select and run a corresponding control scheme among different control schemes for each first storage block based on the number of first non-open (N / O) strings included in each first storage block.

[0007] According to another aspect of the present invention, a storage device is provided, comprising: a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells stacked in a direction perpendicular to a substrate; and control logic configured to: detect unopened (N / O) strings in a first target memory block among the memory blocks in response to a first type of command received from an external source; convert a plurality of bits of target data to be written to the plurality of target memory cells included in the detected N / O strings into bits having predetermined values ​​to limit the number of times a write voltage is applied; and perform a general write operation on a second target memory block among the memory blocks in response to a second type of command received from the external source.

[0008] According to another aspect of the present invention, a memory controller is provided, comprising: an internal memory configured to store N / O string information relating to the number of unopened (N / O) strings included in each of a plurality of memory blocks included in an external storage device; and a processor configured to: operate a first target memory block including at least one N / O string among the plurality of memory blocks according to the N / O string information and a first control scheme; and operate a second target memory block not including any N / O strings according to a second control scheme different from the first control scheme.

[0009] In another aspect, a storage device includes: a storage cell region including a first metal pad; a peripheral circuit region including a second metal pad and configured to be perpendicularly connected to the storage cell region via the first metal pad and the second metal pad; a storage cell array located in the storage cell region and including a plurality of storage blocks, each storage block including a plurality of storage cells stacked in a direction perpendicular to a substrate; and control logic located in the peripheral circuit region and configured to: detect unopened (N / O) strings in a first target storage block among the storage blocks in response to a first type of command received by the storage device; convert a plurality of bits of target data of the plurality of target storage cells included in the detected N / O strings to have predetermined values ​​to limit the number of times a write voltage is applied; and perform a general write operation on a second target storage block among the storage blocks in response to a second type of command received by the storage device.

[0010] In another aspect, a storage device includes: a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells stacked in a direction perpendicular to a substrate; and control logic configured to: detect unopened (N / O) strings in a first target memory block among the memory blocks in response to a first type of command received by the storage device; avoid writing target data pre-specified to be written to the plurality of target memory cells included in the detected N / O strings, instead writing data bits, each having a predetermined value, to the plurality of target memory cells to limit the number of times a write voltage is applied to the plurality of target memory cells; and perform a general write operation on a second target memory block among the memory blocks in response to a second type of command received by the storage device. Attached Figure Description

[0011] The embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating an example embodiment of a storage system according to a concept of the present invention;

[0013] Figure 2 This is a diagram illustrating the operation of a storage device according to an exemplary embodiment of the concept of the present invention;

[0014] Figure 3A and Figure 3B It is used for detailed description Figure 2 A flowchart of an embodiment of operation S130;

[0015] Figures 4A to 4C It is used to describe in detail what it is for Figure 3A Diagrams illustrating the operations of the first and second type of commands;

[0016] Figure 5A It is shown Figure 1 A block diagram of a storage cell array. Figure 5B yes Figure 1 A perspective cross-sectional view of a first example of a memory cell array, and Figure 5C yes Figure 1 A perspective cross-sectional view of a second example of a memory cell array;

[0017] Figure 6 This is a diagram illustrating an example embodiment of a chip-to-chip (C2C) structure applied to a memory device according to a concept of the present invention;

[0018] Figure 7 It is used to describe in detail the response to Figure 4A A flowchart of the operation of the storage device for the first type of command;

[0019] Figures 8A to 8C It is used to describe the response to Figure 4A A diagram illustrating the method of operating storage devices using the first type of command;

[0020] Figure 9 It is used for detailed description Figure 7 Flowchart of operation S210;

[0021] Figures 10A to 10C It is used to describe the response to Figure 4A A diagram illustrating the method of operating storage devices using first-type and second-type erase commands;

[0022] Figure 11A and Figure 11B It is used for detailed description Figure 3B Diagrams of the first and second type of memory blocks;

[0023] Figures 12A to 12C This is a diagram illustrating an embodiment of selecting and running a corresponding control scheme among different control schemes for each sub-block included in a storage block;

[0024] Figure 13 This is a flowchart of a method for operating a memory controller according to an exemplary embodiment of the present invention;

[0025] Figure 14 This is a block diagram illustrating an example embodiment of a storage system according to a concept of the present invention;

[0026] Figure 15 It is shown Figure 14 A table of examples of N / O string information;

[0027] Figure 16 This is a flowchart of a method for operating a memory controller according to an exemplary embodiment of the present invention;

[0028] Figure 17A and Figure 17B It is used for detailed description Figure 16 Diagrams of the first type of storage device and the second type of storage device; and

[0029] Figure 18 This is a block diagram illustrating a test system for generating N / O string information according to an example embodiment of the concept of the present invention. Detailed Implementation

[0030] In the following description, embodiments of the inventive concept may be referred to with reference to NAND flash memory (specifically, vertical NAND flash memory). However, the inventive concept can also be applied to various non-volatile memory devices such as electrically erasable programmable read-only memory (EEPROM), NOR flash memory devices, phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM). In this document, the memory device may be referred to as a memory chip.

[0031] Figure 1 This is a block diagram illustrating an example embodiment of a storage system 10 according to a concept of the present invention, and Figure 2 This is a diagram illustrating the operation of a storage system 10 according to an exemplary embodiment of the present invention.

[0032] Reference Figure 1 The storage system 10 may include a memory controller 100 and a storage device 200. The memory controller 100 may include a processor 110 and internal memory 120. The processor 110 may control the overall operation of the storage system 10, including the memory controller 100, and may control storage operations such as write operations, read operations, or erase operations of the storage device 200. (Hereinafter, a write operation may sometimes be referred to as a “programming” operation.) The internal memory 120 may store unopened string (hereinafter referred to as N / O string) information 122, which forms the basis for performing operations according to an exemplary embodiment of the present invention. Reference will be made below. Figure 5C Provide a detailed description of the N / O string.

[0033] The internal memory 120 can be implemented using volatile memory such as dynamic random access memory (DRAM) and static random access memory (SRAM), and is not limited thereto; it can also be implemented using non-volatile memory such as PRAM and MRAM. In some embodiments, the internal memory 120 can store firmware driven by the processor 110, and can temporarily store data to be written to the storage device 200 or data to be provided to the host. Moreover, the internal memory 120 can store initial commands, data, and various variables input from the host, or various data and information output from the storage device 200.

[0034] Storage device 200 may include a memory cell array 210 and control logic 220. The memory cell array 210 may include a plurality of memory blocks 210_1, each memory block comprising a plurality of memory cells stacked in a direction perpendicular to the substrate to form a 3D structure (commonly referred to as a vertical structure). Examples of 3D memory structures and their operation methods are found in U.S. patents Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. patent applications Nos. 2011 / 0233648, 2012 / 0051138, and 2011 / 0204420. Any of these types of memory cell array structures / operations (which do not conflict with the structures / operations described herein) may be applied to memory cell array 110.

[0035] According to an exemplary embodiment of the present invention, processor 110 can execute a control method selected from a set of different control methods for each memory block 210_1 based on N / O string information 122, some of which may be heterogeneous. For example, in some embodiments, an overall heterogeneous control method is applied to the memory block when different control schemes are applied to different sub-blocks of the memory block. (Hereinafter, the operations performed by processor 110 are sometimes described as operations of memory controller 100.) In an exemplary embodiment, N / O string information 122 may include information about the number of N / O strings included in each memory block 210_1. For example, N / O string information 122 may include information about the number of N / O strings corresponding to each memory block 210_1. Processor 110 can check the number of N / O strings included in each memory block 210_1 by referring to N / O string information 122. Processor 110 can operate on storage block 210_1 corresponding to the number of N / O strings equal to or greater than a predetermined threshold, according to a first control scheme that takes into account the existence of N / O strings. Furthermore, processor 110 can operate on storage block 210_1 corresponding to the number of N / O strings less than the predetermined threshold, according to a second control scheme. In some embodiments, the second control scheme differs from the first control scheme, and the second control scheme may correspond to a general storage operation scheme.

[0036] The predetermined threshold is a pre-set value and can be a fixed value or can vary depending on the operating environment of the storage system 10. In some embodiments, since the threshold can be set to "1", the processor 110 can operate a storage block including at least one N / O string according to a first control scheme, and can operate a storage block without any N / O string according to a second control scheme.

[0037] The control scheme of the exemplary embodiment of the present invention may include a write / programming operation control scheme, an erase operation control scheme, a control scheme for operating the storage block as different storage cell types, and a control scheme for specifying that the storage block is dedicated to storing "hot data (H)" or "cold data (C)". In the following, the various represented storage cell types are assumed to have their own different storage capacities; for example, single-level cell (SLC), multi-level cell (MLC), third-level cell (TLC), and fourth-level cell (QLC) are storage cell types with progressively increasing storage capabilities. For example, each storage block 210_1 can operate normally at its inherent level when formed as a defect-free block with no N / O strings. For example, if it is determined that a QLC type storage block with only QLC cells is defect-free, the selected control scheme for the QLC storage block may be a QLC type scheme. On the other hand, if it is determined that the number of N / O strings of a QLC storage block is greater than a predetermined threshold, an SLC, MLC, or TLC type control scheme can be selected and executed for that storage block. Reference will be made below. Figure 3A and Figure 3B Provide a detailed description of the control scheme.

[0038] Because the integration of storage cells has been significantly improved, a storage block can include a large number of storage cells. A storage block can be divided into multiple sub-blocks for fast and flexible storage operations, thus storage operations can be performed on a sub-block basis. According to an exemplary embodiment of the present invention, the processor 110 can select and run a corresponding control method among different control methods for each of the multiple sub-blocks defined in each storage block 210_1, based on N / O string information 122. Specifically, each storage block 210_1 can be divided into sub-blocks with N / O strings greater than or equal to a threshold and sub-blocks with N / O strings less than the threshold. Here, the N / O string information 122 can include information about the number of N / O strings in each sub-block included in the storage block 210_1. Reference will be made below. Figures 12A to 12C Provide a detailed description of the sub-block.

[0039] According to an exemplary embodiment of the present invention, the memory controller 100 can execute a corresponding control scheme selected based on the presence of N / O strings for each memory block 210_1 of the memory device 200, thereby minimizing the negative impact caused by N / O strings and optimizing the operation of the memory device 200 including N / O strings in terms of data reliability.

[0040] Reference Figure 2 In operation S100, the memory controller 100 may request N / O string information 122 from the memory device 200. In an embodiment, the N / O string information 122 may be pre-generated through a test operation during the manufacturing stage of the memory device 200, and the N / O string information 122 may be stored in some memory cells of the memory cell array 210 of the memory device 200, or may be stored in latches included in the peripheral circuitry of the memory device 200. In operation S110, in response to the request in operation S100, the memory device 200 may read the N / O string information 122 and provide the read N / O string information 122 to the memory controller 100. In operation S120, the memory controller 100 may store the N / O string information 122 in the internal memory 120. As described above, the internal memory 120 may be implemented using volatile memory or non-volatile memory. When the internal memory 120 is implemented using volatile memory, the internal memory 120 can receive and store N / O string information 122 from the memory device 200 each time the memory controller 100 is powered on. In operation S130, the memory controller 100 can control the storage operation of the memory device 200 based on the N / O string information 122.

[0041] Figure 3A and Figure 3B It is used for detailed description Figure 2 A flowchart of an embodiment of operation S130 is provided below. For ease of explanation, reference will be made to... Figure 1 Provide a description.

[0042] Reference Figure 3A In operation S120 ( Figure 2Following this, in operation S131a, the memory controller 100 can refer to the N / O string information 122 and check the state of the target memory block to be controlled in memory block 210_1. In other words, the memory controller 100 can check the number of N / O strings included in the target memory block and select a control scheme for operating the target memory block. In operation S132a, the memory controller 100 can check whether the number of N / O strings included in the target memory block is equal to or greater than a first threshold. In an example embodiment, the first threshold can be one of a variety of preset values. In some embodiments, the first threshold can be set to "1", so that memory blocks including N / O strings and memory blocks without N / O strings can be controlled according to different control schemes.

[0043] When operation S132a is "Yes", in operation S133a, the memory controller 100 can generate a first type command for controlling the storage operation of the target memory block. The first type command may refer to a command for controlling the storage operation of the target memory block with a number of N / O strings equal to or greater than a first threshold to minimize the negative impact of N / O strings. When operation S132a is "No", in operation S134a, the memory controller 100 can generate a second type command for controlling the storage operation of the target memory block. The second type command may refer to a command for controlling a general storage operation of the target memory block with a number of N / O strings less than the first threshold. In operation S135a, the memory controller 100 can provide either the first type command or the second type command to the storage device 200 to control the storage operation of the target memory block. In the example embodiment, the first type command and the second type command may have different voltage levels and / or pulse sequences. In the example embodiment, the first type command and the second type command may have different codes.

[0044] Reference Figure 3B In operation S120 ( Figure 2 Following this, in operation S131b, the memory controller 100 can refer to the N / O string information 122 and check the status of each memory block 210_1. In other words, the memory controller 100 can check the number of N / O strings included in each memory block 210_1 and select a control scheme for operating each memory block 210_1. In operation S132b, the memory controller 100 can check whether the number of N / O strings included in each memory block 210_1 is equal to or greater than a second threshold. In the example embodiment, the second threshold can be one of a variety of preset values. The second threshold can be set to be equal to or different from... Figure 3AThe first threshold. In some embodiments, the second threshold can be set to "1", so that storage blocks including N / O strings and storage blocks not including N / O strings can be controlled according to different control schemes.

[0045] When operation S132b is "Yes", in operation S133b, the memory controller 100 can designate a memory block 210_1 with the number of N / O strings equal to or greater than a second threshold as a first type of memory block ("first type memory block"). A first type memory block may refer to a memory block operated according to a control scheme that takes into account the state of the N / O strings, which is not preferred in terms of data reliability. When operation S132b is "No", in operation S134b, the memory controller 100 can designate a memory block 210_1 with the number of N / O strings less than the second threshold as a second type of memory block ("second type memory block"). A second type memory block may refer to a memory block operated according to a control scheme that considers that a second type memory block can provide higher data reliability than a first type memory block. In operation S135b, the memory controller 100 can store the designation information, including the result of designating memory block 210_1 in operations S133b and S134b, in the internal memory 120. In some embodiments, specified information may be backed up in a region of the storage cell array 210 of the storage device 200, and in this case, the memory controller 100 may request the specified information from the storage device 200 when the memory controller is powered on.

[0046] Figures 4A to 4C It is used to describe in detail what it is for Figure 3A The diagram illustrates the operations of the first type of command and the second type of command. Figures 4A to 4C Example write / programming operations based on example embodiments of various control schemes are illustrated in detail.

[0047] Reference Figure 4A The storage device 200 may include a memory cell array 210, control logic 220, a voltage generator 230, an address decoder 240, a page buffer circuit 250, and data input / output (I / O) circuitry 260. Furthermore, the control logic 220 may include an N / O string control module 222 for performing programming operations according to an exemplary embodiment of the present invention. Although in Figure 4A Although not shown, storage device 200 may also include various other functional blocks related to storage operations. The N / O string control module 222 may be implemented as hardware logic or as software logic. Furthermore, the N / O string control module 222 may be included within the memory controller.

[0048] The memory cell array 110 may include multiple strings (or cell strings) arranged on a substrate along row and column directions. Each string may include multiple memory cells stacked in a direction perpendicular to the substrate. In other words, memory cells may be stacked in a direction perpendicular to the substrate to form a 3D structure. Each memory cell may be used as a cell type such as a single-order cell, a multi-order cell, a third-order cell, or a fourth-order cell. The inventive concept can be flexibly applied according to various cell types of memory cells. In an example embodiment, the memory cell array 210 may include first to third memory blocks 210_11 to 210_13.

[0049] Reference Figure 4B As shown in Table TB1, the first to third storage blocks 210_11 to 210_13 may each include “A”, “B”, and “C” N / O strings, respectively. Based on the N / O string information included in Table TB1, the memory controller can select and run different types of control schemes for the first to third storage blocks 210_11 to 210_13.

[0050] The memory cells of the memory cell array 210 can be connected to the word line WL, the serial select line SSL, the ground select line GSL, and the bit line BL. The memory cell array 210 can be connected to the address decoder 240 via the word line WL, the serial select line SSL, and the ground select line GSL, and can be connected to the page buffer circuit 250 via the bit line BL.

[0051] Page buffer circuit 250 can temporarily store data to be written to and read from memory cell array 210. Page buffer circuit 250 may include multiple latch units (or page buffers). For example, each latch unit may include multiple latches corresponding to multiple bit lines BL, and can store data page by page. In some embodiments, page buffer circuit 250 may include sense latch units, and sense latch units may include multiple sense latches corresponding to bit lines BL. Moreover, each sense latch may be connected to a sense node through which data is sensed via the corresponding bit line.

[0052] Control logic 220 controls the overall operation of storage device 200. For example, based on the command CMD, address ADDR, and control signal CTRL received from the memory controller (not shown), control logic 220 can output various internal control signals for writing data to memory cell array 210, reading data from memory cell array 210, or erasing data stored in memory cell array 210.

[0053] Various internal control signals output from control logic 220 can be provided to page buffer circuit 250, voltage generator 230, and address decoder 240. Specifically, control logic 220 can provide the voltage control signal CTRL_vol to voltage generator 230. Voltage generator 230 may include one or more pumps (not shown), and voltage generator 240 can generate voltages VWL with various levels based on the voltage control signal CTRL_vol according to the pumping operation. Simultaneously, control logic 220 can provide row address X_ADD to address decoder 240 and column address Y_ADD to page buffer circuit 250. The operation of N / O string control module 222 will be described below. Control logic 220 can generate internal control signals corresponding to the operation of N / O string control module 222 and output these internal control signals to function blocks in storage device 200.

[0054] Although the following description will focus on performing storage operations through storage blocks, this is merely an example, and the inventive concept is not limited thereto. Storage operations to which the inventive concept is applied can be performed through storage sub-blocks and various other memory groups.

[0055] According to an exemplary embodiment of the present invention, the N / O string control module 222 can receive a first type command CMD1 or a second type command CMD2 from the memory controller for write operations to target memory blocks among the first to third memory blocks 210_11 to 210_13. (Refer to the above...) Figure 3A As described, it is assumed that a first type of command CMD1 is generated to control write operations on target storage blocks with an N / O string count equal to or greater than a first threshold, and a second type of command CMD2 is generated to control write operations on target storage blocks with an N / O string count less than the first threshold.

[0056] N / O string control module 222 can detect N / O strings from among multiple strings included in the target memory block of memory cell array 110 in response to a first type command CMD1 received from the memory controller. For example, N / O string control module 222 can detect N / O strings in the target memory block or target memory sub-block of memory cell array 210 corresponding to the address ADDR corresponding to the first type command CMD1. N / O string control module 222 can provide internal control signals CTRL_vol, X_ADD, and Y_ADD to voltage generator 230, address decoder 240, and page buffer circuit 250, respectively, to detect N / O strings.

[0057] For example, the N / O string control module 222 can apply a check voltage greater than a reference voltage to multiple word lines WL of the target memory block connected to the memory cell array 210 using a voltage generator 230. The level of the check voltage can vary depending on the cell type of the target memory block (depending on whether an erase operation is primarily performed during a write operation), or it can be constant regardless of the cell type of the target memory block. Depending on whether an erase operation on the target memory block or a target memory sub-block is primarily performed during a write operation, the reference voltage can be a voltage used to verify the highest write state of the memory cell, or a voltage used to verify the erase state of the memory cell.

[0058] When a check voltage is applied to the word line WL connected to the target memory block, the page buffer circuit 250 can provide a result signal RS output from the bit line BL to the N / O string control module 222. The N / O string control module 222 can detect N / O strings from multiple strings in the target memory block based on the result signal RS received from the page buffer circuit 250. For example, the N / O string control module 222 can identify multiple target memory cells in the target memory block that are turned off due to the check voltage based on the result signal RS, thereby detecting an N / O string including multiple target memory cells.

[0059] The N / O string control module 222 can convert multiple bits of target data previously intended to be written to multiple target memory cells included in the detected N / O string into predetermined values. By writing such predetermined values ​​to the target memory cells, the number of write voltages applied to the multiple target memory cells can be limited. (Note that the original target data can be copied and then stored in different memory locations.) For example, the N / O string control module 222 can provide the data conversion signal DCS and the column address Y_ADD corresponding to the target data to the page buffer circuit 250, thereby converting the target data latched to the page buffer circuit 250 into predetermined values. Simultaneously, before the N / O string control module 222 converts the value of the target data, the data DATA to be written to the memory cell array 210 can be pre-latched into the page buffer circuit 250 via the data input / output circuit 260.

[0060] As the number of write voltages applied to multiple target memory cells included in an N / O string increases through word lines, the N / O string may be subjected to more severe stress. Therefore, the N / O string may negatively affect adjacent strings or adjacent memory cells. Thus, a predetermined value can be a value preset to limit the number of write voltages applied to the target memory cells. For example, the predetermined value could be a value used to form a threshold voltage distribution corresponding to the erase state.

[0061] Note that storage device 200 can avoid writing target data to target memory cells included in the detected N / O string, instead of converting the bits of the target data as described above, by writing data bits, each with a predetermined value, to multiple target memory cells. This also limits the number of times write voltages are applied to multiple target memory cells.

[0062] The N / O string control module 222 can control write operations to write data, including the converted target data, to the memory cell array 210 via the page buffer circuit 250. By operating the N / O string control module 222, the number of write voltages applied to the word lines of the multiple target memory cells connected to the N / O string can be limited, and the stress on the N / O string can be reduced, thereby minimizing the adverse effects of the N / O string.

[0063] Reference Figure 4C The N / O string control module 222 can execute the following series of programming sequences PS: in response to the first type command CMD1, detect the N / O string of the target memory block in the memory cell array 210, convert the target data corresponding to the detected N / O string using the page buffer circuit 250, and write the data including the converted target data into the memory cell array 210. The following will refer to... Figures 7 to 9 Provide a detailed description.

[0064] N / O string control module 222 can perform a general write operation in response to a second type write command CMD2 received from the memory controller. For example, N / O string control module 222 can write data received from data input / output circuit 260 to memory cell array 210 in response to the second type write command CMD2.

[0065] According to an exemplary embodiment of the present invention, the N / O string control module 222 can receive from the memory controller a first type erase command CMD1 or a second type erase command CMD2 for erase operations on target memory blocks among the first to third memory blocks 210_11 to 210_13. (Refer to the above...) Figure 3A As described, it is assumed that a first type of erase command CMD1 is generated to control the erase operation on a target memory block with an N / O string number equal to or greater than a first threshold, and a second type of erase command CMD2 is generated to control the erase operation on a target memory block with an N / O string number less than the first threshold.

[0066] The N / O string control module 222 can, in response to a first type of erase command CMD1 received from the memory controller, perform an erase operation on a target memory block of the memory cell array 210 by using an erase voltage having a first level for a first time period. The N / O string control module 222 can, in response to a second type of erase command CMD2 received from the memory controller, perform an erase operation on a target memory block of the memory cell array 210 by using an erase voltage having a second level for a second time period. In an example embodiment, the first level may be higher than the second level, and the first time period may be shorter than the second time period. Reference will be made below. Figures 10A to 10C Provide a detailed description.

[0067] Figure 5A It is shown Figure 1 A block diagram of the storage cell array 210. Figure 5B yes Figure 1 A perspective cross-sectional view of a first example of a memory cell array 210, and Figure 5C yes Figure 1 A perspective cross-sectional view of a second example of a storage cell array 210.

[0068] Reference Figure 1 and Figure 5A The memory cell array 210 may include multiple memory blocks BLK1 to BLKz. Each memory block BLK1 to BLKz may have a 3D structure (“vertical structure”). For example, memory blocks BLK1 to BLKz may include structures extending upwards in a first direction to a third direction. Each memory block BLK1 to BLKz may include multiple strings (not shown) extending in a second direction. The strings may be spaced apart from each other in the first and third directions. A string (not shown) of a memory block may be connected to multiple bit lines BL, multiple string select lines SSL, multiple word lines WL, ground select lines GSL or multiple ground select lines GSL, and a common source line (not shown). The strings (not shown) of memory blocks BLK1 to BLKz may share a bit line BL. For example, the bit line BL may extend in the second direction and may be shared by memory blocks BLK1 to BLKz.

[0069] It can be by Figure 2 The address decoder 240 shown selects memory blocks BLK1 through BLKz. For example, the address decoder 240 can be configured to select a target memory block from memory blocks BLK1 through BLKz that corresponds to the received address ADDR. Write operations, read operations, and erase operations can be performed on the selected target memory block.

[0070] Reference Figure 5B and Figure 5CA substrate 211 is provided. For example, the substrate 211 may be a well having a first conductivity type. A plurality of common source regions CSRs extending in a first direction and spaced apart from each other in a second direction may be formed on the substrate 211. The common source regions CSRs may be interconnected to form a common source line. The common source regions CSRs have a second conductivity type different from the conductivity type of the substrate 211.

[0071] Between two adjacent common source regions (CSRs) in a common source region (CSR), a plurality of insulating materials 212 and 212a may be sequentially disposed on the substrate 211 along a third direction (i.e., a direction perpendicular to the substrate 211). The insulating materials 212 and 212a may be spaced apart from each other in the third direction. The insulating materials 212 and 212a may extend in a first direction.

[0072] Between two adjacent common source regions (CSRs), a plurality of pillars PL can be provided, arranged sequentially along a first direction and penetrating insulating materials 212 and 212a along a third direction. For example, the plurality of pillars PL can penetrate insulating materials 212 and 212a and contact substrate 211. For example, between two adjacent common source regions (CSRs), the pillars PL can be spaced apart from each other in the first direction. The pillars PL can be arranged in rows along the first direction.

[0073] For example, the columnar structure PL may include a variety of materials. For example, the columnar structure PL may include a channel film 214 and an internal material 215. The channel film 214 may include a semiconductor material having a first conductivity type (e.g., silicon). The channel film 214 may include a semiconductor material having the same conductivity type as the substrate 211 (e.g., silicon). The channel film 214 may include an intrinsic semiconductor that does not have a conductivity type.

[0074] The internal material 215 may include an insulating material. For example, the internal material 215 may include an insulating material such as silicon oxide. For example, the internal material 215 may include an air gap. Between two adjacent common source regions CSR, an information storage film 216 may be disposed on the exposed surfaces of the insulating materials 212 and 212a and the columnar material PL. The information storage film 216 can store information by capturing or releasing charge.

[0075] Conductive materials CM1 to CM8 are disposed on the exposed surface of the information storage film 216 between two adjacent common source regions CSR and between insulating materials 212 and 212a. The conductive materials CM1 to CM8 may extend in a first direction. On the common source regions CSR, the conductive materials CM1 to CM8 may be separated by word line cuts (WL cuts). The word line cuts (WL cuts) can expose the common source regions CSR. The word line cuts (WL cuts) may extend in the first direction. For example, the conductive materials CM1 to CM8 may include metallic conductive materials. The conductive materials CM1 to CM8 may also include non-metallic conductive materials such as polycrystalline silicon.

[0076] For example, the information storage film 216 disposed on the top surface of the uppermost insulating material of insulating materials 212 and 212a can be removed. For example, the information storage film 216 disposed on the side surface of the side surface of insulating materials 212 and 212a opposite to the column PL can be removed.

[0077] Multiple drains 320 may be disposed on the pillar PL. For example, drains 320 may comprise a semiconductor material having a second conductivity type (e.g., silicon). For example, drains 320 may comprise a semiconductor material having an N conductivity type (e.g., silicon).

[0078] On the drain 320, bit lines BL extending in a second direction and spaced apart from each other in the first direction may be provided. Bit lines BL are connected to the drain 320. For example, the drain 320 and bit lines BL may be connected via contact plugs (not shown). For example, bit lines BL1 and BL2 may comprise a metallic conductive material. For example, bit lines BL1 and BL2 may comprise a non-metallic conductive material such as polysilicon. Conductive materials CM1 to CM8 may sequentially have a first height to an eighth height, respectively, starting from the substrate 211.

[0079] The pillars PL can form multiple strings together with the information storage film 216 and conductive materials CM1 to CM8. Each pillar PL forms a string together with the information storage film 216 and adjacent conductive materials CM1 to CM8. Pillars PL can be arranged in both row and column directions on the substrate 211. Eighth conductive materials CM8 can form rows. Pillars PL connected to the same eighth conductive material can form a row. Bit lines BL can form columns. Pillars PL connected to the same bit line can form a column. The pillars PL, together with the information storage film 116 and conductive materials CM1 to CM8, form multiple strings arranged in both row and column directions. Each string may include multiple unit transistors CT (or memory cells) stacked in a direction perpendicular to the substrate 211.

[0080] Reference Figure 5CIn part A, a defect may occur at the pad between the drain 320 and the bit line BL during the manufacturing process, so the corresponding string may not be electrically connected to the bit line BL.

[0081] Reference Figure 5C In part B, due to defects in the manufacturing process, the hole in which the pillar PL is to be formed may not reach the substrate 211. In other words, the hole in which the pillar PL is to be formed may not be formed to a sufficient depth, and in this case, the channel film 214 may not contact the substrate 211. Specifically, due to etching failure during the formation of the pillar PL, the pillar PL may not be connected to the ground select transistor.

[0082] Reference Figure 5C In the C portion, defects may occur due to etching or deposition failures when forming the channels of the memory cells.

[0083] Because of Figure 5C The defects in parts A to C do not form a channel, so the corresponding string can correspond to an N / O string, and the memory cells included in the N / O string can always be read as OFF during the read operation, regardless of the data written to them.

[0084] Figure 6 This is a diagram illustrating a chip-to-chip (C2C) structure applied to a memory device 400 (an example of a memory device 200) according to an exemplary embodiment of the present invention.

[0085] Reference Figure 6 The memory device 400 may have a C2C structure. A C2C structure can refer to a structure formed by: fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and interconnecting the upper and lower chips by bonding. For example, bonding can refer to an electrical connection between a bonding metal formed on the topmost metal layer of the upper chip and a bonding metal formed on the topmost metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding can be a Cu-Cu bonding, and the bonding metal may also include aluminum or tungsten.

[0086] The peripheral circuit region PERI and cell region CELL of the storage device 400 may each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0087] The peripheral circuit region (PERI) may include a first substrate 510, an interlayer insulating layer 515, a plurality of circuit elements 520a, 520b, and 520c formed on the first substrate 510, first metal layers 530a, 530b, and 530c respectively connected to the circuit elements 520a, 520b, and 520c, and second metal layers 540a, 540b, and 540c respectively formed on the first metal layers 530a, 530b, and 530c. In an embodiment, the first metal layers 530a, 530b, and 530c may include tungsten with relatively high resistance, while the second metal layers 540a, 540b, and 540c may include copper with relatively low resistance.

[0088] Although only the first metal layers 530a, 530b, and 530c and the second metal layers 540a, 540b, and 540c are shown and described in this specification, the inventive concept is not limited thereto, and one or more metal layers may be further formed on the second metal layers 540a, 540b, and 540c. At least some of the metal layers formed on the second metal layers 540a, 540b, and 540c may comprise a material such as aluminum having a lower resistivity than the copper constituting the second metal layers 540a, 540b, and 540c.

[0089] An interlayer insulating layer 515 is disposed on the first substrate 510 to cover circuit elements 520a, 520b and 520c, first metal layers 530a, 530b and 530c, second metal layers 540a, 540b and 540c, and may include an insulating material such as silicon oxide or silicon nitride.

[0090] Lower bonding metals 571b and 572b may be formed on a second metal layer 540b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 571b and 572b in the peripheral circuit region PERI may be electrically connected to the upper bonding metals 671b and 672b in the cell region CELL by bonding, wherein the lower bonding metals 571b and 572b and the upper bonding metals 671b and 672b may comprise aluminum, copper, or tungsten.

[0091] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 610 and a common source line 620. Multiple word lines 631 to 638 (hereinafter collectively referred to as 630) may be stacked on the second substrate 610 in a direction perpendicular to the top surface of the second substrate 610 (Z-axis direction). Serial select lines and ground select lines may be arranged at the top and bottom of the word lines 630, and the word lines 630 may be arranged between the serial select lines and the ground select lines.

[0092] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the top surface of the second substrate 610 and pass through the word line 630, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 650c and the second metal layer 660c. For example, the first metal layer 650c may be a bit line contact, and the second metal layer 660c may be a bit line. In an embodiment, the bit line 660c may extend in a first direction (Y-axis direction) parallel to the top surface of the second substrate 610.

[0093] exist Figure 6 In the illustrated embodiment, the region where the channel structure CH and bit line 660c are arranged can be defined as a bit line bonding region BLBA. Bit line 660c can be electrically connected in the bit line bonding region BLBA to circuit element 520c that provides a page buffer 693 in the peripheral circuit region PERI. For example, in the cell region CELL, bit line 660c is connected to upper bonding metals 671c and 672c, and upper bonding metals 671c and 672c can be connected to lower bonding metals 571c and 572c that are connected to the circuit element 520c of the page buffer 693.

[0094] In the Word Line Bonding Area (WLBA), word lines 630 may extend in a second direction (X-axis direction) parallel to the top surface of the second substrate 610 and may be connected to a plurality of cell contact plugs 641 to 647 (hereinafter collectively referred to as 640). Word lines 630 and cell contact plugs 640 may be connected to each other at pads provided by at least some of the word lines 630 extending at different lengths along the second direction. A first metal layer 650b and a second metal layer 660b may be sequentially connected to the top of the cell contact plugs 640 connected to the word lines 630. In the Word Line Bonding Area (WLBA), cell contact plugs 640 may be connected to the Peripheral Circuit Area (PERI) via upper bonding metals 671b and 672b in the Cell Area (CELL) and lower bonding metals 571b and 572b in the Peripheral Circuit Area (PERI).

[0095] The cell contact plug 640 can be electrically connected to circuit element 520b that provides a row decoder 694 in the peripheral circuitry region PERI. In an embodiment, the operating voltage of circuit element 520b providing the row decoder 694 may differ from the operating voltage of circuit element 520c providing the page buffer 693. For example, the operating voltage of circuit element 520c providing the page buffer 693 may be greater than the operating voltage of circuit element 520b providing the row decoder 694.

[0096] A common source line contact plug 680 may be disposed in the external pad bonding region PA. The common source line contact plug 680 may comprise a conductive material such as a metal, metal compound, or polysilicon, and may be electrically connected to the common source line 620. A first metal layer 650a and a second metal layer 660a may be sequentially stacked on the common source line contact plug 680. For example, the region where the common source line contact plug 680, the first metal layer 650a, and the second metal layer 660a are disposed may be defined as the external pad bonding region PA.

[0097] Simultaneously, input / output pads 505 and 605 can be arranged in the external pad bonding area PA. A lower insulating film 501 covering the bottom surface of the first substrate 510 can be formed below the first substrate 510, and the first input / output pad 505 can be formed on the lower insulating film 501. The first input / output pad 505 is connected to at least one of the circuit elements 520a, 520b, and 520c arranged in the peripheral circuit area PERI via a first input / output contact plug 503, and can be separated from the first substrate 510 by the lower insulating film 501. Moreover, a side insulating film (not shown) can be disposed between the first input / output contact plug 503 and the first substrate 510 to electrically separate the first input / output contact plug 503 from the first substrate 510.

[0098] An upper insulating film 601 covering the top surface of the second substrate 610 may be formed on the second substrate 610, and a second input / output pad 605 may be disposed on the upper insulating film 601. The second input / output pad 605 may be connected to at least one of the circuit elements 520a, 520b, and 520c arranged in the peripheral circuit region PERI via a second input / output contact plug 603.

[0099] According to an embodiment, the second substrate 610 and the common source line 620 may not be arranged in the region where the second input / output contact plug 603 is provided. Furthermore, the second input / output pad 605 may not overlap with the word line 630 in the third direction (Z-axis direction). The second input / output contact plug 603 is separated from the second substrate 610 in a direction parallel to the top surface of the second substrate 610, and can pass through the interlayer insulating layer 615 in the cell region and connect to the second input / output pad 605.

[0100] According to embodiments, the first input / output pad 505 and the second input / output pad 605 can be selectively formed. For example, the storage device 400 may include only the first input / output pad 505 disposed on the first substrate 501, or only the second input / output pad 605 disposed on the second substrate 601. Alternatively, the storage device 400 may include both the first input / output pad 505 and the second input / output pad 605.

[0101] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell region CELL and the peripheral circuit region PERI, the metal pattern of the uppermost metal layer may be a dummy pattern or the uppermost metal layer may be omitted.

[0102] In the storage device 400, in the external pad bonding area PA, corresponding to the upper metal pattern 672a formed on the uppermost metal layer in the cell region CELL, a lower metal pattern 573a with the same shape as the upper metal pattern 672a in the cell region CELL can be formed on the uppermost metal layer in the peripheral circuit region PERI. The lower metal pattern 573a formed on the uppermost metal layer in the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, corresponding to the lower metal pattern formed on the uppermost metal layer in the peripheral circuit region PERI, an upper metal pattern with the same shape as the lower metal pattern in the peripheral circuit region PERI can be formed on the uppermost metal layer in the cell region CELL.

[0103] Lower bonding metals 571b and 572b can be formed on the second metal layer 540b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 571b and 572b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 671b and 672b in the cell region CELL by bonding.

[0104] Furthermore, in the bit line bonding region BLBA, corresponding to the lower metal pattern 552 formed on the uppermost metal layer in the peripheral circuit region PERI, an upper metal pattern 692 with the same shape as the metal pattern 552 can be formed on the uppermost metal layer in the cell region CELL. It is not necessary to form a contact on the upper metal pattern 692 formed on the uppermost metal layer in the cell region CELL.

[0105] Figure 7 It is used to describe in detail the response to Figure 4A The flowchart shows the operation of the storage device of the first type of command CMD1.

[0106] Reference Figure 7 In operation S200, the storage device can detect N / O strings from among multiple strings of the target storage block to be written in response to a first type of command. In operation S210, the storage device can convert the target data to be written to the storage cells included in the detected N / O strings into data with a predetermined value. In operation S220, the storage device can perform an operation to write data including the converted target data to the storage cell array. While only one N / O string is mentioned in the description for ease of explanation, the inventive concept is not limited thereto. Multiple N / O strings may exist, and the inventive concept can be applied to write operations involving multiple N / O strings. Moreover, the write operation for the storage device according to the exemplary embodiment of the inventive concept can be performed by a storage sub-block or by a predetermined group of memory.

[0107] Figures 8A to 8C It is used to describe the response to Figure 4A A diagram illustrating the method of operating storage devices using the first type of command, CMD1.

[0108] Figure 8A yes Figure 5A The equivalent circuit diagram of the first memory block BLK1. (Refer to...) Figure 8A Cell strings CS11, CS12, CS21, and CS22 can be located between bit lines BL1 and BL2 and the common source line CSL. Cell strings CS11 and CS21 can be connected between the first bit line BL1 and the common source line CSL. Cell strings CS12 and CS22 can be connected between the second bit line BL2 and the common source line CSL. Common source region ( Figure 3B The CSRs can be publicly connected to each other to form a common source line (CSL).

[0109] Memory cells of the same height are typically connected to a single word line, and when voltage is supplied to a word line of a specific height, voltage can be supplied to all strings CS11, CS12, CS21, and CS22. Strings from different rows can be connected to different string select lines SSL1 and SSL2. By selecting and deselecting the first string select line SSL1 and the second string select line SSL2, strings CS11, CS12, CS21, and CS22 can be selected and deselected row by row. For example, strings CS11 and CS12 or strings CS21 and CS22 connected to the unselected string select lines SSL1 or SSL2 can be electrically isolated from bit lines BL1 and BL2. Strings CS21 and CS22 or CS11 and CS12 connected to the selected string select lines SSL2 or SSL1 can be electrically connected to bit lines BL1 and BL2.

[0110] Strings CS11, CS12, CS21, and CS22 can be connected column-wise to bit lines BL1 and BL2. Strings CS11 and CS21 can be connected to the first bit line BL1, and strings CS12 and CS22 can be connected to the second bit line BL2. By selecting and deselecting bit lines BL1 and BL2, strings CS11, CS12, CS21, and CS22 can be selected and deselected column-wise. In the following text, this will be explained by focusing on... Figure 8A The structure of the first storage block BLK1 shown is used to describe a write operation of an exemplary embodiment of the present invention. However, this is only an exemplary embodiment; the inventive concept can be applied to storage blocks BLK1 with different structures.

[0111] Turn Figure 8B The memory device can respond to a first type command in the operation DT_STEP for detecting N / O strings from strings CS11, CS12, CS21 and CS22 by applying a first bit line voltage VBL1 to bit lines BL1 and BL2, applying a first string select line voltage VSSL1 (or on voltage) to the string select line selected from string select lines SSL1 and SSL2, applying a second string select line voltage VSSL2 (or off voltage) to the unselected string select line, sequentially applying a check voltage VCK to word lines WL1 to WL6, applying a first ground select line voltage VGSL1 to ground select line GSL, applying a first common source line voltage VCSL1 to common source line CSL, and applying a ground voltage VSS to the substrate.

[0112] For example, the first line voltage VBL1 can be the power supply voltage VCC, the first string selection line voltage VSSL1 can be the power supply voltage VCC, and the second string selection line voltage VSSL2 can be the ground voltage VSS or a low voltage with a similar level. As mentioned above, the level of the check voltage VCK can be higher than the level of the predetermined reference voltage.

[0113] Reference Figure 8C , refer to the above Figure 8B The voltages described can be applied at the start of the DT_STEP operation to the bit line BL, the selected string select line (SSL), the unselected string select line (SSL), the selected word line (WL), the ground select line (GSL), and the common source line (CSL). For example, the voltage on the bit line BL connected to the general string can become lower than a predetermined reference voltage at the first bit line voltage VBL1, and the voltage on the bit line BL connected to the N / O string can be maintained at the first bit line voltage VBL1. Therefore, the memory device can detect the N / O string.

[0114] Figure 9 It is used for detailed description Figure 7 The flowchart of operation S210.

[0115] Reference Figure 9 In operation S212, the storage device can pre-latch data to be written to the memory cell array into a page buffer circuit comprising multiple latch cells. This data can be data encoded by the memory controller. For example, the memory controller can encode data received from the host into error-correcting codewords and provide them to the storage device. In operation S214, the target data latched into the latch cells corresponding to the target memory cells included in the N / O string can be converted or maintained to each have a predetermined value. In an example embodiment, the predetermined value can be preset to a value corresponding to prohibition data used to form a threshold voltage distribution in the erase state.

[0116] Figures 10A to 10C It is used to describe the response to Figure 4A A diagram illustrating the method of operating storage devices using the first type of erase command CMD1 and the second type of erase command CMD2.

[0117] Reference Figure 10A The memory device can perform an erase operation E_STEP to erase the target memory block in response to a first type of erase command or a second type of erase command. In an example embodiment, the memory device can float bit lines BL1 and BL2 and the common source line CSL during operation E_STEP, and string select lines SSL1 and SSL2 can be floated or supplied with a third string select line voltage VSSL3. The memory device can supply word line erase voltage Vwe to word lines WL1 to WL6. The word line erase voltage Vwe can be ground voltage VSS or a low voltage (including positive and negative voltages) with a level similar to ground voltage VSS. Moreover, the memory device can float the ground select line GSL, or supply a second ground select line voltage VGSL2, and supply a first erase voltage Vers1 or a second erase voltage Vers2 to the substrate 211 ( Figure 5B The first erase voltage Vers1 can correspond to a first type of erase command, and the second erase voltage Vers2 can correspond to a second type of erase command.

[0118] Turn Figure 10B Channel membrane 214 ( Figure 5B ) can respond to a first type of erase command by supplying the substrate 211 during a first time period t1. Figure 5B The first erase voltage Vers1 is charged to the level of the first erase voltage Vers1. This is because the word line erase voltage Vwe supplied to word lines WL1 to WL6 is related to the channel membrane 214 ( Figure 5B The voltage difference between the first erase voltage Vers1 and the first erase voltage captures the charge leakage in the memory cells MC1 to MC6, thus enabling erasure. The erase operation can be performed until the second time period t2a.

[0119] Reference Figure 10C Channel membrane 214 ( Figure 5B ) can respond to a second type of erase command by supplying the substrate 211 during the second time period t1. Figure 5B The second erase voltage Vers2 is charged to the level of the second erase voltage Vers2. This is because the word line erase voltage Vwe supplied to word lines WL1 to WL6 is related to the channel membrane 214 ( Figure 5B The voltage difference between the second erase voltage Vers2 and the second erase voltage captures the charge leakage in the memory cells MC1 to MC6, thus enabling erasure. The erase operation can be performed until the third time period t2b.

[0120] In the example embodiment, the first erase voltage Vers1 may have a higher level than the second erase voltage Vers2, and the time period between the first time period t1 and the second time period t2a may be shorter than the time period between the first time period t1 and the third time period t2b.

[0121] In other words, the data reliability supported by a target memory block with a number of N / O strings equal to or greater than the first threshold may be slightly lower. Therefore, even if an erase operation is performed for a shorter period of time than usual using an erase voltage with a higher level than the normal erase voltage, the target memory block can be operated to ensure data reliability. Thus, a fast erase operation can be performed on the target memory block, thereby improving the performance of the entire storage device. Simultaneously, by performing a normal erase operation on a target memory block corresponding to a number of N / O strings less than the first threshold, the target memory block can be operated to ensure high data reliability.

[0122] Figure 11A and Figure 11B It is used for detailed description Figure 3B The diagram illustrates the first and second type of memory blocks. In the following, it is assumed that the memory controller designates the first memory block BLK1 and the second memory block BLK2, both corresponding to the number of N / O strings equal to or greater than a second threshold, as first type memory blocks, and the third memory block BLK3, corresponding to the number of N / O strings less than the second threshold, as a second type memory block.

[0123] Reference Figure 11AAs shown in Table TB2, the memory controller can use the storage cells of the first storage block BLK1 and the second storage block BLK2 as third-order cells (TLC). Furthermore, the memory controller can use the storage cells of the third storage block BLK3 as single-order cells (SLC). In other words, because the data reliability supported by the first type of storage block, corresponding to the number of N / O strings equal to or greater than the second threshold, may be relatively low, the first type of storage block can be used as a high-order cell. In contrast, because the data reliability supported by the second type of storage block, corresponding to the number of N / O strings less than the second threshold, may be relatively high, the second type of storage block can be used as a low-order cell.

[0124] In other embodiments, the first storage block BLK1 and the second storage block BLK2 are used as multi-level or fourth-level cells. Furthermore, in other embodiments, the first type of storage block can be used as a low-level cell, and the second type of storage block can be used as a higher-level cell than the first type of storage block.

[0125] Still refer to Figure 11B As shown in Table TB3, the memory controller can operate the first memory block BLK1 and the second memory block BLK2 exclusively for writing cold data to them. Furthermore, the memory controller can operate the third memory block BLK3 exclusively for writing hot data to it. In other words, because the data reliability supported by the first type of memory block, corresponding to the number of N / O strings equal to or greater than the second threshold, may be relatively low, the first type of memory block can be dedicated to writing cold data with an access frequency lower than the reference frequency. Because the data reliability supported by the second type of memory block, corresponding to the number of N / O strings less than the second threshold, may be relatively high, the second type of memory block can be dedicated to writing hot data with an access frequency higher than the reference frequency.

[0126] Figures 12A to 12C This is a diagram illustrating an embodiment of performing a selected control scheme for each of a plurality of sub-blocks included in a storage block in detail.

[0127] Reference Figure 12AAs shown in Table TB4, the first storage block BLK1 may include a first sub-block SB11 and a second sub-block SB12, the second storage block BLK2 may include a third sub-block SB21 and a fourth sub-block SB22, and the third storage block BLK3 may include a fifth sub-block SB31 and a sixth sub-block SB32. The first to sixth sub-blocks SB11, SB12, SB21, SB22, SB31, and SB32 may each include "A1", "A2", "B1", "B2", "C1", and "C2" N / O strings, respectively. Based on the N / O string information including Table TB4, the memory controller can select and run different types of control schemes for the first to sixth sub-blocks SB11, SB12, SB21, SB22, SB31, and SB32. In the example embodiment, the N / O string information including Table TB4 can be pre-generated and stored in the memory cell array of the storage device.

[0128] Figure 12B This is a diagram illustrating the structure of the first sub-block SB11 and the second sub-block SB12 of the first storage block BLK1 in detail. (Refer to...) Figure 12B The first sub-block SB11 may include storage units for strings connected to the first select line SSL1 and the second select line SSL2, and the second sub-block SB12 may include storage units for strings connected to the third select line SSL3 and the fourth select line SSL4.

[0129] The first select line SSL1 and the second select line SSL2 are both connected to at least one N / O string, and the first sub-block SB11 may include a number of N / O strings equal to or greater than a predetermined threshold. Therefore, the first sub-block SB11 can be composed of... Figure 3A The first type of command is used to control, or can be specified to be used with Figure 3B The first type of sub-block operates in the same manner as the first type of storage block. The third string select line SSL3 and the fourth string select line SSL4 are only connected to general strings, and the second sub-block SB12 can include a number of N / O strings less than a predetermined threshold. Therefore, the second sub-block SB12 can be... Figure 3A The second type of command is used to control, or can be specified to be used with Figure 3B The second type of sub-block operates in the same way as the second type of storage block.

[0130] In other words, sub-blocks can be grouped according to string selection lines, and the string selection lines corresponding to the sub-blocks can be adjacent to each other or separated from each other.

[0131] Figure 12C This is a diagram showing in detail the circuit structure of the first sub-block SB11 and the second sub-block SB12 of the first memory block BLK1. (Refer to...) Figure 12CThe first sub-block SB11 may include storage units MC1 to MC6 connected to the first to fourth strings CS11, CS12, CS21, and CS22 of the first select line SSL1 and the second select line SSL2. The second sub-block SB12 may include storage units MC1 to MC6 connected to the fifth to eighth strings CS31, CS32, CS41, and CS42 of the third select line SSL3 and the fourth select line SSL4.

[0132] Figure 13 This is a flowchart of a method for operating a memory controller according to an exemplary embodiment of the present invention.

[0133] Reference Figure 13 In operation S300, the memory controller can select a control scheme for each of the multiple sub-blocks based on N / O string information. In operation S320, the memory controller can control the storage operation of the storage device through the sub-blocks based on the selected control scheme.

[0134] Figure 14 This is a block diagram illustrating an example embodiment of a storage system 20 according to a concept of the present invention, and Figure 15 It is shown Figure 14 The table shows an example of N / O string information 1220.

[0135] Reference Figure 14 The storage system 20 may include a memory controller 1000 and first to nth storage devices 2000_1 to 2000_n. The memory controller 1000 may include a processor 1100 and internal memory 1200. The internal memory 1200 may include N / O string information 1220. The N / O string information 1220 may include information indicating the number of N / O strings included in a storage block of each of the first to nth storage devices 2000_1 to 2000_n. The processor 1000 may select and run a control scheme for each storage block of the first to nth storage devices 2000_1 to 2000_n based on the N / O string information 1220.

[0136] like Figure 15As shown in Table TB5, the N / O string information 1220 may include information indicating the number of N / O strings included in storage blocks BLK11 to BLK13, BLK21 to BLK23, and BLK31 to BLK33 of the first to third storage devices 2000_1 to 2000_3. The first to third storage blocks BLK11 to BLK13 may each include "A1", "B1", and "C1" N / O strings, respectively. The fourth to sixth storage blocks BLK21 to BLK23 may each include "A2", "B2", and "C2" N / O strings, respectively. The seventh to ninth storage blocks BLK31 to BLK33 may each include "A3", "B3", and "C3" N / O strings, respectively. Although Table TB5 is shown to include N / O string information for the first to third storage devices 2000_1 to 2000_3 for ease of illustration, Table TB5 may also include N / O string information for other storage devices 2000_4 to 2000_n.

[0137] The processor 1100 can select and run a corresponding control scheme from different control schemes for each of the storage blocks BLK11 to BLK13, BLK21 to BLK23, and BLK31 to BLK33 of the first to third storage devices 2000_1 to 2000_3 based on the fifth table TB5. Hereinafter, embodiments of the control operations performed by the processor 1100 through the storage devices, applying exemplary embodiments of the inventive concept, will be described.

[0138] Figure 16 This is a flowchart of a method for operating a memory controller according to an exemplary embodiment of the present invention. In the following description, reference will be made to... Figure 14 Provide a description.

[0139] Reference Figure 16 In operation S120 ( Figure 2 In operation S131c, the memory controller 1000 can refer to the N / O string information to check the status of each of the memory devices 2000_1 to 2000_n connected to the memory controller 1000. In operation S132c, the memory controller 1000 can check whether the number of N / O strings included in each of the memory devices 2000_1 to 2000_n is equal to or greater than a third threshold.

[0140] When operation S132c is "Yes", in operation S133c, the memory controller 100 can designate a memory device among memory devices 2000_1 to 2000_n whose number of N / O strings is equal to or greater than a third threshold as a first type of memory device. The first type of memory device may refer to a memory device operated according to a control scheme taking into account the state of the N / O strings, which is not preferred in terms of data reliability. When operation S132c is "No", in operation S134c, the memory controller 100 can designate a memory device among memory devices 2000_1 to 2000_n whose number of N / O strings is less than the third threshold as a second type of memory device. The second type of memory device may refer to a memory device operated according to a control scheme taking into account that the second type of memory block can support higher data reliability than the first type of memory block. In operation S135c, the memory controller 1000 may store specified information, including the results of the specified memory devices 2000_1 to 2000_n specified in operations S133c and S134c, in the internal memory 1200.

[0141] Figure 17A and Figure 17B It is used for detailed description Figure 16 The diagram illustrates the first type of storage device and the second type of storage device. In the following, it is assumed that the memory controller designates the first storage device MD1 and the second storage device MD2, both corresponding to the number of N / O strings equal to or greater than a third threshold, as first type storage devices, and designates the third storage device MD3, corresponding to the number of N / O strings less than the third threshold, as second type storage devices.

[0142] Reference Figure 17A As shown in Table TB6, the memory controller can use the storage cells of the first memory device MD1 and the second memory device MD2 as TLC. Furthermore, the memory controller can use the storage cells of the third memory device MD3 as SLC. In other words, because the data reliability supported by the first type of memory device, corresponding to the number of N / O strings equal to or greater than the third threshold, may be relatively low, the storage cells of the first type of memory device can be used as high-order cells. In contrast, because the data reliability supported by the second type of memory device, corresponding to the number of N / O strings less than the third threshold, may be relatively high, the storage cells of the second type of memory device can be used as low-order cells.

[0143] However, this is merely an example embodiment, and the inventive concept is not limited thereto. The first storage device MD1 and the second storage device MD2 can also be used as multi-level or fourth-level cells. Furthermore, the storage cells of the first type of storage device can be used as low-level cells, and the storage cells of the second type of storage device can be used as higher-level cells than those of the first type of storage device.

[0144] Reference Figure 17B As shown in Table 7 (TB7), the memory controller can operate the first memory device MD1 and the second memory device MD2 to dedicate them to writing cold data. Furthermore, the memory controller can operate the third memory device MD3 to dedicate it to writing hot data. In other words, because the data reliability supported by the first type of memory device, corresponding to the number of N / O strings equal to or greater than the third threshold, may be relatively low, the first type of memory device can be dedicated to writing cold data with an access frequency lower than the reference frequency. Because the data reliability supported by the second type of memory device, corresponding to the number of N / O strings less than the third threshold, may be relatively high, the second type of memory device can be dedicated to writing hot data with an access frequency higher than the reference frequency.

[0145] Figure 18 This is a block diagram illustrating a test system 3000 for generating N / O string information according to an example embodiment of the present invention.

[0146] Reference Figure 18 The test system 3000 may include a storage device 3100 and a test device 3200. The test device 3200 can generate N / O string information by detecting N / O strings included in each memory block of the storage device 3100. The test device 3200 can store the generated N / O string information in the storage device 3100 and can read the N / O string information from a memory controller (not shown), thereby enabling it to perform operations according to an exemplary embodiment of the present invention.

[0147] Although the inventive concept described herein has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the claimed subject matter as defined by the appended claims and their equivalents.

Claims

1. A storage system, comprising: A first storage device, the first storage device including a plurality of first storage blocks, each first storage block including a plurality of first storage cells stacked in a direction perpendicular to the substrate; as well as A memory controller configured to control the storage operations of the first storage device. The memory controller is further configured to select and run a corresponding control scheme from different control schemes for each of the first memory blocks, based on the number of unopened strings (N / O strings) in each first memory block. The memory controller is further configured to: when the number of N / O strings in the first target memory block among the plurality of first memory blocks is equal to or exceeds a threshold, provide the first memory device with a first type of command for the first target memory block. The storage system further includes control logic configured to: detect at least one N / O string from among a plurality of strings included in the first target storage block in response to a command of the first type; convert multiple bits of target data to be written to the plurality of target storage cells included in the detected at least one N / O string into data bits having predetermined values ​​and write data bits having the predetermined values ​​to the plurality of target storage cells, thereby limiting the number of times a write voltage is applied to the target storage cells.

2. The storage system according to claim 1, wherein, The memory controller is further configured to provide a second type of command to the first storage device for the first target storage block when the number of N / O strings in the first target storage block is less than the threshold.

3. The storage system according to claim 2, wherein, The second type of command is used for general write operations, and the memory controller is further configured to provide the second type of command to the first storage device when controlling a write operation for a second target storage block corresponding to the number of N / O strings less than the threshold among the plurality of first storage blocks.

4. The storage system according to claim 1, wherein, The memory controller is further configured to: when controlling the erasure of a first target memory block in the first memory block corresponding to the number of N / O strings equal to or greater than a threshold, provide a first type of erase command to the first memory device; And when erasing a second target memory block in the first memory block corresponding to the number of N / O strings less than the threshold, a second type of erase command is provided to the first memory device.

5. The storage system according to claim 4, wherein, The first storage device is configured to: in response to the first type of erase command, perform an erase operation on the first target storage block by using an erase voltage having a first level for a first time period; And in response to the second type of erase command, an erase operation is performed on the second target memory block by using an erase voltage with a second level for a second duration.

6. The storage system according to claim 5, wherein, The first level is higher than the second level, and The first time period is shorter than the second time period.

7. The storage system according to claim 1, wherein, The memory controller is further configured to: designate a first target memory block in the first memory block corresponding to the number of N / O strings equal to or greater than a threshold as a first type memory block, and designate a second target memory block in the first memory block corresponding to the number of N / O strings less than the threshold as a second type memory block, the second type memory block having higher data reliability than the first type memory block.

8. The storage system according to claim 7, wherein, The second type of storage block is used as a lower-order unit than the first type of storage block.

9. The storage system according to claim 7, wherein, The first type of storage block is used to write cold data that is accessed at a frequency lower than the reference frequency, and The second type of storage block is used to write hot data to it at an access frequency higher than the reference frequency.

10. The storage system according to claim 1, wherein, The memory controller is also configured to request first N / O string information related to the number of N / O strings from the first memory device, and The first storage device is also configured to provide the first N / O string information to the memory controller in response to the request.

11. The storage system according to claim 1, wherein, The memory controller is further configured to select and run the appropriate control scheme among the different control schemes for each of the multiple sub-blocks defined in the first memory block, based on the number of N / O strings.

12. The storage system according to claim 11, wherein, Each of the first storage blocks is classified into a first sub-block that does not include N / O strings and a second sub-block that includes at least one N / O string.

13. The storage system of claim 1, further comprising a second storage device, the second storage device comprising a plurality of second storage blocks, each second storage block comprising a plurality of second storage cells stacked in a direction perpendicular to the substrate, and in, The memory controller is also configured to select and run the appropriate control scheme among the different control schemes for each second memory block based on second N / O string information about the number of N / O strings included in each second memory block.

14. A memory controller, comprising: Internal memory, configured to store N / O string information about the number of unopened strings, i.e., N / O strings, included in each of a plurality of memory blocks included in an external storage device; as well as A processor configured to operate a first target storage block, which includes at least one N / O string, among the plurality of storage blocks based on the N / O string information, according to a first control scheme, and to operate a second target storage block that does not have any N / O strings according to a different second control scheme. The processor is further configured to: when the number of N / O strings in the first target storage block among the plurality of storage blocks is equal to or exceeds a threshold, provide the external storage device with a first type of command for the first target storage block, such that the external storage device, in response to the first type of command, detects the at least one N / O string from the first target storage block, converts multiple bits of target data to be written to the plurality of target storage cells included in the detected at least one N / O string into data bits having predetermined values, and writes data bits having the predetermined values ​​to the plurality of target storage cells, thereby limiting the number of times a write voltage is applied to the target storage cells.

15. The memory controller according to claim 14, wherein, The processor is further configured to: generate a first type of command with a first code, and output the first type of command to the external storage device, wherein the first type of command includes the detection of the N / O string and the conversion of the detected N / O string for the target storage cell in the first target storage block in a programming sequence for the first target storage block; And generate a second type of command with a second code, and output the second type of command to the external storage device, the second type of command being used to normally execute the programming sequence for the second target storage block.

16. The memory controller of claim 14, wherein, The processor is further configured to: generate a first type of erase command with a first code, and output the first type of erase command to the external storage device, wherein the first type of erase command is used to perform an erase operation on the first target storage block for a first time period using an erase voltage with a first level. The system generates a second type of erase command with a second code and outputs the second type of erase command to the external storage device. The second type of erase command is used to perform an erase operation on the second target storage block for a second time period, which is longer than the first time period, using an erase voltage with a second level lower than the first level.

17. The memory controller according to claim 14, wherein, The processor is also configured to use the second target memory block as a lower-order unit than the first target memory block.

18. The memory controller according to claim 14, wherein, The processor is further configured to: operate on the first target storage block to write cold data to it at an access frequency lower than a reference frequency; and operate on the second target storage block to write hot data to it at an access frequency higher than the reference frequency.

19. A storage device comprising: A memory cell array, the memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells stacked in a direction perpendicular to the substrate; as well as The control logic is configured to: in response to a first type of command received by the storage device, detect unopened strings, i.e., N / O strings, in a first target storage block within the storage block; avoid writing target data to multiple target storage cells included in the detected N / O strings that are pre-specified to be written to, and instead write data bits, each with a predetermined value, to the multiple target storage cells to limit the number of times a write voltage is applied to the multiple target storage cells; And in response to a second type of command received by the storage device, a general write operation is performed on a second target storage block within the storage block. In this context, the storage cells of the second target storage block are used as lower-order cells than the storage cells of the first target storage block.

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