Adaptive parity techniques for memory devices

Abstract

This disclosure relates to adaptive parity techniques for memory devices. A device such as a memory device can support access operations using one or more error correction code (ECC) schemes, an error cache, or both. The memory device can receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device can read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device can read or write the data without using an ECC scheme or using a second ECC scheme that is different from the first ECC scheme.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 993,959, filed August 14, 2020, entitled “Adaptive Parity Technologies for a Memory Device,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to adaptive parity checking technology for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to different states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from external power. Summary of the Invention

[0006] A method is described. The method may include: receiving a command to read data from a memory array, the command indicating an address associated with the data; reading the data from the memory array in response to the command; determining, at least in part, an indication that a cache contains the address and a set of parity bits for the data based on the address; and using the set of parity bits to check for one or more errors in the data, at least in part, based on the indication that the cache contains the address and the set of parity bits.

[0007] A method is described. The method may include: receiving a command to write data to a memory array, the command indicating an address associated with the data; determining, in response to the command, an indication that a cache contains the address; generating a set of parity bits for the data based at least in part on the indication that the cache contains the address; and writing the data to the memory array and writing the set of parity bits to the cache.

[0008] An apparatus is described. The apparatus may include: a memory array; a cache configured to store multiple entries, each corresponding to a respective set of memory cells, within the memory array, each of the multiple entries including an indication of an address associated with the respective set of memory cells, a parity bit of data associated with the respective set of memory cells, or a combination thereof; and circuitry configured to cause the apparatus to receive a command to read data from the memory array, the command indicating an address associated with the data, and to read the data from the memory array in response to the command. Attached Figure Description

[0009] Figure 1 This document describes an example of a system that supports adaptive parity checking techniques for memory devices, based on examples disclosed herein.

[0010] Figure 2 This describes an example of a memory die that supports adaptive parity checking technology for memory devices, based on examples disclosed herein.

[0011] Figure 3 This document describes an example of a system that supports adaptive parity checking techniques for memory devices, based on examples disclosed herein.

[0012] Figure 4 This document describes an example of a process flow that supports adaptive parity checking techniques for memory devices, based on examples disclosed herein.

[0013] Figure 5This document describes an example of a process flow that supports adaptive parity checking techniques for memory devices, based on examples disclosed herein.

[0014] Figure 6 A block diagram illustrating a memory array that supports adaptive parity checking techniques for memory devices according to aspects of this disclosure.

[0015] Figure 7 and 8 The flowchart illustrates one or more methods supporting adaptive parity techniques for memory devices, based on examples disclosed herein. Detailed Implementation

[0016] Some memory systems utilize error detection or correction techniques (often referred to as error checking techniques) to detect or correct errors in data retrieved from a memory array. For example, a memory system may implement error checking techniques (e.g., parity check schemes) to determine if data is corrupted while stored in the memory array and, in some cases, attempt to correct detected errors. However, a given error checking technique may be limited to detecting or correcting up to a certain number of errors (with at least a certain level of reliability). For example, a single error correction (SEC) scheme may be able to detect and correct a single error in a set of data, and a double error detection (DED) scheme may be able to detect up to two errors and correct one error in a set of data, as well as other instances of parity check schemes. In some cases, the data may contain more errors than the number of correctable or detectable errors of an error checking scheme (e.g., a SECDED scheme may not be able to reliably detect or correct three errors in a set of data, as well as other instances of such numbers and schemes).

[0017] The techniques described herein enable memory systems to implement adaptive parity checking schemes for error correction, resulting in relatively more robust error checking techniques while mitigating increased processing or storage overhead, or both, and other advantages. Some errors associated with a memory array may be fixed (e.g., due to defective memory cells, such as being "stuck" in storing a logical state), while others may be time-varying (e.g., due to transient conditions such as temperature or electromagnetic effects, making the associated memory cells potentially not actually defective). Memory devices may include or otherwise be able to access a cache, which may be referred to as an error cache and may be managed (e.g., filled and evicted or otherwise maintained) to include indications of memory cells associated with fixed errors and not include (e.g., evicted over time) indications of memory cells associated with time-varying errors. Memory devices may use an error cache to select a parity checking scheme for a set of data based on whether a set of memory cells to which data is written or read is indicated by the cache to contain one or more defective memory cells. Therefore, if the error cache contains this indication, a more robust parity scheme can be selected and used for the data, and if the error cache does not contain this indication, a less robust parity scheme (or no parity scheme) can be selected and used for the data.

[0018] In some instances, the memory system may query an error cache that supports read operations. As an illustrative example, the memory system may receive a command from the host system to read data from a memory array. The command may indicate the address of data in the memory array. The memory system may read the data and search the error cache for the entry associated with the command. Such an entry may contain an address indication and a set of parity bits. The memory system may use one or more ECC schemes to check the data for one or more errors based on whether the error cache contains the entry. For example, if the cache contains an entry for the address, the memory device may use a first ECC scheme (e.g., using a set of parity bits stored in the error cache, a set of parity bits stored in the memory array, or a combination thereof) to check the data. This scheme can be relatively more robust, which improves the error correction and detection capabilities relative to addresses that are more likely to contain errors. As another example, if the cache lacks an entry for the address, the memory array may use a second ECC scheme to check the data (or in some cases, may forgo error checking of the data). For example, the second ECC scheme could be the default or a relatively less robust parity scheme (e.g., using a set of parity bits stored in the memory array, or other error checking techniques that do not use parity bits). Using the default scheme for addresses not included in the cache reduces processing overhead (e.g., using fewer parity bits), uses relatively less storage space for addresses that are less likely to contain errors, and has other advantages.

[0019] Alternatively, the memory system may query an error cache that supports write operations. For example, the memory system may determine whether the error cache contains one or more entries for the address of data. If the error cache lacks entries for the address, the memory system may write the data and / or parity bits to the memory array without using an ECC scheme (e.g., the memory system may prevent the generation of parity bits for the data) or with a default, relatively less robust ECC scheme (e.g., the memory system may generate a certain number of parity bits for a second ECC scheme). If the error cache contains one or more entries for the address, the memory system may use a relatively more robust ECC scheme. For example, the memory system may generate a relatively high number of parity bits, and in some cases, when the error cache contains one or more entries for the address, at least a portion of the parity bits are stored in the error cache.

[0020] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figures 3 to 5 The features of this disclosure are described in the context of the memory system and process flow described herein. (See references...) Figures 6 to 8 The device diagrams and flowcharts relating to adaptive parity checking techniques for memory devices are described in further detail, and these and other features of this disclosure are described with reference to the device diagrams and flowcharts.

[0021] Figure 1 This document describes an example of a system 100 that supports adaptive parity checking techniques for memory devices, based on examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0022] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0023] At least a portion of system 100 may be an instance of host device 105. Furthermore, host device 105 may be an instance of a processor or other circuitry within a device that uses memory to perform processes within, for example, a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or some other fixed or portable electronic device, and other examples. In some instances, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0024] Memory device 110 may be a separate device or component that can be used to provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0025] Memory device 110 may be used to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0026] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other via bus 135.

[0027] Processor 125 may be used to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0028] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or any other non-volatile memory.

[0029] Memory device 110 may include device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0030] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and are used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0031] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0032] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components that can be used to control the operation of memory die 160. In some instances, the local memory controller 165 may be used to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0033] External memory controller 120 can be used to implement the communication of one or more of the information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret the communications exchanged between components of host device 105 and memory device 110. In some instances, the external memory controller 120, or other components of system 100 or host device 105, or its functionality as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, system 100, or other components of host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120, or its functionality as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0034] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths for carrying signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to serve as part of a channel.

[0035] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol of a signal (e.g., signal level) may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols of a signal (e.g., signal levels) may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0036] In some instances, CA channel 186 can be used to communicate commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, the commands carried by CA channel 186 may include a read command with an address containing the desired data. In some instances, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) that decode one or more of the address or command data.

[0037] In some instances, data channel 190 may be used to communicate one or more of data or control information between host device 105 and memory device 110. For example, data channel 190 may communicate information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110. In some instances, one or more other channels 192 may include one or more error detection code (EDC) channels. EDC channels may be used to communicate error detection signals, such as checksums, to improve system reliability. EDC channels may contain any number of signal paths.

[0038] In some instances, bit errors can be attributed to defects in the memory cell (e.g., defects arising from the manufacturing process, potential defects occurring after manufacturing, etc.). For example, a memory cell may contain defects that produce fixed errors (e.g., the memory cell may be defective), or the detected errors in the memory cell may be time-varying errors (e.g., relative to functionality, a memory cell may contain random errors due to operating conditions or other random environments).

[0039] Error checking techniques can detect or correct up to a certain number of errors in data written to and subsequently read from a memory array, based on parity information generated for the data. This parity information may, in some cases, be stored in the memory array (e.g., associated with the corresponding data). For example, the SEC parity scheme can support the detection or correction of a single error in data based on the data's parity information, the SECDED parity scheme can support the detection of up to two errors and the correction of a single error based on the data's parity information, and other instances of error detection schemes. In some cases, the data may contain more errors than the number that can be corrected based on associated parity information.

[0040] As described herein, system 100 may implement an adaptive parity check scheme for error correction, which can produce a relatively more robust error checking technique while reducing associated processing or storage overhead, or both, and other advantages. For example, one or more components of system 100 (e.g., memory device 110, host device 105, device memory controller 155, local memory controller 165, external memory controller 120, or any combination thereof) may maintain an error cache to provide information for error correction to the error correction engine, as described herein, including, for example, references to… Figures 3 to 5 .

[0041] Memory device 110 may perform access operations using an error cache according to one or more parity schemes. Memory device 110 may store entries for one or more addresses of memory array 170 in the error cache. For example, memory device 110 may detect an error at an address and update the error cache to include an address indication and one or more parity bits (e.g., the error cache may contain a list of addresses that may contain errors based on previous error detection operations).

[0042] In some instances, memory device 110 may support one or more ECC schemes (e.g., parity schemes) and may use an error cache to select or identify an error scheme for a given set of data. As an illustrative example, memory device 110 may receive a command from a host system to read data from memory array 170. The command may indicate the address of data in memory array 170. Memory device 110 may read the data and search the error cache for entries associated with the command. Such entries may contain an address indication and a set of parity bits. Memory device 110 may use one or more parity schemes to check for one or more errors in the data based on whether the error cache contains an entry. For example, if the cache contains an entry for an address, the memory array may use a first scheme (e.g., using a set of parity bits stored in the error cache, a set of parity bits stored in memory array 170, or a combination thereof) to check the data. This scheme may be relatively more robust, which improves the error correction and detection capabilities relative to addresses that are more likely to contain errors. As another example, if the cache lacks an entry for an address, memory device 110 can use a first scheme (e.g., a default parity scheme) to check the data (e.g., using a set of parity bits stored in memory array 170, or other error checking techniques). Using the default memory scheme for addresses not included in the cache reduces processing overhead (e.g., using fewer parity bits), uses relatively less storage space for addresses that are relatively unlikely to contain errors, and has other advantages. Alternatively, memory device 110 may receive a command to write data to an address and generate (or prevent the generation of) parity bits according to one or more ECC schemes as described herein.

[0043] Figure 2 This describes an example of a memory die 200 that supports an improved error-correcting error caching technology for memory devices, as disclosed herein. The memory die 200 may be a reference. Figure 1Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store different logical states (e.g., programmed to be one of a set of two or more possible states). For example, memory cells 205 may be used to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cells 205 (e.g., multi-level memory cells) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference]. Figure 1 The memory array 170 is described.

[0044] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing a programmable state. In other memory architectures, other memory devices and components are possible. For example, a nonlinear dielectric material may be used. Memory cell 205 may include logic memory components such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be a cell board reference voltage, such as Vpl, or may be ground, such as Vss.

[0045] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern such as a grid pattern. Access lines may be conductive lines coupled to memory cells 205 and used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0046] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 at its intersection can be accessed by applying a bias voltage to word line 210 and digital line 215 (e.g., applying a voltage to word line 210 or digital line 215). The intersection of word line 210 and digital line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of memory cell 205.

[0047] The access memory unit 205 can be controlled via either row decoder 220 or column decoder 225. For example, row decoder 220 may receive a row address from local memory controller 260 and activate word line 210 based on the received row address. Column decoder 225 may receive a column address from local memory controller 260 and activate digital line 215 based on the received column address.

[0048] The selection or deselection of memory cell 205 can be achieved by activating or deactivating switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switch assembly 235. For example, when switch assembly 235 is deactivated, capacitor 230 can be isolated from digital line 215, and when switch assembly 235 is activated, capacitor 230 can be coupled to digital line 215.

[0049] Sensing component 245 can be used to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or otherwise convert the signal generated by accessing memory cell 205. Sensing component 245 can compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 245 (e.g., to input / output 255) and can indicate the detected logic state to another component of the memory device including memory die 200.

[0050] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference. Figure 1Examples of the described local memory controller 165. In some instances, one or more of the row decoder 220, column decoder 225, and sensing component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transmit data from memory die 200 to host device 105 based on the performance of said one or more operations. The local memory controller 260 may generate row signals and column address signals to activate target word line 210 and target digital line 215. The local memory controller 260 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0051] The local memory controller 260 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 can be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0052] The local memory controller 260 can be used to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 260 can identify the target memory cell 205 to which a write operation will be performed. The local memory controller 260 can identify a target word line 210 and a target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. The local memory controller 260 can apply a specific signal (e.g., a write pulse) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205. The pulse used as part of the write operation may contain one or more voltage levels over a duration.

[0053] The local memory controller 260 can be used to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 260 can identify the target memory cell 205 to which the read operation will be performed. The local memory controller 260 can identify the target word line 210 and the target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. The target memory cell 205 can transmit a signal to the sensing component 245 in response to applying a bias voltage to the access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate the sensing component 245 (e.g., a latching sensing component), thereby comparing the signal received from the memory cell 205 with a reference 250. Based on the comparison, the sensing component 245 can determine the logic state stored in the memory cell 205.

[0054] The local memory controller 260 and the memory die 200 may include, be coupled to, or otherwise utilize the error cache 265 to support error correction for data stored in and read from the memory array. Figure 2The local memory controller 260 is shown as the local memory cache 265. Alternatively, in some cases, the error cache 265 may be coupled to the local memory controller 260. And in some cases (e.g., where memory cell 205 is non-volatile), the error cache 265 may be or contain a portion of the memory array.

[0055] For example, the local memory controller 260 (or another controller of the memory device 110 or the host device 105) may maintain (e.g., manage) the contents of the error cache 265 to provide information for error correction, such as references. Figures 3 to 5 As described. Error cache 265 may be filled with one or more entries indicating the address (and in some cases, parity bits) associated with one or more defective memory cells of memory die 200. For example, local memory controller 260 may identify errors in the data associated with the address, and local memory controller 260 may write an indication containing the address of the identified error to error cache 265. Alternatively, local memory controller 260 may generate a set of parity bits for a parity check scheme and store the parity bits in error cache 265 with the indication of the address.

[0056] When performing various operations (e.g., access operations) and while supporting one or more programs for error correction or detection, the local memory controller 260 may query the error cache 265. For example, error checking logic (e.g., within the memory die 200) may use parity bits stored in the error cache 265, parity bits stored in the memory die 200, or a combination thereof, to detect and / or correct a certain number of errors in data read from the memory array. The error checking logic may be or include, as referenced... Figure 3 The description includes one or more error correction engines 315. The local memory controller 260 can query the error cache 265 to select a parity scheme to be used for a given set of data or to identify a parity scheme previously selected for said set of data. In some cases, different parity schemes may correspond to different respective error correction engines 315.

[0057] As an illustrative example, the local memory controller 260 may receive a command from a host system to read data from a memory array. The command may indicate the address of data in the memory array. The local memory controller 260 may read the data and search an error cache for entries associated with the command. Such entries may contain an address indication and a set of parity bits. The local memory controller 260 may use one or more parity schemes to check for one or more errors in the data based on whether the error cache contains an entry. For example, if the cache contains an entry for an address, the memory array may use a first scheme (e.g., using a set of parity bits stored in the error cache, a set of parity bits stored in the memory array, or a combination thereof) to check the data. This scheme can be relatively more robust, which improves the error correction and detection capabilities relative to addresses that are more likely to contain errors. As another example, if the cache lacks an entry for an address, the local memory controller 260 may use a first scheme (e.g., a default parity scheme) to check the data (e.g., using a set of parity bits stored in the memory array, or other error checking techniques). Using the default memory scheme for addresses not included in the cache reduces processing overhead (e.g., uses fewer parity bits) and uses relatively less storage space for addresses that are less likely to contain errors, among other advantages. Alternatively, the local memory controller 260 may receive commands to write data to an address and generate (or prevent) parity bits according to one or more ECC schemes as described herein.

[0058] Figure 3 This describes an example of a system 300 that supports adaptive parity checking techniques for memory devices, as disclosed herein. System 300 may be as described in the references... Figure 1 and 2 Examples of aspects of the described system 100 or memory device 110.

[0059] System 300 may include a memory array 310, which may be an instance of memory array 170. System 300 may also include an error cache 305 and one or more error correction engines 315 (e.g., error correction engine 315-b and error correction engine 315-a). In some instances, the error correction engine 315 may be alternatively referred to as error checking circuitry or error checking logic. System 300 may be configured to use one or more error correction engines 315 and the error cache 305 to perform one or more error checking procedures, which can reduce the probability of errors in communication (e.g., transmitting corrupted data from memory array 310), reduce the associated processing or storage overhead of system 300, or a combination thereof. Generally, Figure 3The components shown herein can implement the error-checking related procedures and operations described herein, but it should be understood that there may be more or fewer components than those shown for implementing the procedures described. Additionally or alternatively, although described individually for clarity of illustration, the various components described herein may be combined or physically located in ways other than those shown.

[0060] Error cache 305 maintains a list of addresses in the memory array associated with previously detected errors (e.g., defective memory cells attributable to addresses). For example, system 300 can detect errors in pages while reading data from an address. For example, system 300 can detect errors using a first ECC scheme (e.g., ECC1), which is, for example, a first parity scheme using a first number of parity bits. Based on the detected error, system 300 can generate a second set of parity bits containing a second, larger number of parity bits according to a second ECC scheme (e.g., ECC2). System 300 can store an address indication and at least a portion of the generated second set of parity bits in error cache 305. As an illustrative example, for data associated with a storage location identified as containing one or more defective memory cells, system 300 may store twenty-eight (28) bits indicating the address and nine (9) of the eighteen (18) parity bits generated for the address according to the ECC2 scheme in error cache 305, and store another nine (9) of the eighteen (18) ECC2 parity bits generated in memory array 310, as well as other instances of quantity and storage scheme (e.g., system 300 may store all generated ECC2 parity bits in error cache 305, etc.). As another illustrative example, for data associated with a storage location in which defective memory cells have not been identified, system 300 may implement the ECC1 scheme for the address and store the data and all nine (9) of the generated ECC1 parity bits in memory array 310 (e.g., error cache 305 may lack an entry for the address or associated parity bits). It should be understood that these and any other specific numerical examples are provided herein for clarity only and do not limit the scope of the claims.

[0061] Typically, a memory device can support N different parity schemes, where N is any value one or greater than one. For data written to addresses associated with one or more memory cells previously identified as faulty, the memory device can generate and store parity bits or a larger number of parity bits. For data written to addresses where the associated memory cells were not identified as faulty, the memory device may not generate and store any parity bits, or may generate and store a smaller number of parity bits. The memory device can thus select and utilize parity schemes and associate the amount of overhead appropriate for the relative probability of introducing errors into the data based on historical information about whether errors have been previously detected in data from a set of memory cells storing the data.

[0062] In some instances, a list of addresses may be generated based on ECC results or according to tests performed during one or more maintenance cycles (e.g., refresh cycles). (For example, system 300 may execute a diagnostic procedure for the memory device during a refresh or other suitable time period, and error cache 305 may be populated based on the results of the procedure.) In some instances, information may be loaded into error cache 305 upon power-on (e.g., in NVM, the list may be loaded into content-addressable memory (CAM) or static RAM upon power-on of the memory device).

[0063] System 300 may receive commands, for example, from a host device. The commands may indicate an address 320 associated with data (e.g., a logical address associated with data or a physical address associated with a set of memory cells within memory array 310) for writing or reading data.

[0064] When the received command is a write command, system 300 may store the data in memory array 310. System 300 may also check error cache 305. If error cache 305 contains an entry for address 320, then system 300 may generate parity bits according to a relatively robust parity scheme and store at least a portion of the generated parity bits in error cache 305 and / or memory array 310. For example, in the illustrative example described above, system 300 may generate eighteen (18) parity bits for the ECC2 scheme and store a first subset of nine (9) of the eighteen (18) parity bits in memory array 310 (e.g., along with the write data), and store a second subset of nine (9) of the eighteen (18) parity bits in error cache 305 (e.g., along with the indication of address 320), but any number of bits, bit distribution across memory array 310 or error cache 305, or ECC scheme may be used.

[0065] When the received command is a read command, the controller of system 300 may perform a read operation to retrieve the corresponding data 340 from the indicated address 320 of memory array 310. In some instances, system 300 may also read parity information of data 340 (e.g., parity bits 355 previously generated based on data 340) from memory array 310. Alternatively, system 300 may read a first set of parity bits from error cache 305. For example, system 300 may store a set of parity bits associated with data (e.g., using a first ECC scheme) or a portion of a set of parity bits associated with data (e.g., using a second ECC scheme that is relatively more robust than the first ECC scheme) in memory array 310. System 300 may query error cache 305 to determine whether error cache 305 contains an entry for address 320. In response to the query, error cache 305 may send information 350 to the corresponding error correction engine 315. For example, if error correction engine 315-b is selected based on the fact that error cache 305 contains an entry for address 320, then information 350 may contain parity bits for the corresponding ECC scheme, and error cache 305 may send the parity bits to error correction engine 315-b. Information 350 may contain error correction information (e.g., parity bits for ECC2 scheme), which enables error correction engine 315 to correct the stated number of errors.

[0066] System 300 may use one or more error correction engines 315 to perform error checking. For example, if error cache 305 contains an indication of address 320, then system 300 may use error correction engine 315-b, and if error cache 305 lacks an indication of address 320, then system 300 may use error correction engine 315-a. Error correction engine 315-b may implement a relatively more robust ECC scheme than error correction engine 315-a. In other words, error correction engine 315-b may be configured to detect or correct a larger number of errors in the data compared to error correction engine 315-a. For example, error correction engine 315-b may use parity bits of an ECC2 scheme (e.g., a relatively high number of parity bits, where a portion of the parity bits are stored in error cache 305 and / or memory array 310). This scheme achieves a higher probability of detecting or correcting errors in data 340. Error correction engine 315-a may implement a relatively less robust but lower-overhead ECC scheme. For example, error correction engine 315-a may not use parity bits for data 340, or it may use a relatively small number of parity bits stored in memory array 310. This approach can reduce the processing overhead of error correction engine 315-a, improve storage efficiency in system 300, or both. Although two error correction engines 315-b and two ECC schemes are shown for clarity, it should be understood that any number of error correction engines or ECC schemes can be used.

[0067] In some cases, the error correction engine 315 can identify that there are no errors in the data 340. For example, the data 340 may not contain any errors or the number of errors may exceed the detection capability of the error correction scheme (e.g., in the case of using the SECDED scheme, if the data 340 contains three or more errors, then the error correction engine 315 can identify that the data 340 is error-free). In such instances, the system 300 can transmit output data 345. In some other cases, the error correction engine 315 can identify the correctable number of one or more errors in the data 340 and can correct one or more errors to obtain the corresponding output data 345. For example, the error correction engine 315-b can identify a single error in the SEC or SECDED scheme and can correct the single error before outputting the output data 345, for example, to the host device requesting the data (e.g., flipping a bit from a first logic state to a correct second logic state, using the parity bit of the scheme associated with the error correction engine 315-b to identify the flipped bit).

[0068] In some instances, error correction engine 315 may send information 335 to error cache 305. For example, if error correction engine 315-a (e.g., using an ECC1 scheme) detects an error in a page of memory array 310, then error correction engine 315-a may indicate address 320 to error cache 305. Alternatively, system 300 may, for example, generate parity bits based on the detected error according to a different ECC scheme (e.g., the relatively more robust ECC2 scheme used for error correction engine 315-b). Error correction engine 315 may indicate at least a portion of the parity bits to error cache 305. As an illustrative example, if system 300 switches from a second ECC scheme (e.g., using parity bits stored in memory array 310) to a first ECC scheme (e.g., using parity bits stored in both memory array 310 and error cache 305), then error correction engine 315-b or error correction engine 315-a can generate parity bits and send a first portion (e.g., 9 bits) to error cache 305 via information 335, and send a second portion (e.g., 9 bits) to memory array 310, but any number of engines, bits, and portions can be used.

[0069] System 300 can maintain an error cache 305. For example, system 300 can employ a method of testing the cache for error locations and continuously updating (e.g., adding or removing) a list of "bad" locations (e.g., addresses containing defective memory cells), which can improve the efficiency of the error cache 305. Error correction engine 315 can determine one or more results of one or more error correction or detection procedures. Error correction engine 315 can send information 335 indicating one or more results. In an illustrative example, error correction engine 315-b can identify that there are no errors in data 340. If the error cache 305 contains an entry for address 320, then information 335 can instruct the removal of said entry based on the identification of no errors. Such removal can result in more efficient cache utilization and the removal of entries from the error cache 305 that may not be the result of fixed errors (e.g., an indication that a page with errors was previously stored based on the identification of a time-varying error), which reduces the probability of storing a relatively high number of parity bits for error-free data 340.

[0070] In some instances, system 300 may remove indications from error cache 305 based on one or more thresholds. For example, system 300 may increment a counter or otherwise track the number of times (e.g., consecutive counts) an error was not detected for address 320, which was indicated by error cache 305 to contain an error. If the number of undetected errors meets a threshold, system 300 may remove the entry in error cache 305 corresponding to address 320. By updating error cache 305 based on meeting thresholds, system 300 may remove entries in error cache that can be associated with time-varying errors, while avoiding removal of entries based on simultaneous error-free determinations (e.g., if a defective memory cell becomes trapped in a state corresponding to a logical value written to the memory cell).

[0071] In some instances, if error cache 305 already contains an entry for address 320, then information 335 may indicate that the error count associated with address 320 be incremented based on the identified error. Writing an indication that address 320 contains an error to error cache 305 (e.g., to determine whether a parity bit with a relatively more robust ECC scheme is generated for error correction engine 315-b) may satisfy a threshold based on the incrementing error count. By using error cache 305 to track the error count of memory cells and switching the ECC scheme from the relatively efficient ECC1 to the relatively robust ECC2 scheme based on the error count at the address, system 300 may reduce the probability of adding memory cells with time-varying errors to error cache 305 (e.g., the threshold may help ensure that error cache 305 contains memory cells with fixed defects, and so on).

[0072] Although two error correction engines 315 are shown for clarity, it should be understood that any number of ECC schemes or error correction engines 315 can be used. For example, if the error cache does not contain an entry for address 320, then error correction engine 315-a or no error correction engine 315 can be used. Alternatively, the error cache may contain one or more entries for address 320. For example, an entry may store an indication of address 320 and a set of parity bits associated with a different ECC scheme (e.g., ECC2). In some instances, error cache 305 may contain multiple entries for address 320 (e.g., multiple slots in a cache structure), each entry storing a set of parity bits. As illustrative examples, an address may correspond to two entries with two sets of bits stored in the error cache 305 and one set of bits stored in the memory array 310 (e.g., ECC3 scheme), or an address may correspond to three entries with three sets of bits stored in the error cache 305 and one set of bits stored in the memory array 310 (e.g., ECC4 scheme), and so on. Such parity schemes may each correspond to a corresponding error correction engine 315. Such adaptive parity schemes allow the system 300 to represent codewords of data multiple times in the error cache 305 for increasingly flexible coding levels. For example, the parity bits in each entry or the slots within an entry may be fragments of the full set of parity bits (e.g., a full parity "string") for a given coding scheme (e.g., ECC1, ECC2, ECC3, etc.).

[0073] System 300 may select error correction engine 315-a based on the number of hits at address 320 (e.g., the number of matches with address 320 in error cache 305). For example, if there are no hits, system 300 may use error correction engine 315-a (e.g., with or without a corresponding ECC scheme) to encode or decode the data; if there is a single hit, system 300 may use error correction engine 315-b (e.g., with a corresponding ECC scheme using relatively more parity bits than error correction engine 315-a) to encode or decode the data; if there are two hits, system 300 may use error correction engine 315-c (e.g., with a corresponding ECC scheme using relatively more parity bits than error correction engine 315-b) to encode or decode the data, and so on. This choice allows system 300 to implement different ECC schemes for different addresses of memory array 310, which can increase error protection for pages with relatively frequent errors and reduce processing overhead for relatively error-free pages, among other advantages.

[0074] Figure 4This describes an example of a process flow 400 supporting adaptive parity checking techniques for memory devices, as disclosed herein. Process flow 400 may be provided by, respectively, as referenced... Figures 1 to 3 Examples of operations performed by the described system 100, memory device 110, or system 300. Generally, Figure 4 The operations shown illustrate the procedures and operations of a memory device (or memory system) using an error cache and one or more ECC schemes to perform error correction procedures. However, it should be understood that there may be more or fewer operations than those shown. Alternatively or in addition, different procedures may be used. Figure 4 The order shown in the text can be added, removed, or the operation performed.

[0075] At 405, the memory device may receive a command. For example, the memory device may receive a read command from the host device. The command may indicate the address (e.g., a logical or physical address) of data to be read from the memory array within the memory device.

[0076] Memory devices can use addresses (e.g., received or obtained based on logical-to-physical mapping to obtain physical addresses) to access memory arrays and check (e.g., query) the memory device's error cache (e.g., reference cache). Figure 3 The memory array 310 and the error cache 305 are described. For example, if the command received at 405 is a read command, then at 410, the memory device can read data from the memory array based on the address indicated by the command. In some instances, the memory device can also read the parity bit associated with the data from the memory array (e.g., if the data is stored according to an ECC scheme that generates the parity bit and is stored in the memory array, as a supplement or replacement for the parity bit used for data stored in the error cache).

[0077] At 415, the memory device may determine whether the cache contains an entry for an address (e.g., the memory device may determine whether the cache contains an entry for the indicated address or an address mapped to the indicated address). For example, the memory device may query the error cache while reading data (e.g., in parallel) and use the parity bit to perform a first error checking procedure for the data. That is, a time period may be allocated for searching the error cache and providing information about any cache (e.g., submitting a query to the error cache and returning the result to the error correction engine) such that the cache information (e.g., the parity bit) is available to the error correction engine before an error correction procedure using the cache information is performed on the original data.

[0078] In some instances, the memory device can determine that an address is located in a cache (e.g., the row address of the data is in a table, and a lookup result returns a hit of the address). At 420, the memory device can use a first ECC scheme to detect or correct errors in the data based on the cache containing entries for the address. For example, the memory device can use a set of parity bits stored in an error cache, a second set of parity bits stored in the memory array, or any combination thereof (e.g., parity bits generated for the ECC2 scheme and partially or entirely stored in the error cache or memory array, as described herein) to check for errors in the data. This scheme can be relatively more robust, which improves the error correction and detection capabilities relative to addresses that are more likely to contain errors.

[0079] In some instances, the memory device may use a first ECC scheme to detect and / or correct errors and output data at 430. In other instances, the memory device may detect that there are no errors in the data and continue outputting data at 430. In some such instances, at 425, the memory device may remove an indication of an address from the cache based on the detection that there are no errors in the data. For example, the memory device may increment a count of the number of times an error cannot be found, and if the count meets a threshold, the memory device may remove the address and prevent the use of the first error scheme (e.g., the memory device may switch to a second ECC scheme and prevent the address or parity bit from being included in the error cache).

[0080] In some instances, the memory device can determine that an address is not found in the cache (e.g., the row address of the data may not be in the table, and the query result may return a miss for the address). At 435, the memory device can use a second ECC scheme (e.g., no ECC scheme or default ECC scheme) to detect or correct errors in the data based on the lack of an entry for the address in the cache. For example, the memory device can use a set of parity bits stored in the memory array (e.g., as referenced herein). Figure 3 The parity bits described for the ECC1 scheme are used to check for errors in the data. This scheme can be relatively efficient (e.g., the default scheme can use fewer parity bits and reduce processing overhead, reduce the storage usage of error caches or memory arrays or both, and other advantages).

[0081] In some instances, the memory device may detect no errors in the data and continue outputting data at 430. In other instances, the memory device may use a second ECC scheme to detect and / or correct errors and output data at 430. In some such instances, at 440, the memory device may write an address indication to a cache based on an error detected in a page (e.g., an address). For example, the memory device may increment a count of the number of errors detected, and if the count meets a threshold, the memory device may write an address indication to an error cache and switch from the second ECC scheme to the first ECC scheme. As an illustrative example, the memory device may generate a set of parity bits for the first ECC scheme (e.g., a larger number of parity bits compared to the number of parity bits for the second ECC scheme) and store at least a portion of the set of parity bits in an error cache, a portion of the set of parity bits in a memory array, or any combination thereof.

[0082] Although two ECC schemes are shown for clarity, it should be understood that any number of ECC schemes or error correction engines can be used. For example, an error cache may contain one or more entries for addresses. Each entry may store an indication of the address and a set of parity bits associated with the corresponding ECC scheme. In some instances, an error cache may contain multiple entries for addresses (e.g., multiple slots in a cache structure), each entry storing a set of parity bits. As an illustrative example, an address may correspond to two entries. A memory device may store the first set of bits in a memory array, and both the second and third sets of bits may be stored in an error cache (e.g., the first, second, and third sets of parity bits may be the full set of parity bits for an ECC3 scheme), an address may correspond to three entries and store three sets of bits in error cache 305, and store one set of bits in a memory array (e.g., an ECC4 scheme), and so on. Such parity schemes may each correspond to a corresponding error correction engine, as referenced in [reference missing]. Figure 3 As described. Such adaptive ECC schemes enable the system to represent codewords of data multiple times in an error cache for increasingly resilient coding levels. For example, the parity bit in each entry can be a portion of the full set of parity bits (e.g., a full parity "string") of a given coding scheme (e.g., ECC1, ECC2, ECC3, etc.).

[0083] Memory devices can select an error correction engine based on the number of address hits (e.g., the number of address matches found in the error cache). For example, if there are no hits, the memory device can use a first error correction engine (e.g., with or without an corresponding ECC scheme) to encode or decode the data; if a single hit occurs, the memory device can use a second error correction engine (e.g., with a corresponding ECC scheme using relatively more parity bits than the first error correction engine) to encode or decode the data, and so on. This selection allows the memory device to implement different ECC schemes for different addresses in the memory array, which can increase error protection for pages with relatively frequent errors and reduce processing overhead for relatively error-free pages, among other advantages.

[0084] Figure 5 This describes an example of a process flow 500 supporting adaptive parity checking techniques for memory devices, as disclosed herein. Process flow 500 may be derived from, respectively, as referenced... Figures 1 to 3 Examples of operations performed by the described system 100, memory device 110, or system 300. Generally, Figure 5 The operations shown illustrate the procedures and operations of a memory device (or memory system) using an error cache and one or more ECC schemes to perform error correction procedures. However, it should be understood that there may be more or fewer operations than those shown. Alternatively or in addition, different procedures may be used. Figure 5 The order shown in the text can be added, removed, or the operation performed.

[0085] At 505, the memory device may receive a command. For example, the memory device may receive a write command from the host device. The command may indicate the address (e.g., logical or physical address) of data to be written to the memory array within the memory device. The memory device may use the address (e.g., as received or based on a logical-to-physical mapping to obtain a physical address) to access the memory array and check (e.g., query) the memory device's error cache (e.g., as referenced). Figure 3 The memory array 310 and error cache 305 described herein.

[0086] For example, at 510, the memory device may determine whether the cache contains an entry for an address (e.g., the memory device may determine whether the cache contains an entry for the indicated address or an address mapped to the indicated address). For example, the memory device may query the error cache to see if one or more entries associated with the address are contained in the error cache.

[0087] In some instances, the memory device may determine that one or more entries for an address are located in a cache (e.g., the row address of the data may be in a table in an error cache, and the lookup result may return a hit of the address). At 515, the memory device may implement a first ECC scheme based on the presence of one or more entries for an address in the cache. For example, the memory device may generate a set of parity bits according to the ECC scheme (e.g., the memory device may generate 18 parity bits as part of an ECC2 scheme as described herein, and other instances of the number of bits and ECC schemes).

[0088] At address 520, the memory device may write data, parity bits, or both to the memory array or error cache. For example, the memory device may write data to the indicated address in the memory array. The memory device may also store a set of parity bits generated according to an ECC scheme. For example, the memory device may use the address indication to store a first portion of the generated bits (e.g., a first set of 9 bits) in the error cache, and the memory device may use data to store a second portion of the generated bits (e.g., a second set of 9 bits) in the memory array, or any combination thereof.

[0089] In some instances, the memory device may determine that one or more entries for an address are not found in the cache (e.g., the row address of the data may not be in the table, and the query result may return an address miss). At 520, the memory device may use a second ECC scheme (or no ECC scheme) based on the absence of one or more cache entries. For example, the memory device may prevent the generation of parity bits and continue writing data to the memory array at 520. As another example, the memory array may use a second ECC scheme (e.g., as referenced) Figure 3 The described default ECC scheme (e.g., ECC1) generates a set of parity bits. The memory device can continue up to 520 and write the data and the generated parity bits into the memory array (e.g., the memory device can generate 9 parity bits as part of the ECC1 scheme and use the data to write the parity bits into the memory array).

[0090] Although two ECC schemes are shown for clarity, it should be understood that any number of ECC schemes or error correction engines can be used. For example, an error cache may contain one or more entries for addresses. Each entry may store an indication of the address and a set of parity bits associated with the corresponding ECC scheme. In some instances, an error cache may contain multiple entries for addresses (e.g., multiple slots in a cache structure), each entry storing a set of parity bits. As an illustrative example, an address may correspond to two entries. A memory device may store the first set of bits in a memory array, and both the second and third sets of bits may be stored in an error cache (e.g., the first, second, and third sets of parity bits may be the full set of parity bits for an ECC3 scheme), an address may correspond to three entries and store three sets of bits in error cache 305, and store one set of bits in a memory array (e.g., an ECC4 scheme), and so on. Such parity schemes may each correspond to a corresponding error correction engine, as referenced in [reference missing]. Figure 3 As described. Such adaptive ECC schemes enable the system to represent codewords of data multiple times in an error cache for increasingly resilient coding levels. For example, the parity bit in each entry can be a portion of the full set of parity bits (e.g., a full parity "string") of a given coding scheme (e.g., ECC1, ECC2, ECC3, etc.).

[0091] Memory devices can select an error correction engine based on the number of address hits (e.g., the number of address matches found in the error cache). For example, if there are no hits, the memory device can use a first error correction engine (e.g., with or without an corresponding ECC scheme) to encode or decode the data; if a single hit occurs, the memory device can use a second error correction engine (e.g., with a corresponding ECC scheme using relatively more parity bits than the first error correction engine) to encode or decode the data, and so on. This selection allows the memory device to implement different ECC schemes for different addresses in the memory array, which can increase error protection for pages with relatively frequent errors and reduce processing overhead for relatively error-free pages, among other advantages.

[0092] Figure 6 A block diagram 600 illustrates a memory array 605 supporting adaptive parity checking techniques for memory devices, according to examples disclosed herein. The memory array 605 may be as described in the references... Figures 1 to 5Examples of aspects of the described memory array are provided. Memory array 605 may include command component 610, read component 615, cache component 620, error component 625, parity component 630, error circuit component 635, write component 640, output component 645, and scheme component 650. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0093] Command component 610 can receive a command to read data from the memory array, the command indicating an address associated with the data. Read component 615 can read data from the memory array in response to the command. Cache component 620 can determine an indication of a cache-contained address and a set of parity bits for the data based on the address. Error component 625 can use the set of parity bits to check for one or more errors in the data based on the determined cache-contained address and the set of parity bits.

[0094] In some instances, the set of parity bits included in the cache may be a second set of parity bits for the data. The parity component 630 may read a first set of parity bits from the memory array in response to a command, wherein checking for one or more errors in the data using the set of parity bits includes checking for one or more errors in the data using a combination of the first and second sets of parity bits. In some cases, the first set of parity bits supports the detection or correction of up to a first number of errors in the data. In some cases, the combination of the first and second sets of parity bits supports the detection or correction of up to a second number of errors in the data, the second number being greater than the first number.

[0095] Error circuit component 635 can input data, a first set of parity bits, and a second set of parity bits into a second error checking circuit coupled to the memory array and different from a first error checking circuit coupled to the memory array, wherein the second error checking circuit is configured to detect or correct up to a greater number of errors in the data than the number of errors in the first error checking circuit, and wherein checking one or more errors in the data is based on the input.

[0096] In some instances, command component 610 may receive a second command from the memory array to read second data, the command indicating a second address associated with the second data. In some instances, read component 615 may read the second data and a third set of parity bits from the memory array in response to the second command. In some instances, cache component 620 may determine, based on the second address, an indication that the cache does not contain the second address. In some instances, error component 625 may use the third set of parity bits to check for one or more errors in the second data based on an indication that the cache lacks the second address.

[0097] In some instances, error component 625 may identify errors in the second data based on a check using a third set of parity bits. In some instances, parity component 630 may generate a fourth set of parity bits for the second data based on the identification of errors in the second data. In some instances, write component 640 may write an indication of the second address and the fourth set of parity bits to the cache.

[0098] In some instances, error circuit component 635 may input second data and a third set of parity bits into a first error checking circuit coupled to the memory array and different from a second error checking circuit coupled to the memory array, wherein the second error checking circuit is configured to detect or correct up to a greater number of errors in the data than the number of errors in the first error checking circuit, and wherein checking one or more errors in the second data is based on the input.

[0099] In some instances, cache component 620 may obtain a third set of parity bits from the cache in response to a command, wherein checking for one or more errors in the data using said set of parity bits includes checking for one or more errors in the data using a combination of the first set of parity bits, the second set of parity bits, and the third set of parity bits.

[0100] In some instances, cache component 620 may determine an indication of a cache-contained address in response to the command. In some instances, error circuit component 635 may select an error checking circuit from a set of error checking circuits each coupled to the memory array based on the number of parity bits in the set, wherein one or more errors are checked in the data using the set of parity bits, and each set of parity bits of the data and the data contained in the cache is input to the selected error checking circuit.

[0101] In some instances, error component 625 may identify errors in the data based on checks. In some instances, error component 625 may use the set of parity bits to correct errors. Output component 645 may output corrected data via a memory device including a memory array in response to a command.

[0102] In some instances, error component 625 may determine that no error was detected based on a check. In some instances, cache component 620 may remove the address indication and the group parity bit from the cache based on the determination that no error was detected.

[0103] In some cases, a cache comprises a second memory array, a portion of a memory array, or a combination thereof. In some cases, a cache comprises a set of entries, each set of entries corresponding to a corresponding set of memory cells within the memory array, each corresponding set of memory cells containing at least one defective memory cell, and each entry in the set containing an indication of an address associated with the corresponding set of memory cells, a parity bit of data associated with the corresponding set of memory cells, or a combination thereof.

[0104] In some instances, command component 610 may receive a command to write data to a memory array, the command indicating an address associated with the data. Cache component 620 may determine an indication of a cache-contained address in response to the command. Parity component 630 may generate a set of parity bits for the data based on the determined cache-contained address indication. Write component 640 may write the data to the memory array and write the set of parity bits to the cache.

[0105] In some instances, the set of parity bits written to the cache may include a second set of parity bits for the data. In some instances, parity component 630 may generate a first set of parity bits for the data. In some instances, write component 640 may write the first set of parity bits to the memory array.

[0106] In some instances, command component 610 may receive a second command to write second data to the memory array, the second command indicating a second address associated with the second data. In some instances, cache component 620 may determine, in response to the second command, that the cache lacks an indication of a second address. In some instances, parity component 630 may generate a third set of parity bits based on the determination of an indication that the cache lacks a second address, the third set of parity bits containing the same number of parity bits as the first set of parity bits. In some instances, write component 640 may write the second data and the third set of parity bits to the memory array.

[0107] In some instances, command component 610 may receive a third command to read second data from the memory array, the third command indicating a second address. In some instances, error component 625 may identify an error in the second data based on a third set of parity bits in response to the third command. In some instances, parity component 630 may generate a fourth set of parity bits and a fifth set of parity bits based on the identification of one or more errors. In some instances, write component 640 may write the fourth set of parity bits to the memory array and write the fifth set of parity bits to the cache.

[0108] In some instances, cache component 620 may determine the number of indications of addresses contained in the cache in response to the command. In some instances, cache component 620 may determine the number of parity bits in the set of data contained in the cache based on the address and in response to the command. Scheme component 650 may select a parity scheme for the data from a set of parity schemes based on the number of indications of addresses contained in the cache, wherein the set of parity bits is generated based on the selected parity scheme.

[0109] Figure 7 The illustration shows a flowchart of one or more methods 700 supporting adaptive parity checking techniques for memory devices according to aspects of this disclosure. Operation of method 700 can be implemented by a memory device or its components as described herein. For example, operation of method 700 can be performed as described in reference... Figure 6 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0110] At 705, the memory device may receive a command to read data from the memory array, the command indicating an address associated with the data. Operation of 705 can be performed according to the methods described herein. In some instances, aspects of operation of 705 may be as described in references... Figure 6 The described command component is executed.

[0111] At 710, the memory device can read data from the memory array in response to a command. The operation of 710 can be performed according to the methods described herein. In some instances, aspects of the operation of 710 may be as described in the references... Figure 6 The described reading component is executed.

[0112] At address 715, the memory device can determine, based on the address, a cache-containing address indicator and a set of parity bits for the data. Operation of 715 can be performed according to the method described herein. In some instances, aspects of operation of 715 may be as described in the references... Figure 6 The described cache component is executed.

[0113] At 720, the memory device can use the set parity bit to check for one or more errors in the data based on an indication of a cache-included address and the set parity bit. Operation of 720 can be performed according to the methods described herein. In some instances, aspects of operation of 720 may be as referenced... Figure 6 The described error occurred during component execution.

[0114] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: receiving a command to read data from a memory array, the command indicating an address associated with the data; reading the data from the memory array in response to the command; determining, based on the address, an indication of a cache-contained address and a set of parity bits for the data; and using the set of parity bits to check for one or more errors in the data based on the determined cache-contained address and the set of parity bits.

[0115] In some instances of method 700 and the device described herein, the set of parity bits included in the cache may include operations, features, means, or instructions for reading data from the memory array in response to a command, wherein checking for one or more errors in the data using the set of parity bits includes checking for one or more errors in the data using a combination of the first set of parity bits and the second set of parity bits.

[0116] In some instances of method 700 and the device described herein, the first set of parity bits supports the detection or correction of up to a first number of errors in the data, and the combination of the first set of parity bits and the second set of parity bits supports the detection or correction of up to a second number of errors in the data, the second number being greater than the first number.

[0117] Method 700 and some examples of the devices described herein may further include operations, features, means, or instructions for inputting data, a first set of parity bits, and a second set of parity bits into a second error checking circuit coupled to the memory array and different from the first error checking circuit coupled to the memory array, wherein the second error checking circuit may be configured to detect or correct up to a greater number of errors in the data than the number of errors in the first error checking circuit, and wherein checking one or more errors in the data may be based on the input.

[0118] Method 700 and some examples of the devices described herein may further include operations, features, means, or instructions for performing: receiving a second command to read second data from a memory array, the command indicating a second address associated with the second data; reading the second data from the memory array and a third set of parity bits of the second data in response to the second command; determining, based on the second address, an indication that the cache does not contain the second address; and using the third set of parity bits to check for one or more errors in the second data based on the indication that the cache lacks the second address.

[0119] Method 700 and some instances of the device described herein may further include operations, features, means, or instructions for performing the following: identifying errors in the second data based on a check using a third set of parity bits; generating a fourth set of parity bits for the second data based on the identified errors; and writing an indication of the second address and the fourth set of parity bits to a cache.

[0120] Method 700 and some examples of the devices described herein may further include operations, features, means, or instructions for inputting second data and a third set of parity bits into a first error checking circuit coupled to and different from a second error checking circuit coupled to the memory array, wherein the second error checking circuit may be configured to detect or correct up to a greater number of errors in the data than the number of errors in the first error checking circuit, and wherein checking one or more errors in the second data may be based on the input.

[0121] Method 700 and some instances of the device described herein may further include operations, features, means, or instructions for obtaining data from a cache in response to a command, wherein checking for one or more errors in the data using said set of parity bits includes checking for one or more errors in the data using a combination of the first set of parity bits, the second set of parity bits, and the third set of parity bits.

[0122] Method 700 and some examples of the devices described herein may further include operations, features, means, or instructions for performing the following: determining, in response to a command and based on an address, the number of sets of parity bits contained in the cache; and selecting an error checking circuit from a respective set of error checking circuits coupled to the memory array based on the number of sets of parity bits, wherein checking for one or more errors in the data using the sets of parity bits includes inputting the data and each set of parity bits contained in the cache to the selected error checking circuit.

[0123] Method 700 and some examples of the devices described herein may further include operations, features, means, or instructions for performing the following: identifying errors in data based on an inspection; correcting errors using the set of parity bits; and outputting corrected data via a memory device including a memory array in response to a command.

[0124] Method 700 and some examples of the devices described herein may further include operations, features, means, or instructions for performing the following: determining, based on an inspection, that an error may not have been detected; and an instruction to remove an address from a cache and the group of parity bits based on the determination that no error was detected.

[0125] In some instances of method 700 and the devices described herein, the cache includes a second memory array, a portion of a memory array, or a combination thereof.

[0126] In some instances of method 700 and the device described herein, the cache includes a set of entries, each set of entries corresponding to a corresponding set of memory cells within a memory array, each corresponding set of memory cells containing at least one defective memory cell, and each entry in the set containing an indication of an address associated with the corresponding set of memory cells, a parity bit of data associated with the corresponding set of memory cells, or a combination thereof.

[0127] Figure 8 The illustration shows a flowchart of one or more methods 800 supporting adaptive parity checking techniques for memory devices according to aspects of this disclosure. Operation of method 800 can be implemented by a memory device or its components as described herein. For example, operation of method 800 can be performed as described in reference... Figure 6 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0128] At 805, the memory device may receive a command to write data to the memory array, the command indicating an address associated with the data. Operation of 805 can be performed according to the methods described herein. In some instances, aspects of operation of 805 may be as described in references... Figure 6 The described command component is executed.

[0129] At 810, the memory device can determine an indication of the cache contain address in response to a command. The operation of 810 can be performed according to the method described herein. In some instances, aspects of the operation of 810 may be as described in the references... Figure 6 The described cache component is executed.

[0130] At 815, the memory device can generate a set of parity bits for data based on an indication that the cache containment address is determined. Operation of 815 can be performed according to the method described herein. In some instances, aspects of operation of 815 can be derived from, as referenced... Figure 6 The parity check component described is executed.

[0131] At 820, the memory device can write data to the memory array and write the set of parity bits to the cache. The operation of 820 can be performed according to the method described herein. In some instances, aspects of the operation of 820 may be as described in the references... Figure 6The described write component is executed.

[0132] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, means, or instructions (e.g., storing processor-executable instructions on a non-transitory computer-readable medium) for performing the following operations: receiving a command to write data to a memory array, the command indicating an address associated with the data; determining an indication of a cache-contained address in response to the command; generating a set of parity bits for the data based on the indication of determining the cache-contained address; and writing the data to the memory array and writing the set of parity bits to the cache.

[0133] In some instances of method 800 and the devices described herein, writing the set of parity bits to a cache may include operations, features, means, or instructions for performing: generating a first set of parity bits for data; and writing the first set of parity bits to a memory array.

[0134] Method 800 and some examples of the devices described herein may further include operations, features, means, or instructions for performing: receiving a second command to write second data to a memory array, the second command indicating a second address associated with the second data; determining, in response to the second command, an indication that the cache lacks a second address; generating a third set of parity bits based on the indication that the cache lacks a second address, the third set of parity bits comprising the same number of parity bits as the first set of parity bits; and writing the second data and the third set of parity bits to the memory array.

[0135] Method 800 and some examples of the devices described herein may further include operations, features, means, or instructions for performing the following: receiving a third command to read second data from a memory array, the third command indicating a second address; in response to the third command identifying an error in the second data based on a third set of parity bits; generating a fourth set of parity bits and a fifth set of parity bits based on the identification of one or more errors; and writing the fourth set of parity bits to the memory array and the fifth set of parity bits to a cache.

[0136] Method 800 and some examples of the devices described herein may further include operations, features, means, or instructions for performing the following: determining, in response to the command, the number of indications of addresses contained in the cache; and selecting a parity scheme for data from a set of parity schemes based on the number of indications of addresses contained in the cache, wherein generating the set of parity bits may be based on the selection of the parity scheme.

[0137] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described can be combined.

[0138] An apparatus is described. The apparatus may include: a memory array; a cache configured to store a set of entries, each set of entries corresponding to a corresponding set of memory cells within the memory array, each entry in the set including an indication of an address associated with the corresponding set of memory cells, parity bits of data associated with the corresponding set of memory cells, or a combination thereof; and circuitry configured to cause the apparatus to: receive a command to read data from the memory array, the command indicating an address associated with the data; read the data from the memory array in response to the command; determine, based on the address, whether the cache contains an entry associated with the address and a set of parity bits of the data; and use the set of parity bits to check for one or more errors in the data when the cache contains an entry associated with the address and the set of parity bits.

[0139] In some instances, when the cache contains the set of parity bits, the set of parity bits may be a second set of parity bits for the data, and the circuitry may be further configured to cause the device to read a first set of parity bits for the data from the memory array in response to the command, and to use the first set of parity bits to check for one or more errors in the data when the cache does not contain an entry associated with the address and a second set of parity bits.

[0140] In some instances, in order to use the set of parity bits to check for one or more errors in the data when the cache contains an address indication and the set of parity bits, the control circuitry may be configured to cause the device to use a combination of a first set of parity bits and a second set of parity bits to check for one or more errors in the data.

[0141] Some examples of the device may include: a first error checking circuit coupled to a memory array and configured to detect or correct up to a first number of errors in the data; and a second error checking circuit coupled to the memory array and configured to detect or correct up to a second number of errors in the data, the second number being greater than the first number. The circuitry may be further configured such that the device selects the first error checking logic when the cache does not contain an address-associated entry and a second set of parity bits, selects the second error checking logic when the cache contains an address-associated entry and a second set of parity bits, and inputs data into one of the first or second error checking logics to check for one or more errors in the data.

[0142] In some instances, the control circuitry may be further configured to cause the device to respond to a third set of parity bits that generates data based on an error detection check, and to write the third set of parity bits of the data to a cache.

[0143] In some instances, the control circuitry may be further configured to cause the device to perform the following operations: receive a second command to write second data to a memory array, the command indicating a second address associated with the second data; determine, in response to the second command, that a cache contains an entry associated with the second address; generate a fifth set of parity bits and a sixth set of parity bits for the second data based on the determination that the cache contains an entry associated with the second address; and write the second data and the fifth set of parity bits to the memory array and the sixth set of parity bits to the cache.

[0144] In some instances, a cache may include a second memory array, a portion of a memory array, or a combination thereof.

[0145] While some examples in this article can be explained with reference to DRAM memory cells, it should be understood that the techniques and structures in this article can be applied to memory devices containing any type of memory cell.

[0146] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0147] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0148] The term "coupling" refers to the condition of moving from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0149] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between them using previously permitted conductive paths.

[0150] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0151] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be end-capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0152] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0153] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash followed by the reference numeral and a second label to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0154] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0155] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0156] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations. Furthermore, as used herein, the word "or" in the list of items included in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0157] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0158] This description is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications to this disclosure and can apply the general principles defined herein to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for error correction, comprising: Receive a command to read data from a memory array, the command indicating an address associated with the data; The data is read from the memory array in response to the command; The cache is determined, at least in part, based on an indication of whether the cache contains the address and a set parity bit of the data; and The set parity bit is used to check for one or more errors in the data, based at least in part on the indication of whether the cache contains the address and the set parity bit.

2. The method according to claim 1, wherein the set of parity bits in the cache includes a second set of parity bits for the data, the method further comprising: Reading a first set of parity bits from the memory array in response to the command, wherein checking for one or more errors in the data using the set of parity bits includes checking for one or more errors in the data using a combination of the first set of parity bits and the second set of parity bits.

3. The method according to claim 2, wherein: The first set of parity bits supports the detection or correction of up to a first number of errors in the data; and The combination of the first set of parity bits and the second set of parity bits supports the detection or correction of up to a second number of errors in the data, the second number being greater than the first number.

4. The method of claim 2, further comprising: The data, the first set of parity bits, and the second set of parity bits are input into a second error checking circuit coupled to the memory array and different from a first error checking circuit coupled to the memory array, wherein the second error checking circuit is configured to detect or correct up to a greater number of errors in the data than the number of errors in the first error checking circuit, and wherein checking one or more errors in the data is based at least in part on the input.

5. The method of claim 2, further comprising: Receive a second command to read second data from the memory array, the second command indicating a second address associated with the second data; In response to the second command, the second data and a third set of parity bits of the second data are read from the memory array; At least in part, based on the second address, determine that the cache does not contain an indication of the second address; and The third set of parity bits is used to check for one or more errors in the second data, at least in part, based on the determination that the cache lacks the indication of the second address.

6. The method of claim 5, further comprising: Errors in the second data are identified at least in part based on the check using the third set of parity bits; The fourth set of parity bits for the second data is generated at least in part based on the identification of the errors in the second data; and Write the indication of the second address and the fourth set of parity bits into the cache.

7. The method of claim 5, further comprising: The second data and the third set of parity bits are input into a first error checking circuit coupled to the memory array and different from a second error checking circuit coupled to the memory array, wherein the second error checking circuit is configured to detect or correct up to a greater number of errors in the data than the first error checking circuit, and wherein checking one or more errors in the second data is based at least in part on the input.

8. The method of claim 2, further comprising: Receiving a third set of parity bits from the cache in response to the command, wherein checking for one or more errors in the data using the set of parity bits includes checking for one or more errors in the data using a combination of the first set of parity bits, the second set of parity bits, and the third set of parity bits.

9. The method of claim 1, further comprising: In response to the command and at least in part based on the address, determine the set of parity bits for the data contained in the cache; and Error checking circuits are selected from a set of error checking circuits each coupled to the memory array, at least in part based on the number of parity bits in the set, wherein checking for one or more errors in the data using the set of parity bits includes inputting the data and each set of parity bits of the data contained in the cache to the selected error checking circuit.

10. The method of claim 1, further comprising: Errors in the data are identified, at least in part, based on the inspection. The error was corrected using the set of parity bits; and In response to the command, data containing corrected errors is output through a memory device containing the memory array.

11. The method of claim 1, further comprising: The determination that no error was detected is based at least in part on the aforementioned inspection; and The indication of the address and the group parity bit are removed from the cache at least in part based on the determination that no error was detected.

12. The method of claim 1, wherein the cache comprises a second memory array, a portion of the memory array, or a combination thereof.

13. The method of claim 1, wherein the cache comprises a plurality of entries, each of the plurality of entries corresponding to a corresponding set of memory cells within the memory array, each corresponding set of memory cells containing at least one defective memory cell, and each of the plurality of entries comprising an indication of an address associated with the corresponding set of memory cells, a parity bit of data associated with the corresponding set of memory cells, or a combination thereof.

14. A method for error correction, comprising: Receive a command to write data to a memory array, the command indicating an address associated with the data; In response to the command, determine whether the cache contains an indication of the address; The group parity bit of the data is generated at least in part based on the indication of whether the cache contains the address; and The data is written to the memory array and the set of parity bits is written to the cache.

15. The method of claim 14, wherein the set of parity bits written to the cache includes a second set of parity bits for the data, the method further comprising: The first set of parity bits for the data is generated; and Write the first set of parity bits into the memory array.

16. The method of claim 15, further comprising: Receive a second command to write second data to the memory array, the second command indicating a second address associated with the second data; In response to the second command, an indication is determined that the cache lacks the second address; A third set of parity bits is generated, at least in part, based on the indication that the cache lacks the second address. This third set of parity bits includes the same number of parity bits as the first set. The second data and the third set of parity bits are written into the memory array.

17. The method of claim 16, further comprising: Receive a third command to read the second data from the memory array, the third command indicating the second address; In response to the third command, errors in the second data are identified at least in part based on the third set of parity bits; The fourth and fifth parity bits are generated at least in part based on the identification of the errors in the second data; and The fourth set of parity bits is written to the memory array and the fifth set of parity bits is written to the cache.

18. The method of claim 14, further comprising: In response to the command, determine the number of indications of the addresses contained in the cache; and A parity check scheme for the data is selected from a set of parity check schemes based at least in part on the number of indications of the addresses contained in the cache, wherein the generation of the set of parity bits is based at least in part on the selection of the parity check scheme.

19. A memory device comprising: Memory array, A cache configured to store multiple entries, each corresponding to a specific set of memory cells within the memory array. Each entry includes an indication of an address associated with the specific set of memory cells, a parity bit or a combination thereof for data associated with the specific set of memory cells, and... Circuitry configured to enable the memory device to: Receive a command to read data from the memory array, the command indicating an address associated with the data; The data is read from the memory array in response to the command; The cache is determined, at least in part, based on the address, whether it contains an entry associated with the address and the group parity bit of the data; and The set parity bit is used to check for one or more errors in the data, based at least in part on whether the cache contains the entry associated with the address and the set parity bit.

20. The memory device of claim 19, wherein when the cache contains the set of parity bits, the set of parity bits includes a second set of parity bits for the data, and wherein the circuitry is further configured to cause the memory device to: In response to the command, the first set of parity bits of the data is read from the memory array; and When the cache does not contain the entry associated with the address and the second set of parity bits, the first set of parity bits is used to check for one or more errors in the data.

21. The memory device of claim 20, wherein, In order to use the set parity bit to check for one or more errors in the data when the cache contains the indication of the address and the set parity bit, the circuitry is configured to cause the memory device to: The combination of the first set of parity bits and the second set of parity bits is used to check for one or more errors in the data.

22. The memory device of claim 20, further comprising: A first error checking circuit is coupled to the memory array and configured to detect or correct up to a first number of errors in the data; and A second error checking circuit, coupled to the memory array and configured to detect or correct up to a second number of errors in the data, the second number being greater than the first number, wherein the circuit is further configured to cause the memory device to: The first error checking circuit is selected when the cache does not contain the entry associated with the address and the second set of parity bits; The second error checking circuit is selected when the cache contains the entry associated with the address and the second set of parity bits; and The data is input into one of the first error checking circuit or the second error checking circuit to check for one or more errors in the data.

23. The memory device of claim 19, wherein the circuitry is further configured to cause the memory device to: In response to identifying an error based at least in part on the check, a second set of parity bits for the data is generated; and Write the second set of parity bits of the data into the cache.

24. The memory device of claim 19, wherein the circuitry is further configured to cause the memory device to: Receive a second command to write second data to the memory array, the second command indicating a second address associated with the second data; In response to the second command, it is determined that the cache contains an entry associated with the second address; The second set of parity bits and the third set of parity bits for the second data are generated at least in part based on determining that the cache contains the entry associated with the second address; and The second data and the second set of parity bits are written to the memory array, and the third set of parity bits are written to the cache.

25. The memory device of claim 19, wherein the cache comprises a second memory array, a portion of the memory array, or a combination thereof.

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