Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method for forming the semiconductor structure includes the following steps. A semiconductor material structure is formed in a substrate. A first pad layer is formed on the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on the sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor structure. A second oxide structure is formed in the trench. The method for forming the semiconductor structure can release stress and inhibit problems caused by high stress, thereby avoiding problems of deviation. Thus, the performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of the electronics industry, integrated circuits (ICs) are moving towards high performance and miniaturization. During the deposition process, an oxide structure is typically formed around the active region, followed by an annealing process. However, stress increases during annealing and causes scattering of the active region pattern, leading to pattern shift issues.

[0003] Pattern scattering can be addressed by increasing the pattern size, but this method may negatively increase the size of the integrated circuit. Therefore, how to effectively solve pattern scattering is a pressing issue that needs to be addressed. Summary of the Invention

[0004] One object of the present invention is a method for forming a semiconductor structure that can relieve stress, thereby improving the performance of the semiconductor structure.

[0005] According to some embodiments of the present invention, a method for forming a semiconductor structure includes the following steps: forming a semiconductor material structure in a substrate; forming a first pad layer on the semiconductor material structure; etching the first pad layer and the semiconductor material structure to form a trench; performing an oxidation process on the sidewalls of the semiconductor material structure to form a first oxide structure on the sidewalls of the semiconductor structure; and forming a second oxide structure in the trench.

[0006] In some embodiments of the present invention, an oxidation process is performed such that one sidewall of the first pad is free of the first oxide structure.

[0007] In some embodiments of the present invention, the formation of a second oxide structure is performed such that the first oxide structure contacts the second oxide structure.

[0008] In some embodiments of the present invention, the method of forming a semiconductor structure further includes forming a second pad on the first pad before etching the first pad and the semiconductor material structure.

[0009] In some embodiments of the present invention, the method of forming a semiconductor structure further includes etching a second pad layer.

[0010] In some embodiments of the present invention, forming a second oxide structure in the trench further includes forming a second oxide structure on a second pad.

[0011] In some embodiments of the present invention, the method of forming a semiconductor structure further includes removing the second pad layer after forming the second oxide structure.

[0012] In some embodiments of the present invention, the oxidation process is performed via thermal oxidation.

[0013] In some embodiments of the present invention, the formation of the second oxide structure is performed by a flow chemical vapor deposition process.

[0014] Another object of the present invention is a semiconductor structure.

[0015] According to some embodiments of the present invention, a semiconductor structure includes a substrate, a semiconductor material structure, a pad layer, a first oxide structure, and a second oxide structure. The semiconductor material structure is located on the substrate. The pad layer is located on the semiconductor material structure. The first oxide structure is located on the sidewall of the semiconductor material structure. The second oxide structure is located on both the sidewall of the first oxide structure and the sidewall of the pad layer.

[0016] In some embodiments of the present invention, the second oxide structure contacts the sidewall of the first oxide structure and the sidewall of the padding layer.

[0017] In some embodiments of the present invention, the second oxide structure and the semiconductor material structure are separated by the first oxide structure.

[0018] In some embodiments of the present invention, the top surface of the second oxide structure and the top surface of the pad layer are located at the same horizontal position.

[0019] In some embodiments of the present invention, the first oxide structure and the second oxide structure are made of the same material.

[0020] According to the above embodiments of the present invention, since an oxidation process is performed on the sidewalls of the semiconductor material structure to form a first oxide structure, a stress-relieving effect can be achieved, and problems caused by high stress can be suppressed, thereby avoiding shift problems. In this way, the performance of the semiconductor structure can be improved.

[0021] It should be understood that the foregoing general description and the following detailed description are merely examples and are intended to provide further explanation of the invention. Attached Figure Description

[0022] Various aspects of the present invention can be understood from the following detailed description of the embodiments and the accompanying drawings.

[0023] Figures 1 to 9 A cross-sectional view illustrating a method for forming a semiconductor structure at various stages according to some embodiments of the present invention is shown.

[0024] Figure 10 Draw Figure 9 A top view of the semiconductor structure.

[0025] Explanation of key figure labels:

[0026] 110 - Substrate, 120 - Semiconductor material structure, 122 - Sidewall, 130 - First pad, 132 - Sidewall, 134 - Top surface, 140 - Second pad, 142 - Sidewall, 144 - Top surface, 150 - Patterned photoresist layer, 160 - First oxide structure, 162 - Sidewall, 170 - Second oxide structure, 174 - Top surface, 9 - Line, T - Trench. Detailed Implementation

[0027] Several embodiments of the present invention will be disclosed below with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the present invention, these practical details are not essential and therefore should not be used to limit the invention. Furthermore, for the sake of simplicity in the drawings, some well-known and conventional structures and elements will be shown in a simple schematic manner. In addition, for the reader's convenience, the dimensions of the elements in the drawings are not drawn to scale.

[0028] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another, as illustrated in the figures. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in one figure is flipped, an element described as being “down” to other elements will be oriented “up” to other elements. Thus, the exemplary term “down” can include both “down” and “up” orientations, depending on the specific orientation of the figure. Similarly, if a device in one figure is flipped, an element described as being “below” or “under” other elements will be oriented “above” other elements. Thus, the exemplary term “below” or “under” can include both “up” and “down” orientations.

[0029] In this document, “approximately,” “about,” “roughly,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. Unless explicitly stated otherwise, the given value or range may be inferred to be “approximately,” “about,” “roughly,” or “substantially.”

[0030] Figures 1 to 9 Cross-sectional views illustrating methods for forming a semiconductor structure at various stages according to some embodiments of the present invention are shown. It should be understood that the semiconductor structure may include an array area and a peripheral area adjacent to the array area. For clarity, the present invention... Figures 1 to 9 The array region of the semiconductor structure is shown in the middle, while Figures 1 to 9 The peripheral region of the semiconductor structure is not shown in the diagram, so it will be explained in advance.

[0031] See Figure 1 and Figure 2 A semiconductor material structure 120 is formed on the substrate 110. In some embodiments, the substrate 110 and / or the semiconductor material structure 120 may include semiconductor elements, such as germanium or silicon; semiconductor compounds, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), and any combination thereof. Furthermore, the substrate 110 may be a p-type substrate, such as silicon material doped with a p-type dopant (e.g., boron).

[0032] In some embodiments, the thickness of the substrate 110 is greater than the thickness of the semiconductor material structure 120. In some embodiments, the substrate 110 and the semiconductor material structure 120 are integrally formed.

[0033] Subsequently, a first pad layer 130 may be formed on the semiconductor material structure 120, and a second pad layer 140 may then be formed on the first pad layer 130. In some embodiments, the first pad layer 130 may be deposited on the semiconductor material structure 120 using suitable techniques, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, and / or combinations thereof, or other suitable techniques. The first pad layer 130 may be a thin pad oxide layer, and the first pad layer 130 may be made of silicon oxide or other suitable materials. In some embodiments, the second pad layer 140 may be deposited on the first pad layer 130 using suitable techniques, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or combinations thereof, or other suitable techniques. The thickness of the second pad layer 140 may be greater than the thickness of the first pad layer 130. The second pad layer 140 may be made of silicon nitride or other suitable materials. In some embodiments, the second pad layer 140 and the first pad layer 130 may be made of different materials. For example, the first pad 130 is made of silicon oxide, while the second pad 140 is made of silicon nitride.

[0034] See Figure 3After forming the second pad 140 on the first pad 130, a patterned photoresist layer 150 is formed on the second pad 140. Specifically, the method for forming the patterned photoresist layer 150 may involve first forming a photoresist layer on the second pad 140, and then patterning the aforementioned photoresist layer using a suitable development technique. For example, after spin-on coating the photoresist layer onto the second pad 140, the photoresist layer is exposed to a pattern of light radiation. In some embodiments, the patterned photoresist layer 150 covers a portion of the second pad 140, and the remaining portion of the second pad 140 is exposed.

[0035] See Figure 4 The second pad layer 140 is etched using a patterned photoresist layer 150 as an etching mask to form the first trench. The second pad layer 140 is etched until the underlying first pad layer 130 is exposed. For example, an anisotropic etching process, such as reactive ion etching (RIE), can be used, and chlorine (Cl2), hydrogen bromide (HBr), or carbon tetrafluoride (CF4) can be used as the etchant for the second pad layer 140.

[0036] After etching the second pad layer 140, the first pad layer 130 is etched using a patterned photoresist layer 150 as an etching mask to form a second trench, wherein the second trench connects to the aforementioned first trench. The first pad layer 130 is etched until the underlying semiconductor material structure 120 is exposed. Then, the semiconductor material structure 120 is etched using the patterned photoresist layer 150 as an etching mask to form a third trench, wherein the third trench connects to the aforementioned second trench. The semiconductor material structure 120 is etched until the underlying substrate 110 is exposed. Thus, a... Figure 4 The trench T includes the aforementioned first trench, the aforementioned second trench, and the aforementioned third trench. In some embodiments, different etchants may be used for etching the second pad 140, etching the first pad 130, and etching the semiconductor material structure 120, while using the patterned photoresist layer 150 as the same etching mask.

[0037] In some implementations, the semiconductor material structure 120 can be considered as an active area in the array region.

[0038] See Figure 4 and Figure 5 Remove the patterned photoresist layer 150. In some embodiments, the patterned photoresist layer 150 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes.

[0039] See Figure 6An oxidation process is performed on the sidewall 122 of the semiconductor material structure 120 to form a first oxide structure 160 on the sidewall 122 of the semiconductor material structure 120. Specifically, the first oxide structure 160 is formed by performing a thermal oxidation process, for example, by performing an in-situ stream generation (ISSG) oxidation process. The first oxide structure 160 may be referred to as an oxide liner layer on the sidewall 122 of the semiconductor material structure 120.

[0040] In some embodiments, the first oxide structure 160 may be made of a combination of silicon and oxygen, wherein the silicon content in the first oxide structure 160 ranges from about 45% to about 50%, and the oxygen content in the first oxide structure 160 ranges from about 50% to about 55%. For example, the silicon content in the first oxide structure 160 is about 47%, and the oxygen content in the first oxide structure 160 is about 53%. In some embodiments, the silicon content in the first oxide structure 160 is substantially equal to the oxygen content in the first oxide structure 160.

[0041] In some embodiments, an oxidation process is performed such that the sidewalls 132 of the first pad 130 have no (do not have) the first oxide structure 160. Furthermore, an oxidation process is performed such that the sidewalls 142 of the second pad 140 have no (do not have) the first oxide structure 160. In other words, the oxidation process on the first pad 130 and the second pad 140 can be ignored, therefore the first oxide structure 160 will not form on the sidewalls 132 of the first pad 130 and the sidewalls 142 of the second pad 140.

[0042] See Figure 6 and Figure 7After forming a first oxide structure 160 on the sidewall 122 of the semiconductor material structure 120, a second oxide structure 170 is formed in the trench T. Specifically, the second oxide structure 170 is formed on the sidewall 162 of the first oxide structure 160, the sidewall 132 of the first pad layer 130, and the sidewall 142 of the second pad layer 140. Furthermore, the second oxide structure 170 is formed on the second pad layer 140 and covers the second pad layer 140. Further, the vertical projection of the second oxide structure 170 onto the substrate 110 overlaps with the vertical projection of the second pad layer 140 onto the substrate 110. In some embodiments, the second oxide structure 170 can be formed in the trench T and on the second pad layer 140 by a deposition process, followed by an annealing process. By configuring the first oxide structure 160, stress in the semiconductor material structure 120 (active region) in the array region can be relieved, and high stress problems that may occur during the annealing process can be effectively suppressed, thereby avoiding shift problems. Therefore, two adjacent semiconductor material structures 120 (active regions) in the array region can be arranged to align with each other, and the performance of the semiconductor structure can be improved.

[0043] In some embodiments, the second oxide structure 170 can be formed by performing chemical vapor deposition (CVD). For example, the second oxide structure 170 can be formed by performing flowable chemical vapor deposition (FCVD).

[0044] In some embodiments, the formation of a second oxide structure 170 is performed such that the second oxide structure 170 contacts the first oxide structure 160. Specifically, the second oxide structure 170 contacts the sidewall 162 of the first oxide structure 160, the sidewall 132 of the first pad 130, and the sidewall 142 of the second pad 140.

[0045] In some embodiments, the first oxide structure 160 and the second oxide structure 170 are made of different materials. The second oxide structure 170 is separated from the semiconductor material structure 120 by the first oxide structure 160. That is, the second oxide structure 170 does not contact the semiconductor material structure 120. In some other embodiments, the second oxide structure 170 and the first oxide structure 160 are made of the same material, such as silicon dioxide (SiO2).

[0046] See Figure 8After the second oxide structure 170 is formed, a planarization process, such as a chemical mechanical polishing (CMP) process, can be performed to remove the upper part of the second oxide structure 170. In this way, the top surface 174 of the second oxide structure 170 and the top surface 144 of the second pad layer 140 are substantially at the same horizontal position. That is, the top surface 174 of the second oxide structure 170 and the top surface 144 of the second pad layer 140 are substantially flush.

[0047] See Figure 9 and Figure 10 , Figure 10 yes Figure 9 A top view of the semiconductor structure. In other words, Figure 9 It is along Figure 10 Line 9-9 shows a cross-sectional view of the semiconductor structure. For clarity, Figure 9 The first pad 130 is not shown. Figure 10 In the planarization process, the second pad 140 and a portion of the second oxide structure 170 adjacent to the second pad 140 are removed, exposing the first pad 130. In some embodiments, the top surface 174 of the second oxide structure 170 is substantially at the same horizontal level as the top surface 134 of the first pad 130. That is, the top surface 174 of the second oxide structure 170 is substantially flush with the top surface 134 of the first pad 130.

[0048] In some embodiments, bit line contacts can be formed on the central portion of the semiconductor material structure 120 (active region), and cell contacts can be formed on the edge portions of the semiconductor material structure 120 (active region). Based on the above process, the misalignment problem can be solved, thus allowing for precise arrangement of bit line contacts and cell contacts on the semiconductor material structure 120 (active region), and avoiding short circuit problems.

[0049] While the embodiments of the present invention have been disclosed in detail above, other embodiments are possible and are not intended to limit the present invention. Therefore, the spirit and scope of the foregoing claims should not be limited to the description of the embodiments of the present invention.

[0050] Any person skilled in the art may make various changes or substitutions without departing from the spirit and scope of the present invention, and all such changes or substitutions should be covered within the protection scope of the claims of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, Include: Forming a semiconductor material structure on a substrate; A first pad layer is formed on the semiconductor material structure; The first pad layer and the semiconductor material structure are etched to form a trench; An oxidation process is performed on the sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure; A second oxide structure is formed in the trench; After the second oxide structure is formed, an annealing process is performed; A planarization process is performed to remove a portion of the second oxide structure, wherein the annealing process is performed between the formation of the second oxide structure and the performance of the planarization process; as well as Bit line contacts are formed above the central portion of the semiconductor material structure, and unit contacts are formed above the edge portion of the semiconductor material structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The oxidation process is performed such that the sidewalls of the first pad layer are free of the first oxide structure.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The formation of the second oxide structure is performed such that the first oxide structure contacts the second oxide structure.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: Before etching the first pad layer and the semiconductor material structure, a second pad layer is formed on the first pad layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, Also includes: The second pad layer is etched.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, Forming the second oxide structure in the trench also includes forming the second oxide structure on the second pad layer.

7. The method for forming a semiconductor structure as described in claim 4, characterized in that, Also includes: After the second oxide structure is formed, the second pad layer is removed.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The oxidation process is performed via thermal oxidation.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The formation of the second oxide structure is performed via a flow chemical vapor deposition process.

10. A semiconductor structure, characterized in that, Include: substrate; A semiconductor material structure is located on the substrate; A pad layer is located on the semiconductor material structure; A first oxide structure is located on the sidewall of the semiconductor material structure, wherein the first oxide structure comprises silicon and oxygen, the ratio of silicon in the first oxide structure is in the range of 45% to 50%, and the ratio of oxygen in the first oxide structure is in the range of 50% to 55%. The second oxide structure is located on the sidewall of the first oxide structure and the sidewall of the pad layer; Bit line contacts are located above the central portion of the semiconductor material structure; as well as The unit contact is located above the edge portion of the semiconductor material structure.

11. The semiconductor structure as claimed in claim 10, characterized in that, The second oxide structure contacts the sidewall of the first oxide structure and the sidewall of the pad.

12. The semiconductor structure as claimed in claim 10, characterized in that, The second oxide structure is separated from the semiconductor material structure by the first oxide structure.

13. The semiconductor structure as described in claim 10, characterized in that, The top surface of the second oxide structure is at the same horizontal position as the top surface of the pad layer.

14. The semiconductor structure as claimed in claim 10, characterized in that, The first oxide structure and the second oxide structure are made of the same material.

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