Method for manufacturing a semiconductor element

Abstract

This disclosure provides a method for fabricating a semiconductor device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersecting a portion of the active region, wherein the portion is an end away from the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure and is covered by the second insulating layer; forming an opening penetrating the first insulating layer and the second insulating layer and exposing a portion of the active region, wherein the opening is laterally spaced from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. formal application No. 16 / 989,238, filed August 10, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for fabricating a semiconductor device. More particularly, it relates to a method for fabricating a semiconductor device having a one-time-programmable memory element. Background Technology

[0003] Non-volatile memory elements retain data even when power is off. Based on the programming time, non-volatile memory elements can be further divided into multi-time-programmable (MTP) memory elements and one-time-programmable (OTP) memory elements. Users can program MTP memory elements multiple times to modify the data stored in them. On the other hand, OTP memory elements can only be programmed once, and the data stored in OTP memory elements cannot be modified.

[0004] Furthermore, OTP memory devices can be categorized into fuse-type and antifuse-type devices. Fuse-type OTP memory devices are short-circuited before programming and open-circuited after programming. Conversely, antifuse-type OTP memory devices are open-circuited before programming and short-circuited after programming. Compared to fuse-type OTP memory devices, antifuse-type OTP memory devices have higher compatibility with complementary metal-oxide-semiconductor (CMOS) processes. However, precisely controlling the programming voltage of antifuse-type OTP memory devices while shrinking their size remains a challenge.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] This disclosure provides a method for fabricating a memory element. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersecting a portion of the active region, wherein the portion is an end away from the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure and is covered by the second insulating layer; forming an opening penetrating the first insulating layer and the second insulating layer and exposing a portion of the active region, wherein the opening is laterally spaced from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

[0007] In some embodiments, the preparation method further includes: forming an isolation structure in the substrate before the formation of the active region, wherein the active region is laterally surrounded by the isolation structure.

[0008] In some embodiments, after the gate structure is formed, a gate spacer is formed to cover one sidewall of the gate structure.

[0009] In some embodiments, a doped region is formed in the active region. This doped region is formed after the gate spacer is formed and before the first insulating layer and the second insulating layer are formed, and is formed by the gate structure and the gate spacer as a mask.

[0010] In some embodiments, the opening overlaps with one of the doped regions.

[0011] In some embodiments, the gate structure is ring-shaped.

[0012] In some embodiments, one of the ends of the active region overlaps with a region laterally surrounded by the gate structure.

[0013] In some embodiments, the gate structure is closer to a first end of the active region than to a second end of the active region, and the antifuse storage unit is closer to the second end of the active region than to the first end of the active region.

[0014] In some embodiments, the preparation method further includes: forming an isolation structure in the substrate and laterally surrounding the active region.

[0015] In some embodiments, the gate structure overlaps with the isolation structure and a portion of the active region.

[0016] In some embodiments, the fabrication method further includes forming a gate dielectric layer between the gate structure and the portion of the active region.

[0017] In some embodiments, the thickness of a gate dielectric layer is different from the thickness of a dielectric layer of the antifuse memory cell.

[0018] In some embodiments, the preparation method further includes: forming a gate spacer that covers a sidewall of the gate structure.

[0019] In some embodiments, the fabrication method further includes forming a contact plug on the gate structure and electrically connecting it to the gate structure.

[0020] In some embodiments, the contact plug is separated from the active area.

[0021] In some embodiments, a top surface of the contact plug is substantially coplanar with a top surface of the electrode of the antifuse storage cell.

[0022] In summary, the memory element of this disclosure embodiment includes a memory cell in an antifuse OTP memory array, and includes an access transistor and an antifuse memory cell connected to one of the source and drain terminals of the transistor. The access transistor includes an active region formed in a substrate and a gate structure formed on the substrate. The active region has a linear top-view shape, and the gate structure has a linear portion intersecting a portion of the active region. This portion of the active region is located away from two ends of the active region, which are particularly susceptible to photolithography and / or etching errors. Therefore, the overlap area between the gate structure and the active region can be better controlled, thereby reducing the impact of incorrect memory element fabrication on the gate coupling region and threshold voltage of the access transistor.

[0023] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0024] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0025] Figure 1A A schematic plan view of a memory element illustrating some embodiments of the present disclosure is shown.

[0026] Figure 1B For along Figure 1A A cross-sectional view of line A-A' in the middle.

[0027] Figure 2 Example Figure 1A and Figure 1B A schematic diagram of the fabrication process of the memory element.

[0028] Figures 3A to 3O Example Figure 2 The diagram shows cross-sectional views of the manufacturing process at different stages.

[0029] Figure 4 A cross-sectional schematic diagram illustrating some embodiments of the present disclosure of memory elements is shown.

[0030] Figure 5 A schematic plan view of a memory element illustrating some embodiments of the present disclosure is shown.

[0031] The reference numerals in the attached figures are explained as follows:

[0032] 10: Memory elements

[0033] 100: Base

[0034] 102: Isolation Structure

[0035] 102: Isolation Structure

[0036] 104: Passage Area

[0037] 106: Gate dielectric layer

[0038] 108: Gate structure

[0039] 108: Gate structure

[0040] 110: Doped region

[0041] 110: Doped region

[0042] 112: Doped region

[0043] 112: Doped region

[0044] 114: Contact plug

[0045] 116: Dielectric layer

[0046] 118: Electrode

[0047] 118: Electrode

[0048] 120: Insulation layer

[0049] 122: Insulation layer

[0050] 106': Dielectric material layer

[0051] GE': Gate electrode layer

[0052] AA: Linear active region

[0053] AA': Line

[0054] AF: Antifuse memory cell

[0055] CL: Contact layer

[0056] CL': Contact material layer

[0057] CM: Conductive material

[0058] E: End

[0059] E1: End

[0060] E2: End

[0061] GE: Gate electrode

[0062] GS: Gate spacer

[0063] GS: Gate spacer

[0064] GS: Gate spacer

[0065] GS': Spacer layer

[0066] RS: Groove

[0067] S11: Steps

[0068] S13: Steps

[0069] S15: Steps

[0070] S17: Steps

[0071] S19: Steps

[0072] S21: Steps

[0073] S23: Steps

[0074] S25: Steps

[0075] S27: Steps

[0076] S29: Steps

[0077] S31: Steps

[0078] S33: Steps

[0079] S35: Steps

[0080] S37: Steps

[0081] S39: Steps

[0082] S41: Steps

[0083] T: Access transistor

[0084] W1: Opening Detailed Implementation

[0085] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0086] The terms "an embodiment," "an embodiment," "an illustrative embodiment," "an other embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0087] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0088] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the apparatus. Furthermore, the description of a first feature being formed "on" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0089] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0090] Figure 1A A schematic plan view of a memory element 10 illustrating some embodiments of the present disclosure is shown. Figure 1B Example edge Figure 1A A cross-sectional view of line A-A'. (Reference) Figure 1A and Figure 1B In some embodiments, memory element 10 is a memory cell in an antifuse OTP memory array. In this embodiment, memory element 10 includes an access transistor T and an antifuse memory cell AF. The antifuse memory cell AF is electrically connected to the source and / or drain terminals of the access transistor T. When memory element 10 is selected for programming, the access transistor T is turned on, and the bias voltage across the antifuse is high, causing dielectric breakdown of the antifuse memory cell AF. Therefore, a permanent conductive path is formed on the antifuse memory cell AF, and the resistance of the antifuse memory cell AF is significantly reduced. On the other hand, if memory element 10 is not selected during a programming operation, memory element 10 remains in a high-resistance state. During a read operation, the access transistor T is also turned on, and the current flowing through the access transistor T and the antifuse memory cell AF is detected by a sensing amplifier (not shown) connected to the antifuse OTP memory array. If memory element 10 is selected for programming, a low-resistance state of the antifuse memory cell AF can be detected. Conversely, if memory element 10 is not selected for programming, a high-resistance state of the antifuse memory cell AF can be identified.

[0091] An active region AA is defined in the substrate 100 for the access transistor T. The active region AA is a well region containing the source region, drain region, and channel region of the access transistor T, and one of the source and drain regions (e.g., doped regions 110, 112, described later) also serves as a terminal of the antifuse memory cell AF. The substrate 100 may be a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. For example, the semiconductor material of the semiconductor wafer or SOI wafer may include: an elemental semiconductor (e.g., Si, Ge), a compound semiconductor (e.g., III-V compound semiconductor, SiC), a semiconductor alloy (e.g., SiGe or III-V semiconductor alloy), or a combination thereof. In some embodiments, the substrate 100 is doped with a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type, or vice versa.

[0092] The active region AA can be defined in the substrate 100 via an isolation structure 102. More specifically, the active region AA can be laterally surrounded by the isolation structure 102. In some embodiments, the isolation structure 102 is a trench isolation structure (e.g., Figure 1B (As shown). In this embodiment, the isolation structure 102 extends from a top surface of the substrate 100 to a depth within the substrate 100. This depth of the isolation structure 102 may be greater than an active region depth of the active region AA. Alternatively, the depth of the isolation structure 102 may be less than or equal to the active region depth of the active region AA. The isolation structure 102 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0093] The access transistor T may include a channel region 104, a gate dielectric layer 106, a gate structure 108, and doped regions 110 and 112. The gate structure 108 serves as the gate terminal of the access transistor T, and the doped regions 110 and 112 serve as the source and drain terminals of the access transistor T, respectively. Furthermore, the channel region 104 and the doped regions 110 and 112 are each formed in a shallow portion of a surface of the active region AA. The channel region 104 and the doped regions 110 and 112 extend from the top surface of the substrate 100 into the substrate 100, with a depth less than the depth of the active region AA, and the channel region 104 is located between the doped regions 110 and 112. Moreover, the channel region 104 overlaps with the gate dielectric layer 106 and the gate structure 108, and the gate dielectric layer 106 is disposed between the channel region 104 and the gate structure 108. In some embodiments, the conductivity type of the channel region 104 is complementary to the conductivity type of the doped regions 110 and 112. For example, if the access transistor T is an N-type transistor, the conductivity type of channel region 104 can be P-type, while the conductivity type of doped regions 110 and 112 can be N-type. Alternatively, if the access transistor T is a P-type transistor, the conductivity type of channel region 104 can be N-type, while the conductivity type of doped regions 110 and 112 can be P-type. Furthermore, except that the doping concentration of active region AA can be lower than that of channel region 104, the conductivity type of active region AA can be the same as that of channel region 104. In some embodiments, the material of gate dielectric layer 106 may include silicon oxide or a high-k dielectric material (e.g., a dielectric material with a dielectric constant greater than 4).

[0094] In some embodiments, the gate structure 108 includes a gate electrode GE and at least one contact layer CL disposed on the gate electrode GE. For example, as Figure 1B As shown, two contact layers CL are stacked on the gate electrode GE. The gate electrode GE and the contact layers CL are each formed of a conductive material. In some embodiments, the conductive materials forming the gate electrode GE and the contact layers CL are different from each other. For example, the gate electrode GE may be made of polysilicon, the upper layer of the contact layers CL may be made of titanium nitride, and the upper layer of the contact layers CL may be made of tungsten. Furthermore, the gate electrode GE may have a greater thickness than the contact layers CL. Additionally, the thicknesses of the contact layers CL may be different from each other. For example, the thickness of the lower layer of the contact layers CL may be less than the thickness of the upper layer of the contact layers CL. Furthermore, in some embodiments, the access transistor T also includes a gate spacer GS. The gate spacer GS covers the sidewalls of the gate dielectric layer 106 and the gate structure 108, and may be made of an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, similar materials, or combinations thereof). In embodiments where the gate structure 108 includes a contact layer CL disposed on the gate electrode GE, a top surface of the contact layer CL may be slightly lower than a top end of the gate spacer GS. Although in Figure 1A and Figure 1BThe gate separator GS is a single layer; alternatively, the gate spacer GS may comprise multiple layers made of the same or different insulating materials.

[0095] like Figure 1A As shown, the active region AA has a linear top-view shape, and the gate structure 108 forms a ring. A portion of the active region AA intersects with and is covered by a linear portion of the gate structure 108. This portion of the active region AA (i.e., the overlapping portion) is an end E away from the active region AA. In some embodiments, one of the ends E of the active region AA (labeled as end E1) overlaps with the region surrounded by the ring gate structure 108, while the other end E of the active region AA (labeled as end E2) is away from the gate structure 108. The channel region 104 is located in the portion where the active region AA overlaps with the gate structure 108, therefore in Figure 1A Not shown in the diagram. On the other hand, doped regions 110 and 112 extend from the overlapping portion to the ends E1 and E2 of the active region AA. In other words, doped regions 110 and 112 may not be covered by the gate structure 108. In some embodiments, the portion of the active region AA that overlaps with the gate structure 108 is closer to end E1 of the active region AA, rather than closer to the other end E2 of the active region AA. In this embodiment, one of the doped regions 110 and 112 is larger than the other. For example, as... Figure 1A As shown, the portion of the active region AA that overlaps with the gate structure 108 is closer to the end E1 where the active region AA and the gate structure 108 overlap, rather than closer to the end E2 of the active region AA that is farther from the gate structure 108. Therefore, the doped region 112 extending to the end E2 of the active region AA that is farther from the gate structure 108 is larger than the doped region 110 extending to the end E1 of the active region AA. Furthermore, in some embodiments, the gate dielectric layer 106 is selectively formed between the gate structure 108 and the active region AA (e.g., Figure 1B (As shown). In these embodiments, a portion of the gate structure 108 is spaced apart from the active region AA by the gate dielectric layer 106, while the remainder of the gate structure 108 contacts the isolation structure 102 without a gate dielectric layer in between.

[0096] Also refer to Figure 1A In some embodiments, the gate structure 108 is formed as an approximately rectangular ring, which can be divided into four segments. The first segment of the gate structure 108 (e.g., as shown in the figure) Figure 1A The right-side segment of the gate structure 108 shown intersects with the active region AA. The second segment of the gate structure 108 (e.g., as shown) Figure 1A The left segment of the gate structure 108 shown is substantially parallel to the first segment of the gate structure 108. The third and fourth segments of the gate structure 108 (e.g., as shown) Figure 1AThe upper and lower line segments of the gate structure 108 shown are substantially perpendicular to the first and second line segments of the gate structure 108 and extend between the first and second line segments of the gate structure 108. In some embodiments, the width of the second line segment of the gate structure 108 is much greater than the width of the first, third, and fourth line segments of the gate structure 108. In these embodiments, the region surrounded by the gate structure 108 is offset from the center of the gate structure. For example, such a region is offset from the center of the gate structure 108 to the right side of the gate structure 108 (e.g., Figure 1A (As shown).

[0097] Furthermore, a contact plug 114 may be disposed on the gate structure 108. In embodiments where the gate structure 108 includes a gate electrode GE and a contact layer CL, the contact plug 114 stands on the contact layer CL. Additionally, in embodiments where the gate structure 108 forms an approximately rectangular ring, the contact plug 114 is located on the wider segment of the gate structure 108 (e.g., on the second segment of the gate structure 108, as shown in reference 108). Figure 1A (as described above). Furthermore, in some embodiments, such as... Figure 1A As shown, the contact plug 114 has a linear top-view shape whose extension direction intersects (e.g., is perpendicular to) the extension direction of the linear shape active region AA. The contact plug 114 is made of a conductive material. For example, the conductive material may include tungsten, copper, similar materials, or combinations thereof.

[0098] In some embodiments, the antifuse memory cell AF is a capacitor. During a programming operation, a large bias voltage is applied between the two terminals of the antifuse memory cell AF, causing the two terminals to short-circuit due to dielectric breakdown between the terminals. In this embodiment, the antifuse memory cell AF includes a dielectric layer 116 disposed between the two terminals. Dielectric breakdown during the programming operation occurs at the dielectric layer 116. In some embodiments, a doped region 112 may serve as one of the terminals of the antifuse memory cell AF. In these embodiments, the dielectric layer 116 is disposed on the doped region 112. In some embodiments, the material of the dielectric layer 116 may be the same as the material of the gate dielectric layer 106. Alternatively, the dielectric layer 116 and the gate dielectric layer 106 may be made of different materials. Furthermore, in some embodiments, a dielectric layer thickness of the dielectric layer 116 may be greater than a gate dielectric layer thickness of the gate dielectric layer 106. In alternative embodiments, the dielectric layer thickness of the dielectric layer 116 may be equal to or less than the gate dielectric layer thickness of the gate dielectric layer 106. Furthermore, another terminal of the antifuse storage unit AF is an electrode 118 that can stand upright on the dielectric layer 116. In some embodiments, such as Figure 1AAs shown, electrode 118 is formed in a linear shape, and one extension direction of the linear electrode 118 may be substantially aligned with the extension direction of the linear active region AA. In these embodiments, the dielectric layer 116 sandwiched between electrode 118 and doped region 112 may also have a linear shape, and the sidewalls of dielectric layer 116 may be substantially coplanar with one sidewall of electrode 118. Electrode 118 is made of a conductive material. For example, the conductive material may include tungsten, copper, similar materials, or combinations thereof.

[0099] In some embodiments, insulating layers 120 and 122 are stacked on substrate 100. The gate dielectric layer 106, gate structure 108, and gate spacer GS of access transistor T are formed in and laterally surrounded by insulating layer 120. In some embodiments, a top surface of insulating layer 120 is substantially aligned with the uppermost end of gate spacer GS and slightly higher than a top surface of the top contact layer CL. Furthermore, dielectric layer 116 and the lower portion of electrode 118 of antifuse memory cell AF are also formed in insulating layer 120 and laterally surrounded by insulating layer 120. On the other hand, insulating layer 122 is disposed on insulating layer 120. Thus, the top surface of the uppermost contact layer CL of access transistor T is covered by insulating layer 122, and the contact plug 114 located on the uppermost contact layer CL is laterally surrounded by insulating layer 122. Similarly, the upper portion of electrode 118 of antifuse memory cell AF is laterally surrounded by insulating layer 122. Insulating layers 120 and 122 are each formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or similar materials. In some embodiments, the insulating materials forming insulating layers 120 and 122 may be different from each other. In alternative embodiments, insulating layers 120 and 122 may be made of the same insulating material.

[0100] As described above, the active region AA of the access transistor T in memory element 10 is formed in a linear shape and intersects with the linear portion of the gate structure 108 at its two ends E1, E2, away from the gate structure 108. During manufacturing, the ends E1, E2 of the active region AA are susceptible to photolithography and / or inaccurate etching, and thus the size and / or shape of the ends E1, E2 may be somewhat deformed from the original layout design. Therefore, if the active region of the transistor overlaps with the gate structure at one of its ends, it will be difficult to control the gate coupling area and the threshold voltage of the transistor. In contrast, since the embodiments of this disclosure avoid using either end E1, E2 of the active region AA as the gate coupling region of the access transistor T, the above-mentioned problems can be effectively prevented. Therefore, the gate coupling area and threshold voltage of the access transistor T according to the embodiments of this disclosure can be better controlled.

[0101] Figure 2 Example Figure 1A and Figure 1BA schematic diagram of the fabrication method of the memory element 10. Figures 3A to 3O Example Figure 2 The diagram shows cross-sectional views of the manufacturing process at different stages. It should be understood that... Figures 3A to 3O For along Figure 1A A cross-sectional view of line A-A' in the middle.

[0102] refer to Figure 2 and Figure 3A A groove RS is formed on one surface of the substrate 100. The corresponding step is illustrated in the figure below. Figure 2 The step S11 is shown. The recess RS defines the location of the subsequently formed isolation structure 102. In other words, the recess RS will accommodate the isolation structure 102 formed in a subsequent step. Figure 1A As shown, the active region AA is laterally surrounded by the isolation structure 102, and therefore the portion of the substrate 100 laterally surrounded by the recessed RS defines the location where the active region AA is subsequently formed. In some embodiments, the method of forming the recessed RS may include a photolithography process and an etching process (e.g., an anisotropic etching process).

[0103] refer to Figure 2 and Figure 3B An insulating material is filled into the groove RS to form an isolation structure 102. The corresponding steps are illustrated in the diagram below. Figure 2 Step S13 is shown. The insulating material can be filled by a deposition process, such as a chemical vapor deposition (CVD) process. In some embodiments, the insulating material filling the groove RS may initially extend to the top surface of the substrate 100 and may be further subjected to a planarization process to remove portions of the insulating material on the top surface of the substrate 100. For example, the planarization process may include a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof.

[0104] refer to Figure 2 and Figure 3C This forms an active region AA. The corresponding steps are illustrated as follows: Figure 2 The step S15 is shown. In some embodiments, the method of forming the active region AA includes performing an ion implantation process on a portion of the substrate 100 laterally surrounded by the isolation structure 102. In such embodiments, the isolation structure 102 can be used as a mask during the ion implantation process, and the formation of the active region AA can be considered a self-aligned process.

[0105] refer to Figure 2 and 3D A channel area 104 is formed in the active area AA. The corresponding steps are as follows: Figure 2Step S17 is shown. In some embodiments, the method of forming the channel region 104 includes forming a mask pattern (not shown) on the substrate 100. The mask pattern has openings as locations defining the channel region 104. After forming the mask pattern, an ion implantation process is performed to form the channel region 104. The mask pattern serves as a doped region (i.e., the region of the channel region 104) defining the ion implantation process. After forming the channel region 104, the mask pattern can be removed. In some embodiments, the mask pattern is a photoresist pattern. In alternative embodiments, the mask pattern is a hard mask pattern and may be made of silicon oxide, silicon nitride, the like, or combinations thereof.

[0106] Please refer to Figure 3E A dielectric material layer 106', a gate electrode layer GE', and at least one contact material layer CL' (e.g., two contact material layers CL') are formed on the substrate 100. The corresponding steps are illustrated in... Figure 2 Step S19 is shown. In some embodiments, the dielectric material layer 106' is selectively formed on the active region AA, and the gate electrode layer GE' and the contact material layer CL' are integrally formed on the substrate 100. In these embodiments, the method of forming the gate dielectric material layer 106' may include an oxidation process, and the methods of forming the gate electrode layer GE' and the contact material layer CL' may each include a deposition process (e.g., a CVD process). In an alternative embodiment, the dielectric material layer 106' completely covers the substrate 100 and can be formed by a deposition process (e.g., a CVD process).

[0107] Reference 2 and Figure 3F The dielectric material layer 106', the gate electrode layer GE', and the contact material layer CL' are patterned to form the gate dielectric layer 106, the gate electrode GE, and the contact layer CL, respectively. The corresponding steps are illustrated in... Figure 2 Step S21 is shown. A portion of the gate dielectric layer 106 and the gate structure 108 (including the gate electrode GE and the contact layer CL) overlaps with the channel region 104. In some embodiments, the method of patterning these layers includes a lithography process and one or more etching processes.

[0108] refer to Figure 2 and 3G A spacer layer GS' is formed on the current structure. The corresponding steps are illustrated as follows: Figure 2 The step S23 is shown. The spacer layer GS' is an exposed surface that can completely cover the isolation structure 102, the active region AA, the channel region 104, the gate dielectric layer 106, and the gate structure 108. In some embodiments, the method of forming the spacer layer GS' includes a deposition process, such as a CVD process.

[0109] refer to Figure 2 and Figure 3HA portion of the spacer layer GS' is removed to form the gate spacer GS. The corresponding steps are illustrated in the diagram below. Figure 2 The step S25 is shown. In some embodiments, the method of forming the gate spacer GS includes performing an anisotropic etching process. During the anisotropic etching process, the horizontally extending portion of the spacer layer GS' is removed, while the vertically extending portion of the spacer layer GS' is shaped to form the gate spacer GS. Furthermore, in some embodiments, a surface portion of the topmost contact layer CL may be consumed during the anisotropic etching process. As a result, a top surface of the topmost contact layer CL may be slightly lower than the topmost point of the gate spacer GS.

[0110] refer to Figure 2 and Figure 3I Doped regions 110 and 112 are formed in the active region AA. The corresponding steps are illustrated as follows: Figure 2 Step S27 is shown. The method for forming the doped regions 110 and 112 may include an ion implantation process. In this ion implantation process, the gate structure 108, the gate spacer GS, and the isolation structure 102 are used as masks, so that the formation of the doped regions 110 and 112 can be a self-aligned process. The portion of the active region AA not covered by the gate structure 108 and the gate spacer GS is suitable for the ion implantation process, while the portion of the active region AA covered by the gate structure 108 and the gate spacer GS is not. Further, a heat treatment may be performed so that the dopant implanted in the exposed portion of the active region AA can diffuse to the region covered by the gate spacer GS.

[0111] refer to Figure 2 and Figure 3J Step 9 involves forming an insulating layer 120 on the substrate 100. The corresponding steps are illustrated in the diagram below. Figure 2 The step S29 is shown. In some embodiments, the method of forming the insulating layer 120 includes a deposition process, such as a CVD process. The insulating layer 120 may initially cover a top surface of the gate structure 108, and then a planarization process may be performed to remove a portion of the insulating layer 120 above the top surface of the gate structure 108. The gate structure 108 and the gate spacer GS are laterally surrounded by the finally formed insulating layer 120. The planarization process may include, for example, a CMP process, an etching process, or a combination thereof. In some embodiments, a surface portion of the topmost contact layer CL may be consumed during the planarization process. As a result, a top surface of the topmost contact layer CL may be slightly lower than the topmost point of the gate spacer GS.

[0112] refer to Figure 2 and Figure 3K Another insulating layer 122 is formed on the insulating layer 120. The corresponding steps are illustrated in the diagram below. Figure 2The step S31 is shown. In some embodiments, the method of forming the insulating layer 120 includes a deposition process, such as a CVD process. Additionally, a planarization process may be further performed on the insulating layer 120. The planarization process may include, for example, a CMP process, an etching process, or a combination thereof.

[0113] refer to Figure 2 and Figure 3L An opening W1 is formed in the stack of insulating layers 120 and 122. The corresponding steps are illustrated in... Figure 2 The step S33 is shown. In a subsequent step, the opening W1 will be filled with the dielectric layer 116 and the electrode 118 of the antifuse memory cell AF. The method of forming the opening W1 may include a photolithography process and one or more etching processes.

[0114] refer to Figure 2 and Figure 3M A dielectric layer 116 is formed in the opening W1. The corresponding steps are illustrated as follows: Figure 2 The step S35 is shown. In some embodiments, the dielectric layer 116 selectively covers a portion of the doped region 112 exposed by the opening W1. In these embodiments, the method of forming the dielectric layer 116 may include an oxidation process, and the formation of the dielectric layer 116 can be considered a self-aligned process.

[0115] refer to Figure 2 and Figure 3N An opening W2 is formed in the insulating layer 122. The corresponding steps are illustrated in the diagram below. Figure 2 The step S37 is shown. By providing the opening W2, the location of the subsequently formed contact plug 114 can be defined. The opening W2 penetrates the insulating layer 122 and exposes a portion of the gate structure 108. For example, the opening W2 exposes a top surface of the uppermost contact layer CL of the gate structure 108. In some embodiments, the method of forming the opening W2 includes a photolithography process and an etching process.

[0116] refer to Figure 2 and Figure 3O A conductive material CM is formed on this current structure. The corresponding steps are illustrated as follows: Figure 2 The step S39 is shown. In the next step, the conductive material CM will be patterned to form the electrode 118 and the contact plug 114. Currently, the conductive material fills the openings W1 and W2 and covers a top surface of the insulating layer 122. In some embodiments, the method for forming the conductive material CM includes a deposition process (e.g., a physical vapor deposition (PVD) process), an electroplating process, or a combination thereof.

[0117] refer to Figure 2 and Figure 1BRemove a portion of the conductive material CM from the top surface of the insulating layer 122. The corresponding steps are illustrated in the diagram below. Figure 2 The step S41 is shown. On the other hand, another portion of the conductive material CM remains in the openings W1 and W2, forming the electrode 118 and the contact plug 114. In some embodiments, a planarization process is used to form the electrode 118 and the contact plug 114. In some embodiments, the planarization process is used to form the electrode 118 and the contact plug 114.

[0118] This completes the fabrication method of memory element 10. Memory element 10 can be further processed to form additional elements, including, for example, word lines, bit lines, and source lines.

[0119] Figure 4 A schematic cross-sectional view of a memory element 10a illustrating some embodiments of this disclosure is shown. Figure 4 The memory element 10a shown is similar to Figure 1B The memory element 10 shown, except for Figure 4 The dielectric layer 116' of the antifuse memory cell AF' in the memory element 10a further includes sidewalls covering the insulating layers 120, 122. In some embodiments, the dielectric layer 116' is conformally formed in the opening W1, such as... Figure 3M As shown, electrode 118 is then filled into the groove defined by dielectric layer 116'. Therefore, one bottom surface and one sidewall of electrode 118 are covered by dielectric layer 116'. In these embodiments, dielectric layer 116' can be formed by a deposition process such as CVD.

[0120] Figure 5 A schematic plan view of a memory element 10b illustrating some embodiments of the present disclosure is shown. Figure 5 The memory element 10b shown is similar to Figure 1A The memory element 10 is shown. Only the differences between them will be described; identical or similar parts will not be repeated. References Figure 5 In some embodiments, the gate structure 108' is formed as an open loop rather than a closed loop. For example, as... Figure 5 As shown, the top view of the gate structure 108' is shaped like a rotatable "C". The area overlapping with the end E1 of the active region AA is not completely surrounded by the gate structure 108'.

[0121] In summary, the memory element of this disclosure includes a memory cell in an antifuse OTP memory array, and includes an access transistor and an antifuse memory cell connected to one of the source and drain terminals of the transistor. The access transistor includes an active region formed in a substrate and a gate structure formed on the substrate. The active region has a linear top-view shape, and the gate structure has a linear portion intersecting a portion of the active region. This portion of the active region is located away from two ends of the active region, which are particularly susceptible to photolithography and / or etching errors. Therefore, the overlap area between the gate structure and the active region can be better controlled, thereby reducing the impact of incorrect memory element fabrication processes on the gate coupling region and threshold voltage of the access transistor.

[0122] This disclosure provides a method for fabricating a memory element. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersecting a portion of the active region, wherein the portion is an end away from the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure and is covered by the second insulating layer; forming an opening penetrating the first insulating layer and the second insulating layer and exposing a portion of the active region, wherein the opening is laterally spaced from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

[0123] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0124] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device, comprising: An active region is formed in a substrate, wherein the active region has a linear top view shape; A gate structure is formed on the substrate, wherein the gate structure has a linear portion intersecting a portion of the active region, wherein the portion is an end away from the active region; A first insulating layer and a second insulating layer are formed on a substrate, wherein the first insulating layer laterally surrounds the gate structure and is covered by the second insulating layer; An opening is formed that penetrates the first insulating layer and the second insulating layer and exposes a portion of the active region, wherein the opening is laterally spaced from the gate structure; as well as A dielectric layer and an electrode are sequentially formed in the opening.

2. The preparation method according to claim 1, further comprising: An isolation structure is formed in the substrate prior to the formation of the active region, wherein the active region is laterally surrounded by the isolation structure.

3. The preparation method according to claim 1, further comprising: After the gate structure is formed, a gate spacer is formed that covers the sidewalls of the gate structure.

4. The preparation method according to claim 3, further comprising: A doped region is formed in the active region. This doped region is formed after the gate spacer is formed and before the first insulating layer and the second insulating layer are formed, and is formed by the gate structure and the gate spacer as a mask.

5. The preparation method of claim 4, wherein the opening overlaps with one of the doped regions.

6. The preparation method according to claim 1, wherein the gate structure is ring-shaped.

7. The fabrication method of claim 6, wherein one of the ends of the active region overlaps with a region laterally surrounded by the gate structure.

8. The fabrication method of claim 6, wherein the gate structure is closer to a first end of the active region than to a second end of the active region, and an antifuse memory cell is closer to the second end of the active region than to the first end of the active region.

9. The preparation method according to claim 8, further comprising: An isolation structure is formed in the substrate and laterally surrounds the active region.

10. The fabrication method of claim 9, wherein the gate structure overlaps with the isolation structure and a portion of the active region.

11. The preparation method according to claim 10, further comprising: A gate dielectric layer is formed between the gate structure and the portion of the active region.

12. The fabrication method of claim 11, wherein the thickness of a gate dielectric layer is different from the thickness of a dielectric layer of the antifuse memory cell.

13. The preparation method according to claim 6, further comprising: A gate spacer is formed by covering one sidewall of the gate structure.

14. The preparation method according to claim 8, further comprising: A contact plug is formed on the gate structure and electrically connected to the gate structure.

15. The preparation method of claim 14, wherein the contact plug is separated from the active region.

16. The preparation method of claim 14, wherein a top surface of the contact plug is substantially coplanar with a top surface of the electrode of the antifuse storage cell.

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