Electrostatic protection device and manufacturing method thereof

Abstract

The present invention provides an electrostatic protection device and a manufacturing method thereof, the electrostatic protection device comprising a substrate; a drift region formed on the substrate; a well region formed on the drift region; a first body region and a second body region, respectively arranged on both sides of the well region, and the distance between the well region and the first body region is smaller than the distance between the well region and the second body region; wherein the first body region only has a first heavily doped region, the second body region is provided with a second heavily doped region and a third heavily doped region, and the well region is provided with only a fourth heavily doped region. The present invention retains only a parasitic PNP triode on one side of the drain end of a traditional LDMOS‑SCR device and a parasitic SCR on the other side, and designs relevant dimensions so that the PNP is triggered before the SCR, so that the electrostatic protection device can effectively provide electrostatic protection while avoiding false triggering of the parasitic SCR when a voltage overshoot or voltage spike occurs, resulting in deep hysteresis to a very low holding voltage causing latch-up.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electrostatic protection device and a manufacturing method thereof. Background Art

[0002] Electrostatic discharge (ESD) is a common phenomenon in daily life. Although it is not easily perceived by the human body, it can pose a serious threat to integrated circuit products. According to statistics from National Semiconductor, 38% of today's failed integrated circuit products are caused by ESD / EOS (Electrostatic-Discharge / Electrical-Over-Stress). For high-voltage CMOS or high-voltage BCD processes, they are widely used in the manufacture of integrated circuit products in the fields of power management, high-voltage drive, and automotive electronics. However, such integrated circuit products often work in high-current, high-voltage, and strong electromagnetic interference environments. ESD protection devices will have problems such as low robustness and false triggering, requiring highly reliable and robust ESD solutions.

[0003] In the existing technology, due to the traditional LDMOS (such as Figure 1 When an ESD pulse comes, the parasitic NPN tube of the nLDMOS device has a non-uniform opening problem, which will lead to local current accumulation. When the electron current density exceeds the impurity concentration in the drift region, the electric field peak is transferred to the near-drain end, and an internal kirk (base extension effect) occurs inside the nLDMOS, causing local overheating and failure. To prevent the occurrence of the kirk effect, such as Figure 2 As shown in FIG. 1 , a P+ injection region is usually inserted into the drain end of a conventional LDMOS device to form a silicon controlled rectifier (SCR) device structure. As an ESD protection device, LDMOS-SCR has excellent robustness and unit area efficiency and can pass a high HBM test. However, Figure 3 As shown, the SCR structure of the traditional LDMOS-SCR device maintains a very low voltage (Vh) after being triggered. If a certain degree of voltage overshoot or voltage spike occurs at the power pin during the chip testing or operation, the SCR device will be falsely triggered and maintained at a very low voltage value, causing a latch effect and burning the chip.

[0004] Therefore, it is necessary to propose a further solution to the problem that the latch-up effect is easily triggered by mistake in the existing electrostatic protection device. Summary of the invention

[0005] The object of the present invention is to provide an electrostatic protection device and a method for manufacturing the same, which can overcome the problem in the prior art that a double-finger LDMOS-SCR device falsely triggers a parasitic SCR when a voltage overshoot or voltage spike occurs, resulting in a deep hysteresis to a very low holding voltage causing a latch-up phenomenon, that is, avoiding false triggering of the latch-up phenomenon.

[0006] In order to achieve the above-mentioned object of the invention, the present invention provides an electrostatic protection device, comprising

[0007] substrate;

[0008] a drift region of a first conductivity type formed on the substrate;

[0009] a well region having a first conductivity type, formed on the drift region;

[0010] A first body region and a second body region are respectively arranged on both sides of the well region, the first body region and the second body region have a second conductivity type, and a distance between the well region and the first body region is smaller than a distance between the well region and the second body region;

[0011] in

[0012] Only a first heavily doped region having a second conductivity type is formed in the first body region;

[0013] A second heavily doped region of the first conductivity type and a third heavily doped region of the second conductivity type are provided in the second body region;

[0014] The well region is provided with only a fourth heavily doped region of the second conductivity type.

[0015] Preferably, a first parasitic device is formed between the fourth heavily doped region and the first heavily doped region, a second parasitic device is formed between the fourth heavily doped region and the second heavily doped region, and the first parasitic device has a smaller breakdown voltage than the second parasitic device.

[0016] Preferably, the first conductivity type is N-type, the second conductivity type is P-type, the first parasitic device is a PNP transistor, and the second device is a silicon-controlled rectifier device.

[0017] Preferably, the first body region and the second body region are provided with electrode lead wires which are in ohmic contact with each heavily doped region, and all the electrode lead wires of the first body region and the second body region are connected at the low voltage end to form the cathode of the electrostatic protection device, and the well region is provided with electrode lead wires which are in ohmic contact with the fourth heavily doped region, and the electrode lead wires on the well region are connected at the high voltage end to form the anode of the electrostatic protection device.

[0018] Preferably, when there is an electrostatic pulse voltage on the anode, the reverse PN junction in the first parasitic device breaks down, causing the first parasitic device to be turned on, and when the electrostatic voltage continues to increase, the voltage on the electrostatic protection device reaches the breakdown voltage of the second parasitic device, causing the second parasitic device to be turned on, forming a maximum discharge mode of the device for electrostatic current.

[0019] Preferably, the electrostatic protection device is an LDMOS-SCR device, and a first gate region is further provided on the first body region, and the first gate region is located between the first heavily doped region and the fourth heavily doped region, and a second gate region is further provided on the second body region, and the second gate region is located between the second heavily doped region and the fourth heavily doped region.

[0020] Preferably, isolation is provided between the first gate region and the second gate region and the fourth heavily doped region respectively, and polysilicon gates are provided on the first gate region and the second gate region, and the polysilicon gates extend onto the isolation to form field plates.

[0021] Preferably, the drift region and the first body region and the second body region respectively form a first reverse PN junction and a second reverse PN junction, and a breakdown voltage of the first reverse PN junction is smaller than a breakdown voltage of the second reverse PN junction.

[0022] According to the purpose of the present invention, a method for manufacturing the electrostatic protection device as described above is also proposed, and the manufacturing method comprises the following steps:

[0023] providing a substrate;

[0024] growing a drift region having a first conductivity type on the substrate;

[0025] Doping is performed on the drift region to respectively form a first body region and a second body region having a second conductivity type, and a well region having a first conductivity type;

[0026] Performing heavy doping in the first body region, the second body region and the well region to form a first heavily doped region, a third heavily doped region and a fourth heavily doped region having a second conductivity type;

[0027] heavily doping the second body region to form a second heavily doped region having the first conductivity type;

[0028] Electrodes are made on the first heavily doped region, the second heavily doped region, the third heavily doped region and the fourth heavily doped region, and electrical lead wires are made on the electrodes. The electrodes on the first body region and the second body region are connected to the low voltage end to form a cathode, and the electrodes on the well region are connected to the high voltage end to form an anode.

[0029] Preferably, the electrostatic protection device is an LDMOS-SCR device, which also includes a first gate region and a second gate region, which are respectively formed on the first body region and the second body region, and the first gate region is located between the first heavily doped region and the fourth heavily doped region. A second gate region is also provided on the second body region, and the second gate region is located between the second heavily doped region and the fourth heavily doped region, and the gates on the first gate region and the second gate region are connected to the cathode through electrical leads.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention leaves only the P+ injection region in the drain N-well of the traditional double-finger LDMOS-SCR device, removes the N+ injection region in the source P-well of the left-side fork finger, retains only the parasitic PNP transistor on the left-side fork finger, and retains the parasitic SCR on the right-side fork finger, and designs relevant dimensions so that the PNP is triggered before the SCR, and combines the characteristic of the PNP without hysteresis and the high robustness of the SCR, so that the electrostatic protection device can effectively provide electrostatic protection while avoiding the false triggering of the parasitic SCR when a voltage overshoot or voltage spike occurs, resulting in a deep hysteresis to a very low holding voltage causing a latch-up phenomenon, that is, avoiding the false triggering of the latch-up phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 Schematic diagram of the traditional LDMOS device structure.

[0033] Figure 2 The present invention is a schematic diagram of the structure of an existing LDMOS-SCR device.

[0034] Figure 3 It is a TLP curve diagram of the existing LDMOS-SCR.

[0035] Figure 4 It is a schematic structural diagram of the electrostatic protection device of the present invention.

[0036] Figure 5 This is the TLP curve of the electrostatic protection device of the present invention. DETAILED DESCRIPTION

[0037] The present invention is described in detail below in conjunction with various embodiments, but it should be noted that these embodiments are not limitations of the present invention, and any equivalent transformations or substitutions in functions, methods, or structures made by ordinary technicians in the field based on these embodiments are all within the scope of protection of the present invention.

[0038] As described in the background technology, in the traditional LDMOS-SCR structure, the latch effect is easy to occur, causing the device to burn out after false triggering. After studying this phenomenon, the applicant found that the principle of this technical problem is as follows: For the traditional LDMOS-SCR structure, its equivalent circuit diagram is as follows Figure 2 As shown, it includes two symmetrically distributed MOS devices, in which the N-well in the middle constitutes the drain region. Since the drain region includes an N-type heavily doped region and two P-type heavily doped regions, each MOS device generates parasitic transistors NPN and PNP. When a positive ESD pulse comes, the positive voltage causes the PN junction formed by the N-drift and P-body in the SCR to be reverse biased. As the ESD voltage gradually increases, the PN junction gradually enters avalanche breakdown. The holes generated by the PN junction avalanche flow from the N-well into the P-well and are finally collected by the P+ injection region in the P-well to generate a current I NW Similarly, the generated electrons flow from the P well into the N well and are finally collected by the N+ injection region of the N well to generate a current I PW Since both the N-well and P-well have parasitic resistance R N-Well and R P-Well , so a voltage drop will be formed on the N-well and P-well. When the voltage drop on the N-well or P-well reaches 0.7V, one of the parasitic transistors NPN or PNP will turn on. When one transistor is turned on, the voltage drop caused by the current generated on its collector will immediately turn on the other parasitic transistor. Finally, the two transistors form an open-circuit positive feedback mechanism, the SCR is fully turned on, forming a low-resistance path, and the voltage is clamped at a very low value. Its TLP curve is as follows Figure 3 If the power pin experiences a certain degree of voltage overshoot or voltage spike during chip testing or operation, the SCR device may be triggered by mistake and maintained at a very low voltage value, causing a latch effect and burning the chip.

[0039] In view of the above problems, in the present invention, Figure 4 As shown in the figure, only the P+ injection region is left in the drain N-well of the traditional double-finger LDMOS-SCR device, and the N+ injection region in the source P-well of the left fork is removed. The left fork forms a parasitic PNP transistor, and the right fork forms a parasitic SCR. At the same time, the drift region L2 on one side of the SCR is enlarged (L2>L1), so that the breakdown voltage of the SCR is greater than that of the PNP transistor. When the ESD pulse comes, the PNP transistor with a lower breakdown voltage is turned on first, and the TLP curve is as shown in the figure. Figure 5As shown, at this point corresponding to Vt1, since the PNP transistor has no hysteresis characteristics, the voltage on the device will continue to rise. When the voltage rises to the breakdown voltage of the SCR, the SCR path is turned on and the ESD current is discharged. From the TLP curve, it can be seen that when a certain degree of voltage overshoot or voltage spike occurs at the chip pin, as long as the current after the PNP is triggered is not higher than the trigger current of the SCR, the SCR path cannot be triggered further, thereby avoiding the false trigger latch effect. The device combines the characteristics of PNP without hysteresis and the high robustness of SCR. While effectively protecting against ESD, it can prevent the false trigger latch effect caused by pin overvoltage.

[0040] The technical solution of the present invention will be described in detail below through specific embodiments. It should be noted that since LDMOS devices are divided into P-type tubes and N-type tubes, the two are distinguished by the carrier type. Although they are different in working characteristics, their working principles for realizing functions are basically the same. Therefore, in the following embodiments, the LDMOS tube with an N-type channel will be used as an example for explanation. At this time, the N-type doping is used as the first conductive type semiconductor, and the P-type doping is used as the second conductive type semiconductor. The P-type tube can be adjusted accordingly based on the idea of ​​this patent.

[0041] See also Figure 4 , Figure 4 This is a schematic diagram of the structure of an electrostatic protection device of the present invention. As shown in the figure, it includes a substrate 100, which is used to provide a carrier required for a semiconductor device. Generally, the conductivity type of the substrate is P-type. An N-type drift region 101 is formed on the substrate 100, and the drift region 101 is used to construct a device region and provide a channel for carrier flow. An N-type well region 110, a P-type first well region 120 and a second body region 130 are respectively formed on the drift region 101, and the first well region 120 and the second body region 130 are distributed on both sides of the well region 110. The N-type well region is mainly used to form the drain region of the LDMOS device, and the P-type first body region 120 and the second body region 130 are mainly used to form the source region and the gate region, so that a pair of bidirectional LDMOS devices can be formed.

[0042] Compared with the conventional LDMOS-SCR device, in the present invention, only the first heavily doped region 121 of P type is formed in the first body region 120, and the second heavily doped region 131 of N type and the third heavily doped region 132 of P type are arranged in the second body region 130, and only the fourth heavily doped region 111 of P type is arranged in the well region 110. Such a setting changes the symmetric structure of the conventional LDMOS-SCR device, so that the MOS devices on both sides have an asymmetric structure. At this time, the MOS device corresponding to the first body region 120 has only one first parasitic device 102 parasitized therein, and the first parasitic device 102 reaches the first heavily doped region 121 in the first body region 120 after passing through the well region 110 and the drift region 101 from the fourth heavily doped region 111, forming a PNP tube. The MOS device corresponding to the second body region 130 has a second parasitic device 103 parasitized therein, and the second parasitic device 103 passes through the fourth heavily doped region 111, the well region 110, and the drift region 101 to reach the second heavily doped region 131 in the second body region 130, forming a PNPN SCR structure. Both the first parasitic device 102 and the second parasitic device 103 have a reverse PN junction inside, and when the ESD voltage comes, the reverse PN junction needs to be broken down, so that the device forms an avalanche current and conducts the leakage current.

[0043] On the other hand, in the present invention, the distance between the well region 110 and the first body region 120 is designed to be smaller than the distance between the well region 110 and the second body region 130. In this way, the first parasitic device 102 has a smaller breakdown voltage than the second parasitic device 103, so that the PNP tube of the first parasitic device 102 reaches the voltage threshold of avalanche breakdown faster and is broken down when the ESD voltage comes. Please refer to Figure 5 , Figure 5 It is the TLP curve diagram of the electrostatic protection device of the present invention, such as Figure 5 As shown, when the reverse PN junction of the first parasitic device 102 is broken down, corresponding to the point Vt1 in the figure, since the PNP transistor has no hysteresis characteristic, the voltage on the device will continue to rise. When the voltage rises to the breakdown voltage of the second parasitic device 103, the SCR device in the second parasitic device 103 is turned on to discharge the ESD current. It can be seen from the TLP curve that when a certain degree of voltage overshoot or voltage spike occurs at the chip pin, as long as the current after the PNP is triggered is not higher than the trigger current of the SCR, the SCR path cannot be triggered further, thereby avoiding the false triggering latch effect.

[0044] Furthermore, electrode lead wires in ohmic contact with each heavily doped region are provided on the first body region 120 and the second body region 130, and all electrode lead wires of the first body region 120 and the second body region 130 are connected to the low voltage end to form the cathode 104 of the electrostatic protection device. Electrode lead wires in ohmic contact with the fourth heavily doped region 111 are provided on the well region 110, and the electrode lead wires on the well region 110 are connected to the high voltage end to form the anode 105 of the electrostatic protection device. When there is an electrostatic pulse voltage on the anode 105, the reverse PN junction in the first parasitic device 102 preferably breaks down so that the first parasitic device 102 is turned on, and when the electrostatic voltage continues to increase, the voltage on the electrostatic protection device reaches the breakdown voltage of the second parasitic device 103, so that the second parasitic device 103 is turned on, forming the maximum discharge mode of the device for electrostatic current.

[0045] Furthermore, the two gate regions of the LDMOS-SCR device are respectively arranged on the partial surface of the first body region 120 and the second body region 130 on one side of the well region 110, wherein the first gate region 122 and the second gate region 132 are respectively provided with isolations 106 and 107 between the fourth heavily doped region 111, and the two isolations 106 and 107 are respectively arranged on the channels of the two MOS devices, and the process of forming the two isolations can be a field oxygen process or a shallow trench isolation process. A polysilicon gate is provided on the first gate region 122 and the second gate region 132, and the polysilicon gate extends onto the isolations 106 and 107 to form a field plate, which can regulate the current and voltage in the channel.

[0046] Furthermore, the drift region and the first body region and the second body region respectively constitute a first reverse PN junction and a second reverse PN junction, i.e., two depletion regions, and since the lengths of the two depletion regions are inconsistent, the breakdown voltage of the first reverse PN junction is smaller than the breakdown voltage of the second reverse PN junction.

[0047] The following is a description of the method for manufacturing the device of the present invention.

[0048] According to the above device, the method for manufacturing the electrical protection device proposed by the present invention comprises the following steps:

[0049] providing a substrate;

[0050] growing a drift region having a first conductivity type on the substrate;

[0051] Doping is performed on the drift region to respectively form a first body region and a second body region having a second conductivity type, and a well region having a first conductivity type;

[0052] Performing heavy doping in the first body region, the second body region and the well region to form a first heavily doped region, a third heavily doped region and a fourth heavily doped region having a second conductivity type;

[0053] heavily doping the second body region to form a second heavily doped region having the first conductivity type;

[0054] Electrodes are made on the first heavily doped region, the second heavily doped region, the third heavily doped region and the fourth heavily doped region, and electrical lead wires are made on the electrodes. The electrodes on the first body region and the second body region are connected to the low voltage end to form a cathode, and the electrodes on the well region are connected to the high voltage end to form an anode.

[0055] Furthermore, the electrostatic protection device is an LDMOS-SCR device, which also includes a first gate region and a second gate region, which are respectively formed on the first body region and the second body region, and the first gate region is located between the first heavily doped region and the fourth heavily doped region. A second gate region is also provided on the second body region, and the second gate region is located between the second heavily doped region and the fourth heavily doped region, and the gates on the first gate region and the second gate region are connected to the cathode through electrical leads.

[0056] In summary, the present invention leaves only the P+ injection region in the drain N-well of the traditional double-finger LDMOS-SCR device, removes the N+ injection region in the source P-well of the left finger, and retains only the parasitic PNP transistor on the left finger and the parasitic SCR on the right finger. At the same time, the relevant dimensions are designed so that the PNP is triggered before the SCR, and the false triggering latch effect is avoided by combining the characteristic of the PNP without hysteresis and the high robustness of the SCR.

[0057] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive in all respects, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention.

[0058] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An electrostatic protection device, characterized in that: include substrate; a drift region of a first conductivity type formed on the substrate; a well region having a first conductivity type, formed on the drift region; A first body region and a second body region are respectively arranged on both sides of the well region, the first body region and the second body region have a second conductivity type, and a distance between the well region and the first body region is smaller than a distance between the well region and the second body region; in, Only a first heavily doped region having a second conductivity type is formed in the first body region; A second heavily doped region of the first conductivity type and a third heavily doped region of the second conductivity type are provided in the second body region; The well region is provided with only a fourth heavily doped region of the second conductivity type; A first parasitic device is formed between the fourth heavily doped region and the first heavily doped region, and a second parasitic device is formed between the fourth heavily doped region and the second heavily doped region, and the first parasitic device has a smaller breakdown voltage than the second parasitic device; the first parasitic device is a triode, and the second parasitic device is a thyristor rectifier device.

2. The electrostatic protection device according to claim 1, characterized in that: The first conductivity type is N type, the second conductivity type is P type, and the first parasitic device is a PNP transistor.

3. The electrostatic protection device according to claim 2, characterized in that: The first body region and the second body region are provided with electrode lead wires that are in ohmic contact with each heavily doped region, and all the electrode lead wires of the first body region and the second body region are connected to the low voltage end to form the cathode of the electrostatic protection device. The well region is provided with electrode lead wires that are in ohmic contact with the fourth heavily doped region, and the electrode lead wires on the well region are connected to the high voltage end to form the anode of the electrostatic protection device.

4. The electrostatic protection device according to claim 3, characterized in that: When there is an electrostatic pulse voltage on the anode, the reverse PN junction in the first parasitic device breaks down, causing the first parasitic device to be turned on. When the electrostatic voltage continues to increase, the voltage on the electrostatic protection device reaches the breakdown voltage of the second parasitic device, causing the second parasitic device to be turned on, forming a maximum discharge mode of the device for electrostatic current.

5. The electrostatic protection device according to claim 1, characterized in that: The electrostatic protection device is an LDMOS-SCR device, a first gate region is further provided on the first body region, the first gate region is located between the first heavily doped region and the fourth heavily doped region, and a second gate region is further provided on the second body region, the second gate region is located between the second heavily doped region and the fourth heavily doped region.

6. The electrostatic protection device according to claim 5, characterized in that: Isolations are respectively provided between the first gate region and the second gate region and the fourth heavily doped region. Polysilicon gates are provided on the first gate region and the second gate region. The polysilicon gates extend onto the isolations to form field plates.

7. The electrostatic protection device according to claim 5, characterized in that: The drift region and the first body region and the second body region respectively form a first reverse PN junction and a second reverse PN junction, and a breakdown voltage of the first reverse PN junction is smaller than a breakdown voltage of the second reverse PN junction.

8. A method for manufacturing an electrostatic protection device according to any one of claims 1 to 7, characterized in that: The production method comprises the following steps: providing a substrate; growing a drift region having a first conductivity type on the substrate; Doping is performed on the drift region to respectively form a first body region and a second body region having a second conductivity type, and a well region having a first conductivity type; Performing heavy doping in the first body region, the second body region and the well region to form a first heavily doped region, a third heavily doped region and a fourth heavily doped region having a second conductivity type; heavily doping the second body region to form a second heavily doped region having the first conductivity type; Electrodes are made on the first heavily doped region, the second heavily doped region, the third heavily doped region and the fourth heavily doped region, and electrical lead wires are made on the electrodes. The electrodes on the first body region and the second body region are connected to the low voltage end to form a cathode, and the electrodes on the well region are connected to the high voltage end to form an anode.

9. The method for manufacturing an electrostatic protection device according to claim 8, characterized in that: The electrostatic protection device is an LDMOS-SCR device, which also includes a first gate region and a second gate region, which are respectively formed on the first body region and the second body region, and the first gate region is located between the first heavily doped region and the fourth heavily doped region. A second gate region is also provided on the second body region, and the second gate region is located between the second heavily doped region and the fourth heavily doped region, and the gates on the first gate region and the second gate region are connected to the cathode through electrical leads.

Images