Integrated chip and method for forming trench capacitor

Abstract

Various embodiments of the present disclosure are directed to trench capacitors with trench patterns for yield improvement. The trench capacitor is located on a substrate and includes a plurality of capacitor segments. The capacitor segments extend into the substrate according to a trench pattern and are spaced apart at a pitch on an axis. The plurality of capacitor segments includes edge capacitor segments located at edges of the trench capacitor and a center capacitor segment located at a center of the trench capacitor. The edge capacitor segments have a width that is greater than a width of the center capacitor segment and / or the pitch at the edge capacitor segments is greater than the pitch at the center capacitor segment. The greater width can facilitate stress absorption and the greater pitch can increase substrate stiffness at the edges of the trench capacitor where the thermal expansion stress is greatest, thereby reducing substrate bow and trench depletion for yield improvement. Embodiments of the present application provide integrated chips and methods for forming trench capacitors.

Description

Technical Field

[0001] Embodiments of this application relate to integrated chips and methods for forming trench capacitors. Background Technology

[0002] An integrated passive device (IPD) is a collection of one or more passive devices integrated onto a semiconductor substrate. Passive devices can include, for example, capacitors, resistors, and inductors. IPDs are formed using semiconductor manufacturing processes and packaged as integrated circuits (ICs). Compared to discrete passive devices, this results in smaller size, lower cost, and higher functional density. IPDs can be used in mobile devices and application processors. Summary of the Invention

[0003] An embodiment of this application provides an integrated chip, including: a substrate; and a trench capacitor located on the substrate, and including a plurality of capacitor segments extending into the substrate; wherein the plurality of capacitor segments include edge capacitor segments located at the edges of the trench capacitor and a center capacitor segment located at the center of the trench capacitor, the capacitor segments being spaced apart on an axis, and the width of the edge capacitor segments being greater than the width of the center capacitor segments and / or the spacing at the edge capacitor segments being greater than the spacing at the center capacitor segments.

[0004] An embodiment of this application provides an integrated chip, comprising: a substrate including a first substrate segment and a second substrate segment; and a trench capacitor located on the substrate, including a central capacitor segment, an intermediate capacitor segment, and an edge capacitor segment; wherein the central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment extend into the substrate, the central capacitor segment and the edge capacitor segment are respectively located at the center of the trench capacitor and the edge of the trench capacitor, the intermediate capacitor segment is located between the central capacitor segment and the edge capacitor segment, the first substrate segment and the second substrate segment respectively separate the intermediate capacitor segment from the central capacitor segment and the edge capacitor segment, and the width of the edge capacitor segment is greater than the width of the central capacitor segment and / or the width of the second substrate segment is greater than the width of the first substrate segment.

[0005] Embodiments of this application also provide a method for forming a trench capacitor, the method comprising: patterning a substrate to form a trench pattern in the substrate, wherein the trench pattern includes a plurality of trench segments spaced apart along an axis, wherein the plurality of trench segments include edge trench segments and a central trench segment located at the edge and center of the trench pattern, respectively, and wherein the width of the edge trench segments is greater than the width of the central trench segment and / or the spacing at the edge trench segments is greater than the spacing at the central trench segment; stacking and depositing a lower electrode layer, an electrode dielectric layer and an upper electrode layer over the substrate, and backing the trench segments, wherein the electrode dielectric layer is located between the lower electrode layer and the upper electrode layer; and patterning the lower electrode layer, the upper electrode layer and the electrode dielectric layer to form a plurality of capacitor electrodes and capacitor dielectric layers, respectively.

[0006] Embodiments of this application provide trench patterns for improving the yield of trench capacitors. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figure 1 Cross-sectional views of some embodiments of trench capacitors with trench patterns for yield improvement are shown.

[0009] Figure 2 Show Figure 1 A cross-sectional view of some alternative embodiments of a trench capacitor having an additional in-trench capacitor segment and an additional substrate segment.

[0010] Figure 3 Show Figure 2 The top layout of some embodiments of the capacitor segment within the trench.

[0011] Figures 4A-4E Show Figure 3 The top layout of some alternative embodiments of the capacitor segment within the trench.

[0012] Figures 5-9 The groove pattern variation is shown. Figure 2 Cross-sectional views of some alternative embodiments of trench capacitors.

[0013] Figure 10 Show Figure 2 A cross-sectional view of some alternative embodiments in which the trench capacitor is replaced by multiple trench capacitors distributed on the capacitor segment within the trench.

[0014] Figures 11-15 Show Figure 2 Cross-sectional views of some alternative embodiments of trench capacitors with components removed or added.

[0015] Figure 16 Showing includes Figure 2 Cross-sectional views of some embodiments of the integrated passive device (IPD) package for trench capacitors.

[0016] Figure 17 Showing includes Figure 16 Cross-sectional views of some embodiments of the integrated fan-out package-on-package (InFO-PoP) structure of the IPD package.

[0017] Figure 18 Showing includes Figure 2 Cross-sectional views of some embodiments of the insert for a trench capacitor.

[0018] Figure 19 Showing includes Figure 18 Chip-on-Wafer-on-Substrate (CoWoS) package for inserts.

[0019] Figures 20-31 A series of cross-sectional views are shown illustrating some embodiments of a method for forming a trench capacitor with a trench pattern for improving yield.

[0020] Figure 32 Show Figures 20-31 Block diagrams of some embodiments of the method. Detailed Implementation

[0021] This invention provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. These are merely examples and are not intended to be limiting. For instance, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of the invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0023] An integrated passive device (IPD) may include a substrate and a trench capacitor located on the substrate. The trench capacitor includes multiple capacitor electrodes and multiple capacitor dielectric layers. The capacitor electrodes and capacitor dielectric layers are stacked alternately over the substrate and define multiple in-trench capacitor segments. The in-trench capacitor segments extend into the substrate and are laterally separated from each other through the substrate segments. The in-trench capacitor segments and substrate segments have a parallel-elongated linear top layout and a uniform width.

[0024] The challenge of trench capacitors lies in the fact that the substrate, capacitor dielectric layer, and capacitor electrodes can have different coefficients of thermal expansion (COPs). For example, the metallic material of a trench capacitor can have a higher COP than the substrate. During high-temperature or high-pressure processes, these different COPs can cause the capacitor segment within the trench to expand faster than the substrate. As a result, the capacitor segment within the trench can exert stress on the substrate. Due to the symmetry in the trench capacitor and therefore the symmetry in the stress pattern, the stress is neutral at the center of the trench capacitor. However, the stress increases from the center of the trench capacitor to its edges in a direction perpendicular to the elongation direction of both the capacitor segment within the trench and the substrate segment. This stress can cause substrate bending and / or trench depletion, particularly at the edges of the trench capacitor. Trench depletion can, for example, correspond to dielectric breakdown of the capacitor dielectric layer caused by stress thinning the dielectric layer. Furthermore, as the substrate and trench segments become smaller, the expected stress will worsen. Substrate bending and / or trench depletion further reduce batch manufacturing yield.

[0025] Various embodiments of this disclosure relate to a method of forming a trench capacitor having a trench pattern for yield improvement, and the resulting trench capacitor. According to some embodiments, the trench capacitor is located on a substrate and includes a plurality of in-trench capacitor segments. The plurality of in-trench capacitor segments include edge in-trench capacitor segments located at the edges of the trench capacitor and a central in-trench capacitor segment located at the center of the trench capacitor. The in-trench capacitor segments extend into the substrate and are spaced apart axially. The width of the edge in-trench capacitor segments is greater than the width of the central in-trench capacitor segments and / or the spacing at the edge in-trench capacitor segments is greater than the spacing at the central in-trench capacitor segments.

[0026] When the width of the capacitor segment within the edge trench is greater than that within the central trench, the edge trench capacitor segment can have a larger gap at the location of maximum stress for stress absorption. When the spacing of the capacitor segments within the edge trench is greater than that within the central trench, the substrate is more rigid and therefore less prone to bending at the location of maximum stress. Therefore, because the capacitor segments within the edge trench have a larger width and / or a larger spacing, substrate bending and / or trench exhaustion can be reduced, thereby increasing yield in mass production.

[0027] refer to Figure 1 A cross-sectional view 100 is provided for some embodiments of a trench capacitor 102 having a trench pattern for yield improvement. The trench capacitor 102 may be an integrated circuit (IC), an IPD, or some other suitable structure, or may be part of such an integrated circuit. The trench capacitor 102 covers a substrate 104 and has a plurality of in-trench capacitor segments 106. The in-trench capacitor segments 106 are laterally spaced along axis A at a spacing P and protrude or extend into the substrate 104 depending on the trench pattern. Furthermore, the in-trench capacitor segments 106 define respective gaps 108 recessed into the substrate 104. In alternative embodiments, one, some, or all of the gaps 108 are omitted.

[0028] Similar to trench capacitor 102, substrate 104 has a plurality of substrate segments 110. The substrate segments 110 are laterally separated along axis A. Furthermore, the substrate segments 110 protrude or extend upward between in-trench capacitor segments 106 to separate the in-trench capacitor segments 106. For example, the in-trench capacitor segments in each pair of adjacent in-trench capacitor segments may be separated by corresponding substrate segments. Substrate 104 may be, for example, a bulk silicon substrate, a bulk oxide substrate, or some other suitable type of substrate.

[0029] In some embodiments, the in-trench capacitor segment 106 can be considered as an in-trench capacitor finger, and the substrate segment 110 can be considered as a substrate finger intersecting the in-trench capacitor finger. Furthermore, in some embodiments, when viewed from above, the in-trench capacitor segment 106 and the substrate segment 110 are linear and extend parallel to each other in a direction perpendicular to axis A. In at least some of these embodiments, the in-trench capacitor segment 106 and the substrate segment 110 can be considered as an in-trench capacitor line and a substrate line, respectively.

[0030] The plurality of in-trench capacitor segments 106 include a pair of edge in-trench capacitor segments 106e and a plurality of inner in-trench capacitor segments 106i. The edge in-trench capacitor segments 106e are located at opposite edges of the trench capacitor 102, and the inner in-trench capacitor segments 106i are located between the edge in-trench capacitor segments 106e. Each edge in-trench capacitor segment 106e has a capacitor edge width W.ce Furthermore, the capacitor segment 106i within the internal trench has a width W smaller than the capacitor edge width. ce The internal width W of a single capacitor ci Capacitor edge width W ce The same and the internal width W of the capacitor ci Same. In other embodiments, the capacitor edge width W ce Different and / or capacitor internal width W ci different.

[0031] The plurality of substrate segments 110 includes a pair of edge substrate segments 110e and a plurality of inner substrate segments 110i. The edge substrate segments 110e are located between and adjacent to the capacitor segments 106e within the edge trench, and the inner substrate segments 110i are located between the edge substrate segments 110e. The edge substrate segments 110e have a respective substrate edge width W. se Furthermore, the inner substrate segment 110i has a width W smaller than the substrate edge width. se The internal width W of each substrate si Substrate edge width W se The same, and the substrate internal width W si Same. In other embodiments, the substrate edge width W se Different and / or substrate internal width W si Different. Because the substrate edge width W se Greater than the inner width W of the substrate si Therefore, the spacing P at the edge substrate segment 110e is larger than that at the inner substrate segment 110i. The spacing P at the edge substrate segment 110e is the same as that at the inner substrate segment 110i. In other embodiments, the spacing P at the edge substrate segment 110e is different and / or different from that at the inner substrate segment 110i.

[0032] The in-trench capacitor segment 106 can have a larger coefficient of thermal expansion than the substrate segment 110, allowing the in-trench capacitor segment 106 to expand by a greater amount than the substrate segment 110 during high-temperature and / or high-pressure processes. As a result, the in-trench capacitor segment 106 can apply stress to the substrate segment 110. Due to the symmetry in the trench capacitor 102 and therefore the symmetry in the stress pattern, the stress is neutral at the center of the trench capacitor 102. However, the stress increases along axis A from the center of the trench capacitor 102 towards the edge of the trench capacitor 102. Without the greater width of the edge in-trench capacitor segment 106e and the edge substrate segment 110e, the stress could cause the edge substrate segment 110e to bend and / or the trench to wear out at the edge in-trench capacitor segment 106e.

[0033] Because the substrate edge width W se Greater than the inner width W of the substrate siTherefore, the stiffness of the edge substrate segment 110e is greater than that of the inner substrate segment 110i. As a result, the edge substrate segment 110e is less prone to bending and reduces trench depletion at the capacitor segment 106e within the edge trench. This is because the capacitor edge width W... ce Greater than the internal width W of the capacitor ci Therefore, the gap 108 of the capacitor segment 106e in the edge trench is larger than the gap 108 of the capacitor segment 106i in the inner trench. The gap 108 promotes stress absorption, and the larger gap at the capacitor segment 106e in the edge trench provides increased stress absorption at the edge of the trench capacitor 102 where stress is greatest. As a result, the edge substrate segment 110e is less prone to bending, and trench depletion at the capacitor segment 106e in the edge trench is reduced. Because the larger width of the capacitor segment 106e in the edge trench and the larger width of the edge substrate segment 110e reduce bending and trench depletion, the yield rate for mass production can be improved.

[0034] The trench capacitor 102 includes a dielectric liner 112, a capacitor dielectric layer 114, and a pair of capacitor electrodes 116. The dielectric liner 112, capacitor dielectric layer 114, and capacitor electrodes 116 are stacked and define a capacitor segment 106 within a trench. The capacitor dielectric layer 114 is located between the capacitor electrodes 116, and the capacitor dielectric layer 114 and capacitor electrodes 116 cover the dielectric liner 112. The widths of the dielectric liner 112, capacitor dielectric layer 114, and capacitor electrodes 116 decrease from the bottom to the top of the trench capacitor 102. The dielectric liner 112 is located in a portion of the trench capacitor 102 and has the same width as the bottom electrode of the capacitor electrode 116. In other embodiments, the dielectric liner 112 covers the top of a substrate 104 and has a wider width than the bottom electrode of the capacitor electrode 116.

[0035] The width of the top electrode of the capacitor dielectric layer 114 and the capacitor electrode 116 is smaller than the width of the bottom electrode of the capacitor electrode 116. In other embodiments, the width of the bottom electrode of the capacitor dielectric layer 114 and the capacitor electrode 116 is greater than the width of the top electrode of the capacitor electrode 116.

[0036] The dielectric liner 112 may be, for example, silicon oxide and / or some other suitable dielectric.

[0037] The capacitor dielectric layer 114 may be, for example, silicon oxide, a high-k dielectric layer, some other suitable dielectric, or any combination thereof. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, titanium oxide, some other suitable metal oxide, some other suitable high-k dielectric, or any combination thereof. The capacitor electrode 116 may be, for example, doped polycrystalline silicon, titanium nitride, tantalum nitride, aluminum copper, some other suitable metal and / or conductive material, or any combination thereof.

[0038] In some embodiments, substrate 104 is or comprises silicon, dielectric liner 112 is or comprises silicon oxide, capacitor dielectric layer 114 is or comprises hafnium oxide, and capacitor electrode 116 is or comprises titanium nitride. However, other suitable materials are also possible. In some embodiments, capacitor electrode 116 and capacitor dielectric layer 114 have a larger coefficient of thermal expansion than dielectric liner 112 and substrate 104. For example, substrate 104 may have a coefficient of thermal expansion of about 2.5 × 10⁻⁶. -6 The coefficient of thermal expansion of the dielectric liner 112 can be approximately 0.5 × 10⁻⁶ K. -6 The coefficient of thermal expansion of / K, the dielectric layer 114 of the capacitor can have a coefficient of approximately 5.6 × 10⁻⁶. -6 The coefficient of thermal expansion is approximately 10.3 × 10⁻⁶ K, and the capacitor electrode 116 can have a coefficient of thermal expansion of approximately 10.3 × 10⁻⁶ K. -6 The coefficient of thermal expansion is / K. However, other suitable coefficients of thermal expansion are also acceptable. In some embodiments, the capacitor edge width W ce and the internal width W of the capacitor ci These are all approximately 0.2-0.6 micrometers, approximately 0.2-0.4 micrometers, approximately 0.4-0.6 micrometers, approximately 0.4 micrometers, or approximately 0.3 micrometers. However, other suitable values ​​are also acceptable.

[0039] although Figure 1 The trench layout (e.g., Figure 1 The area occupied by the in-trench capacitor segment 106 is concentrated on the trench capacitor 102; however, it should be understood that the trench layout is applicable to other suitable devices using a metal-insulator-metal (MIM) structure with an in-trench segment. For example, dynamic random access memory (DRAM) devices and microelectromechanical systems (MEMS) devices can have such a MIM structure.

[0040] refer to Figure 2 Provided Figure 1Cross-sectional view 200 shows some alternative embodiments of the trench capacitor 102, wherein the trench capacitor 102 has additional in-trench capacitor segments 106 and additional substrate segments 110. For example, instead of five in-trench capacitor segments 106 and four substrate segments 110, the trench capacitor 102 may have seven in-trench capacitor segments 106 and six substrate segments 110. In other embodiments, the trench capacitor 102 may have N in-trench capacitor segments 106 and N-1 substrate segments 110, where N is an integer variable greater than 1.

[0041] refer to Figure 3 Provided Figure 2 The top layout 300 of some embodiments of the capacitor segment 106 within the trench. The top layout 300 may, for example, be along... Figure 2 Cut off axis A in the middle, and / or Figure 2 The cross-sectional view 200 can, for example, be along... Figure 3 The trench capacitor segment 106 and substrate segment 110 are cut off from axis A. The capacitor segment 106 and substrate segment 110 extend linearly and parallelly in a direction orthogonal or perpendicular to axis A. Furthermore, the substrate 104 extends in multiple closed paths, each independent of and surrounding the capacitor segment 106 within the trench. As a result, the capacitor segment 106 within the trench... Figure 3 The top layout of 300 is not connected.

[0042] refer to Figures 4A-4E Provided Figure 3 Some alternative embodiments of the top layout 400A-400E of the capacitor segment 106 within the trench. Any of the top layouts 400A-400E can, for example, be along... Figure 2 Cut off axis A in the middle, and / or Figure 2 The cross-sectional view 200 can, for example, be along... Figures 4A-4E The axis A of any one of them is cut off.

[0043] exist Figure 4A In this embodiment, the capacitor segments 106 within the trench are arranged in multiple rows. For example, the capacitor segments 106 within the trench may be arranged in two rows. In other embodiments, the capacitor segments 106 within the trench may be arranged in even more rows.

[0044] exist Figure 4B In the middle, the capacitor segment 106 in the trench is connected along the axis A in a serpentine trench pattern.

[0045] exist Figure 4C In the trench, capacitor segments 106 are connected in a pattern extending in multiple closed paths, each independent of and surrounding the substrate segment 110. As a result, the substrate segment 110... Figure 4C The top layout of 400C is not connected.

[0046] exist Figure 4DIn the trench, capacitor segments 106 are connected at their longitudinal center. The length of the capacitor segments 106 corresponds to the dimension along the direction in which the capacitor segments 106 extend parallel to each other. As mentioned above, this direction is orthogonal to or perpendicular to axis A.

[0047] exist Figure 4E In the trench, capacitor segments 106 are connected by a grid trench pattern. As a result, substrate segments 110 have multiple rows and columns, and the grid trench pattern extends in multiple closed paths, each independent of and surrounding the substrate segment 110. Furthermore, the grid trench pattern remains unchanged when rotated 90 degrees around its center, giving it rotational symmetry. Due to this rotational symmetry, Figure 2 The cross-sectional view 200 can also be taken along axis B, which is orthogonal to axis A.

[0048] refer to Figure 5 Provided Figure 2 Cross-sectional view 500 of some alternative embodiments of the trench capacitor 102, wherein the substrate edge width W se and substrate internal width W si The spacing P is uniform from the center of the trench capacitor 102 to its edge. Furthermore, the capacitor edge width W... ce Maintain a width greater than the internal width W of the capacitor ci This enhances stress absorption at the edges of the trench capacitor 102. As described above, this can mitigate substrate bending and / or trench depletion at the edges of the trench capacitor 102, and thus improve yield in mass production.

[0049] refer to Figure 6 Provided Figure 2 Cross-sectional view 600 of some alternative embodiments of the trench capacitor 102, wherein the capacitor edge width W ce and the internal width W of the capacitor ci Same. Furthermore, the substrate edge width W se Maintain a width greater than the inner width W of the substrate si This increases the stiffness at the edges of the trench capacitor 102. As described above, this can reduce substrate bending and / or trench depletion at the edges of the trench capacitor 102, and thus improve the yield of mass production.

[0050] refer to Figure 7 Provided Figure 2 Cross-sectional view 700 of some alternative embodiments of the trench capacitor 102, wherein the width W of each capacitor segment 106 within the trench is... c Along axis A, the width gradually increases from the center of trench capacitor 102 towards the edge of trench capacitor 102. Furthermore, the width W of each substrate segment 110...s Along axis A, the spacing P gradually increases from the center of trench capacitor 102 towards the edge of trench capacitor 102. In other words, the spacing P gradually increases along axis A from the center of trench capacitor 102 towards the edge of trench capacitor 102.

[0051] Concentrated on capacitor width W c Above, the width of the capacitor segment 106c in the central trench is smaller than the width of the first inner trench capacitor segment 106i1 adjacent to and disposed between the central trench capacitor segment 106c. The width of the first inner trench capacitor segment 106i1 is smaller than the width of the second inner trench capacitor segment 106i2 adjacent to and disposed between the first inner trench capacitor segment 106i1. The width of the second inner trench capacitor segment 106i2 is smaller than the width of the edge trench capacitor segment 106e adjacent to and disposed between the second inner trench capacitor segment 106i2. The capacitor width W of the first inner trench capacitor segment 106i1 is... c Similarly, the capacitor width W of capacitor segment 106i2 in the second internal trench is... c The same applies, and the capacitor width W of capacitor segment 106e within the edge trench is... c The same. In other embodiments, the capacitor width W of the capacitor segment 106i1 within the first internal trench is... c Unlike the second internal trench, the capacitor width W of capacitor segment 106i2 is... c The capacitor width W of the capacitor segment 106e within the edge trench is different. c Different, or any combination thereof.

[0052] Concentrated on substrate width W s Above, the width of the central substrate segment 110c is smaller than the width of the first inner substrate segment 110i1 that is adjacent to and disposed between the central substrate segment 110c. The width of the first inner substrate segment 110i1 is smaller than the width of the edge substrate segments 110e that are adjacent to and disposed between the first inner substrate segment 110i1. The substrate width W of the central substrate segment 110c s Similarly, the substrate width W of the first internal substrate segment 110i1 s The same applies to the substrate width W of the edge substrate segment 110e. s Same. In other embodiments, the substrate width W of the central substrate segment 110c is... s The difference lies in the substrate width W of the first internal substrate segment 110i1. s The substrate width W of the edge substrate segment 110e is different. sDifferent, or any combination thereof.

[0053] The in-trench capacitor segment 106 can have a larger coefficient of thermal expansion than the substrate segment 110, allowing the in-trench capacitor segment 106 to expand by a greater amount than the substrate segment 110 during high-temperature and / or high-pressure processes. As a result, the in-trench capacitor segment 106 can apply stress to the substrate segment 110. Due to the symmetry in the trench capacitor 102, the stress is neutral at the center of the trench capacitor 102. However, the stress increases along axis A from the center of the trench capacitor 102 towards the edge of the trench capacitor 102.

[0054] Because the substrate width W s The stiffness of the substrate segment 110 increases from the center to the edge of the trench capacitor 102, so the stiffness of the substrate segment 110 also increases from the center to the edge of the trench capacitor 102. As a result, the strength of the substrate segment 110 increases with increasing thermal expansion stress. This reduces the likelihood of the substrate segment 110 bending and further reduces the likelihood of trench exhaustion. Because the capacitor width W... c The gap 108 of the capacitor segment 106 within the trench increases from the center to the edge of the trench capacitor 102. The gap 108 promotes stress absorption, and the increased size of the gap 108 provides increased stress absorption with increasing thermal expansion stress. As a result, the substrate segment 110 is less prone to bending, and trench depletion at the capacitor segment 106 within the trench is reduced. This is because the increased capacitor width W... c and increased substrate width W s This reduces substrate bending and trench depletion, thus improving yield in mass production.

[0055] refer to Figure 8 Provided Figure 7 Cross-sectional view 800 of some alternative embodiments of the trench capacitor 102, wherein the substrate width W s The spacing P is uniform from the center of the trench capacitor 102 to its edge. Furthermore, the capacitor width W... c The trench capacitor 102 is progressively increased from its center toward its edge to enhance stress absorption when stress increases. As described above, this can mitigate substrate bending and / or trench depletion, and thus improve yield in mass production.

[0056] refer to Figure 9 Provided Figure 7 Cross-sectional view 900 of some alternative embodiments of the trench capacitor 102, wherein the capacitor width W c Same. However, substrate width Ws The stiffness is gradually increased from the center of the trench capacitor 102 towards its edge to enhance rigidity when stress increases. As described above, this can mitigate substrate bending and / or trench depletion, and thus improve yield in mass production.

[0057] refer to Figure 10 Provided Figure 2 Cross-sectional view 1000 of some alternative embodiments shows that the trench capacitor 102 is replaced by a plurality of trench capacitors 102 distributed on trench capacitor segments 106. From left to right, the trench capacitors 102 include two trench capacitor segments, one trench capacitor segment, three trench capacitor segments, and one trench capacitor segment, respectively. In alternative embodiments, more or less trench capacitors are distributed on the trench capacitor segments 106. Additionally, in alternative embodiments, the trench capacitors 102 include different numbers of trench capacitor segments.

[0058] refer to Figure 11 Provided Figure 2 Cross-sectional view 1100 of some alternative embodiments of the trench capacitor 102, wherein gap 108 is removed from capacitor segments 106e in the edge trench and capacitor segments 106i in the inner trench.

[0059] refer to Figure 12 Provided Figure 2 A cross-sectional view 1200 of some alternative embodiments of the trench capacitor 102 shows that a gap 108 is removed from the inner trench capacitor segment 106i, but still exists at the edge trench capacitor segment 106e. The gap 108 at the edge trench capacitor segment 106e helps to absorb stress at the edge of the trench capacitor 102 where stress is greatest.

[0060] refer to Figure 13 Provided Figure 2 A cross-sectional view 1300 of some alternative embodiments of the trench capacitor 102 is shown, wherein the trench capacitor 102 further includes a doped well 1302. The doped well 1302 corresponds to a doped semiconductor region of a p-type or n-type doped substrate 104. The doped well 1302 can then be used as an additional capacitor electrode to increase capacitance density. For example, the doped well 1302, the dielectric liner 112, and the bottom electrode of the capacitor electrode 116 can define a first capacitor, while the capacitor electrode 116 and the capacitor dielectric layer 114 can define a second capacitor. The first and second capacitors are electrically coupled in parallel by electrically coupling the top electrode of the doped well 1302 and the capacitor electrode 116 to a first terminal of the trench capacitor 102, and by electrically coupling the bottom electrode of the capacitor electrode 116 to a second terminal of the trench capacitor 102. Thus, the capacitance of the trench capacitor 102 is the sum of the capacitances of the first and second capacitors.

[0061] refer to Figure 14 Provided Figure 2 Cross-sectional view 1400 of some alternative embodiments of the trench capacitor 102, wherein the dielectric liner 112 covers the top of the substrate 104 with a width greater than that of the capacitor electrode 116 and the capacitor dielectric layer 114. Furthermore, the capacitor dielectric layer 114 and the bottom electrode of the capacitor electrode 116 share the same width.

[0062] refer to Figure 15 Provided Figure 2 Cross-sectional view 1500 shows some alternative embodiments of the trench capacitor 102, wherein the trench capacitor 102 includes additional capacitor electrodes 116 and additional capacitor dielectric layers 114. For example, instead of two capacitor electrodes 116 and one capacitor dielectric layer 114, the trench capacitor 102 may include four capacitor electrodes 116 and three capacitor dielectric layers 114. In other embodiments, the trench capacitor 102 may have M capacitor electrodes 116 and M-1 capacitor dielectric layers 114, where M is an integer variable greater than 1.

[0063] The capacitor electrode 116 and the capacitor dielectric layer 114 are in Figure 2 The following description is provided. Furthermore, capacitor electrodes 116 and capacitor dielectric layers 114 are alternately stacked above the dielectric substrate 112. The widths of the capacitor electrodes 116 and capacitor dielectric layers 114 decrease from the bottom to the top of the trench capacitor 102. Additionally, in some embodiments, each capacitor dielectric layer has substantially the same width as the adjacent upper capacitor electrode. In other embodiments, each capacitor dielectric layer has substantially the same width as the adjacent lower capacitor electrode.

[0064] Although Figure 3 and Figures 4A-4E Described about Figure 2 The top layout of the capacitor segment 106 within the trench, however it should be understood, can be applied to Figures 5-15 Any one of them. For example, Figure 7 The capacitor section 106 within the trench can be as follows: Figure 4B The arrangement is in the form of a serpentine groove pattern. Although Figures 5-9 Described Figure 2 Variations of these designs, in which the groove pattern changes, should be understood that these variations can be applied to... Figure 3 , Figures 4A-4E and Figures 10-15 Any one of them. Although Figure 10 Described Figure 2 A variation thereof, in which multiple trench capacitors 102 are used instead of trench capacitors 102, but it should be understood that this variation can be applied to Figure 3 , Figures 4A-4E , Figures 5-9 and Figures 11-15 Any one of them. Although Figures 11-15 Described Figure 2 Variations in which components are removed or added, but it should be understood that any one or combination of variations may be applied to Figure 3 , Figures 4A-4E and Figures 5-10 Any one of them. For example, as about Figure 11 As described, from Figure 5 Remove gap 108 in the middle.

[0065] refer to Figure 16 It provides including Figure 2 A cross-sectional view 1600 of some embodiments of the IPD package of the trench capacitor 102 is shown. An interconnect structure 1602 covers and is electrically coupled to the trench capacitor 102. The interconnect structure 1602 includes a plurality of contacts 1604 and a plurality of leads 1606. The contacts 1604 and leads 1606 correspond to capacitor electrodes 116, and the contacts 1604 extend from the leads 1606 to the capacitor electrodes 116, respectively. The contacts 1604 and leads 1606 are or comprise metal and / or some other suitable conductive material. In an alternative embodiment, a plurality of additional leads and a plurality of vias are alternately stacked over and electrically coupled to the contacts 1604.

[0066] A dielectric structure surrounds the contact 1604 and the conductor 1606. The dielectric structure includes an interlayer dielectric (ILD) layer 1608, an intermetallic dielectric (IMD) layer 1610, a passivation layer 1612, and a plurality of etch stop layers 1614. The passivation layer 1612 covers the IMD layer 1610 and the conductor 1606, and is separated from the IMD layer 1610 by corresponding etch stop layers 1614. Furthermore, the passivation layer 1612 defines an opening 1616, which is independent of and exposes the conductor 1606 separately. The IMD layer 1610 surrounds the ILD layer 1608 and the conductor 1606 above the contact 1604. Furthermore, the IMD layer 1610 is separated from the ILD layer 1608 by corresponding etch stop layers 1614. The ILD layer 1608 surrounds the contact 1604 above the trench capacitor 102. Furthermore, the ILD layer 1608 is separated from the trench capacitor 102 by a corresponding etch stop layer 1614. The etch stop layer 1614 is a dielectric and can be a different material type from the adjacent upper dielectric layer. For example, the material type of the etch stop layer on top of the etch stop layer 1614 is different from that of the passivation layer 1612.

[0067] The hard mask 1618 and the cap structure 1620 are located below the dielectric structure and on the top electrode of the capacitor electrode 116. The cap structure 1620 is located between the hard masks 1618 and partially fills the gap 108 of the trench capacitor 102. In an alternative embodiment, the cap structure 1620 completely fills the gap 108.

[0068] In some embodiments, the cover structure 1620 is a dielectric. For example, the cover structure 1620 may be silicon oxide and / or some other suitable dielectric. In other embodiments, the cover structure 1620 is conductive. For example, the cover structure 1620 may be or include pure / elemental titanium, some other suitable metals, metallic materials, titanium nitride, tantalum nitride, some other suitable metal nitrides, some other suitable conductive materials, or any combination thereof. In some embodiments, the hard mask 1618 is or includes silicon nitride, silicon oxide, polymers, bottom anti-reflective coating (BARC), some other suitable hard mask materials, or any combination thereof.

[0069] refer to Figure 17 It provides including Figure 16 A cross-sectional view 1700 shows some embodiments of an integrated fan-out package-on-package (InFO-PoP) structure of an IPD package (hereinafter referred to as 1702). The IPD package 1702 is located on the bottom side of an integrated fan-out structure 1704 having a first bump array 1708. As a result, the trench capacitor 102 of the IPD package 1702 can also be referred to as a pad-side capacitor (LSC).

[0070] The integrated fan-out structure 1704 includes a molding compound 1710, a through-hole 1712, and a plurality of redistribution layers (RDLs) 1714. The molding compound 1710 is adjacent to the first IC chip package 1716 on a sidewall, and the RDLs 1714 are located between a first bump array 1708 and the first IC chip package 1716. The first IC chip package 1716 may be, for example, a system-on-a-chip (SoC) package or some other suitable type of IC chip package. The through-hole 1712 extends from the corresponding RDL through the molding compound 1710 to a second bump array 1718 on the upper side of the integrated fan-out structure 1704. The RDLs 1714 are located in the fan-out dielectric layer 1720 and define conductive paths that interconnect the first bump array 1708, the through-hole 1712, the pads 1722, and the IPD package 1702 of the first IC chip package 1716. The IPD package 1702 can be electrically coupled to the corresponding RDL, for example, through the conductive material 1724.

[0071] The second IC chip package 1726 covers and is electrically coupled to the integrated fan-out structure 1704 via the second bump array 1718. The second IC chip package 1726 has a larger size than the first IC chip package 1716 and may be, for example, a DRAM chip package, some other suitable type of memory chip package, or some other suitable type of IC chip package.

[0072] refer to Figure 18 It provides including Figure 2 A cross-sectional view 1800 shows some embodiments of the insert for the trench capacitor 102. The insert includes an interposer 1802, an interposer interconnect structure 1804, and a substrate through-hole (TSV) 1806. The interposer 1802 accommodates the TSV 1806 and the trench capacitor 102. Furthermore, the interposer 1802 is located below the interposer interconnect structure 1804. The interposer 1802 may be, for example, or comprise a bulk silicon substrate or some other suitable type of substrate.

[0073] Intermediate interconnect structure 1804 is located on and electrically coupled to TSV 1806 and trench capacitor 102. Intermediate interconnect structure 1804 includes multiple conductors 1808 and multiple vias 1810. Conductors 1808 and vias 1810 are alternately stacked to define conductive paths leading out from TSV 1806 and trench capacitor 102. Furthermore, conductors 1808 and vias 1810 are alternately stacked in an intermediate dielectric layer 1812. Intermediate dielectric layer 1812 defines openings 1814, which are independent of and respectively expose the top conductors of intermediate interconnect structure 1804.

[0074] refer to Figure 19 It provides including Figure 18 Cross-sectional view 1900 of some embodiments of the chip-on-wafer (CoWoS) package with insert (hereinafter referred to as 1902) on the substrate. Note that... Figure 19 An enlarged view of insert 1902 is provided, wherein insert 1902 includes a plurality of TSVs 1806 and a plurality of trench capacitors 102. Figure 18 This could be, for example, a part of insert 1902 within box C.

[0075] Insert 1902 covers package substrate 1904 and is electrically coupled to it via a first bump array 1906. Furthermore, insert 1902 is located beneath a pair of IC chip packages 1908 and is electrically coupled to them via a second bump array 1910. The IC chip packages 1908 may correspond, for example, to SoC packages and DRAM packages. Alternatively, one or both of the IC chip packages 1908 may correspond to other suitable types of IC packages. Package substrate 1904 includes multiple conductive traces 1912 that define conductive paths from the first bump array 1906 to the third bump array 1914 on the underside of package substrate 1904.

[0076] Although using Figure 2 An embodiment of the trench capacitor 102 is shown. Figures 16-19 However, alternatives can be used. Figures 5-15 An embodiment of any one of the trench capacitors 102. In other words, Figures 16-19 Any one of the trench capacitors 102 can be Figures 5-15 Replace any one of the trench capacitors 102.

[0077] refer to Figures 20-31 A series of cross-sectional views 2000-3100 are provided for some embodiments of a method for forming a trench capacitor with a trench pattern for improving yield. Using Figure 15 An embodiment of a trench capacitor illustrates this method. However, this method can also be used to form... Figure 1 , Figure 2 , Figure 3 , Figures 4A-4E and Figures 5-14 Any of the trench capacitor embodiments or other suitable embodiments of trench capacitors.

[0078] like Figure 20 As shown in cross-sectional view 2000, substrate 104 is patterned using trench pattern 2002 to form a plurality of trench segments 2004 and a plurality of substrate segments 110. In some embodiments, the trench segments 2004 are disconnected outside cross-sectional view 2000 and can be considered as independent trenches. In other embodiments, the trench segments 2004 are connected outside cross-sectional view 2000 and can be considered as part of a common trench. Substrate 104 can be, for example, a bulk silicon substrate, a bulk oxide substrate, or some other suitable type of substrate.

[0079] In some embodiments, the process for patterning the substrate 104 includes: 1) forming a hard mask 2006 over the substrate 104 using a trench pattern 2002; and 2) etching the substrate 104 while the hard mask 2006 is in place. However, other processes may also be used to pattern the substrate 104. In some embodiments, the process for forming the hard mask 2006 includes: 1) depositing a hard mask layer over the substrate 104; 2) forming a photoresist mask over the hard mask layer using photolithography; 3) etching the hard mask layer while the photoresist mask is in place; and 4) removing the photoresist mask after etching. However, other processes may be used to form the hard mask 2006.

[0080] Trench segments 2004 are laterally separated along axis A at a spacing P and extend into the top of substrate 104. In some embodiments, the depth D of trench segments 2004 extending into substrate 104 is about 1-30 micrometers, about 1-15 micrometers, about 15-30 nanometers, or other suitable values. Similar to trench segments 2004, substrate segments 110 are laterally separated along axis A. Furthermore, substrate segments 110 protrude between trench segments 2004 or extend upward to separate trench segments 2004. For example, the trench segments in each pair of adjacent trench segments can be separated by the corresponding substrate segments.

[0081] In some embodiments, the top layout of the groove pattern 2002 is as follows: Figure 3 and Figures 4A-4E Any one of them is shown. It should be understood that groove pattern 2002 corresponds to Figure 3 and Figures 4A-4E The area occupied by the trench capacitor 102 in the middle. Therefore, the trench pattern 2002 can have, for example, as shown in the figure. Figure 3 The multiple parallel lines shown. As another example, the groove pattern 2002 can be as follows: Figure 4B and Figure 4E The shape shown is either serpentine or grid-like.

[0082] The plurality of groove segments 2004 include a pair of edge groove segments 2004e and a plurality of inner groove segments 2004i. The edge groove segments 2004e are located on opposite edges of the groove pattern 2002, and the inner groove segments 2004i are located between the edge groove segments 2004e. The edge groove segments 2004e have individual groove edge widths W. te The internal groove section 2004i has a separate internal groove width W. ti Less than the width W of the trench edge te The width W of the trench edge te The same, and the internal width W of the trench ti Same. In other embodiments, the trench edge width W te Different, and / or the internal width W of the trench tiDifferent. For example, the internal width W of the trench. ti The groove pattern 2002 can gradually increase in size from its center toward its edge. Figure 7 and Figure 8 An example of this gradual increase is provided, in which the trench pattern 2002 corresponds to the area occupied by the capacitor segment 106 within the trench.

[0083] The plurality of substrate segments 110 includes a pair of edge substrate segments 110e and a plurality of inner substrate segments 110i. The edge substrate segments 110e are located between and adjacent to the capacitor segments 106e within the edge trench, and the inner substrate segments 110i are located between the edge substrate segments 110e. The edge substrate segments 110e have a respective substrate edge width W. se Furthermore, the inner substrate segment 110i has a width W smaller than the substrate edge width. se The internal width W of each substrate si Substrate edge width W se The same, and the substrate internal width W si Same. In other embodiments, the substrate edge width W se Different and / or substrate internal width W si Different. For example, the width W inside the substrate. si The groove pattern 2002 can gradually increase in size from its center toward its edge. Figure 7 and Figure 9 This gradually increasing example is provided, where the trench pattern 2002 corresponds to the region occupied by the capacitor segment 106 within the trench. Because the substrate edge width W... se Greater than the inner width W of the substrate si Therefore, the spacing P at the edge substrate segment 110e is larger than that at the inner substrate segment 110i. The spacing P at the edge substrate segment 110e is the same as that at the inner substrate segment 110i. In other embodiments, the spacing P at the edge substrate segment 110e is different and / or different from that at the inner substrate segment 110i.

[0084] As described above, the trench pattern 2002 makes the substrate edge width W se Greater than the inner width W of the substrate si And the width W of the groove edge te Greater than the internal width W of the trench ti However, in an alternative embodiment, the substrate edge width W se With substrate internal width W si Same, or the width W of the trench edge te With the inner width W of the trench ti same. Figure 5 and Figure 6A non-limiting example is provided, wherein the trench pattern 2002 corresponds to the area occupied by the capacitor segment 106 within the trench.

[0085] like Figure 21 As shown in the cross-sectional view 2100, the hard mask 2006 is removed (for example, see...). Figure 20 Removal can be performed, for example, by etching or some other suitable removal process.

[0086] Also through Figure 21 Cross-sectional view 2100 shows a deposited dielectric liner 112 covering the substrate 104 and further lining and partially filling the trench segment 2004. In some embodiments, the dielectric liner 112 is or includes silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination thereof. The dielectric liner 112 can be formed, for example, by vapor deposition, thermal oxidation, some other suitable deposition process, or any combination thereof.

[0087] like Figure 22 As shown in cross-sectional view 2200, multiple electrode dielectric layers 2202 and multiple electrode layers 2204 are deposited. Electrode dielectric layers 2202 and electrode layers 2204 are alternately deposited and stacked above the dielectric liner 112. Furthermore, electrode dielectric layers 2202 and electrode layers 2204 deposit and line and partially fill the remaining portion of the trench segment 2004. Because the electrode dielectric layers 2202 and electrode layers 2204 partially fill the remaining portion of the trench segment 2004, gaps 108 are retained in the trench segment 2004. Gap 108 corresponds to the unfilled portion of the trench segment 2004 and may also be referred to as an air gap, void, cavity, or other suitable name. Electrode dielectric layers 2202 and electrode layers 2204 can be formed, for example, by vapor deposition and / or some other suitable deposition process.

[0088] In some embodiments, the electrode dielectric layer 2202 is or includes silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination thereof. The high-k dielectric can be or includes, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, titanium oxide, some other suitable high-k dielectric, or any combination thereof. In some embodiments, the electrode layer 2204 is or includes titanium nitride, tantalum nitride, aluminum copper, some other suitable conductive materials and / or metals, or any combination thereof.

[0089] The dielectric liner 112, electrode dielectric layer 2202, and electrode layer 2204 define a plurality of in-trench capacitor segments 106. The in-trench capacitor segments 106 are independent of and respectively located within the trench segment 2004. Furthermore, the in-trench capacitor segments 106 are arranged according to the trench pattern 2002, and in some embodiments have, as shown in... Figure 3 and Figures 4A-4EAny of the top layouts shown. For example, the in-trench capacitor segment 106 can have, as shown in the example... Figure 4B The serpentine outline shown.

[0090] The capacitor segment 106 within the trench can have a larger coefficient of thermal expansion than the substrate segment 110, allowing the capacitor segment 106 to expand by a greater amount than the substrate segment 110 during high-temperature and / or high-pressure processes. As a result, the capacitor segment 106 within the trench can apply stress to the substrate segment 110. Due to the symmetry in the trench pattern 2002, the stress is neutral at the center of the trench pattern 2002. However, the stress increases along axis A from the center of the trench pattern 2002 towards the edge of the trench pattern 2002.

[0091] Such as about Figure 20 In this discussion, the width of the substrate segment 110 at the edge of the trench pattern 2002 is greater than the width of the substrate segment 110 inside the trench pattern 2002. For example, compare... Figure 20 Edge substrate segment 110e and Figure 20 The inner substrate segment 110i. Because the width of the substrate segment 110 at the edge of the trench pattern 2002 is greater than the width of the substrate segment 110 inside the trench pattern 2002, the substrate segment 110 at the edge of the trench pattern 2002 has greater stiffness than the substrate segment 110 inside the trench pattern 2002. Since the stress is greatest at the edge of the trench pattern 2002, the greater stiffness reduces the possibility of bending of the substrate segment 110 at the edge of the trench pattern 2002. This, in turn, reduces the possibility of trench exhaustion and improves the manufacturing yield.

[0092] In addition, such as regarding Figure 20 In this discussion, the width of the groove segment 2004 at the edge of the groove pattern 2002 is greater than the width of the groove segment 2004 inside the groove pattern 2002. For example, compare... Figure 20 Edge groove section 2004e and Figure 20 The internal trench segment 2004i. Because the width of the trench segment 2004 at the edge of the trench pattern 2002 is greater than the width of the trench segment 2004 inside the trench pattern 2002, the gap 108 at the edge of the trench pattern 2002 is greater than the gap 108 inside the trench pattern 2002. The gap 108 promotes stress absorption, and the larger gap at the edge of the trench pattern 2002 provides increased stress absorption at the edge of the trench pattern 2002 where the stress is greatest. As a result, the substrate segment 110 at the edge of the trench pattern 2002 is less prone to bending, and the possibility of trench exhaustion at the edge of the trench pattern 2002 is reduced. This, in turn, improves the manufacturing yield.

[0093] like Figure 23As shown in cross-sectional view 2300, a capping layer 2302 is deposited. The capping layer 2302 is deposited to cover the electrode dielectric layer 2202 and the electrode layer 2204. Furthermore, the capping layer 2302 is deposited to fill the gap 108 (e.g., see...). Figure 22 In some embodiments, the capping layer 2302 completely fills the gap 108. In other embodiments, the capping layer 2302 only partially fills the gap 108.

[0094] In some embodiments, capping layer 2302 is a dielectric. For example, capping layer 2302 may be silicon oxide and / or some other suitable dielectric. In some embodiments where capping layer 2302 is a dielectric, capping layer 2302 is deposited by atomic layer deposition (ALD) or some other suitable deposition process. In other embodiments, capping layer 2302 is conductive. For example, capping layer 2302 may be or include pure / elemental titanium, some other suitable metals, metallic materials, titanium nitride, tantalum nitride, some other suitable metal nitrides, some other suitable conductive materials, or any combination thereof. In some embodiments where capping layer 2302 is conductive, capping layer 2302 is deposited by metal-organic chemical vapor deposition (MOCVD) or some other suitable deposition process.

[0095] like Figure 24 As shown in cross-sectional view 2400, the capping layer 2302 is patterned to form a cap structure 1620 located above the trench pattern 2002. In some embodiments, the process for patterning the capping layer 2302 includes: 1) forming a photoresist mask 2402 over the capping layer 2302 by photolithography; 2) etching the capping layer 2302 while the photoresist mask 2402 is in place; and 3) removing the photoresist mask 2402. However, other processes are also possible.

[0096] like Figure 25 As shown in cross-sectional view 2500, a hard mask layer 2502 is deposited over the cap structure 1620, the electrode dielectric layer 2202, and the electrode layer 2204. The hard mask layer 2502 may be or include, for example, silicon nitride, silicon oxide, silicon carbide, BARC, some other suitable hard mask material, or any combination thereof. The hard mask layer 2502 may be formed, for example, by vapor deposition, spin coating, or some other suitable deposition process. In some embodiments, the hard mask layer 2502 is or includes BARC and is deposited by spin coating such that the top surface of the hard mask layer 2502 is horizontal under gravity.

[0097] like Figure 26As shown in cross-sectional view 2600, the hard mask layer 2502, the top electrode layer of the electrode layer 2204, and the top dielectric layer of the electrode dielectric layer 2202 are patterned together. The patterning forms a hard mask 1618, a capacitor electrode 116, and a capacitor dielectric layer 114. The hard mask 1618 covers the cover structure 1620. The capacitor electrode 116 is located below the hard mask 1618 and the cover structure 1620, and the capacitor dielectric layer 114 is located below the capacitor electrode 116. In some embodiments, the process for performing the patterning includes: 1) forming a photoresist mask 2602 over the hard mask layer 2502 using photolithography; 2) etching the hard mask layer 2502, the top electrode layer of the electrode layer 2204, and the top dielectric layer of the electrode dielectric layer 2202 while the photoresist mask 2602 is in place; and 3) removing the photoresist mask 2602. However, other processes are also possible.

[0098] If passed Figures 27-29 As shown in cross-sectional views 2700-2900, the remaining portions of electrode dielectric layer 2202, electrode layer 2204, and dielectric substrate 112 are patterned sequentially from top to bottom. The remaining electrode layers are patterned together with the adjacent lower electrode dielectric layer. Furthermore, dielectric substrate 112 is patterned together with the adjacent upper electrode layer. In an alternative embodiment, dielectric substrate 112 is not patterned but used as an etch stop layer for the adjacent upper electrode layer. Patterning localizes dielectric substrate 112 to trench pattern 2002 and forms additional capacitor electrodes 116 and additional capacitor dielectric layers 114 alternately stacked above dielectric substrate 112.

[0099] In some embodiments, patterning the remaining electrode layer and the adjacent underlying dielectric layer includes: 1) forming a photoresist mask over the electrode layer using photolithography; 2) etching the electrode layer and dielectric layer with the photoresist mask in place; and 3) removing the photoresist mask. However, other processes are also possible. Examples of photoresist masks include... Figure 27 First photoresist mask 2702 Figure 28 The second photoresist mask 2802 and Figure 29 The third photoresist mask 2902.

[0100] After completion Figures 26-29 After patterning, multiple capacitor dielectric layers 114 and multiple capacitor electrodes 116 are retained. The capacitor dielectric layers 114 and capacitor electrodes 116 are stacked alternately and define a trench capacitor 102 including an in-trench capacitor segment 106. Furthermore, in Figures 26-29 While patterning each electrode layer together with the adjacent lower electrode dielectric layer, each electrode layer can be patterned together with the adjacent upper electrode dielectric layer alternately.

[0101] like Figure 30 As shown in cross-sectional view 3000, a pair of contact etch stop layers 1614c are deposited above the trench capacitor 102. In an alternative embodiment, more contact etch stop layers are deposited. In an alternative embodiment, only one contact etch stop layer is deposited. The contact etch stop layers 1614c are different dielectric materials and may include, for example, oxides, silicon nitride, some other suitable dielectrics, or any combination thereof. In some embodiments, the bottom contact etch stop layer of the contact etch stop layer 1614c is silicon oxide, while the top contact etch stop layer of the contact etch stop layer 1614c is silicon nitride. However, other suitable materials are also possible. The contact etch stop layers 1614c may be formed, for example, by vapor deposition and / or some other suitable deposition process.

[0102] like Figure 31 As shown in cross-sectional view 3100, an interconnect structure 1602 is formed above the contact etch stop layer 1614c. The interconnect structure 1602 includes a plurality of contacts 1604, a plurality of wires 1606, and a plurality of vias 3102. The contacts 1604 extend from the capacitor electrode 116, and the wires 1606 and vias 3102 are alternately stacked above and electrically coupled to the contacts 1604.

[0103] A dielectric structure surrounds the contact 1604, the conductor 1606, and the via 3102. The dielectric structure includes an ILD layer 1608, multiple IMD layers 1610, a passivation layer 1612, and multiple etch stop layers 1614. The passivation layer 1612 covers the conductor 1606 and defines an opening 1616 exposing the top conductor. The IMD layers 1610 are located beneath the passivation layers 1612 and surround the conductor 1606 and the via 3102. The ILD layer 1608 is located beneath the IMD layers 1610 and surrounds the contact 1604. The etch stop layers 1614 separate the ILD layers 1608, IMD layers 1610, and passivation layers 1612 from each other.

[0104] Although the reference method describes Figures 20-31 However, it should be understood that Figures 20-31 The structure shown is not limited to this method, but can be used independently of it. Furthermore, although Figures 20-31 The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some actions illustrated and / or described may be omitted entirely or in part.

[0105] refer to Figure 32 Provided Figures 20-31 A block diagram 3200 shows some embodiments of the method.

[0106] At 3202, the substrate is patterned to form a trench pattern in the substrate, wherein the trench pattern includes a plurality of trench segments spaced apart along an axis, wherein the plurality of trench segments include edge trench segments and a center trench segment located respectively at the edge and center of the trench pattern, and wherein the width of the edge trench segments is greater than the width of the center trench segments and / or the spacing at the edge trench segments is greater than the spacing at the center trench segments. See, for example. Figure 20 .

[0107] At 3204, a dielectric liner, a lower electrode layer, an electrode dielectric layer, and an upper electrode layer are stacked and deposited on top of the substrate, and the trench segment is further linerred and partially filled. See, for example, [link to relevant documentation]. Figure 21 and Figure 22 .

[0108] At 3206, a cap structure is formed above and electrically coupled to the upper electrode layer, wherein the cap structure seals or fills the unfilled portion of the trench segment. See, for example, [link to relevant documentation]. Figure 23 and Figure 24 .

[0109] At 3208, a hard mask layer is deposited to cover the cap structure and the upper electrode layer. See, for example, [link to example]. Figure 25 .

[0110] At 3210, the hard mask layer, upper electrode layer, and capacitor dielectric layer are patterned together using a common pattern to form the hard mask, upper capacitor electrode, and capacitor dielectric layer. See, for example, [link to documentation]. Figure 26 .

[0111] At 3212, the lower electrode layer is patterned to form a lower capacitor electrode located below the upper capacitor electrode. See, for example, [reference needed]. Figures 27-29 As described at 3210, the capacitor dielectric layer and the upper electrode layer are patterned together using a common pattern. In an alternative embodiment, the capacitor dielectric layer and the lower electrode layer are patterned together using a common pattern.

[0112] At position 3214, a contact etch stop layer is deposited above the upper and lower capacitor electrodes. See, for example, [link to example]. Figure 30 .

[0113] At 3216, an interconnect structure is formed above the contact etch stop layer. This interconnect structure includes multiple contacts, multiple wires, and multiple vias. The contacts extend from the lower capacitor electrode and the upper capacitor electrode, respectively, and the wires and vias are alternately stacked above and electrically coupled to the contacts. See, for example, [link to example]. Figure 31 .

[0114] Although this article will Figure 32Block diagram 3200 illustrates and describes a series of actions or events; however, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, it is not required that all actions shown are used to implement one or more aspects or embodiments described herein, and one or more actions shown herein may be performed in one or more separate actions and / or phases.

[0115] In some embodiments, this disclosure provides an integrated chip, comprising: a substrate; and a trench capacitor located on the substrate, and including a plurality of capacitor segments extending into the substrate; wherein the plurality of capacitor segments include edge capacitor segments located at the edges of the trench capacitor and a center capacitor segment located at the center of the trench capacitor, the capacitor segments being spaced apart on an axis by a spacing, and the width of the edge capacitor segments being greater than the width of the center capacitor segments and / or the spacing at the edge capacitor segments being greater than the spacing at the center capacitor segments. In some embodiments, the width of the edge capacitor segments is greater than the width of the center capacitor segments, and the spacing at the edge capacitor segments is greater than the spacing at the center capacitor segments. In some embodiments, the width of the edge capacitor segments is greater than the width of the center capacitor segments, wherein the spacing is uniform from the edge capacitor segments to the center capacitor segments. In some embodiments, the width of the edge capacitor segments is the same as the width of the center capacitor segments, wherein the spacing at the edge capacitor segments is greater than the spacing at the center capacitor segments. In some embodiments, the plurality of capacitor segments includes an intermediate capacitor segment located between the edge capacitor segments and the center capacitor segments, wherein the width of the edge capacitor segments is greater than the width of the intermediate capacitor segments, and wherein the width of the intermediate capacitor segments is greater than the width of the center capacitor segments. In some embodiments, the plurality of capacitor segments includes an intermediate capacitor segment located between an edge capacitor segment and a center capacitor segment, wherein the spacing between the edge capacitor segment and the intermediate capacitor segment is greater than the spacing between the intermediate capacitor segment and the center capacitor segment. In some embodiments, the capacitor segments have a linear top arrangement.

[0116] In some embodiments, this disclosure provides an integrated chip, comprising: a substrate including a first substrate segment and a second substrate segment; and a trench capacitor located on the substrate, including a central capacitor segment, an intermediate capacitor segment, and an edge capacitor segment; wherein the central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment extend into the substrate, the central capacitor segment and the edge capacitor segment are respectively located at the center of the trench capacitor and the edge of the trench capacitor, the intermediate capacitor segment is located between the central capacitor segment and the edge capacitor segment, the first substrate segment and the second substrate segment respectively separate the intermediate capacitor segment from the central capacitor segment and the edge capacitor segment, and the width of the edge capacitor segment is greater than the width of the central capacitor segment and / or the width of the second substrate segment is greater than the width of the first substrate segment. In some embodiments, the width of the intermediate capacitor segment is the same as the width of the central capacitor segment, wherein the width of the edge capacitor segment is greater than the width of the central capacitor segment. In some embodiments, the width of the intermediate capacitor segment is greater than the width of the central capacitor segment, wherein the width of the edge capacitor segment is greater than the width of the intermediate capacitor segment. In some embodiments, the width of the second substrate segment is greater than the width of the first substrate segment. In some embodiments, the central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment at least partially define a serpentine pattern in the substrate. In some embodiments, the central capacitor segment, intermediate capacitor segment, and edge capacitor segment partially define a grid pattern in the substrate. In some embodiments, the trench capacitor includes a plurality of capacitor electrodes and a plurality of capacitor dielectric layers, wherein the capacitor electrodes and capacitor dielectric layers are recessed into the substrate at the central capacitor segment, intermediate capacitor segment, and edge capacitor segment, and wherein the capacitor electrodes and capacitor dielectric layers surround the top of the first substrate segment and the second substrate segment.

[0117] In some embodiments, this disclosure provides a method for forming a trench capacitor, the method comprising: patterning a substrate to form a trench pattern in the substrate, wherein the trench pattern includes a plurality of trench segments spaced apart along an axis, wherein the plurality of trench segments include edge trench segments and a central trench segment located at the edge and center of the trench pattern, respectively, and wherein the width of the edge trench segments is greater than the width of the central trench segment and / or the spacing at the edge trench segments is greater than the spacing at the central trench segments; stacking and depositing a lower electrode layer, an electrode dielectric layer and an upper electrode layer over the substrate, and backing the trench segments, wherein a dielectric electrode layer is located between the lower electrode layer and the upper electrode layer; and patterning the lower electrode layer, the upper electrode layer and the dielectric electrode layer to form a plurality of capacitor electrodes and a capacitor dielectric layer, respectively. In some embodiments, the edge trench segments and the central trench segments have a linear top arrangement that extends parallel to each other in a direction perpendicular to the axis. In some embodiments, the width of the edge trench segments is greater than the width of the central trench segment, and the spacing at the edge trench segments is greater than the spacing at the central trench segments. In some embodiments, the plurality of trench segments includes additional edge trench segments spaced apart from the central trench segment along an axis on the side of the central trench segment opposite to the edge trench segments, wherein the edge trench segments and the additional edge trench segments have the same width. In some embodiments, the plurality of trench segments includes an intermediate trench segment located on an axis between the edge trench segments and the central trench segment, wherein the width of the intermediate trench segment is greater than the width of the central trench segment, and wherein the width of the edge trench segments is greater than the width of the intermediate trench segment. In some embodiments, the plurality of trench segments includes an intermediate trench segment located on an axis between the edge trench segments and the central trench segment, wherein the width of the intermediate trench segment is the same as the width of the central trench segment, and wherein the width of the edge trench segments is greater than the width of the intermediate trench segment.

[0118] Embodiments of this application provide an integrated chip, including: a substrate; and a trench capacitor located on the substrate, comprising a plurality of capacitor segments extending into the substrate; wherein the plurality of capacitor segments include edge capacitor segments located at the edges of the trench capacitor and a center capacitor segment located at the center of the trench capacitor, the capacitor segments being spaced apart along an axis, and the width of the edge capacitor segments being greater than the width of the center capacitor segments and / or the spacing at the edge capacitor segments being greater than the spacing at the center capacitor segments. In some embodiments, the width of the edge capacitor segments is greater than the width of the center capacitor segments, and the spacing at the edge capacitor segments is greater than the spacing at the center capacitor segments. In some embodiments, the width of the edge capacitor segments is greater than the width of the center capacitor segments, and wherein the spacing is uniform from the edge capacitor segments to the center capacitor segments. In some embodiments, the width of the edge capacitor segments is the same as the width of the center capacitor segments, and wherein the spacing at the edge capacitor segments is greater than the spacing at the center capacitor segments. In some embodiments, the plurality of capacitor segments includes an intermediate capacitor segment located between the edge capacitor segments and the center capacitor segment, wherein the width of the edge capacitor segment is greater than the width of the intermediate capacitor segment, and wherein the width of the intermediate capacitor segment is greater than the width of the center capacitor segment. In some embodiments, the plurality of capacitor segments includes an intermediate capacitor segment located between the edge capacitor segments and the center capacitor segment, wherein the spacing between the edge capacitor segments and the intermediate capacitor segment is greater than the spacing between the intermediate capacitor segment and the center capacitor segment. In some embodiments, the capacitor segments have a linear top arrangement.

[0119] Embodiments of this application provide an integrated chip, comprising: a substrate including a first substrate segment and a second substrate segment; and a trench capacitor located on the substrate, including a central capacitor segment, an intermediate capacitor segment, and an edge capacitor segment; wherein the central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment extend into the substrate, the central capacitor segment and the edge capacitor segment are respectively located at the center and the edge of the trench capacitor, the intermediate capacitor segment is located between the central capacitor segment and the edge capacitor segment, the first substrate segment and the second substrate segment respectively separate the intermediate capacitor segment from the central capacitor segment and the edge capacitor segment, and the width of the edge capacitor segment is greater than the width of the central capacitor segment and / or the width of the second substrate segment is greater than the width of the first substrate segment. In some embodiments, the width of the intermediate capacitor segment is the same as the width of the central capacitor segment, and wherein the width of the edge capacitor segment is greater than the width of the central capacitor segment. In some embodiments, the width of the intermediate capacitor segment is greater than the width of the central capacitor segment, and wherein the width of the edge capacitor segment is greater than the width of the intermediate capacitor segment. In some embodiments, the width of the second substrate segment is greater than the width of the first substrate segment. In some embodiments, the central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment at least partially define a serpentine pattern in the substrate. In some embodiments, the central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment partially define a grid pattern in the substrate. In some embodiments, the trench capacitor includes a plurality of capacitor electrodes and a plurality of capacitor dielectric layers, wherein the capacitor electrodes and the capacitor dielectric layers are recessed into the substrate at the central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment, and wherein the capacitor electrodes and the capacitor dielectric layers surround the top of the first substrate segment and the second substrate segment.

[0120] Embodiments of this application also provide a method for forming a trench capacitor, the method comprising: patterning a substrate to form a trench pattern in the substrate, wherein the trench pattern includes a plurality of trench segments spaced apart along an axis, wherein the plurality of trench segments include edge trench segments and a central trench segment located at the edge and center of the trench pattern, respectively, and wherein the width of the edge trench segments is greater than the width of the central trench segment and / or the spacing at the edge trench segments is greater than the spacing at the central trench segments; stacking and depositing a lower electrode layer, an electrode dielectric layer and an upper electrode layer over the substrate, and backing the trench segments, wherein the electrode dielectric layer is located between the lower electrode layer and the upper electrode layer; and patterning the lower electrode layer, the upper electrode layer and the electrode dielectric layer to form a plurality of capacitor electrodes and capacitor dielectric layers, respectively. In some embodiments, the edge trench segments and the central trench segments have a top arrangement of linear extensions parallel to each other in a direction perpendicular to the axis. In some embodiments, the width of the edge groove segments is greater than the width of the central groove segment, and the spacing at the edge groove segments is greater than the spacing at the central groove segments. In some embodiments, the plurality of groove segments includes additional edge groove segments spaced apart from the central groove segment along the axis and on the side of the central groove segment opposite to the edge groove segments, wherein the edge groove segments and the additional edge groove segments have the same width. In some embodiments, the plurality of groove segments includes an intermediate groove segment located on the axis between the edge groove segments and the central groove segment, wherein the width of the intermediate groove segment is greater than the width of the central groove segment, and wherein the width of the edge groove segments is greater than the width of the intermediate groove segment. In some embodiments, the plurality of groove segments includes an intermediate groove segment located on the axis between the edge groove segments and the central groove segment, wherein the width of the intermediate groove segment is the same as the width of the central groove segment, and wherein the width of the edge groove segments is greater than the width of the intermediate groove segment.

[0121] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, comprising: Substrate; and A trench capacitor, located on the substrate, and comprising a plurality of capacitor segments extending into the substrate; The plurality of capacitor segments include edge capacitor segments located at the edges of the trench capacitor and center capacitor segments located at the center of the trench capacitor. The capacitor segments are spaced apart on the axis, and The width of the edge capacitor segment is equal to the width of the center capacitor segment, and the spacing at the edge capacitor segment is greater than the spacing at the center capacitor segment.

2. The integrated chip according to claim 1, wherein, The trench capacitor also includes a dielectric liner on the sidewalls and bottom of the liner trench.

3. The integrated chip according to claim 1, wherein, The trench capacitor includes multiple capacitor electrodes and multiple capacitor dielectric layers, wherein the capacitor electrodes and the capacitor dielectric layers are recessed into the substrate at the central capacitor segment and the edge capacitor segment.

4. The integrated chip according to claim 1, wherein, The central capacitor segment and the edge capacitor segment partially define a grid pattern in the substrate.

5. The integrated chip according to claim 1, wherein, The central capacitor segment and the edge capacitor segment at least partially define a serpentine pattern in the substrate.

6. The integrated chip according to claim 1, wherein, The plurality of capacitor segments includes an intermediate capacitor segment located between the edge capacitor segment and the center capacitor segment, wherein the spacing between the edge capacitor segment and the intermediate capacitor segment is greater than the spacing between the intermediate capacitor segment and the center capacitor segment.

7. The integrated chip according to claim 1, wherein, The capacitor segment has a linear top layout.

8. An integrated chip, comprising: The substrate includes a first substrate segment and a second substrate segment; and A trench capacitor is located on the substrate and includes a central capacitor segment, an intermediate capacitor segment, and an edge capacitor segment. The central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment extend into the substrate. The central capacitor segment and the edge capacitor segment are located at the center and edge of the trench capacitor, respectively. The intermediate capacitor segment is located between the central capacitor segment and the edge capacitor segment. The first substrate segment and the second substrate segment respectively separate the intermediate capacitor segment from the central capacitor segment and the edge capacitor segment. The widths of the edge capacitor segment, the middle capacitor segment, and the center capacitor segment are the same, and the width of the second substrate segment is greater than the width of the first substrate segment.

9. The integrated chip according to claim 8, wherein, The trench capacitor also includes a dielectric liner on the sidewalls and bottom of the liner trench.

10. The integrated chip according to claim 9, wherein, The coefficient of thermal expansion of the dielectric liner is less than that of the substrate.

11. The integrated chip according to claim 8, wherein, The central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment each have their own linear top layout.

12. The integrated chip according to claim 8, wherein, The central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment at least partially define a serpentine pattern in the substrate.

13. The integrated chip according to claim 8, wherein, The central capacitor segment, the intermediate capacitor segment, and the edge capacitor segment partially define a grid pattern in the substrate.

14. The integrated chip according to claim 8, wherein, The trench capacitor includes a plurality of capacitor electrodes and a plurality of capacitor dielectric layers, wherein the capacitor electrodes and the capacitor dielectric layers are recessed into the substrate at the central capacitor segment, the intermediate capacitor segment and the edge capacitor segment, and wherein the capacitor electrodes and the capacitor dielectric layers surround the top of the first substrate segment and the second substrate segment.

15. A method for forming a trench capacitor, the method comprising: A substrate is patterned to form a trench pattern in the substrate, wherein the trench pattern includes a plurality of trench segments spaced apart along an axis, wherein the plurality of trench segments include an edge trench segment and a center trench segment located at the edge and center of the trench pattern, respectively, and wherein the width of the edge trench segment is equal to the width of the center trench segment, and the spacing at the edge trench segment is greater than the spacing at the center trench segment; A lower electrode layer, an electrode dielectric layer, and an upper electrode layer are stacked and deposited over the substrate, and the trench section is lined, wherein the electrode dielectric layer is located between the lower electrode layer and the upper electrode layer; and The lower electrode layer, the upper electrode layer, and the electrode dielectric layer are patterned to form multiple capacitor electrodes and capacitor dielectric layers, respectively.

16. The method according to claim 15, wherein, The edge groove segment and the center groove segment have a linear top layout that extends parallel to each other in a direction perpendicular to the axis.

17. The method according to claim 15, wherein, The edge trench segment and the center trench segment at least partially define a serpentine pattern in the substrate.

18. The method according to claim 15, wherein, The plurality of groove segments include additional edge groove segments spaced apart from the central groove segment along the axis and on the side of the central groove segment opposite to the edge groove segments, wherein the edge groove segments and the additional edge groove segments have the same width.

19. The method according to claim 15, wherein, The plurality of groove segments include an intermediate groove segment located on the axis between the edge groove segment and the central groove segment, wherein the width of the intermediate groove segment is equal to the width of the central groove segment, and wherein the width of the edge groove segment is equal to the width of the intermediate groove segment.

20. The method of claim 15, wherein, The plurality of groove segments include an intermediate groove segment located on the axis between the edge groove segment and the center groove segment, wherein the spacing at the intermediate groove segment is greater than the spacing at the center groove segment, and wherein the spacing at the edge groove segment is greater than the spacing at the intermediate groove segment.

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