Semiconductor device and method of forming a semiconductor device

Abstract

A semiconductor device and a method for forming the same can solve the problems of poor shape and poor conductivity of a peripheral contact landing pad, and improve the yield of a memory. The method for forming the semiconductor device includes the following steps: providing a substrate having a peripheral region, a bonding region and a device region in sequence; forming a metal layer on the upper surface of the substrate; forming a dielectric layer above the metal layer; forming an opening in the dielectric layer, the opening being above at least one of the peripheral region or the bonding region to expose the metal layer to form a contact window, and the upper surface height of the metal layer exposed to the contact window being lower than the upper surface height of the metal layer in the device region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication, and more particularly to semiconductor devices and methods for forming semiconductor devices. Background Technology

[0002] In existing technologies, during memory fabrication, contact windows are formed in the peripheral area of ​​the memory, near the device area, to expose the conductive metal within the memory, facilitating the formation of peripheral contact landing pads that are electrically connected to the bit lines. As the critical dimensions of memory gradually shrink, the distance between adjacent bit lines also decreases. Before forming the bit line structure, a mask structure needs to be formed on the upper surface of the metal layer used to form the bit line structure. Furthermore, trenches with a high aspect ratio are formed from the upper surface of the mask structure downwards in a direction perpendicular to the upper surface of the mask structure to create the required bit line structure with a smaller critical dimension.

[0003] In existing technologies, when forming contact windows and preparing peripheral contact landing pads, there are often problems such as poor shape and poor conductivity of the peripheral contact landing pads, which affect the yield of memory fabrication. Summary of the Invention

[0004] This invention proposes a semiconductor device and a method for forming a semiconductor device, which can solve the problems of poor shape and poor conductivity of the peripheral contact landing pads, and improve the fabrication yield of memory.

[0005] To address the aforementioned problems, a method for forming a semiconductor device is provided, comprising the following steps: providing a substrate having a peripheral region, a bonding region, and a device region sequentially adjacent to each other; forming a metal layer on the upper surface of the substrate; forming a dielectric layer above the metal layer; forming an opening in the dielectric layer, the opening being located above at least one of the peripheral region or the bonding region to expose the metal layer to form a contact window, wherein the height of the upper surface of the metal layer exposed to the contact window is lower than the height of the upper surface of the metal layer located in the device region.

[0006] Optionally, forming the metal layer includes the following steps: forming a first insulating layer on the upper surface of the substrate; partially removing the first insulating layer to form a stepped first insulating layer, wherein the height of the upper surface of the first insulating layer in the peripheral region is lower than the height of the upper surface of the first insulating layer in the device region; forming the stepped metal layer on the upper surface of the first insulating layer, wherein the height of the upper surface of the metal layer in the peripheral region is lower than the height of the upper surface of the metal layer in the device region.

[0007] Optionally, the partial removal of the first insulating layer includes the following steps: forming a patterned first mask layer on the upper surface of the first insulating layer, the peripheral region and a portion of the bonding region being exposed to the first mask layer, the first mask layer covering the device region and the remaining bonding region; removing the first insulating layer using the first mask layer as a mask; and removing the first mask layer.

[0008] Optionally, the first insulating layer includes a nitride layer.

[0009] Optionally, the method further includes the following steps: forming a second insulating layer on the upper surface of the substrate; partially removing the second insulating layer to form a groove at a position corresponding to the contact window, the bottom surface of the groove also being located within the second insulating layer; forming the metal layer on the upper surface of the second insulating layer, wherein the upper surface height of the metal layer formed in the groove is lower than the upper surface height of the metal layer in the device region.

[0010] Optionally, partial removal of the second insulating layer includes the following steps: forming a patterned second mask layer on the upper surface of the second insulating layer, the second mask layer having through holes at positions corresponding to the contact window; etching the second insulating layer downward from the through holes in a direction perpendicular to the upper surface of the substrate to form the groove on the surface of the second insulating layer; and removing the second mask layer.

[0011] Optionally, the method further includes the step of etching the metal layer to form a bit line structure, wherein the bit line structure has a portion extending over the peripheral region.

[0012] Optionally, etching the metal layer to form the bit line structure includes the following steps: forming a patterned third mask layer over the metal layer, the third mask layer covering the device region, the bonding region and a portion of the peripheral region; using the third mask layer as a mask to pattern the metal layer to form the bit line structure, with one end of the third mask layer covering the peripheral region; and removing the third mask layer.

[0013] To address the aforementioned technical problems, a semiconductor device is also provided, comprising: a substrate having a peripheral region, a device region, and a bonding region; a metal layer formed above the substrate; and a dielectric layer formed above the metal layer, wherein a contact window is formed on the surface of the dielectric layer to expose the metal layer, and the upper surface height of the metal layer exposed through the contact window is lower than the upper surface height of the metal layer located in the device region.

[0014] Optionally, it further includes: a first insulating layer formed on the upper surface of the substrate, located below the metal layer, and the height of the upper surface of the first insulating layer located below the peripheral region is lower than the height of the upper surface of the first insulating layer located below the device region.

[0015] Optionally, it further includes: a second insulating layer formed on the upper surface of the substrate, located below the metal layer, and the upper surface height of the second insulating layer located below the contact window is lower than the upper surface height of the second insulating layer below the device region.

[0016] Optionally, the semiconductor device includes a bit line structure formed by the metal layer and having a portion extending over the peripheral region.

[0017] In the semiconductor device and semiconductor device formation method of the present invention, the upper surface height of the metal layer exposed in the contact window is lower than the upper surface height of the metal layer located in the device region. This effectively prevents the etching gas from contacting the upper surface of the metal layer located in the contact window region first during etching of the metal layer, thus avoiding affecting the conductivity of the peripheral contact landing pads formed based on the contact window. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the morphological structure of the metal layer used to fabricate the bit line structure in a memory device in the prior art.

[0019] Figure 2 This is a schematic diagram of the preparation method in one specific embodiment of the present invention.

[0020] Figures 3 to 9 This is a schematic diagram of the semiconductor device structure corresponding to each step of the preparation method in a specific embodiment of the present invention.

[0021] Figures 10 to 13 This is a schematic diagram of the semiconductor device structure corresponding to each step of the fabrication method for bit line structures.

[0022] Figures 14 to 16 This is a schematic diagram of the semiconductor device structure corresponding to each step when partially removing the second insulating layer. Detailed Implementation

[0023] Research has found that the poor morphology and conductivity of the peripheral contact landing pads are due to the fact that, in existing technologies, the upper surface of the metal layer where the contact window is expected to form is higher than the upper surface of the metal layer in the device area. The entire metal layer exhibits a Z-shaped distribution from the peripheral area to the device area, with the metal layer in the peripheral area generally higher than that in the device area. (See here for more information.) Figure 1 A bonding region 102 is also provided between the device region 103 and the peripheral region 101. The contact window is located within the bonding region 102. The height of the metal layer 104 in the bonding region 102 and the peripheral region 101 is higher than its height in the device region 103.

[0024] Thus, when etching the metal layer and forming the bit line structure based on the high aspect ratio trench, the etching gas will first contact the metal layer located at the preset contact window position and etch it first, and then contact the metal layer located in the device area and etch that metal layer belonging to the device area. This results in the etching gas first contacting the metal layer located at the preset contact window position and etching it first, and then contacting the metal layer located in the device area and etching that metal layer belonging to the device area. In this way, the metal layer located at the preset contact window position is contacted by the etching gas first, and its morphology is etched more than that of the metal layer located in the device area. It is very easy for necking or even breakage to occur, affecting the conductivity of the final peripheral contact landing pad.

[0025] The following explanation and elaboration, with reference to the illustrations, further elaborates on semiconductor devices and their fabrication methods.

[0026] Please see Figures 2 to 9 ,in Figure 2 This is a schematic diagram of the preparation method in one specific embodiment of the present invention. Figures 3 to 9 This is a schematic diagram of the semiconductor device structure corresponding to each step of the preparation method in a specific embodiment of the present invention.

[0027] In this specific embodiment, a method for forming a semiconductor device is proposed, including the following steps: S21, a substrate 201 is provided, the substrate 201 having a peripheral region 101, a bonding region 102, and a device region 103 sequentially adjacent to each other, see here. Figure 3 S22 forms a metal layer 104 on the upper surface of the substrate 201, see here. Figure 7 S23 forms a dielectric layer 204 above the metal layer 104, see here. Figure 8 S24 forms an opening in the dielectric layer 204, see here. Figure 9 The opening is located above at least one of the peripheral region 101 or the bonding region 102 to expose the metal layer 104 forming a contact window 205, and the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103.

[0028] In this specific embodiment, the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103. This effectively prevents the etching gas from contacting the upper surface of the metal layer 104 located in the contact window 205 region first when etching the metal layer 104, thus avoiding affecting the conductivity of the peripheral contact landing pads formed based on the contact window 205.

[0029] In one specific embodiment, forming the metal layer 104 includes the following steps: forming a first insulating layer 202 on the upper surface of the substrate 201; partially removing the first insulating layer 202 to form a stepped first insulating layer 202, wherein the height of the upper surface of the first insulating layer 202 located in the peripheral region 101 is lower than the height of the upper surface of the first insulating layer 202 located in the device region 103; forming the stepped metal layer 104 on the upper surface of the first insulating layer 202, wherein the height of the upper surface of the metal layer 104 located in the peripheral region 101 is lower than the height of the upper surface of the metal layer 104 located in the device region 103.

[0030] In this specific embodiment, when generating a metal layer 104 of uniform thickness, the height of the upper surface of the metal layer 104 located in the contact window 205 can be ensured to be lower than the height of the upper surface of the metal layer 104 located in the device region 103. Furthermore, this step is consistent with the process flow for fabricating a memory. When this fabrication method is applied to the fabrication of a memory, this step can correspond to the peripheral nitride removal step.

[0031] In one specific embodiment, the first insulating layer 202 includes a nitride layer. During the fabrication of the memory, a silicon nitride layer needs to be formed below the metal layer 104, and this layer can serve as the first insulating layer 202.

[0032] Please see Figures 4 to 6 In one specific embodiment, the partial removal of the first insulating layer 202 includes the following steps: forming a patterned first mask layer 210 on the upper surface of the first insulating layer 202, exposing the peripheral region 101 and a portion of the bonding region 102 to the first mask layer 210, and the first mask layer 210 covering the device region 103 and the remaining bonding region 102. (See also...) Figure 4 The first insulating layer 202 is removed using the first mask layer 210 as a mask. Please refer to [link to relevant documentation]. Figure 5 ; Remove the first mask layer 210, please refer to Figure 6 .

[0033] In this way, when partially removing the first insulating layer 202 based on the first mask layer 210, the peripheral region 101 exposed to the first mask layer 210 and part of the bonding region 102 can be partially removed. In one embodiment, the region exposed outside the first mask layer 210 is completely etched to expose the surface of the substrate 201. In some other embodiments, the region exposed outside the first mask layer 210 is only etched to a certain depth and does not penetrate the first insulating layer 202.

[0034] In one specific embodiment, when partially removing the first insulating layer 202, the etching depth of the first insulating layer 202 can be set as needed. If a memory needs to be fabricated using this type of semiconductor device, the removal depth when the first insulating layer 202 is partially removed needs to be set according to the minimum thickness of the first insulating layer 202 required by the memory.

[0035] In one specific embodiment, at least one of dry etching or wet etching is used to partially remove the first insulating layer 202.

[0036] exist Figures 4 to 6 In the specific embodiment shown, the first insulating layer 202 after partial removal is stepped. Subsequently, if other material layers are grown on the upper surface of the first insulating layer 202, and the thickness of the material layers is equal, the other material layers grown on the upper surface of the first insulating layer 202 are also stepped. Even if the metal layer 104 is formed on top of these subsequently generated material layers, a stepped metal layer 104 can be obtained, ensuring that the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103.

[0037] In one specific embodiment, the method further includes the following steps: forming a second insulating layer 203 on the upper surface of the substrate 201; partially removing the second insulating layer 203 to form a groove at a position corresponding to the contact window 205, the bottom surface of the groove also being located within the second insulating layer 203; forming the metal layer 104 on the upper surface of the second insulating layer 203, wherein the height of the upper surface of the metal layer 104 formed in the groove is lower than the height of the upper surface of the metal layer 104 of the device region 103.

[0038] When this fabrication method is applied to the fabrication of a memory, this step corresponds to the formation process of bit line contact plugs in a bit line structure, specifically the step of patterning the polysilicon layer below the metal layer 104 in the bit line structure. In this specific embodiment, no requirements are placed on the morphology of the nitride layer below the polysilicon layer; instead, the morphology of the polysilicon layer is directly modified to make it step-shaped. Consequently, the metal layer 104 grown on the upper surface of the polysilicon layer also forms a step shape, and the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the upper surface of the metal layer 104 located in the device region 103.

[0039] Based on the nitride layer as the first insulating layer 202, a polycrystalline silicon layer is also formed on the upper surface of the nitride layer, which is consistent with the memory fabrication process. Therefore, in addition to patterning the nitride layer to change the height of the surface to which the metal layer 104 is formed, the polycrystalline silicon layer can also be patterned to change the height of the surface to which the metal layer 104 is formed.

[0040] In this specific embodiment, the polysilicon layer, serving as the second insulating layer 203, is patterned to form the groove in a predetermined area. This ensures that when the metal layer 104 is formed on the upper surface of the polysilicon layer, the height of the upper surface of the metal layer 104 within the groove is lower than the height of the upper surface of the metal layer 104 located outside the groove. Thus, by pre-setting the position of the groove, the height of the upper surface of the metal layer 104 exposed to the contact window 205 can be limited to be lower than the height of the upper surface of the metal layer 104 located in the device region 103, achieving the desired effect.

[0041] In one specific embodiment, partially removing the second insulating layer 203 includes the following steps: forming a patterned second mask layer 208 on the upper surface of the second insulating layer 203, wherein the second mask layer 208 has through holes 209 formed at positions corresponding to the contact window 205. Figure 14 , Figure 14 The through-hole 209 includes the location where the contact window 205 is to be formed; the second insulating layer 203 is etched downward from the through-hole 209 in a direction perpendicular to the upper surface of the substrate 201 to form the groove on the surface of the second insulating layer 203, see here. Figure 15 Remove the second mask layer 208. The location of the groove is limited by restricting the exposed area of ​​the patterned second mask layer 208; see here. Figure 16 .

[0042] exist Figure 15In the specific embodiment shown, the second insulating layer 203 is penetrated by the groove. In fact, when the preparation method is applied to the preparation of memory, the bottom surface of the groove should be located inside the second insulating layer 203, which is related to the minimum thickness of the second insulating layer 203, i.e., the polysilicon layer, required to form the memory.

[0043] Additionally, it is important to note that in Figures 14 to 16 In the specific embodiment shown, the via 209 formed after the second mask layer 208 is patterned does not have the same characteristics as... Figures 4 to 6 Similar to the first patterned mask layer 210, which exposes all the peripheral areas 101, this second patterned mask layer 208 only exposes the location of the contact window 205 and the area surrounding it. In fact, the area exposed after patterning the second mask layer 208 can also be similar. Figures 4 to 6 As shown, all the peripheral regions 101 are exposed to form a stepped second mask layer 208.

[0044] In one embodiment, the method further includes the step of etching the metal layer 104 to form a bit line structure, wherein the bit line structure has a portion extending over the peripheral region 101.

[0045] This is the operation after the metal layer 104 has been formed. In this operation, during the etching of the metal layer 104 to form the bit line structure, the length of the bit line structure is extended, extending the bit line structure into the peripheral area 101 by a predetermined distance. This makes the end of the bit line structure near the contact window 205 also have a higher height, and the height is basically the same as the upper surface of the metal layer 104 exposed by the contact window 205. This can also prevent poor contact between the contact window 205 and the bit line structure.

[0046] Please see Figures 10 to 13 In one specific embodiment, etching the metal layer 104 to form the bit line structure includes the following steps: forming a patterned third mask layer 206 over the metal layer 104. (See also...) Figure 10 The third mask layer 206 covers the device region 103, the bonding region 102, and a portion of the peripheral region 101; the metal layer 104 is patterned using the third mask layer 206 as a mask to form a bit line structure, and one end of the third mask layer 206 extends to the peripheral region 101. (See also...) Figure 11 ; For removal of the third mask layer 206, please refer to [link / reference]. Figure 12 .exist Figures 10 to 13 The specific embodiment shown also demonstrates the large aspect ratio of the trench 207 formed after patterning the third mask layer during the formation of the bitline structure. Figures 10 to 13In this context, the ratio between the depth D and the width W of the trench 207 is the aspect ratio of the trench 207. When this value is large, it is difficult to control the uniformity of etching when the etching gas etches the metal layer below the trench 207.

[0047] Depend on Figure 13 It can be seen that the end of the third mask layer 206 extends into the peripheral region 101, based on which Figure 13 The bitline structure formed by the third mask layer 206 shown also extends into the peripheral region 101.

[0048] This structure is applicable to both situations where the upper surface of the metal layer 104 in the area of ​​the contact window 205 is lower than the upper surface of the metal layer 104 in the device area 103, and situations where the upper surface of the metal layer 104 in the area of ​​the contact window 205 is not lower than the upper surface of the metal layer 104 in the device area 103.

[0049] In one specific embodiment, the metal layer 104 includes a conductive metal material layer such as a tungsten layer. When fabricating the memory using the aforementioned method, a TiN layer or the like is further disposed between the polysilicon layer and the metal layer 104. The TiN layer or the like also follows the undulations of at least one of the stepped polysilicon layer or nitride layer, forming steps to ensure that the metal layer 104 formed on the upper surface of these TiN layers or the like has a stepped upper surface.

[0050] In this specific embodiment, a semiconductor device is also provided, including: a substrate 201 having a peripheral region 101, a device region 103, and a bonding region 102; a metal layer 104 formed above the substrate 201; a dielectric layer 204 formed above the metal layer 104, wherein a contact window 205 is formed on the surface of the dielectric layer 204 to expose the metal layer 104, and the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103.

[0051] In this specific embodiment, the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103. This effectively prevents the etching gas from contacting the upper surface of the metal layer 104 located in the contact window 205 region first when etching the metal layer 104, thus avoiding affecting the conductivity of the peripheral contact landing pads formed based on the contact window 205.

[0052] In one specific embodiment, the device further includes a first insulating layer 202 formed on the upper surface of the substrate 201, located below the metal layer 104, wherein the height of the upper surface of the first insulating layer 202 located below the peripheral region 101 is lower than the height of the upper surface of the first insulating layer 202 located below the device region 103. In one specific embodiment, the first insulating layer 202 comprises a nitride layer. During the fabrication of the memory, to ensure consistency with the memory fabrication process, the first insulating layer 202 here refers to the silicon nitride layer located below the metal layer 104.

[0053] In one specific embodiment, it further includes: a second insulating layer 203 formed on the upper surface of the substrate 201, located below the metal layer 104, and the height of the upper surface of the second insulating layer 203 located below the contact window 205 is lower than the height of the upper surface of the second insulating layer 203 located below the device region 103.

[0054] In the process of fabricating the memory, in order to be consistent with the fabrication process of the memory, the second insulating layer 203 here refers to the polycrystalline silicon layer located below the metal layer 104 and above the silicon nitride layer.

[0055] Based on the nitride layer as the first insulating layer 202, a polycrystalline silicon layer is also formed on the upper surface of the nitride layer, which is consistent with the memory fabrication process. Therefore, in addition to patterning the nitride layer to change the height of the surface to which the metal layer 104 is formed, the polycrystalline silicon layer can also be patterned to change the height of the surface to which the metal layer 104 is formed.

[0056] In this specific embodiment, the polysilicon layer, serving as the second insulating layer 203, is patterned to form the groove in a predetermined area. This ensures that when a metal layer 104 is formed on the upper surface of the polysilicon layer, the height of the upper surface of the metal layer 104 within the groove is lower than the height of the upper surface of the metal layer 104 located outside the groove. Thus, by pre-setting the position of the groove, the height of the upper surface of the metal layer 104 exposed to the contact window 205 can be limited to be lower than the height of the upper surface of the metal layer 104 located in the device region 103, achieving the desired effect.

[0057] In one embodiment, the semiconductor device includes a bit line structure formed by the metal layer 104 and having a portion extending above the peripheral region 101. This is an operation performed after the metal layer 104 has been formed. In this embodiment, the length of the bit line structure is extended into the peripheral region 101 by a predetermined distance, such that the end of the bit line structure near the contact window 205 also has a higher height, substantially matching the height of the upper surface of the metal layer 104 exposed by the contact window 205. This also prevents poor contact between the contact window 205 and the bit line structure.

[0058] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate having a peripheral region, a bonding region and a device region that are sequentially adjacent to each other; A metal layer is formed on the upper surface of the substrate; A dielectric layer is formed over the metal layer; An opening is formed in the dielectric layer, the opening being located above at least one of the peripheral region or bonding region, to expose the metal layer to form a contact window, and the upper surface of the metal layer exposed to the contact window is lower than the upper surface of the metal layer located in the device region; The formation of the metal layer includes the following steps: A first insulating layer is formed on the upper surface of the substrate; The first insulating layer is partially removed to form a stepped first insulating layer, and the height of the upper surface of the first insulating layer in the peripheral region is lower than the height of the upper surface of the first insulating layer in the device region. A stepped metal layer is formed on the upper surface of the first insulating layer, and the height of the upper surface of the metal layer in the peripheral region is lower than the height of the upper surface of the metal layer in the device region; The removal of the first insulating layer includes the following steps: A patterned first mask layer is formed on the upper surface of the first insulating layer, the peripheral region and a portion of the bonding region are exposed to the first mask layer, and the first mask layer covers the device region and the remaining bonding region; The first insulating layer is removed using the first mask layer as a mask. Remove the first mask layer.

2. The method for forming a semiconductor device according to claim 1, characterized in that, The first insulating layer includes a nitride layer.

3. The method for forming a semiconductor device according to claim 1, characterized in that, It also includes the following steps: A second insulating layer is formed on the upper surface of the substrate; The second insulating layer is partially removed to form a groove at a position corresponding to the contact window, the bottom surface of which is also located within the second insulating layer; The metal layer is formed on the upper surface of the second insulating layer, and the height of the upper surface of the metal layer formed in the groove is lower than the height of the upper surface of the metal layer in the device region.

4. The method for forming a semiconductor device according to claim 3, characterized in that, Partial removal of the second insulating layer includes the following steps: A patterned second mask layer is formed on the upper surface of the second insulating layer, and the second mask layer has through holes at positions corresponding to the contact window; The second insulating layer is etched downward from the through-hole in a direction perpendicular to the upper surface of the substrate to form the groove on the surface of the second insulating layer; Remove the second mask layer.

5. The method for forming a semiconductor device according to claim 1, characterized in that, It also includes the following steps: The metal layer is etched to form a bit line structure, and the bit line structure has a portion extending over the peripheral region.

6. The method for forming a semiconductor device according to claim 5, characterized in that, Etching the metal layer to form the bit line structure includes the following steps: A patterned third mask layer is formed above the metal layer, the third mask layer covering the device region, the bonding region and part of the peripheral region; The metal layer is patterned using the third mask layer as a mask to form a bit line structure, and one end of the third mask layer covers the peripheral area; Remove the third mask layer.

7. A semiconductor device, characterized in that, include: The substrate has a peripheral region, a device region, and a bonding region. A metal layer is formed above the substrate; A dielectric layer is formed above the metal layer, and a contact window is formed on the surface of the dielectric layer to expose the metal layer, and the height of the upper surface of the metal layer exposed to the contact window is lower than the height of the upper surface of the metal layer located in the device region; Also includes: A first insulating layer is formed on the upper surface of the substrate, below the metal layer, and the height of the upper surface of the first insulating layer below the peripheral region is lower than the height of the upper surface of the first insulating layer below the device region. The first insulating layer includes a nitride layer.

8. The semiconductor device according to claim 7, characterized in that, Also includes: A second insulating layer is formed on the upper surface of the substrate, below the metal layer, and the height of the upper surface of the second insulating layer below the contact window is lower than the height of the upper surface of the second insulating layer below the device region.

9. The semiconductor device according to claim 7, characterized in that, The semiconductor device includes a bit line structure formed by the metal layer and having a portion extending over the peripheral region.

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