Integrated assembly and method of forming an integrated assembly

Abstract

This application relates to integrated assemblies and methods of forming integrated assemblies. Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has a channel material including a semiconductor material. The channel material has a first end and an opposite second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. A conductive gate material is adjacent the side of the channel material. A first hemispherical metal-containing cap is over the conductive structure and under the channel material, and / or a second hemispherical metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.

Description

Technical Field

[0001] Integrated assemblies (e.g., integrated memory). Methods for forming integrated assemblies. Background Technology

[0002] The memory may use memory cells, which individually include access means (e.g., access transistors) combined with storage elements (e.g., capacitors, resistive memory devices, phase-change memory devices, etc.).

[0003] The goal is to develop improved transistors and better memory architectures. Summary of the Invention

[0004] One aspect of this application relates to an apparatus comprising: a semiconductor material including at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table; a conductive structure below the semiconductor material and configured to be electrically coupled to the semiconductor material in at least one operating mode of the apparatus; and a hemispherical metal-containing cap above the conductive structure and below the semiconductor material.

[0005] Another aspect of this application relates to an integrated assembly comprising access means between a memory element and a conductive structure; the access means comprising: a channel material comprising a semiconductor material; the channel material having a first end and an opposing second end, and having a side extending from the first end to the second end; the first end being adjacent to the conductive structure, and the second end being adjacent to the memory element; the semiconductor material comprising at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table; a conductive gate material adjacent to the side of the channel material; and at least one of a first hemispherical metal-containing cap and a second hemispherical metal-containing cap, the first hemispherical metal-containing cap being above the conductive structure and below the channel material, and the second hemispherical metal-containing cap being above the channel material and below the memory element.

[0006] Another aspect of this application relates to a method of forming an integrated assembly, comprising: forming conductive features over a semiconductor substrate, the conductive features including a first conductive material, the conductive features being spaced apart from each other by intervening insulating regions, a configuration including conductive features and insulating regions, an upper surface of the configuration including conductive portions corresponding to the upper surface of the conductive features, and including insulating portions corresponding to the upper surface of the intervening insulating regions; selectively forming a second conductive material over the conductive portions relative to the insulating portions; forming access device pillars over the second conductive material, the access device pillars including a channel material, the channel material including a semiconductor material having at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table; forming an insulating material along one or more sidewalls of each of the access device pillars; forming a conductive gate adjacent to the insulating material; and forming a memory element over the access device pillars, and gate-coupled the memory element to the conductive features through the channel material of the access device pillars.

[0007] Another aspect of this application relates to a method of forming an integrated assembly, comprising: forming a first linearly extending conductive structure over a semiconductor substrate, the first linearly extending conductive structure extending along a first direction; forming access device pillars over the first linearly extending conductive structure, the access device pillars including a channel material comprising a semiconductor material having at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table; forming a first insulating material along one or more sidewalls of the access device pillars; forming a conductive gate adjacent to the first insulating material; the conductive gate along a second linearly extending feature extending along a second direction, wherein the second direction intersects the first direction; forming a second insulating material over the conductive gate and between the access device pillars, the configuration including the access device pillars and the second insulating material, the configuration having an upper surface having conductive regions corresponding to the upper surface of the access device pillars, and having insulating regions between the conductive regions including the second insulating material; selectively forming a conductive overlay material over the conductive regions relative to the insulating regions; and forming a memory element coupled to the conductive overlay material. Attached Figure Description

[0008] Figures 1 to 1B A diagrammatic view of the region including the instance transistor. Figure 1A For along Figure 1 The side view of the cross section of line AA, and Figure 1B For along Figure 1 A side view of the cross section of line BB. Figure 1 For along Figure 1A and 1B A top-down cross-sectional view of line CC.

[0009] Figures 2 to 2BA diagrammatic view of the region including the instance transistor. Figure 2A For along Figure 2 The side view of the cross section of line AA, and Figure 2B For along Figure 2 A side view of the cross section of line BB. Figure 2 For along Figure 2A and 2B A top-down cross-sectional view of line CC.

[0010] Figures 3 to 3B A diagrammatic view of the region including the instance transistor. Figure 3A For along Figure 3 The side view of the cross section of line AA, and Figure 3B For along Figure 3 A side view of the cross section of line BB. Figure 3 For along Figure 3A and 3B A top-down cross-sectional view of line CC.

[0011] Figures 4 to 4B A diagrammatic view of the region including the instance transistor. Figure 4A For along Figure 4 The side view of the cross section of line AA, and Figure 4B For along Figure 4 A side view of the cross section of line BB. Figure 4 For along Figure 4A and 4B A top-down cross-sectional view of line CC.

[0012] Figures 5 to 5B This is a diagrammatic view of the instance processing phase of an instance method. Figure 5A For along Figure 5 The side view of the cross section of line AA, and Figure 5B For along Figure 5 A side view of the cross section of line BB. Figure 5 This is a top view.

[0013] Figures 6 to 6B for Figures 5 to 5B The district Figures 5 to 5B A diagrammatic view of the instance processing phase following the instance processing phase. Figure 6A For along Figure 6 The side view of the cross section of line AA, and Figure 6B For along Figure 6 A side view of the cross section of line BB. Figure 6 This is a top view.

[0014] Figures 7 to 7B for Figures 5 to 5B The district Figures 6 to 6B A diagrammatic view of the instance processing phase following the instance processing phase. Figure 7A For along Figure 7 The side view of the cross section of line AA, and Figure 7B For along Figure 7 A side view of the cross section of line BB. Figure 7 This is a top view.

[0015] Figures 8 to 8B for Figures 5 to 5B The district Figures 7 to 7B A diagrammatic view of the instance processing phase following the instance processing phase. Figure 8A For along Figure 8 The side view of the cross section of line AA, and Figure 8B For along Figure 8 A side view of the cross section of line BB. Figure 8 This is a top view.

[0016] Figures 9 to 9B for Figures 5 to 5B The district Figures 8 to 8B A diagrammatic view of the instance processing phase following the instance processing phase. Figure 9A For along Figure 9 The side view of the cross section of line AA, and Figure 9B For along Figure 9 A side view of the cross section of line BB. Figure 9 This is a top view.

[0017] Figure 10 This is a schematic diagram of a region in an instance memory array. Detailed Implementation

[0018] Some embodiments include a transistor having a channel material comprising a semiconductor material (e.g., a semiconductor oxide), and having a first hemispherical metal cap below the channel material and / or a second hemispherical metal cap above the channel material. The transistor can be used as an access means for a memory cell. Some embodiments include a method of forming an integrated assembly. Reference Figures 1 to 10 Describe an example implementation.

[0019] refer to Figures 1 to 1B The integrated assembly 10 includes an access device 12 coupled between the storage element 14 and the conductive structure 16.

[0020] The storage element 14 can be any suitable device having at least two detectable states; and in some embodiments, it can be, for example, a capacitor, a resistive memory device, a conductive bridging device, a phase-change memory (PCM) device, a programmable metallization cell (PMC), etc.

[0021] The conductive structure 16 may be a linear extension (as shown) and may correspond, for example, to a digital line (bit line, sense line, etc.). The linear extension 16 extends along a first direction, wherein this first direction indicates along... Figures 1 to 1B The view along the y-axis. Although the linear extension structure 16 is shown as straight, in other embodiments it may be curved, wavy, etc. Structure 16 in Figure 1 The conductive structure 16 is indicated by a dashed line to show that it is below other structures and materials. The conductive structure 16 includes a conductive material 58. The conductive material 58 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, molybdenum, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive structure 16 may include tungsten and / or molybdenum, be primarily composed of tungsten and / or molybdenum, or be composed of tungsten and / or molybdenum.

[0022] Conductive structure 16 may be coupled to sensing circuitry (e.g., sensing amplifier circuitry) 18, such as Figure 1A and 1B As shown in the image.

[0023] Conductive structure 16 may be made of a semiconductor substrate (see below). Figures 5 to 5B (Description) Support.

[0024] The conductive structures 16 are spaced apart from each other by intervention regions 20 comprising insulating material 22. The insulating material 22 may comprise any suitable composition, such as silicon dioxide.

[0025] Each of the access devices 12 includes a pillar 24 comprising a semiconductor material 26 and a conductive oxide material 28. The pillar 24 is located in... Figures 1 to 1B In the configuration, it extends vertically (i.e., along the illustrated z-axis). In some embodiments, the support 24 may be referred to as a vertically extending support. The support 24 may be substantially vertical, wherein the term "substantially vertical" means vertical within reasonable manufacturing and measurement tolerances. In some embodiments, the vertically extending support may extend orthogonally relative to the illustrated x-axis. In some embodiments, the vertically extending support may be approximately orthogonal to the illustrated x-axis, wherein the term "approximately orthogonal" means orthogonal within approximately ±15°.

[0026] The semiconductor material 26 of the pillar 24 can be considered to correspond to the channel region 30, and the conductive oxide material 28 of the pillar can be considered to correspond to the first source / drain region 32 and the second source / drain region 34. Each of the illustrated channel regions 30 has a lower end (first end) 31 and an upper end (second end) 33, wherein the upper end and the lower end are in a relative relationship. The first source / drain region 32 directly abuts the lower end 31, and the second source / drain region 34 directly abuts the upper end 33. In some embodiments, the lower end 31 of the channel region 30 can be considered to be adjacent to the conductive structure 16, and the upper end 33 of the channel region 30 can be considered to be adjacent to the memory element 14. In some embodiments, the lower source / drain region 32 can be considered to be a first conductive region between the conductive structure 16 and the channel region 30, and the upper source / drain region 34 can be considered to be a second conductive region between the channel region 30 and the memory element 14.

[0027] The described boundary between the semiconductor material 26 and the conductive oxide material 28 within the pillar 24 may be an abrupt interface, a gradient, or any other suitable boundary.

[0028] In some embodiments, the semiconductor material 26 may be referred to as the channel material within the access device 12. This channel material has a sidewall 35 extending from the first end 31 to the second end 33.

[0029] Semiconductor material 26 may comprise any suitable composition; and in some embodiments may comprise, consist primarily of, or consist of at least one metal (e.g., one or more of aluminum, gallium, indium, thallium, tin, cadmium, zinc, etc.) and one or more of oxygen, sulfur, selenium, and tellurium. In some embodiments, semiconductor material 26 may comprise at least one element from Group 13 of the periodic table (e.g., gallium) and at least one element from Group 16 of the periodic table (e.g., oxygen). For example, semiconductor material 26 may comprise at least one element selected from the group consisting of gallium, indium, and mixtures thereof, and at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium, and mixtures thereof. In some embodiments, semiconductor material 26 may comprise a semiconductor oxide (i.e., a semiconductor material including oxygen), consist primarily of a semiconductor oxide, or consist of a semiconductor oxide. For example, in some embodiments, semiconductor material 26 may comprise InGaZnO, consist primarily of InGaZnO, or consist of InGaZnO (wherein the chemical formula indicates the major component rather than a specific stoichiometry).

[0030] The conductive oxide material 28 may comprise any suitable composition, and in some embodiments may comprise, consist primarily of, or consist of oxygen and one or more of indium, zinc, and tin. In some embodiments, the conductive oxide material 28 may comprise oxygen and zinc, and may further comprise one or both of aluminum and gallium. Aluminum and gallium may be present as dopants within the zinc oxide.

[0031] Access device 12 includes an insulating material 36 along the sidewall 35 of channel material 26. In the illustrated embodiment, the insulating material 36 extends along the entire vertical dimension of the pillar 24. In other embodiments, the insulating material 36 may extend only a portion of the vertical dimension of the pillar 24. The insulating material 36 may be referred to as a gate dielectric material. The insulating material 36 may include any suitable composition, and in some embodiments, may include silicon dioxide and / or one or more high-k compositions (wherein the term "high-k" means a dielectric constant greater than that of silicon dioxide). Examples of high-k compositions (materials) include alumina, zirconium oxide, hafnium dioxide, etc.

[0032] The conductive gate 38 is adjacent to the side 35 of the channel material 26. The conductive gate 38 includes a conductive gate material 40. The conductive gate material may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, molybdenum, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). The conductive gate material 40 is configured as a linear structure 42. The linear structure 42 extends along a second direction (illustrated x-axis direction) spanning a first direction (illustrated y-axis direction). The second direction of the second linear structure 42 may be orthogonal (or at least substantially orthogonal) to the first direction of the first linear structure 16 (as shown). Although the second linear structure 42 is shown as straight, in other embodiments, the second linear structure 42 may be curved, wavy, etc.

[0033] The second linear structure may correspond to word lines WL1, WL2, and WL3 (as shown). These word lines may be coupled to driver circuitry 44 (e.g., word line driver circuitry).

[0034] Insulating material 39 is located above the linear conductive structure 42 (word line) and between the access devices 12. Insulating material 39 may include any suitable composition, and in some embodiments may include one or more of silicon dioxide, silicon nitride, etc., or be mainly composed of one or more of silicon dioxide, silicon nitride, etc.

[0035] In some embodiments, access device 12 may correspond to access transistors. Operation of such transistors involves gate-coupled source / drain regions 32 and 34 to each other via channel region 30. When used herein, the term "gate-coupled" refers to the controlled coupling / decoupling of source / drain regions 32 and 34 induced by electrical activation / deactivation of word lines WL1 to WL3. In some operating modes of the transistor, current through channel region 30 is induced by an electric field provided by gate 38, and thus conductive structure 16 is electrically coupled to memory element 14 via channel material (semiconductor material) 26. In other operating modes, no electric field is generated, and thus conductive structure 16 is decoupled from memory element 14. In some embodiments, each of the access transistors 12 may be considered to have at least one operating mode in which semiconductor material 26 is electrically coupled to one of conductive structures 16 and one of memory elements 14.

[0036] The illustrated access device (access transistor) 12 includes a metal-containing cap 46 above the conductive structure 16. In the illustrated embodiment, the metal-containing cap is hemispherical (i.e., including a central region above the edge region). The metal-containing cap may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, molybdenum, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the metal-containing cap may include one or more of, be primarily composed of, or be composed of one or more of Cu, Ru, Pt, Pd, Co, Ni, W, Mo, and Ti. In some embodiments, the metal-containing cap may include one or both of metal silicides (e.g., titanium silicide, tungsten silicide, molybdenum silicide, etc.) and metal nitrides (e.g., titanium nitride, tungsten nitride, molybdenum nitride, etc.).

[0037] The advantage of having a metal cap 46 is that it can mitigate oxidation of the conductive material of structure 16, which can be further induced by the conductive oxide 28. For example, in some embodiments, the conductive structure 16 includes tungsten, molybdenum (or other oxidizable materials). In these embodiments, direct contact between the conductive oxide 28 and the oxidizable conductive material of the conductive structure 16 can be problematic because it can induce oxidation on the upper surface of the oxidizable material of the conductive structure, which can problematically lead to increased resistance along the interface where the conductive oxide 28 bonds to the conductive material of the conductive structure 16. The conductive cap 46 can prevent this problematic oxidation of the upper surface of the conductive structure 16.

[0038] The hemispherical shape of the conductive cap 46 can be advantageous because it reduces the contact resistance along the interface between the conductive cap 46 and the conductive oxide 28 by providing additional surface area (compared to a non-hemispherical conductive cap). Alternatively, the hemispherical shape can reduce the interfacial stress between the conductive cap 46 and the conductive oxide 28, which can enhance mechanical robustness.

[0039] The hemispherical shape of the conductive cap 46 may or may not propagate through the material of the support 24, depending on how the support is manufactured. In the illustrated embodiment, the hemispherical shape of the conductive cap propagates through some of the material of the support 24 (specifically, the lower conductive oxide material 28 and the channel material 26).

[0040] The pillars 24 can be configured as an array, wherein the rows of the array extend along the illustrated x-axis direction and the columns of the array extend along the illustrated y-axis direction. Therefore, word lines WL1 to WL3 can be considered to extend along the rows of the array, and digital lines 16 can be considered to extend along the columns of the array. Each of the access devices 12 can be considered to be uniquely addressed by one of the word lines and one of the digital lines. The access devices 12 and the storage elements 14 can be considered to correspond to memory cells of the array. The array may include hundreds, thousands, millions, etc., of such memory cells, wherein the memory cells are substantially identical to each other (wherein the term "substantially identical" means identical within reasonable tolerances of manufacture and measurement).

[0041] Figures 2 to 2B Another embodiment of assembly 10 is described. Figures 2 to 2B The assembly does not include the conductive cover 46 ( Figures 1 to 1B Alternatively, it has a metal cap 48 located above and directly abutting the upper source / drain region 34 of the access device 12. The metal cap 48 may include any of the conductive materials described above as suitable for the metal cap 46. In some embodiments, the metal cap 48 may include one or more of the following, be primarily composed of one or more of the following, or be composed of one or more of the following: Cu, Ru, Pt, Pd, Co, Ni, W, Mo, and Ti. In some embodiments, the metal cap 48 may include one or both of a metal silicide (e.g., titanium silicide, tungsten silicide, molybdenum silicide, etc.) and a metal nitride (e.g., titanium nitride, tungsten nitride, molybdenum nitride, etc.).

[0042] The described metal-containing cap 48 has a similar Figures 1 to 1B The cover of 46 is a hemispherical shape.

[0043] In the illustrated embodiment, the conductive interconnect 50 is above and directly abuts the conductive cover 48.

[0044] The conductive interconnect 50 may include any suitable configuration. The illustrated conductive interconnect includes a first conductive material 52 configured as an upwardly open container shape, and a second conductive material 54 including a core material configured as an upwardly open shape within the container shape.

[0045] The first conductive material 52 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, molybdenum, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the first conductive material 52 may include one or more metal nitrides (e.g., molybdenum nitride, tungsten nitride, and titanium nitride).

[0046] The second conductive material 54 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, molybdenum, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the second conductive material 54 may include one or more metals (e.g., one or more of molybdenum, titanium, and tungsten), be mainly composed of one or more metals, or be composed of one or more metals.

[0047] In the illustrated embodiment, the storage element 14 is electrically coupled to the conductive interconnect 50 and electrically coupled to the upper source / drain region 34 of the access device 12 via the conductive interconnect 50 and the conductive cover 48.

[0048] The conductive cap 48 advantageously improves the electrical coupling between the interconnect 50 and the upper source / drain region 34. Specifically, in embodiments where the metal nitride directly contacts the conductive oxide, the barrier height along the interface between the metal nitride 52 (e.g., titanium nitride) and the conductive oxide 28 (e.g., indium oxide) is relatively large. The conductive cap advantageously provides an improved conductive interface from the conductive oxide 28 to the metal nitride 52.

[0049] The hemispherical shape of the conductive cap 48 offers several advantages. For example, it provides additional surface area compared to a similar cap without a hemispherical shape. However, it should be noted that there may be applications where the interface between materials 48 and 52 is sufficiently conductive to render the additional surface area of ​​little benefit.

[0050] In some embodiments, Figures 1 to 1B The conductive cover 46 can be referred to as the first conductive cover, and Figures 2 to 2B The conductive cap 48 can be referred to as the second conductive cap. For example... Figures 1 to 1B and Figures 2 to 2BAs shown, the first conductive cap and the second conductive cap can be used interchangeably. In some embodiments, the first conductive cap and the second conductive cap can be used together, such as... Figures 3 to 3B As shown in the image.

[0051] In some embodiments, conductive oxide 28 ( Figures 1 to 1B , Figures 2 to 2B and Figures 3 to 3B The upper and lower regions of semiconductor material 26 can be omitted, and alternatively, the upper and lower regions can be suitably doped to serve as source / drain regions 32 and 34, while the central region of material 26 remains as channel region 30. Examples of these embodiments are shown in Figures 4 to 4B The illustrated example has both a lower (first) hemispherical structure 46 and an upper (second) hemispherical structure 48. Other examples may include one or the other of hemispherical structure 46 and hemispherical structure 48, similar to... Figures 1 to 1B and Figures 2 to 2B The configuration shown in the image.

[0052] The assemblies described above can be formed through any suitable processing. (Reference) Figures 5 to 9 Describe instance processing.

[0053] refer to Figures 5 to 5B Assembly 10 is shown in a processing stage after the conductive structure (feature) 16 and insulating material 22 are formed over the semiconductor substrate 56. The substrate 56 may include semiconductor materials; and may include, for example, monocrystalline silicon, be primarily composed of monocrystalline silicon, or be composed of monocrystalline silicon. The substrate 56 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction that includes semiconductor materials, including but not limited to bulk semiconductor materials, such as semiconductor wafers (alone or in assemblies including other materials), and semiconductor material layers (alone or in assemblies including other materials). The term "substrate" means any support structure, including but not limited to the semiconductor substrates described above. In some applications, the substrate 56 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0054] Conductive feature 16 can be Figures 5 to 5B In the processing stage or at any other suitable processing stage, selectively with the sensing circuitry 18 (in Figures 1 to 1B It was shown in the middle, but not in the middle. Figures 5 to 5B (The coupling is shown in the middle.)

[0055] Conductive feature 16 includes conductive material 58. This conductive material may include the material referenced above. Figures 1 to 1B Any of the described compositions, and in some embodiments may include tungsten and / or molybdenum.

[0056] Conductive feature 16 is a linear extension feature and can correspond to a digital line.

[0057] Intervention region 20 is shown between conductive features 16 and includes insulating material 22. In some embodiments, intervention region 20 may be referred to as intervention insulating region.

[0058] The insulating material 22 and the conductive material 58 can be considered to form the structure 60 together. The structure 60 has a planarized upper surface 61 extending across the conductive material 58 and the insulating material 22. The planarized surface 61 can be formed by any suitable treatment, including, for example, chemical mechanical polishing (CMP). The upper surface 61 includes a conductive portion (region) 62 corresponding to the upper surface of the conductive feature 16, and includes an insulating portion (region) 64 corresponding to the upper surface of the intervening insulating region 22 (i.e., the upper surface of the insulating material 22).

[0059] refer to Figures 6 to 6B Conductive material 66 is selectively formed above the conductive portion 62 of surface 61 relative to the insulating portion 64. Conductive material 66 may be referred to as a second conductive material to distinguish it from the first conductive material 58. Conductive material 66 is configured as described above relative to... Figures 1 to 1B The conductive cap 46 is described and may include any of the compositions suitable for such a conductive cap described above. For example, in some embodiments, the conductive material 66 may include one or more of the following, be primarily composed of one or more of the following, or be composed of one or more of the following: Cu, Ru, Pt, Pd, Co, Ni, W, Mo, and Ti.

[0060] Material 66 can be selectively formed on conductive region 62 using any suitable process, including one or more of, such as plating, atomic layer deposition (ALD), and chemical vapor deposition (CVD). If plating is used, it can include electrolytic plating or electroless plating. Electrolytic plating can use a chemical solution having ions of the metal desired within material 66 of conductive cap 46, and can use a current applied through conductive structure 16 to induce the metal to deposit from the chemical solution onto conductive structure 16 to form conductive cap 46 over such conductive structure. Electroless plating can use an autocatalytic plating solution to achieve selective plating on conductive material 58.

[0061] Because the conductive material 66 deposits faster along the central region of the conductive structure 16 than along the edge region, the conductive cap 46 can be formed into the illustrated hemispherical structure. In the case of electroplating, this hemispherical protrusion occurs because the central region of the conductive structure 16 has a higher current than the edge region. In the case of no electroplating, CVD and ALD; because the deposition of material 66 begins in the central region of the feature and therefore the duration along the central region of the feature is longer than the duration along the edge region of the feature, this hemispherical protrusion also occurs.

[0062] refer to Figures 7 to 7B The access device support 24 is formed above the second conductive material 66 of the conductive cover 46. The access device support 24 includes the features described above. Figures 1 to 1B The semiconductor material 26 and conductive oxide 28 are described. In other embodiments, the access device pillar 24 may only include materials similar to those described above. Figures 4 to 4B Semiconductor material 26 of the described embodiment.

[0063] An insulating material 36 is formed along the sidewall of the pillar 24, and a conductive gate material 40 is formed adjacent to the insulating material 36. An insulating material 39 is then formed over the conductive gate material 40. In some embodiments, the insulating materials 36 and 39 may be referred to as a first insulating material and a second insulating material, respectively.

[0064] The conductive gate material 40 is configured as a linearly extending structure 42. In some embodiments, this structure may be a word line and may be connected to the drive circuitry 44 (in...). Figures 1 to 1B It was shown in the middle, but not in the middle. Figures 7 to 7B (As shown in the image) Electrical coupling. The coupling between word line 42 and drive circuit system 44 can be provided at any suitable processing stage, including, for example... Figures 7 to 7B In the processing stage or Figures 7 to 7B The processing stage following the processing stage.

[0065] Figures 7 to 7B The configuration can be viewed as a structure 68 comprising access device pillar 24 and insulating material 39. Structure 68 has a planarized upper surface 69 that extends across the conductive oxide 28 of the upper source / drain region 34 (i.e., it extends across the upper surface of the access device pillar 24) and across the insulating material 39. In the illustrated embodiment, the planarized surface 69 also extends across a portion of the insulating material 36.

[0066] The planarized surface 69 can be formed using any suitable process, including, for example, CMP. The upper surface 69 includes conductive portions (regions) 70 corresponding to the upper surface of the access device pillar 24, and includes insulating portions (regions) 72 between the conductive regions 70.

[0067] refer to Figures 8 to 8B Conductive material 74 is selectively formed above the conductive portion 70 of surface 69 relative to the insulating portion 72 of this surface. Conductive material 74 may be referred to as a third conductive material to distinguish it from the first conductive material 58 and the second conductive material 66. Conductive material 74 is configured as described above relative to... Figures 2 to 2B The conductive cap 48 is described and may include any of the compositions suitable for such a conductive cap described above. For example, in some embodiments, the conductive material 74 may include one or more of the following, be primarily composed of one or more of the following, or be composed of one or more of the following: Cu, Ru, Pt, Pd, Co, Ni, W, Mo, and Ti.

[0068] Material 74 can be selectively formed on conductive region 70 using any suitable processing, including one or more of, for example, plating, ALD, and CVD; wherein such processing is similar to that described above. Figures 6 to 6B The described process.

[0069] refer to Figures 9 to 9B Conductive interconnects 50 are formed above conductive cap 48. In the illustrated embodiment, an insulating material 76 is provided across cap 48. An opening is formed through this insulating material to expose the upper surface of the cap, and then the interconnect 50 is formed within this opening. Metal nitride 52 is formed as a liner opening, and then core material 54 is formed within the liner opening. Subsequently, CMP or other suitable processes can be used to form a planarized surface 77 extending across the illustrated interconnect 50 and insulating material 76. In subsequent processing, storage element 14 ( Figures 2 to 2B It can be electrically coupled to interconnect 54.

[0070] Figures 5 to 9 The process forms both a bottom conductive cap 46 and a top conductive cap 48. In other embodiments, the process can be used to form an assembly having only the bottom conductive cap 46 (similar to...). Figures 1 to 1B (assemblies) or assemblies having only the upper conductive cover 48 (similar to) Figures 2 to 2B (Assemblies).

[0071] Access device support 24 can be configured similarly to the above reference. Figures 1 to 1B The described array is a memory array in which each of the access device pillars is uniquely addressed by one of the first linear extension structures 16 and one of the second linear extension structures 42.

[0072] The memory array, including the access device pillar 24 and the storage element 14, can include any suitable configuration. Figure 10An example configuration of a DRAM array 80 is shown. This configuration has digital lines 16 (DL1 to DL4) coupled to a sensing circuitry 18 and extending along the columns of the array, and word lines 42 (WL1 to WL4) coupled to a driving circuitry 44 and extending along the rows of the array. Memory cells 82 include access transistors 12 and storage elements 14, wherein the illustrated storage elements are configured as capacitors. Each of the capacitors has a first electrical node coupled to the associated access device 12 and a second electrical node coupled to a reference voltage source 84 (e.g., a common board voltage, such as ground, VCC / 2, etc.). Each of the memory cells 82 is uniquely addressed by one of the digital lines and one of the word lines.

[0073] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0074] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0075] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. In some cases, the term “dielectric” and in others, the term “insulating” (or “electrically insulating”) may be used within this disclosure to provide linguistic variation to simplify the premises within the appended claims, rather than to indicate any significant chemical or electrical differences.

[0076] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others provides linguistic variation within this disclosure to simplify the presuppositions of the appended claims.

[0077] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in or rotated relative to the specific orientation of the drawings.

[0078] Unless otherwise specified, the accompanying cross-sectional drawings show only the features within the cross-sectional plane and not the material behind the cross-sectional plane in order to simplify the drawings.

[0079] When a structure is referred to above as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be intervening structures. In contrast, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0080] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure typically extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may extend substantially orthogonally relative to or not relative to the upper surface of the substrate.

[0081] Some embodiments include a device having a semiconductor material comprising at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table. The device has a conductive structure below the semiconductor material and configured to be electrically coupled to the semiconductor material in at least one operating mode of the device. The device has a hemispherical metal cap above the conductive structure and below the semiconductor material.

[0082] Some embodiments include an integrated assembly having access means between a memory element and a conductive structure. The access means has a channel material comprising a semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table. The channel material has a first end and an opposing second end, and has sides extending from the first end to the second end. The first end is adjacent to the conductive structure, and the second end is adjacent to the memory element. A conductive gate material is adjacent to the sides of the channel material. A first hemispherical metal cap is above the conductive structure and below the channel material, and / or a second hemispherical metal cap is above the channel material and below the memory element.

[0083] Some embodiments include a method of forming an integrated assembly. A conductive feature is formed on a semiconductor substrate. The conductive feature includes a first conductive material. The conductive features are spaced apart from each other by intervening insulating regions. The configuration includes the conductive features and the insulating regions. An upper surface of the configuration includes a conductive portion corresponding to the upper surface of the conductive feature and an insulating portion corresponding to the upper surface of the intervening insulating region. A second conductive material is selectively formed above the conductive portion relative to the insulating portion. An access device pillar is formed above the second conductive material. The access device pillar includes a channel material comprising a semiconductor material having at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table. An insulating material is formed along one or more sidewalls of each of the access device pillars. A conductive gate is formed adjacent to the insulating material. A memory element is formed above the access device pillar and gate-coupled to the conductive feature through the channel material of the access device pillar.

[0084] Some embodiments include a method of forming an integrated assembly. A first linearly extending conductive structure is formed over a semiconductor substrate. The first linearly extending conductive structure extends along a first direction. Access device pillars are formed over the first linearly extending conductive structure. The access device pillars include a channel material comprising a semiconductor material having at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table. A first insulating material is formed along one or more sidewalls of the access device pillars. A conductive gate is formed adjacent to the first insulating material. The conductive gate extends along a second linear extension feature along a second direction, wherein the second direction intersects the first direction. A second insulating material is formed over the conductive gate and between the access device pillars. The configuration includes access device pillars and a second insulating material. The configuration has an upper surface having conductive regions corresponding to the upper surfaces of the access device pillars, and insulating regions between the conductive regions that include the second insulating material. A conductive overlay material is selectively formed over the conductive regions relative to the insulating regions. A memory element is formed that is coupled to the conductive overlay material.

[0085] As per the description, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims have the full scope as stated in the writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A memory device comprising: A semiconductor material comprising a transistor channel and at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table, the transistor channel comprising a hemispherical uppermost surface. A conductive structure, which is beneath the semiconductor material and configured to be electrically coupled to the semiconductor material in at least one operating mode of the memory device; A hemispherical metal cap is located above the conductive structure and below the semiconductor material; The source / drain region abuts the uppermost hemispherical surface of the transistor channel; and The source / drain region includes the lowermost surface of the uppermost hemispherical surface that abuts the transistor channel.

2. The memory device according to claim 1, wherein the semiconductor material is a semiconductor oxide material.

3. The memory device of claim 1, wherein the metal cap comprises one or more of Cu, Ru, Pt, Pd, Co, Ni, W, Mo and Ti.

4. The memory device of claim 1, wherein the metal cap comprises one or both of a metal silicide and a metal nitride.

5. The memory device of claim 1, wherein the semiconductor material directly abuts the hemispherical metal cap.

6. The memory device of claim 1, comprising a conductive oxide material between the semiconductor material and the hemispherical metal cap.

7. The memory device of claim 6, wherein the conductive oxide material comprises oxygen and one or more of indium, zinc and tin.

8. The memory device of claim 7, wherein the conductive oxide material comprises the oxygen and the zinc, and further comprises one or both of aluminum and gallium.

9. The memory device of claim 1, wherein the semiconductor material comprises InGaZnO, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

10. An integrated memory, comprising access means between a storage element and a conductive structure; The access device includes: A channel material, comprising a semiconductor material; the channel material having a first end and an opposing second end, and having a side extending from the first end to the second end; the first end being adjacent to the conductive structure, and the second end being adjacent to the memory element; the semiconductor material comprising at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table; A conductive gate material, adjacent to the sidewall of the channel material; and At least one of a first hemispherical metal-containing cap and a second hemispherical metal-containing cap, wherein the first hemispherical metal-containing cap is above the conductive structure and below the channel material, and the second hemispherical metal-containing cap is above the channel material and below the storage element.

11. The integrated memory of claim 10, wherein the semiconductor material is a semiconductor oxide.

12. The integrated memory of claim 10, wherein the conductive structure is a first linear structure coupled to a sensing circuit system, and wherein the conductive gate material is part of a second linear structure coupled to a driver circuit system.

13. The integrated memory of claim 10, comprising the first hemispherical metal cap.

14. The integrated memory of claim 10, comprising the second hemispherical metal cap.

15. The integrated memory according to claim 10, comprising both the first hemispherical metal-containing cap and the second hemispherical metal-containing cap.

16. The integrated memory of claim 10, wherein the storage element and the access means are located within a memory cell, and wherein the memory cell is one of a plurality of substantially identical memory cells in a memory array.

17. The integrated memory according to claim 10, comprising: A first conductive region is located between the conductive structure and the channel material; and A second conductive region is located above the channel material, wherein the first and second conductive regions comprise conductive oxides.

18. The integrated memory according to claim 17, comprising: The second hemispherical metal cap is located above and directly abuts the conductive oxide in the second conductive region. and A conductive interconnect is located above the second hemispherical metal cap, and the conductive interconnect is electrically coupled to the storage element.

19. The integrated memory of claim 18, wherein the conductive interconnect comprises a metal nitride directly abutting the second hemispherical metal cap.

20. The integrated memory of claim 19, wherein the metal nitride is configured in an upwardly open container shape and includes a metal-containing core material within the upwardly open container shape; the core material is substantially composed of one or more metals.

21. The integrated memory of claim 20, wherein the metal nitride comprises one or more of titanium nitride, molybdenum nitride, and tungsten nitride, and wherein the core material comprises one or more of titanium, molybdenum, and tungsten.

22. The integrated memory of claim 10, comprising an insulating material between the conductive gate material and the channel material.

23. The integrated memory of claim 22, wherein the insulating material comprises silicon dioxide and / or one or more high-k compositions.

24. A method of forming an integrated memory, comprising: A conductive feature is formed on a semiconductor substrate, the conductive feature comprising a first conductive material, the conductive feature being spaced apart from each other by an intervening insulating region, the structure comprising the conductive feature and the insulating region, the upper surface of the structure comprising a conductive portion corresponding to the upper surface of the conductive feature, and comprising an insulating portion corresponding to the upper surface of the intervening insulating region; A second conductive material is selectively formed over the conductive portion relative to the insulating portion; An access device pillar is formed above the second conductive material, the access device pillar comprising a channel material comprising a semiconductor material having at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table. An insulating material is formed along one or more sidewalls of each of the support pillars of the access device; A conductive gate is formed adjacent to the insulating material; and A storage element is formed above the access device pillar, and the storage element is gate-coupled to the conductive feature through the channel material of the access device pillar.

25. The method of claim 24, wherein the semiconductor material is a semiconductor oxide material.

26. The method of claim 24, wherein the selective formation of the second conductive material utilizes one or more of plating, ALD, and CVD.

27. The method of claim 24, wherein the access device support comprises conductive oxides above and below the channel material.

28. The method of claim 24, wherein the conductive feature is a first linear extension feature extending along a first direction.

29. The method of claim 28, wherein the second conductive material forms a hemispherical cap over the first linear extension feature.

30. The method of claim 28, wherein the conductive gate extends along a second linear extension feature extending in a second direction, wherein the second direction intersects the first direction.

31. The method of claim 30, wherein the first linear extension feature is electrically coupled to the sensing circuit system, and wherein the second linear extension feature is electrically coupled to the driver circuit system.

32. The method of claim 31, wherein the access device pillars are arranged in an array, wherein each of the access device pillars is uniquely addressed by one of the first linear extension features and one of the second linear extension features.

33. The method of claim 24, wherein the insulating material comprises one or more high-k compositions.

34. The method of claim 24, further comprising: A second insulating material is formed above the conductive gate and between the access device pillars. The second configuration includes the access device pillars and the second insulating material. The second configuration has an upper surface, the upper surface having a second conductive portion corresponding to the upper surface of the access device pillars, and having a second insulating portion between the second conductive portions and including the second insulating material. and A third conductive material is selectively formed over the second conductive portion relative to the second insulating portion.

35. A method for forming an integrated memory, comprising: A first linearly extending conductive structure is formed on a semiconductor substrate, the first linearly extending conductive structure extending along a first direction; An access device pillar is formed above the first linearly extended conductive structure, the access device pillar comprising a channel material comprising a semiconductor material having at least one element selected from Group 13 of the periodic table and at least one element selected from Group 16 of the periodic table. A first insulating material is formed along one or more sidewalls of the support pillar of the access device; A conductive gate is formed adjacent to the first insulating material, the conductive gate being a second linear extension feature extending along a second direction, wherein the second direction intersects the first direction; A second insulating material is formed above the conductive gate and between the access device pillars. The configuration includes the access device pillars and the second insulating material. The configuration has an upper surface, the upper surface has a conductive region corresponding to the upper surface of the access device pillar, and has an insulating region between the conductive regions that includes the second insulating material. A conductive covering material is selectively formed over the conductive region relative to the insulating region; and A storage element coupled to the conductive covering material is formed.

36. The method of claim 35, wherein the semiconductor material is a semiconductor oxide material.

37. The method of claim 35, wherein the conductive covering material forms a hemispherical cover over the conductive area.

38. The method of claim 35, wherein the selective formation of the conductive coating material utilizes one or more of plating, ALD, and CVD.

39. The method of claim 35, wherein the access device support comprises conductive oxides above and below the channel material.

40. The method of claim 35, wherein the first linear extension feature is electrically coupled to the sensing circuit system, and wherein the second linear extension feature is electrically coupled to the driver circuit system.

41. The method of claim 40, wherein the access device pillars are arranged in an array, wherein each of the access device pillars is uniquely addressed by one of the first linear extension features and one of the second linear extension features.

42. The method of claim 35, wherein the conductive covering material forms a conductive cover over the conductive region; and the method further comprises forming a conductive interconnect over the conductive cover, the conductive interconnect being electrically coupled to the storage element.

43. The method of claim 42, wherein the conductive interconnect comprises a metal nitride directly abutting the conductive cap, wherein the metal nitride is configured in an upwardly open container shape; and wherein a metal core material is contained within the upwardly open container shape.

44. The method of claim 43, wherein the metal nitride comprises one or more of titanium nitride, molybdenum nitride, and tungsten nitride, and wherein the core material comprises one or more of titanium, molybdenum, and tungsten.

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