Semiconductor device with low-K spacer

Abstract

A semiconductor device with a low-k spacer is provided. The semiconductor device includes: a bit line structure, which includes a bit line contact plug, a bit line, and a bit line hard mask stacked in sequence on a substrate; a storage node contact plug, which is spaced apart from the bit line structure; a conformal spacer, which is located between the bit line and the storage node contact plug and includes a low-k material; and a seed liner, which is located between the conformal spacer and the bit line and is thinner than the conformal spacer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0105302, filed on August 21, 2020, and No. 10-2021-0013422, filed on January 29, 2021, which are hereby incorporated by reference in their entirety. Technical Field

[0003] Various embodiments of the present invention relate generally to a semiconductor device, and more particularly, to a semiconductor device having a low-k spacer. Background Art

[0004] In semiconductor devices, dielectric materials can be formed between adjacent pattern structures. As the integration of semiconductor devices increases, the distance between pattern structures decreases, which in turn may increase the occurrence of significant parasitic capacitance problems. This is because the increase in parasitic capacitance can degrade the performance of semiconductor devices. Therefore, solving the parasitic capacitance problem has become a limiting factor that needs to be solved in order to further obtain enhanced integration of semiconductor devices. Summary of the invention

[0005] An embodiment of the present invention is directed to a semiconductor device capable of reducing parasitic capacitance between adjacent pattern structures.

[0006] According to one embodiment of the present invention, a semiconductor device includes: a bit line structure, which includes a bit line contact plug, a bit line and a bit line hard mask stacked in sequence on a substrate; a storage node contact plug, which is separated from the bit line structure; a conformal spacer, which is located between the bit line and the storage node contact plug and includes a low-k material; and a seed liner, which is located between the conformal spacer and the bit line, wherein the seed liner is thinner than the conformal spacer.

[0007] According to another embodiment of the present invention, a semiconductor device includes: bit lines, which are separated from each other by linear openings above a substrate; bit line contact plugs, which are respectively located below the bit lines; multiple plug isolation layers, which divide the linear openings into multiple contact openings; storage node contact plugs, which respectively fill the contact openings; a first spacer structure, which is arranged between the storage node contact plugs and the bit lines and includes a stack of a first silicon nitride, a first low-k material, silicon oxide, and a second low-k material; and a second spacer structure, which is arranged between the bit line contact plug and the storage node contact plug and includes a stack of a second silicon nitride, a third low-k material, and a third silicon nitride, wherein the second silicon nitride extends from the first silicon nitride and the third low-k material extends from the first low-k material.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a plurality of bit line structures above a substrate, the plurality of bit line structures including bit line contact plugs and bit lines above the bit line contact plugs; forming spacer structures on side walls of the bit line structures; and forming storage node contact plugs of the contact spacer structures between the bit line structures, wherein the step of forming the spacer structures includes: forming a nitrogen-containing seed liner on the side walls of the bit line structures; and conformally forming a first low-k spacer on the nitrogen-containing seed liner, the first low-k spacer having a lower dielectric constant than the nitrogen-containing seed liner.

[0009] These and other advantages and features of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0011] Figure 2A is along Figure 1 A cross-sectional view taken along line AA′.

[0012] Figure 2B is along Figure 1 A cross-sectional view taken along line A1-A1′.

[0013] Figure 3A and Figure 3B is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0014] Figure 4 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0015] Figure 5 is a plan view showing a semiconductor device according to another embodiment of the present invention.

[0016] Fig. 6A is along Figure 5 A cross-sectional view taken along line AA′.

[0017] Figure 6B is along Figure 5 A cross-sectional view taken along line BB′.

[0018] Figure 6C Shows Fig. 6A A modified example of the second spacer structure 215U shown in FIG.

[0019] Figures 7 to 19 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0020] Figure 20 to Figure 22is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[0021] Fig.23 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0022] Figure 24 to Figure 27 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[0023] Figure 28 to Figure 32 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[0024] Fig.33 and Fig.34 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, in each figure and embodiment of the present invention, the same reference numerals refer to the same parts.

[0026] The drawings are not necessarily drawn to scale, and in some cases, the proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as "on a second layer" or "on a substrate", it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0027] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Figure 2A is along Figure 1 A cross-sectional view taken along line AA′. Figure 2B is along Figure 1 A cross-sectional view taken along line A1-A1′.

[0028] refer to Figure 1 , Figure 2A and Figure 2B , the semiconductor device 100 may include a substrate 101, a pattern structure 105, and a dielectric structure 110 formed on both sidewalls of the pattern structure 105. The two sidewalls may be opposite sidewalls.

[0029] The pattern structure 105 may be formed over the substrate 101. The pattern structure 105 may include a first conductive pattern 102 formed over the substrate 101. The pattern structure 105 may also include a second conductive pattern 103 over the first conductive pattern 102 and a hard mask pattern 104 over the second conductive pattern 103. The first conductive pattern 102 may directly contact the substrate 101. Although not shown, the first conductive pattern 102 and the substrate 101 may be electrically disconnected by an insulating material or a dielectric material layer. The first conductive pattern 102 and the second conductive pattern 103 may be in direct contact and may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The hard mask pattern 104 may be directly formed on the second conductive pattern 103 and may include a dielectric material.

[0030] refer to Figure 1 , the length L1 of the second conductive pattern 103 may be shorter than the length L2 of the first conductive pattern 102. Figure 2A and Figure 2B , the pattern structure 105 may extend in one direction. In one embodiment, the length L1 of the second conductive pattern 103 may be longer than the length L2 of the first conductive pattern 102. The second conductive pattern 103 may extend while overlapping the first conductive pattern 102.

[0031] The dielectric structure 110 may include a lower-level dielectric structure 110L and an upper-level dielectric structure 110U. The upper-level dielectric structure 110U may be located on both sidewalls of the second conductive pattern 103 and the hard mask pattern 104 of the pattern structure 105, but may extend longer in one direction, which is more generally referred to as the length direction of the upper-level dielectric structure 110U and the length direction of the pattern structure 105. Along the length direction of the pattern structure 105, the lower-level dielectric structure 110L may be located on both sidewalls of the first conductive pattern 102 of the pattern structure 105. The length L2 of the lower-level dielectric structure 110L may be shorter than the length L1 of the upper-level dielectric structure 110U. The upper-level dielectric structure 110U may be located at a higher level than the lower-level dielectric structure 110L. The lower-level dielectric structure 110L and the upper-level dielectric structure 110U may be integral, meaning that they may be formed uninterruptedly as a single continuous structure. The lower level dielectric structure 110L may be vertically continued from the upper level dielectric structure 110U. The lower level dielectric structure 110L and the upper level dielectric structure 110U may have the same structure. The lower level dielectric structure 110L and the upper level dielectric structure 110U may be made of the same material or materials. In one embodiment, the lower level dielectric structure 110L and the upper level dielectric structure 110U may have the same structure or the same material.

[0032] The dielectric structure 110 may include multiple layers of dielectric material. The dielectric structure 110 may include a seed liner 111 located on both sidewalls of the pattern structure 105. The dielectric structure 110 may also include a conformal layer 112 formed on the seed liner 111. The stack of the seed liner 111 and the conformal layer 112 may be located on both sidewalls of the first conductive pattern 102. The stack of the seed liner 111 and the conformal layer 112 may be located on both sidewalls of the second conductive pattern 103. The lower level dielectric structure 110L and the upper level dielectric structure 110U may each include a stack of the seed liner 111 and the conformal layer 112.

[0033] The seed liner 111 may be used as a seed for depositing the conformal layer 112. The seed liner 111 may improve the step coverage of the conformal layer 112. The seed liner 111 may have a thickness of about or less. The seed liner 111 may have a thickness ranging from about To date Thickness.

[0034] Conformal layer 112 may have a first dielectric constant and seed liner 111 may have a second dielectric constant. The value of the first dielectric constant may be lower than the value of the second dielectric constant. Conformal layer 112 may have a lower dielectric constant than seed liner 111. For example, the second dielectric constant may be about 7.5 and the first dielectric constant may be less than about 7. For example, the first dielectric constant may be about 4.4 or less. In one embodiment, conformal layer 112 may include a low-k material and seed liner 111 may have a dielectric constant greater than the low-k material. The dielectric constant of conformal layer 112 may be lower than the dielectric constant of silicon oxide. For example, in one embodiment, seed liner 111 may include silicon nitride and the dielectric constant of conformal layer 112 may be lower than the dielectric constant of silicon oxide. Seed liner 111 may be thinner than conformal layer 112. Therefore, the thickness of the conformal layer 112 in the dielectric structure 110 may be relatively large compared to the thickness of the seed liner 111 , and since the seed liner 111 is very thin, the overall dielectric constant of the dielectric structure 110 may be reduced.

[0035] The seed liner 111 and the conformal layer 112 may include a silicon-based material. The seed liner 111 and the conformal layer 112 may include a silicon-based dielectric material. The seed liner 111 may not contain impurities, and the conformal layer 112 may contain impurities. Since the conformal layer 112 contains impurities, the dielectric constant of the conformal layer 112 may be lower than the dielectric constant of the seed liner 111. The seed liner 111 may contain an impurity-free silicon-based material, and the conformal layer 112 may contain an impurity-containing silicon-based material. The conformal layer 112 may contain carbon, boron, or a combination thereof as an impurity. The impurity-containing silicon-based material may include a carbon-containing material, a boron-containing material, or a carbon- and boron-containing material. For example, the impurity-containing silicon-based material may include SiC (silicon carbide), SiCO (silicon oxycarbide), SiCN (silicon carbide nitride), SiOCN (silicon oxycarbon nitride), SiBN (silicon boron nitride), or SiBCN (silicon boron carbon nitrogen). The seed liner 111 may include silicon nitride, and the conformal layer 112 may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN. The seed liner 111 may prevent impurities from diffusing from the conformal layer 112 .

[0036] The dielectric structure 110 may include a NK (nitride-low-k) structure. In the NK structure, N may correspond to the seed liner 111, and K may correspond to the conformal layer 112. The NK structure may be formed by a stack of the seed liner 111 and the conformal layer 112. An example of the NK structure may include a stack of silicon nitride and a low-k material. Another example of the NK structure may include a stack of silicon nitride and an impurity-containing silicon-based material. An example of the NK structure may include a stack of Si3N4 / SiCO.

[0037] Figure 3A and Figure 3B is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0038] Figure 3A The semiconductor device 100 ′ and Figure 3B The semiconductor device 100 ″ may be similar to Figure 1 A semiconductor device 100 is provided.

[0039] Figure 3A The semiconductor device 100 ′ may include a substrate 101 , a pattern structure 105 over the substrate 101 , and dielectric structures 110 ′ on both sides of the pattern structure 105 .

[0040] The pattern structure 105 may include a first conductive pattern 102 formed over a substrate 101. The pattern structure 105 may also include a second conductive pattern 103 over the first conductive pattern 102 and a hard mask pattern 104 over the second conductive pattern 103. The first conductive pattern 102 may be in direct contact with the substrate 101. The first conductive pattern 102 and the substrate 101 may be electrically disconnected by an insulating material or a dielectric material layer. The first conductive pattern 102 and the second conductive pattern 103 may be in direct contact and may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The hard mask pattern 104 may be formed directly on the second conductive pattern 103 and may include a dielectric material. The pattern structure 105 may extend longer in one direction, which will be referred to as a length direction. As shown in FIG. Figure 3A As shown, the length L1 of the second conductive pattern 103 may be shorter than the length L2 of the first conductive pattern 102. The second conductive pattern 103 may extend while overlapping the first conductive pattern 102. In one embodiment, the length L1 of the second conductive pattern 103 may be longer than the length L2 of the first conductive pattern 102, as shown in FIG. Figure 2A and Figure 2B shown.

[0041] The dielectric structure 110′ may include a lower-level dielectric structure 110L′ and an upper-level dielectric structure 110U′. The upper-level dielectric structure 110U′ may be located on both sidewalls of the second conductive pattern 103 and the hard mask pattern 104 of the pattern structure 105, but may extend longer in its length direction. The lower-level dielectric structure 110L′ may be located on both sidewalls of the first conductive pattern 102 of the pattern structure 105. The lower-level dielectric structure 110L′ may be shorter than the upper-level dielectric structure 110U′ along the length direction of the pattern structure 105. The upper-level dielectric structure 110U′ may be located at a higher level than the lower-level dielectric structure 110L′. The lower-level dielectric structure 110L′ and the upper-level dielectric structure 110U′ may include an integrated common portion. The integrated common portion may extend vertically from the lower-level dielectric structure 110L′ to the upper-level dielectric structure 110U′. The lower-level dielectric structure 110L′ and the upper-level dielectric structure 110U′ may have different structures or different materials.

[0042] The dielectric structure 110′ may include multiple layers of dielectric materials. The dielectric structure 110′ may include a seed liner 111 located on both sidewalls of the pattern structure 105. The dielectric structure 110′ may also include a conformal layer 112 formed on the seed liner 111. The stack of the seed liner 111 and the conformal layer 112 may be located on both sidewalls of the first conductive pattern 102. The stack of the seed liner 111 and the conformal layer 112 may be located on both sidewalls of the second conductive pattern 103. The lower level dielectric structure 110L′ and the upper level dielectric structure 110U′ may jointly include a stack of the seed liner 111 and the conformal layer 112.

[0043] The seed liner 111 may be used as a seed for depositing the conformal layer 112. The step coverage of the conformal layer 112 may be improved by the seed liner 111. The seed liner 111 may have a thickness of about In one embodiment, the seed liner 111 may have a thickness of about 1 to about The seed liner 111 may be thinner than the conformal layer 112 .

[0044] The conformal layer 112 may have a first dielectric constant, and the seed liner 111 may have a second dielectric constant. The value of the first dielectric constant may be lower than the value of the second dielectric constant. The conformal layer 112 may have a lower dielectric constant than the seed liner 111. The first dielectric constant may be approximately 4.4 or less, and the second dielectric constant may be approximately 7.5. The conformal layer 112 may include a low-k material. The seed liner 111 may have a dielectric constant greater than the low-k material. The seed liner 111 may include silicon nitride, and the dielectric constant of the conformal layer 112 may be lower than the dielectric constant of silicon nitride. The dielectric constant of the conformal layer 112 may be lower than the dielectric constant of silicon oxide.

[0045] The seed liner 111 and the conformal layer 112 may include a silicon-based material. The seed liner 111 may not contain impurities, while the conformal layer 112 may contain impurities. Since the conformal layer 112 contains impurities, the dielectric constant of the conformal layer 112 may be lower than the dielectric constant of the seed liner 111. The seed liner 111 may include a silicon-based material without impurities, while the conformal layer 112 may include a silicon-based material containing impurities. The conformal layer 112 may include a carbon-containing material, a boron-containing material, or a material containing carbon and boron. For example, the conformal layer 112 may include carbon, boron, or a combination thereof as impurities. The impure silicon-based material may include SiCO, SiCN, SiOCN, SiBN, or SiBCN. The seed liner 111 may include silicon nitride, and the conformal layer 112 may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0046] The dielectric structure 110′ may further include a first spacer 113, a second spacer 114, and a third spacer 115. The first spacer 113 may be formed on the conformal layer 112. The seed liner 111 and the conformal layer 112 may be located between the first spacer 113 and the first conductive pattern 102. The second spacer 114 may be formed on the conformal layer 112, and the third spacer 115 may be formed on the second spacer 114. The seed liner 111 and the conformal layer 112 may be located between the second conductive pattern 103 and the second spacer 114, and the second spacer 114 may be located between the conformal layer 112 and the third spacer 115.

[0047] The lower level dielectric structure 110L′ may include a stack of a seed liner 111, a conformal layer 112, and a first spacer 113. The upper level dielectric structure 110U′ may include a stack of a seed liner 111, a conformal layer 112, a second spacer 114, and a third spacer 115. The third spacer 115 may have a lower dielectric constant than the first spacer 113 and the second spacer 114. According to another embodiment of the present invention, the third spacer 115 may have a higher dielectric constant than the second spacer 114. The conformal layer 112 and the third spacer 115 may have the same dielectric constant. According to another embodiment of the present invention, the third spacer 115 may have a higher dielectric constant than the conformal layer 112. The third spacer 115 has excellent etching resistance. Therefore, the third spacer 115 can prevent the loss of the second spacer 114. The conformal layer 112 and the third spacer 115 may be formed of the same material. The first spacer 113 and the second spacer 114 may be formed of different materials. The first spacer 113 may include silicon nitride, and the second spacer 114 may include silicon oxide. The third spacer 115 may include a silicon-based material containing impurities. The third spacer 115 may include a carbon-containing material, a boron-containing material, or a material containing carbon and boron. For example, the third spacer 115 may include carbon, boron, or a combination thereof as impurities. The silicon-based material containing impurities may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0048] The lower level dielectric structure 110L′ may include a NKN (nitride-low-k-nitride) structure. The NKN structure may be formed by a stack of a seed liner 111, a conformal layer 112, and a first spacer 113. An example of a NKN structure may include a stack of silicon nitride, a low-k material, and silicon nitride. Another example of a NKN structure may include a stack of silicon nitride, an impurity-containing silicon-based material, and silicon nitride. An example of a NKN structure may include a stack of Si3N4 / SiCO / Si3N4.

[0049] The upper level dielectric structure 110U′ may include a NKOK (nitride-low-k-oxide-low-k) structure. The NKOK structure may be formed by a stack of a seed liner 111, a conformal layer 112, a second spacer 114, and a third spacer 115. An example of the NKOK structure may include a stack of silicon nitride, a low-k material, silicon oxide, and a low-k material. Another example of the NKOK structure may include a stack of silicon nitride, an impure silicon-based material, silicon oxide, and an impure silicon-based material. An example of the NKOK structure may include a stack of Si3N4 / SiCO / SiO2 / SiCO.

[0050] Figure 3B The semiconductor device 100 ″ may include a substrate 101 , a pattern structure 105 over the substrate 101 , and a dielectric structure 110 ″ on both sides of the pattern structure 105 .

[0051] The pattern structure 105 may include a first conductive pattern 102 formed over a substrate 101. The pattern structure 105 may also include a second conductive pattern 103 over the first conductive pattern 102 and a hard mask pattern 104 over the second conductive pattern 103. The first conductive pattern 102 may directly contact the substrate 101. The first conductive pattern 102 and the substrate 101 may be electrically disconnected by an insulating material or a dielectric material layer. The first conductive pattern 102 and the second conductive pattern 103 may directly contact and may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The hard mask pattern 104 may be directly formed on the second conductive pattern 103 and may include a dielectric material. The pattern structure 105 may extend in one direction. As shown in FIG. Figure 2A and Figure 2B As shown, the length L1 of the second conductive pattern 103 may be longer than the length L2 of the first conductive pattern 102. The second conductive pattern 103 may extend while overlapping the first conductive pattern 102.

[0052] The dielectric structure 110″ may include a lower-level dielectric structure 110L′ and an upper-level dielectric structure 110U″. The upper-level dielectric structure 110U″ may be located on both sidewalls of the second conductive pattern 103 and the hard mask pattern 104 of the pattern structure 105, but may extend longer in the length direction of the pattern structure 105. The lower-level dielectric structure 110L′ may be located on both sidewalls of the first conductive pattern 102 of the pattern structure 105. Along the length direction of the pattern structure 105, the lower-level dielectric structure 110L′ may be shorter than the upper-level dielectric structure 110U″. The upper-level dielectric structure 110U″ may be located at a higher level than the lower-level dielectric structure 110L′. The lower-level dielectric structure 110L″ and the upper-level dielectric structure 110U″ may have an integrated common portion. The integrated common portion may extend from the upper-level dielectric structure 110U″ to the lower-level dielectric structure 110L′. The lower-level dielectric structure 110L′ and the upper-level dielectric structure 110U″ may have different structures or different materials.

[0053] The dielectric structure 110″ may include multiple layers of dielectric material. The dielectric structure 110″ may include a seed liner 111 located on both sidewalls of the pattern structure 105. The dielectric structure 110″ may also include a conformal layer 112 formed on the seed liner 111. The stack of the seed liner 111 and the conformal layer 112 may be located on both sidewalls of the first conductive pattern 102. The stack of the seed liner 111 and the conformal layer 112 may be located on both sidewalls of the second conductive pattern 103. Each of the lower-level dielectric structure 110L′ and the upper-level dielectric structure 110U″ may include a stack of the seed liner 111 and the conformal layer 112.

[0054] The seed liner 111 may be used as a seed for depositing the conformal layer 112. The step coverage of the conformal layer 112 may be improved by the seed liner 111. The seed liner 111 may have a thickness of approximately In one embodiment, the seed liner 111 may have a thickness of about 1 to about The seed liner 111 may be thinner than the conformal layer 112 .

[0055] The conformal layer 112 may have a first dielectric constant and the seed liner 111 may have a second dielectric constant. The first dielectric constant may have a lower value than the second dielectric constant. The conformal layer 112 may have a lower dielectric constant than the seed liner 111. For example, the first dielectric constant may be about 3.9 or less, and the second dielectric constant may be about 7.5. The conformal layer 112 may include a low-k material. The seed liner 111 may have a higher dielectric constant than the low-k material. The conformal layer 112 may have a lower dielectric constant than silicon oxide. The seed liner 111 may include silicon nitride.

[0056] The seed liner 111 and the conformal layer 112 may include a silicon-based material. The seed liner 111 may not contain impurities, while the conformal layer 112 may contain impurities. Since the conformal layer 112 contains impurities, the dielectric constant of the conformal layer 112 may be lower than the dielectric constant of the seed liner 111. The seed liner 111 may include a silicon-based material without impurities, and the conformal layer 112 may include a silicon-based material containing impurities. The conformal layer 112 may include a carbon-containing material, a boron-containing material, or a material containing carbon and boron. For example, the conformal layer 112 may include carbon, boron, or a combination thereof as impurities. The impure silicon-based material may include SiCO, SiCN, SiOCN, SiBN, or SiBCN. The seed liner 111 may include silicon nitride, while the conformal layer 112 may include SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0057] The dielectric structure 110″ may further include a first spacer 113, a second spacer 114, a third spacer 115, and a fourth spacer 116. The first spacer 113 may be conformally formed on the conformal layer 112. The seed liner 111 and the conformal layer 112 may be located between the first spacer 113 and the first conductive pattern 102. The second spacer 114 may be formed on the conformal layer 112, and the third spacer 115 may be formed on the second spacer 114. The fourth spacer 116 may be formed on the third spacer 115. The seed liner 111 and the conformal layer 112 may be located between the second conductive pattern 103 and the second spacer 114, and the second spacer 114 may be located between the conformal layer 112 and the third spacer 115. The third spacer 115 may be located between the second spacer 114 and the fourth spacer 116.

[0058] The lower-level dielectric structure 110L′ may include a stack of a seed liner 111, a conformal layer 112, and a first spacer 113. The upper-level dielectric structure 110U″ may include a stack of a seed liner 111, a conformal layer 112, a second spacer 114, a third spacer 115, and a fourth spacer 116. The third spacer 115 may have a lower dielectric constant than the first spacer 113, the second spacer 114, and the fourth spacer 116. The conformal layer 112 and the third spacer 115 may have the same dielectric constant. The conformal layer 112 and the third spacer 115 may be formed of the same material, and the first spacer 113 and the second spacer 114 may be formed of the same material as the conformal layer 112 and the third spacer 115. The materials of the spacer 115 are formed of different materials. The seed liner 111, the first spacer 113 and the fourth spacer 116 may include silicon nitride, and the second spacer 114 may include silicon oxide. The third spacer 115 may include a silicon-based material containing impurities. The third spacer 115 may include a carbon-containing material, a boron-containing material, or a material containing carbon and boron. For example, the third spacer 115 may include carbon, boron, or a combination thereof as an impurity. The silicon-based material containing impurities may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0059] The lower level dielectric structure 110L′ may include a NKN (nitride-low-k-nitride) structure. The NKN structure may be formed by a stack of a seed liner 111, a conformal layer 112, and a first spacer 113. An example of a NKN structure may include a stack of silicon nitride, a low-k material, and silicon nitride. Another example of a NKN structure may include a stack of silicon nitride, an impurity-containing silicon-based material, and silicon nitride. An example of a NKN structure may include a stack of Si3N4 / SiCO / Si3N4.

[0060] The upper-level dielectric structure 110U″ may include a NKOKN (nitride-low-k-oxide-low-k-nitride) structure. The NKOKN structure may include a seed liner 111, a conformal layer 112, a second spacer 114, a third spacer 115, and a fourth spacer 116. An example of the NKOKN structure may include a stack of silicon nitride, a low-k material, silicon oxide, a low-k material, and silicon nitride. Another example of the NKOKN structure may include a stack of silicon nitride, an impurity-containing silicon-based material, silicon oxide, an impurity-containing silicon-based material, and silicon nitride. An example of the NKOKN structure may include a stack of Si3N4 / SiCO / SiO2 / SiCO / Si3N4.

[0061] Figure 4 1 is a cross-sectional view showing a semiconductor device 100M according to another embodiment of the present invention. Figure 4 In, appears Figures 1 to 3B The same reference numerals in the drawings may denote the same constituent elements.

[0062] Figure 4 The semiconductor device 100M shown may be similar to the semiconductor devices 100, 100' and 100" described above. The semiconductor device 100M may be similar to Figure 3A Hereinafter, the semiconductor device 100' may be omitted. Figure 4 Also appears in Figures 1 to 3B Detailed description of the constituent elements in .

[0063] refer to Figure 4 The semiconductor device 100M may include a substrate 101 , a pattern structure 105 over the substrate 101 , a plug structure 120 between the pattern structures 105 , and a dielectric structure 110 ′ between the pattern structure 105 and the plug structure 120 .

[0064] Each pattern structure 105 may include a first conductive pattern 102 formed above a substrate 101. The pattern structure 105 may also include a second conductive pattern 103 above the first conductive pattern 102 and a hard mask pattern 104 above the second conductive pattern 103. The first conductive pattern 102 may be in direct contact with the substrate 101. The first conductive pattern 102 and the substrate 101 may be electrically disconnected by an insulating material or a dielectric material layer. The first conductive pattern 102 and the second conductive pattern 103 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The hard mask pattern 104 may be directly formed on the second conductive pattern 103 and may include a dielectric material. For example, the pattern structure 105 may be stacked on the substrate 101 in a direction perpendicular to the top surface of the substrate 101 and extend in one direction.

[0065] The dielectric structure 110′ may include a lower-level dielectric structure 110L′ and an upper-level dielectric structure 110U′. The upper-level dielectric structure 110U′ may be located on both sidewalls of the second conductive pattern 103 and the hard mask pattern 104 of the pattern structure 105. The upper-level dielectric structure 110U′ may extend very long in the length direction. The lower-level dielectric structure 110L′ may be located on both sidewalls of the first conductive pattern 102 of the pattern structure 105. Along the length direction of the pattern structure 105, the lower-level dielectric structure 110L′ may be shorter than the upper-level dielectric structure 110U′. The upper-level dielectric structure 110U′ may be located at a higher level than the lower-level dielectric structure 110L′. The lower-level dielectric structure 110L′ and the upper-level dielectric structure 110U′ may include an integrated common portion. The integrated common portion may include a seed liner 111 and a conformal layer 112 and may continue from the upper level dielectric structure 110U' to the lower level dielectric structure 110L'. The lower level dielectric structure 110L' and the upper level dielectric structure 110U' may include different structures or different materials.

[0066] The dielectric structure 110′ may include multiple layers of dielectric materials. The dielectric structure 110′ may include a seed liner 111 located on both sidewalls of the pattern structure 105. The dielectric structure 110′ may also include a conformal layer 112 formed directly on the seed liner 111. The stack of the seed liner 111 and the conformal layer 112 may be located on both sidewalls of the first conductive pattern 102. The stack of the seed liner 111 and the conformal layer 112 may be located on both sidewalls of the second conductive pattern 103. Each of the lower-level dielectric structure 110L′ and the upper-level dielectric structure 110U′ may include a stack of the seed liner 111 and the conformal layer 112.

[0067] The seed liner 111 may be used as a seed for depositing the conformal layer 112. The step coverage of the conformal layer 112 may be improved by the seed liner 111. The seed liner 111 may have a thickness of about The seed liner 111 may be thinner than the conformal layer 112 .

[0068] The conformal layer 112 may have a first dielectric constant and the seed liner 111 may have a second dielectric constant. The first dielectric constant may have a lower value than the second dielectric constant. The conformal layer 112 may have a lower dielectric constant than the seed liner 111. The first dielectric constant may be about 3.9 or less, and the second dielectric constant may be about 7.5. The conformal layer 112 may include a low-k material. The seed liner 111 may have a dielectric constant greater than the low-k material. The conformal layer 112 may have a lower dielectric constant than silicon oxide. The seed liner 111 may include silicon nitride.

[0069] The seed liner 111 and the conformal layer 112 may include a silicon-based material. The seed liner 111 may not contain impurities, while the conformal layer 112 may contain impurities. Since the conformal layer 112 contains impurities, the dielectric constant of the conformal layer 112 may be lower than the dielectric constant of the seed liner 111. The seed liner 111 may include a silicon-based material without impurities, and the conformal layer 112 may include a silicon-based material containing impurities. The conformal layer 112 may include a carbon-containing material, a boron-containing material, or a material containing carbon and boron. For example, the conformal layer 112 may include carbon, boron, or a combination thereof as impurities. The impure silicon-based material may include SiCO, SiCN, SiOCN, SiBN, or SiBCN. The seed liner 111 may include silicon nitride, and the conformal layer 112 may include SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0070] The dielectric structure 110′ may further include a first spacer 113, a second spacer 114, and a third spacer 115. The first spacer 113 may be formed on the conformal layer 112. The seed liner 111 and the conformal layer 112 may be located between the first spacer 113 and the first conductive pattern 102. The second spacer 114 may be formed on the conformal layer 112, and the third spacer 115 may be formed on the second spacer 114. The seed liner 111 and the conformal layer 112 may be located between the second conductive pattern 103 and the second spacer 114, and the second spacer 114 may be disposed between the conformal layer 112 and the third spacer 115.

[0071] The lower level dielectric structure 110L′ may include a stack of a seed liner 111, a conformal layer 112, and a first spacer 113. The upper level dielectric structure 110U′ may include a stack of a seed liner 111, a conformal layer 112, a second spacer 114, and a third spacer 115. The first spacer 113 may be thicker than the second spacer 114 and the third spacer 115. The second spacer 114 may be thicker than the third spacer 115. The third spacer 115 may have a lower dielectric constant than the first spacer 113 and the second spacer 114. The conformal layer 112 and the third spacer 115 may have the same dielectric constant. The conformal layer 112 and the third spacer 115 may be formed of the same material. The first spacer 113 and the second spacer 114 may be formed of different materials. The first spacer 113 may include silicon nitride, and the second spacer 114 may include silicon oxide. The third spacer 115 may include a silicon-based material containing impurities. The third spacer 115 may include a carbon-containing material, a boron-containing material, or a material containing carbon and boron. For example, the third spacer 115 may include carbon, boron, or a combination thereof as an impurity. The impurity-containing silicon-based material may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0072] The lower level dielectric structure 110L′ may include a NKN (nitride-low-k-nitride) structure. The NKN structure may be formed by a stack of a seed liner 111, a conformal layer 112, and a first spacer 113. An example of a NKN structure may include a stack of silicon nitride, a low-k material, and silicon nitride. Another example of a NKN structure may include a stack of silicon nitride, an impurity-containing silicon-based material, and silicon nitride. An example of a NKN structure may include a stack of Si3N4 / SiCO / Si3N4.

[0073] The upper level dielectric structure 110U′ may include a NKOK (nitride-low-k-oxide-low-k) structure. The NKOK structure may be formed by a stack of a seed liner 111, a conformal layer 112, a second spacer 114, and a third spacer 115. An example of the NKOK structure may include a stack of silicon nitride, a low-k material, silicon oxide, and a low-k material. Another example of the NKOK structure may include a stack of silicon nitride, an impure silicon-based material, silicon oxide, and an impure silicon-based material. An example of the NKOK structure may include a stack of Si3N4 / SiCO / SiO2 / SiCO.

[0074] refer to Figure 4 , the semiconductor device 100M may be a part of a memory cell.

[0075] In the pattern structure 105, the first conductive pattern 102 may be a bit line contact plug, and the second conductive pattern 103 may include a bit line. The plug structure 120 may include a storage node contact plug.

[0076] The dielectric structure 110 ′ may reduce parasitic capacitance between the first conductive pattern 102 and the plug structure 120 . In addition, the dielectric structure 110 ′ may reduce parasitic capacitance between the second conductive pattern 103 and the plug structure 120 .

[0077] According to another embodiment of the present invention, the first conductive pattern 102 and the second conductive pattern 103 may be gate electrodes of a transistor. The plug structure 120 may be a contact plug coupled to the source / drain region of the transistor. The dielectric structure 110′ may be a gate spacer or a contact spacer. Therefore, the dielectric structure 110′ may reduce the parasitic capacitance between the gate electrode and the contact plug.

[0078] According to another embodiment of the present invention, the pattern structure 105 may be a linear metal line. Therefore, the dielectric structure 110' can reduce the parasitic capacitance between adjacent metal lines.

[0079] refer to FIG. 3A to FIG. 4 , the total thickness of the conformal layer 112 and the second spacer 114 may be greater than the thickness of the seed liner 111 .

[0080] Figure 5 is a plan view showing a semiconductor device 200 according to another embodiment of the present invention. Fig. 6A is along Figure 5 A cross-sectional view taken along line AA′. Figure 6B is along Figure 5 A cross-sectional view taken along line BB′.

[0081] The semiconductor device 200 may include a plurality of memory cells. Each memory cell may include a cell transistor including a buried word line 207 , a bit line 213 , and a storage element 230 .

[0082] The semiconductor device 200 will be described in detail.

[0083] The isolation layer 202 and the active area 203 may be formed in the substrate 201. A plurality of active areas 203 may be defined by the isolation layer 202. The substrate 201 may be a material suitable for semiconductor processing. The substrate 201 may include a semiconductor substrate. The substrate 201 may be formed of a silicon-containing material. The substrate 201 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 201 may also include other semiconductor materials, such as germanium. The substrate 201 may include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs (gallium arsenide). The substrate 201 may include a silicon on insulator (SOI) substrate. The isolation layer 202 may be formed by a shallow trench isolation (STI) process.

[0084] The gate trench 205 may be formed in the substrate 201. A gate dielectric layer 206 may be conformally formed on the surface of the gate trench 205. A buried word line 207 may be formed on the gate dielectric layer 206 to partially fill the gate trench 205. A gate cap layer 208 may be formed over the buried word line 207 to fill the rest of the gate trench 205. The top surface of the buried word line 207 may be located at a level lower than the top surface of the substrate 201. The buried word line 207 may be a low-resistance metal material. In one embodiment, in the buried word line 207, titanium nitride and tungsten may be stacked in sequence. According to another embodiment of the present invention, the buried word line 207 may be formed solely of titanium nitride (TiN only). The buried word line 207 may be referred to as a buried gate electrode. The buried word line 207 may extend very long in a first direction D1, which is also referred to as the length direction of the buried word line 207.

[0085] The first impurity region 209 and the second impurity region 210 may be formed in the substrate 201. The first impurity region 209 and the second impurity region 210 may be spaced apart from each other by the gate trench 205. The first impurity region 209 and the second impurity region 210 may be referred to as a source / drain region. The first impurity region 209 and the second impurity region 210 may contain N-type impurities such as arsenic (As) or phosphorus (P). Therefore, the buried word line 207 and the first impurity region 209 and the second impurity region 210 may become a cell transistor. The cell transistor may present an improved short channel effect through the buried word line 207.

[0086] The bit line contact plug 212 may be formed over the substrate 201. The bit line contact plug 212 may be coupled to the first impurity region 209. The bit line contact plug 212 may be located in the bit line contact hole 211. The bit line contact hole 211 may penetrate the hard mask layer 204 to extend to the substrate 201. The hard mask layer 204 may be formed over the substrate 201. The hard mask layer 204 may include a dielectric material. The bit line contact hole 211 may expose the first impurity region 209. The lower surface of the bit line contact plug 212 may be lower than the upper surface of the active region 203 and the isolation layer 202. The bit line contact plug 212 may be made of polysilicon or a metal material. A portion of the bit line contact plug 212 may have a line width smaller than the diameter of the bit line contact hole 211. The bit line 213 may be formed over the bit line contact plug 212 and may be in direct contact with each other. The bit line hard mask 214 may be formed on the bit line 213 and may be in direct contact with each other. The stacked structure of the bit line contact plug 212, the bit line 213 and the bit line hard mask 214 may be referred to as a bit line structure. The bit line 213 may have a line shape extending in the second direction D2 intersecting the buried word line 207. A portion of the bit line 213 may be coupled to the bit line contact plug 212. When viewed from the perspective of the AA′ direction, the bit line 213 and the bit line contact plug 212 may have the same line width. Therefore, the bit line 213 may extend in the second direction D2 while covering the bit line contact plug 212. The bit line 213 may include a metal material, such as tungsten. The bit line hard mask 214 may include a dielectric material.

[0087] The first spacer structure 215L may be formed on the sidewall of the bit line contact plug 212. The second spacer structure 215U may be formed on the sidewall of the bit line 213. The first spacer structure 215L may be formed on both sidewalls of the bit line contact plug 212. The second spacer structure 215U may be formed on both sidewalls of the bit line 213. The bit line contact hole 211 may be filled with the bit line contact plug 212 and the first spacer structure 215L. The bit line contact hole 211 may include a gap G defined on both sides of the bit line contact plug 212. The first spacer structure 215L may fill the inside of the gap G. The second spacer structure 215U may extend parallel to both sidewalls of the bit line 213.

[0088] The storage node contact plug 221 may be formed between adjacent bit line structures. The storage node contact plug 221 may be coupled to the second impurity region 210. The storage node contact plug 221 may include a lower plug 222 and an upper plug 224. The storage node contact plug 221 may also include an ohmic contact layer 223 between the lower plug 222 and the upper plug 224. The ohmic contact layer 223 may include a metal silicide. For example, the lower plug 222 may include a silicon-containing material, such as polysilicon. For example, the upper plug 224 may include a metal-containing material, such as a metal nitride, a metal material, or a combination thereof.

[0089] When viewed from a direction parallel to the bit line structure, a plug isolation layer 225 may be formed between adjacent storage node contact plugs 221. The plug isolation layer 225 may be formed between adjacent bit line structures. Adjacent storage node contact plugs 221 may be isolated by the plug isolation layer 225. Between adjacent bit line structures, a plurality of plug isolation layers 225 and a plurality of storage node contact plugs 221 may be alternately disposed.

[0090] The storage element 230 may be formed above the upper plug 224. The storage element 230 may include a capacitor having a storage node. The storage node may include a columnar storage node. A dielectric layer and a plate node may also be formed above the storage node. In another embodiment, the storage node may include a cylindrical / barrel-shaped storage node.

[0091] The first spacer structure 215L and the second spacer structure 215U are described in detail below.

[0092] The first spacer structure 215L may include a seed liner 216, a conformal spacer 217, and a gap-filling spacer 218. The second spacer structure 215U may include a seed liner 216, a conformal spacer 217, a protection spacer 219, and a low-k spacer 220. The seed liner 216 of the first spacer structure 215L and the seed liner 216 of the second spacer structure 215U may be the same material. The seed liner 216 of the first spacer structure 215L may extend to cover the sidewalls of the bit line contact plug 212 while covering the sidewalls of the bit line 213. The seed liner 216 may directly contact the bit line 213 and the bit line contact plug 212. The conformal spacer 217 of the first spacer structure 215L and the conformal spacer 217 of the second spacer structure 215U may be the same material. The conformal spacer 217 may extend to cover the sidewalls of the bit line contact plug 212 while covering the sidewalls of the bit line 213, with the seed liner 216 interposed therebetween. The gap-filling spacer 218 may be located on the sidewalls of the bit line contact plug 212 and may fill the gap G. The protection spacer 219 may be located on the sidewalls of the bit line 213 and may not be located on the sidewalls of the bit line contact plug 212. The low-k spacer 220 may be located between the protection spacer 219 and the storage node contact plug 221.

[0093] Conformal spacer 217 and low-k spacer 220 may be formed of the same material. Conformal spacer 217 and low-k spacer 220 may have a dielectric constant of about 4.4 or less. Conformal spacer 217 and low-k spacer 220 may have a lower dielectric constant than seed liner 216. Conformal spacer 217 and low-k spacer 220 may have a higher dielectric constant or a lower dielectric constant than protective spacer 219. Conformal spacer 217 and low-k spacer 220 may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN. Conformal spacer 217 and low-k spacer 220 may have a higher dielectric constant than silicon nitride, but may include different low-k materials.

[0094] The seed liner 216 may include silicon nitride and may have a thickness of about In one embodiment, the seed liner 216 may have a thickness of about 1 to about In other words, the seed liner 216 may include ultra-thin silicon nitride, which means that the seed liner 216 is made of silicon nitride and has a thickness of about 1 to about The seed liner 216 may be thinner than the conformal spacer 217. For example, the conformal spacer 217 may be twice as thick as the seed liner 216. The seed liner 216 may be thinner than the protection spacer 219 and the low-k spacer 220. According to another embodiment of the present invention, the total thickness of the conformal spacer 217 and the protection spacer 219 may be greater than the thickness of the seed liner 216.

[0095] The seed liner 216 may be used as a seed for uniformly depositing the conformal spacer 217. The conformal spacer 217 and the seed liner 216 may be in direct contact with each other. The protective spacer 219 may be used to protect the conformal spacer 217. The seed liner 216 may also be referred to as a surface liner. Since the seed liner 216 is thin, the volume occupied by the seed liner 216 in the second spacer structure 215U may be minimized, and therefore, the parasitic capacitance between the bit line 213 and the storage node contact plug 221 may be further reduced.

[0096] As described above, the seed liner 216, conformal spacer 217, and gap-filling spacer 218 may be located between the bit line contact plug 212 and the storage node contact plug 221. The seed liner 216, conformal spacer 217, protection spacer 219, and low-k spacer 220 may be located between the bit line 213 and the storage node contact plug 221.

[0097] The seed liner 216 and the gap-filling spacer 218 may include silicon nitride, and the conformal spacer 217 and the low-k spacer 220 may include a low-k material. The protective spacer 219 may include silicon oxide. Therefore, the second spacer structure 215U may have an NKOK structure and may be disposed along a CC' line between the bit line 213 and the storage node contact plug 221, and the first spacer structure 215L having an NKN structure may be disposed along a DD' line between the bit line contact plug 212 and the storage node contact plug 221.

[0098] According to another embodiment of the present invention, the protection spacer 219 may be replaced with an air gap. In this case, a second spacer structure 215U having a NKAK (nitride-low-k-air gap-low-k) structure may be disposed along a CC' line between the bit line 213 and the storage node contact plug 221. A first spacer structure 215L having a NKN structure may be disposed along a line DD' between the bit line contact plug 212 and the storage node contact plug 221.

[0099] The parasitic capacitance between the bit line 213 and the storage node contact plug 221 may be reduced by the conformal spacer 217 and the low-k spacer 220. The step coverage of the conformal spacer 217 may be improved by the seed liner 216. The protection spacer 219 may prevent the conformal spacer 217 from being lost / degraded.

[0100] The plug isolation layer 225 may include silicon nitride or a low-k material. When the plug isolation layer 225 includes a low-k material, the parasitic capacitance between the adjacent storage node contact plugs 221 between which the plug isolation layer 225 is disposed can be reduced. The plug isolation layer 225 may include SiC, SiCO, SiCN, SiOCN, SiBN or SiBCN. The conformal spacer 217, the low-k spacer 220 and the plug isolation layer 225 may include a low-k material. The low-k material of the plug isolation layer 225 may be different from the low-k material of the conformal spacer 217 and the low-k spacer 220. For example, the conformal spacer 217 and the low-k spacer 220 may include a carbon-containing low-k material, and the plug isolation layer 225 may include a boron-containing low-k material. The conformal spacer 217 and the low-k spacer 220 may include SiC, SiCO, SiCN or SiOCN, and the plug isolation layer 225 may include SiBN or SiBCN.

[0101] refer to Figures 5 to 6B , since the conformal spacer 217 is formed on the thin seed liner 216, the step coverage of the conformal spacer 217 can be improved. Since the thickness occupied by the seed liner 216 in the first spacer structure 215L and the second spacer structure 215U is reduced, the increase of the parasitic capacitance can be suppressed. By forming the conformal spacer 217 between the bit line contact plug 212 and the storage node contact plug 221, the parasitic capacitance between the bit line contact plug 212 and the storage node contact plug 221 can be reduced. By forming the conformal spacer 217 and the low-k spacer 220 between the bit line 213 and the storage node contact plug 221, the parasitic capacitance between the bit line 213 and the storage node contact plug 221 can be reduced.

[0102] As described above, since parasitic capacitance is reduced by the first and second spacer structures 215L and 215U including low-k materials such as conformal spacers 217 and low-k spacers 220 , a sensing margin of a memory cell may be improved.

[0103] According to another embodiment of the present invention, Figure 6C As shown, the protection spacer 219 may be replaced by an air gap.

[0104] Figure 6C It is shown Fig. 6A 2 is a cross-sectional view of a modified example of the second spacer structure 215U shown in FIG. The second spacer structure 215U may include a seed liner 216, a conformal spacer 217, an air gap AG, and a low-k spacer 220. The air gap AG may be removed by Fig. 6AThe protective spacer 219 shown in the figure is formed, and the upper part of the air gap AG can be covered with the air gap cover layer AGC. In this case, the second spacer structure 215U having the NKAK (nitride-low-k-air gap-low-k) structure can be disposed along the line CC' between the bit line 213 and the storage node contact plug 221. In addition, the first spacer structure 215L having the NKN structure can be disposed along the line DD' between the bit line contact plug 212 and the storage node contact plug 221. Compared with the NKOK structure, the NKAK structure can have a higher effect of reducing parasitic capacitance.

[0105] Figures 7 to 19 is a cross-sectional view illustrating a method of manufacturing a semiconductor device 200 according to an embodiment of the present invention. FIG. Figures 7 to 19 is shown along Figure 5 A cross-sectional view of the manufacturing method taken along lines AA′ and BB′.

[0106] refer to Figure 7 , an isolation layer 12 may be formed in the substrate 11. A plurality of active areas 13 may be defined by the isolation layer 12. The isolation layer 12 may be formed by an STI process. The STI process may be performed as follows. The substrate 11 may be etched to form an isolation trench. The isolation trench may be filled with a dielectric material. As a result, an isolation layer 12 may be formed. The isolation layer 12 may include a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be performed to fill the isolation trench with a dielectric material. A planarization process such as chemical mechanical polishing (CMP) may be additionally used.

[0107] Subsequently, a buried word line structure may be formed in the substrate 11. The buried word line structure may include a gate trench 15, a gate dielectric layer 16 conformally covering a bottom and sidewall of the gate trench 15, a buried word line 17 partially filling the gate trench 15 above the gate dielectric layer 16, and a gate cap layer 18 formed above the buried word line 17.

[0108] The method of forming the buried word line structure is as follows.

[0109] First, a gate trench 15 may be formed in the substrate 11. The gate trench 15 may have a line shape intersecting the active region 13 and the isolation layer 12. The gate trench 15 may be formed by an etching process of forming a mask pattern on the substrate 11 and using the mask pattern as an etching mask. In order to form the gate trench 15, a hard mask layer 14 may be used as an etching barrier. The hard mask layer 14 may have a shape patterned by a mask pattern. The hard mask layer 14 may include silicon oxide. For example, the hard mask layer 14 may include tetraethyl orthosilicate (TEOS). The bottom surface of the gate trench 15 may be located at a level higher than the bottom surface of the isolation layer 12.

[0110] A portion of the isolation layer 12 may be recessed to protrude the active region 13 below the gate trench 15. Figure 5 In the BB′ direction of FIG. 1 , the isolation layer 12 below the gate trench 15 may be selectively recessed. Therefore, a fin region may be formed below the gate trench 15. The fin region may be a part of the channel region.

[0111] Subsequently, a gate dielectric layer 16 may be formed on the bottom surface and sidewalls of the gate trench 15. Before forming the gate dielectric layer 16, etching damage to the surface of the gate trench 15 may be repaired. For example, after forming a sacrificial oxide by a thermal oxidation process, the sacrificial oxide may be removed.

[0112] The gate dielectric layer 16 may be formed by a thermal oxidation process. For example, the gate dielectric layer 16 may be formed by oxidizing the bottom and sidewalls of the gate trench 15 .

[0113] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 16 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, and a combination thereof.

[0114] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by depositing a liner polysilicon layer and then completely oxidizing the liner polysilicon layer.

[0115] According to yet another embodiment of the present invention, the gate dielectric layer 16 may be formed by forming a liner silicon nitride layer and completely oxidizing the liner silicon nitride layer.

[0116] Subsequently, a buried word line 17 may be formed on the gate dielectric layer 16. In order to form the buried word line 17, a recess process may be performed after forming a conductive layer to fill the gate trench 15. The etch-back process may be performed as a recess process, or a chemical mechanical polishing (CMP) process and an etch-back process may be performed sequentially. The buried word line 17 may have a recessed shape that partially fills the gate trench 15. In other words, the upper surface of the buried word line 17 may be located at a level lower than the upper surface of the active area 13. The buried word line 17 may include a metal, a metal nitride, or a combination thereof. For example, the buried word line 17 may be formed of titanium nitride (TiN), tungsten (W), or a stack (TiN / W) of titanium nitride and tungsten. The titanium nitride / tungsten (TiN / W) stack may have a structure in which the gate trench 15 is partially filled with tungsten after conformally forming titanium nitride. The buried word line 17 may include titanium nitride alone, and this may be referred to as a buried word line 17 having a "TiN-only" structure. The buried word line 17 may include a double gate structure of a titanium nitride / tungsten (TiN / W) stack and a polysilicon layer.

[0117] Subsequently, a gate capping layer 18 may be formed on the buried word line 17. The gate capping layer 18 may include a dielectric material. The remaining portion of the gate trench 15 may be filled with the gate capping layer 18 above the buried word line 17. The gate capping layer 18 may include silicon nitride. According to another embodiment of the present invention, the gate capping layer 18 may include silicon oxide. According to yet another embodiment of the present invention, the gate capping layer 18 may have a NON (nitride-oxide-nitride) structure. The upper surface of the gate capping layer 18 may be located on the same horizontal plane as the upper surface of the hard mask layer 14. To this end, a CMP process may be performed when the gate capping layer 18 is formed.

[0118] After forming the gate capping layer 18, impurity regions 19 and 20 may be formed. The impurity regions 19 and 20 may be formed by a doping process such as, for example, an implantation process. The impurity regions 19 and 20 may include a first impurity region 19 and a second impurity region 20. The first impurity region 19 and the second impurity region 20 may be doped with impurities of the same conductivity type. The first impurity region 19 and the second impurity region 20 may have the same depth. According to another embodiment of the present invention, the first impurity region 19 may be deeper than the second impurity region 20. The first impurity region 19 and the second impurity region 20 may be referred to as source / drain regions. The first impurity region 19 may be a region coupled to a bit line contact plug, and the second impurity region 20 may be a region coupled to a storage node contact plug. The first impurity region 19 and the second impurity region 20 may be located in different active regions 13. In addition, the first impurity region 19 and the second impurity region 20 may be separated from each other by the gate trench 15 to be located in each active region 13.

[0119] A cell transistor of a memory cell may be formed by the buried word line 17 and the first and second impurity regions 19 and 20 .

[0120] refer to Figure 8 , a bit line contact hole 21 may be formed. The bit line contact hole 21 may be formed by etching the hard mask layer 14 using a contact mask. From the perspective of a plan view, the bit line contact hole 21 may have a circular shape or an elliptical shape. A portion of the substrate 11 may be exposed by the bit line contact hole 21. The diameter of the bit line contact hole 21 may be controlled by a predetermined line width. The bit line contact hole 21 may have a shape that exposes a portion of the active region 13. For example, the first impurity region 19 may be exposed by the bit line contact hole 21. The bit line contact hole 21 may have a diameter greater than the width of the short axis of the active region 13. Therefore, in the etching process for forming the bit line contact hole 21, a portion of the first impurity region 19, the isolation layer 12, and the gate cover layer 18 may be etched. In other words, the isolation layer 12, the gate cover layer 18, and the first impurity region 19 below the bit line contact hole 21 may be recessed to a predetermined depth. Therefore, the bottom of the bit line contact hole 21 may extend to the inside of the substrate 11. As the bit line contact hole 21 extends, the surface of the first impurity region 19 may be recessed and may be located at a lower level than an upper surface of the active region 13 as indicated by an upper surface of the second impurity region 20 .

[0121] refer to Fig. 9 , a pre-plug 22A may be formed. The pre-plug 22A may be formed by a selective epitaxial growth (SEG) process. For example, the pre-plug 22A may include SEG silicon phosphorus (SiP). In this way, a pre-plug 22A without a void may be formed by a selective epitaxial growth process. According to another embodiment of the present invention, the pre-plug 22A may be formed by depositing a polysilicon layer followed by a chemical mechanical polishing (CMP) process. The pre-plug 22A may fill the bit line contact hole 21. The upper surface of the pre-plug 22A may be located at the same level as the upper surface of the hard mask layer 14.

[0122] refer to Fig.10, a bit line conductive layer 23A and a bit line hard mask layer 24A may be stacked. The bit line conductive layer 23A and the bit line hard mask layer 24A may be sequentially stacked over the pre-plug 22A and the hard mask layer 14. The bit line conductive layer 23A may include a metal-containing material. The bit line conductive layer 23A may include a metal, a metal nitride, a metal silicide, or a combination thereof. According to an embodiment of the present invention, the bit line conductive layer 23A may include tungsten (W). According to another embodiment of the present invention, the bit line conductive layer 23A may include a stack of titanium nitride and tungsten (TiN / W). Here, titanium nitride may be used as a barrier layer. The bit line hard mask layer 24A may be formed of a dielectric material having an etching selectivity relative to the bit line conductive layer 23A and the pre-plug 22A. The bit line hard mask layer 24A may include silicon oxide or silicon nitride. According to an embodiment of the present invention, the bit line hard mask layer 24A may be formed of silicon nitride.

[0123] refer to Fig.11 , a bit line 23 and a bit line contact plug 22 may be formed. The bit line 23 and the bit line contact plug 22 may be formed through the bit line mask layer using an etching process.

[0124] The bit line hard mask layer 24A and the bit line conductive layer 23A may be etched by using the bit line mask layer as an etching barrier. Thus, the bit line 23 and the bit line hard mask 24 may be formed. The bit line 23 may be formed by etching the bit line conductive layer 23A. The bit line hard mask 24 may be formed by etching the bit line hard mask layer 24A.

[0125] Subsequently, the pre-plug 22A may be etched with the same line width as the line width of the bit line 23. Thus, a bit line contact plug 22 may be formed. The bit line contact plug 22 may be formed above the first impurity region 19. The bit line contact plug 22 may couple the first impurity region 19 and the bit line 23 to each other. The bit line contact plug 22 may be formed in the bit line contact hole 21. The line width of the bit line contact plug 22 may be smaller than the diameter of the bit line contact hole 21. Thus, a gap 25 may be defined on both sides of the bit line contact plug 22.

[0126] As described above, as the bit line contact plug 22 is formed, the gap 25 may be formed in the bit line contact hole 21. This is because the bit line contact plug 22 is formed by being etched to be smaller than the diameter of the bit line contact hole 21. The gap 25 may not have an enclosing shape that encloses the bit line contact plug 22, but may be independently formed on both sidewalls of the bit line contact plug 22. As a result, one bit line contact plug 22 and a pair of gaps 25 may be located in the bit line contact hole 21, and the pair of gaps G may be separated by the bit line contact plug 22. The bottom surface of the gap 25 may extend to the inside of the isolation layer 12. The lower surface of the gap 25 may be located at a level lower than the recessed upper surface of the first impurity region 19.

[0127] The structure in which the bit line contact plug 22, the bit line 23, and the bit line hard mask 24 are stacked in the order mentioned may be referred to as a bit line structure. The bit line structure may be a linear pattern structure extending long in one direction when viewed from a top view.

[0128] refer to Fig.12 , a seed layer 26A and a conformal layer 27A may be sequentially formed. The seed layer 26A may cover both sidewalls of the bit line contact plug 22 and both sidewalls of the bit line 23. The seed layer 26A may cover both sidewalls and an upper surface of the bit line hard mask 24. The seed layer 26A may provide uniform deposition of the conformal layer 27A, thereby improving the step coverage of the conformal layer 27A. The seed layer 26A may include a passivation material capable of inhibiting oxidation of the bit line 23. The seed layer 26A may include a dielectric material. According to an embodiment of the present invention, for example, the seed layer 26A may include silicon nitride. The seed layer 26A may include thin silicon nitride, and the thin silicon nitride may be formed to have a thickness of about or less, such as from about 1 to about Thus, by applying thin silicon nitride as the seed layer 26A, the parasitic capacitance between the bit line 23 and the subsequent storage node contact plug can be reduced.

[0129] Conformal layer 27A may have a lower dielectric constant than seed layer 26A. Conformal layer 27A may include a low-k material, and conformal layer 27A may have a dielectric constant lower than the dielectric constants of silicon nitride and silicon oxide. Conformal layer 27A may have a dielectric constant of about 3.5 or less. Conformal layer 27A may include a silicon-based material. Conformal layer 27A may include at least one chemical selected from carbon and boron. Conformal layer 27A may include a silicon-based material containing carbon, a silicon-based material containing boron, or a silicon-based material containing carbon and boron. Conformal layer 27A may include a silicon-based material doped with carbon or a silicon-based material doped with boron. Conformal layer 27A may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0130] Conformal layer 27A may be formed, for example, by atomic layer deposition (ALD). For example, conformal layer 27A may be formed by SiBN ALD or SiCO ALD. SiBN ALD may include a unit cycle of "SiH2Cl2 (or SiH4) / purge / BCl3 / purge / NH3 / purge". SiCO ALD may include a unit cycle of "SiH2Cl2 (or SiH4) / purge / C2H4 (or CH4) / purge / O3 / purge". SiH2Cl2 and SiH4 are silicon source gases, and BCl3 is a boron source gas. NH3 is a nitrogen source gas, and O3 is an oxygen source gas. The silicon source gas, the boron source gas, the nitrogen source gas, and the oxygen source gas may include other source materials in addition to the above-mentioned source materials.

[0131] refer to Fig.13 and Fig.14 , a gap-filling spacer 28 may be formed. The gap-filling spacer 28 may be formed on the conformal layer 27A. The conformal layer 27A may have a lower dielectric constant than the gap-filling spacer 28. The gap-filling spacer 28 and the seed layer 26A may be formed of the same material, but the gap-filling spacer 28 may be thicker than the seed layer 26A. The gap-filling spacer 28 may include silicon nitride.

[0132] The gap-filling spacer 28 may be recessed to fill the gap 25. For example, to form the gap-filling spacer 28, a gap-filling material 28A may be deposited on the bit line structure and the conformal layer 27A to fill the gap 25, and then the gap-filling material 28A may be recessed by an etch-back process. The upper surface of the gap-filling spacer 28 may be located at a level lower than the upper surface of the bit line contact plug 22. According to another embodiment of the present invention, the upper surface of the gap-filling spacer 28 and the upper surface of the bit line contact plug 22 may be located at the same level. The gap-filling material 28A may include silicon nitride.

[0133] The gap 25 may be filled with a seed layer 26A, a conformal layer 27A, and a gap-filling spacer 28. The gap-filling spacer 28 may be referred to as a dielectric plug or a plug spacer. According to another embodiment of the present invention, the gap-filling spacer 28 may be formed of silicon oxide or a low-k material.

[0134] After forming the gap-filling spacer 28 , a line-shaped opening LO may be defined between adjacent bit lines 23 .

[0135] refer to Fig.15 and Fig.16 , a protection spacer 29 may be formed on the gap-filling spacer 28. The protection spacer 29 may have a line shape extending long along both sidewalls of the bit line structure. The protection spacer 29 may directly contact the upper surface of the gap-filling spacer 28. The protection spacer 29 may directly contact the conformal layer 27A. The protection spacer 29 may have a lower dielectric constant than the gap-filling spacer 28 and the seed layer 26A, and the protection spacer 29 may have a smaller or larger dielectric constant than the conformal layer 27A. The protection spacer 29 may be thicker than the conformal layer 27A. The protection spacer 29 may include silicon oxide. The protection spacer 29 may have an etching selectivity relative to the conformal layer 27A.

[0136] To form the protection spacer 29, after depositing the protection material 29A on the gap-filling spacer 28 and the bit line structure, an etch-back process may be performed. The protection material 29A may include silicon oxide. The bottom surface of the protection spacer 29 may be located at a level lower than the lower surface of the bit line 23. The upper surface of the protection spacer 29 may be located at a level higher than the upper surface of the bit line hard mask 24. The total thickness of the protection spacer 29 and the conformal layer 27A may be greater than the thickness of the seed layer 26A.

[0137] The protection spacer 29 can prevent the conformal layer 27A on both sidewalls of the bit line 23 from being damaged during subsequent processes.

[0138] refer to Fig.17 , a low-k spacer layer 30A may be conformally formed on the protective spacer 29. The low-k spacer layer 30A may have a lower dielectric constant than the seed layer 26A. The dielectric constant of the low-k spacer layer 30A may be the same as the dielectric constant of the conformal layer 27A. The low-k spacer layer 30A and the conformal layer 27A may be formed of the same material. The low-k spacer layer 30A may include a low-k material, and the low-k spacer layer 30A may have a dielectric constant lower than that of silicon nitride. The low-k spacer layer 30A may have a dielectric constant of about 4.4 or less. The low-k spacer layer 30A may include a silicon-based material. The low-k spacer layer 30A may include at least one chemical selected from carbon and boron. The low-k spacer layer 30A may include a carbon-doped silicon-based material or a boron-doped silicon-based material. The low-k spacer layer 30A may include SiC, SiCO, SiCN, SiOCN, SiBN or SiBCN.

[0139] The low-k spacer layer 30A may be formed, for example, by atomic layer deposition (ALD). Since the protective spacer 29 and the low-k spacer layer 30A are sequentially formed on the conformal layer 27A having improved step coverage, the step coverage of the low-k spacer layer 30A may also be improved. According to another embodiment of the present invention, the low-k spacer layer 30A may have a worse step coverage than the conformal layer 27A.

[0140] refer to Fig.18 , a plurality of plug isolation layers 31 may be formed on the low-k spacer layer 30A. The plug isolation layers 31 may separate the line-shaped openings LO between the bit line structures into a plurality of contact openings CO. Figure 5, in the AA′ direction, the plug isolation layer 31 may vertically overlap the buried word line 17 above the buried word line 17, respectively. The plug isolation layer 31 may include silicon nitride or a low-k material. According to another embodiment of the present invention, the plug isolation layer 31 may include a low-k material containing boron, and the conformal layer 27A and the low-k spacer layer 30A may include a low-k material containing carbon. According to another embodiment of the present invention, a portion of the bit line hard mask 24 may be consumed when forming the plug isolation layer 31. In order to form the plug isolation layer 31, a sacrificial material, such as an oxide filled between the bit line structures, may be formed on the low-k spacer layer 30A, and a portion of the sacrificial material may be replaced by the plug isolation layer 31. Subsequently, by removing the remaining sacrificial material, a plurality of contact openings CO may be formed between the plug isolation layers 31.

[0141] refer to Figure 5 , as viewed from a top view, in the direction in which the bit lines 23 extend, the contact openings CO and the plug isolation layers 31 may be alternately formed between adjacent bit lines 23. Adjacent contact openings CO may be arranged in an isolated shape by the bit line structure and the plug isolation layer 31. As viewed from a top view, the contact openings CO may have a rectangular hole shape.

[0142] The lower material may be etched to be self-aligned with the contact opening CO. Thus, a plurality of recessed regions 32 exposing a portion of the active region 13 may be formed between the bit line structures. The recessed regions 32 may be formed using anisotropic etching or a combination of anisotropic etching and isotropic etching. For example, in a structure exposed through the contact opening CO between the bit line structures, the low-k spacer layer 30A, the conformal layer 27A, and the seed layer 26A may be anisotropically etched sequentially. Then, the portion of the active region 13 exposed thereafter may be isotropically etched. According to another embodiment of the present invention, the hard mask layer 14 may also be isotropically etched. Portions of the active region 13 and the gap-filling spacer 28 may be exposed by the recessed regions 32.

[0143] The recessed region 32 may extend into the substrate 11. When the recessed region 32 is formed, the isolation layer 12, the gate cap layer 18, and the second impurity region 20 may be recessed to a predetermined depth. The bottom surface of the recessed region 32 may be located at a level lower than the upper surface of the bit line contact plug 22. The bottom surface of the recessed region 32 may be located at a level higher than the bottom surface of the bit line contact plug 22. The contact opening CO and the recessed region 32 may be coupled to each other. The vertical structure of the contact opening CO and the recessed region 32 may be referred to as a "storage node contact hole".

[0144] A dielectric structure (or a spacer structure) may be formed on the sidewall of the bit line structure by performing an etching process for forming the recess region 32. The dielectric structure may include materials having different dielectric constants.

[0145] The dielectric structure may include a seed liner 26, a conformal spacer 27, a protection spacer 29, and a low-k spacer 30. The seed liner 26 may directly contact the sidewalls of the bit line contact plug 22 and the sidewalls of the bit line 23. The conformal spacer 27 may cover the seed liner 26. The protection spacer 29 may cover the conformal spacer 27, and the low-k spacer 30 may cover the protection spacer 29. The seed liner 26 may be located between the conformal spacer 27 and the bit line contact plug 22, and the seed liner 26 may extend to be located between the conformal spacer 27 and the bit line 23. The conformal spacer 27 may be located between the protection spacer 29 and the seed liner 26, and the conformal spacer 27 may extend to be located between the gap-filling spacer 28 and the seed liner 26. Protection spacer 29 may be located between low-k spacer 30 and conformal spacer 27, and a bottom surface of protection spacer 29 may contact an upper surface of gap-filling spacer 28. A bottom surface of low-k spacer 30 may contact an upper surface of gap-filling spacer 28.

[0146] The seed liner 26, the conformal spacer 27, the protection spacer 29, and the low-k spacer 30 may be sequentially stacked on the sidewalls of the bit line 23. The seed liner 26, the conformal spacer 27, and the gap-filling spacer 28 may be stacked on the sidewalls of the bit line contact plug 22. The sidewalls and bottom surfaces of the gap-filling spacer 28 may be covered by the stack of the seed liner 26 and the conformal spacer 27.

[0147] refer to Fig.19 , a storage node contact plug 33 may be formed. The storage node contact plug 33 may fill the contact opening CO and the recessed region 32. The storage node contact plug 33 may contact the second impurity region 20. The storage node contact plug 33 may be adjacent to the bit line structure. From the perspective of the top view, a plurality of storage node contact plugs 33 may be located between a plurality of bit line structures. In a direction parallel to the bit line 23, a plurality of storage node contact plugs 33 and a plurality of plug isolation layers 31 may be alternately located between adjacent bit lines 23.

[0148] In the storage node contact plug 33 , a lower plug 33L, an ohmic contact layer 33M, and an upper plug 33U may be sequentially stacked.

[0149] The lower plug 33L may include a silicon-containing material. The lower plug 33L may include polysilicon. The polysilicon may be doped with impurities. The lower plug 33L may be coupled to the second impurity region 20. The upper surface of the lower plug 33L may be higher than the upper surface of the bit line 23. The lower plug 33L may be formed by depositing polysilicon to fill the contact opening CO and the recessed region 32, and then sequentially performing a planarization process and an etch-back process.

[0150] The ohmic contact layer 33M may be formed on the lower plug 33L. The ohmic contact layer 33M may include a metal silicide. The ohmic contact layer 33M may be formed by depositing a silicideable metal layer and then performing an annealing process. Therefore, silicide may occur at an interface where the silicideable metal layer and the lower plug 33L contact each other, thereby forming a metal silicide layer. The ohmic contact layer 33M may, for example, include cobalt silicide. According to an embodiment of the present invention, the ohmic contact layer 33M may include cobalt silicide of a "CoSi2 phase".

[0151] When cobalt silicide of the CoSi 2 phase is formed as the ohmic contact layer 33M, it is possible to form cobalt silicide of low resistance and improve contact resistance at the same time.

[0152] The upper plug 33U may be formed on the ohmic contact layer 33M. The upper plug 33U may be formed by gap filling and planarizing a metal material. The upper plug 33U may be formed while filling the contact opening CO above the ohmic contact layer 33M. The upper plug 33U may include a metal-containing layer. The upper plug 33U may include a tungsten-containing material. The upper plug 33U may include a tungsten layer or a tungsten compound.

[0153] According to another embodiment of the present invention, an upper portion of the upper plug 33U may extend to overlap an upper surface of the bit line hard mask 24. For example, to form the upper plug 33U, a metal material may be deposited on the ohmic contact layer 33M, and then the metal material may be removed.

[0154] Since the lower plug 33L includes polysilicon, and the ohmic contact layer 33M and the upper plug 33U include a metal material, the storage node contact plug 33 may be referred to as a hybrid plug or a semi-metal plug.

[0155] As described above, seed liner 26, conformal spacer 27, and gap-filling spacer 28 may be located between bit line contact plug 22 and lower plug 33L. Seed liner 26, conformal spacer 27, protection spacer 29, and low-k spacer 30 may be located between bit line 23 and lower plug 33L.

[0156] The seed liner 26 and the gap filling spacer 28 may include silicon nitride, and the conformal spacer 27 and the low-k spacer 30 may include a low-k material. The protection spacer 29 may include silicon oxide. Therefore, a dielectric structure of an NKOK structure may be disposed between the bit line 23 and the lower plug 33L, and a dielectric structure of an NKN structure may be disposed between the bit line contact plug 22 and the lower plug 33L. According to another embodiment of the present invention, referring to Figure 6C, the protection spacer 29 may be replaced with an air gap. In this case, a NKAK (nitride-low-k-air gap-low-k) structure may be provided between the bit line 23 and the storage node contact plug 33. In order to form the air gap AG, the protection spacer 29 may be selectively removed, and an air gap capping layer AGC may be formed over the air gap AG.

[0157] The parasitic capacitance between the bit line 23 and the lower plug 33L may be reduced by the conformal spacer 27 and the low-k spacer 30. The step coverage of the conformal spacer 27 may be improved by the seed liner 26. The protection spacer 29 may prevent the conformal spacer 27 from being lost.

[0158] As described above, since the parasitic capacitance is reduced, the sensing margin of the memory cell may be improved.

[0159] Subsequently, a storage element may be formed over the upper plug 33U (see Fig. 6A According to another embodiment of the present invention, a landing pad may be formed between the upper plug 33U and the memory element.

[0160] According to another embodiment of the present invention, Figure 6C As shown, after forming the upper plug 33U, the protection spacer 29 may be removed to form the air gap AG. Subsequently, an air gap capping layer AGC may be formed over the air gap AG.

[0161] Figure 20 to Figure 22 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention. Figure 20 to Figure 22 In, also appears Figures 7 to 19 The same reference numerals in the drawings may denote the same constituent elements, and their detailed descriptions may be omitted here.

[0162] refer to Fig. 20 , by executing the above reference Figures 7 to 17 After forming the bit line contact plugs 22 and the bit lines 23 over the substrate 11 by the described process, a seed layer 26A, a conformal layer 27A, a gap-fill spacer 28, a protection spacer 29, and a low-k spacer layer 30A may be formed.

[0163] Subsequently, a protective liner layer 41A may be formed on the low-k spacer layer 30A. The protective liner layer 41A may be formed of the same material as the seed layer 26A. The protective liner layer 41A may be thinner than the conformal layer 27A and the low-k spacer layer 30A. The low-k spacer layer 30A may have a lower dielectric constant than the protective liner layer 41A. The protective liner layer 41A may have an etch selectivity relative to the low-k spacer layer 30A. The protective liner layer 41A may include silicon nitride. The protective liner layer 41A may have a thickness of about 1000 Å. or less, such as from about 1 to about thickness, and may include ultra-thin silicon nitride.

[0164] refer to Fig.21 , the contact opening CO and the plug isolation layer 31 can be connected with the reference Fig.18 The described manner is similarly formed alternately. Subsequently, the recessed region 32 may be formed.

[0165] A dielectric structure (or a spacer structure) may be formed on the sidewall of the bit line structure by performing an etching process for forming the recess region 32. The dielectric structure may include materials having different dielectric constants.

[0166] The dielectric structure may include a seed liner 26, a conformal spacer 27, a protection spacer 29, a low-k spacer 30, and a protection liner 41. The seed liner 26 may directly contact the sidewalls of the bit line contact plug 22 and the sidewalls of the bit line 23. The conformal spacer 27 may cover the seed liner 26. The protection spacer 29 may cover the conformal spacer 27, and the low-k spacer 30 may cover the protection spacer 29. The protection liner 41 may cover the low-k spacer 30. The seed liner 26 may be located between the conformal spacer 27 and the bit line contact plug 22, and the seed liner 26 may extend to be located between the conformal spacer 27 and the bit line 23. The conformal spacer 27 may be located between the protection spacer 29 and the seed liner 26, and the conformal spacer 27 may extend to be located between the gap-filling spacer 28 and the seed liner 26. Protection spacer 29 may be located between low-k spacer 30 and conformal spacer 27, and a bottom surface of protection spacer 29 may contact an upper surface of gap-filling spacer 28. A bottom surface of low-k spacer 30 may contact an upper surface of gap-filling spacer 28.

[0167] The seed liner 26, the conformal spacer 27, the protection spacer 29, the low-k spacer 30, and the protection liner 41 may be sequentially stacked on the sidewalls of the bit line 23. The seed liner 26, the conformal spacer 27, and the gap-filling spacer 28 may be stacked on the sidewalls of the bit line contact plug 22. The sidewalls and bottom surfaces of the gap-filling spacer 28 may be covered by the stack of the seed liner 26 and the conformal spacer 27.

[0168] refer to Fig. 22 , the storage node contact plug 33 can be connected to the reference Fig.19 The method is similar to that described above.

[0169] As described above, the seed liner 26, conformal spacer 27, and gap-filling spacer 28 may be located between the bit line contact plug 22 and the lower plug 33L. The seed liner 26, conformal spacer 27, protection spacer 29, low-k spacer 30, and protection liner 41 may be located between the bit line 23 and the lower plug 33L.

[0170] The seed liner 26, the gap filling spacer 28 and the protection liner 41 may include silicon nitride, and the conformal spacer 27 and the low-k spacer 30 may include a low-k material. The protection spacer 29 may include silicon oxide. Therefore, a dielectric structure of an NKOKN structure may be disposed between the bit line 23 and the lower plug 33L, and a dielectric structure of an NKN structure may be disposed between the bit line contact plug 22 and the lower plug 33L.

[0171] According to another embodiment of the present invention, the protection spacer 29 may be removed to form an air gap. In this case, a NKAKN (nitride-low-k-air gap-low-k-nitride) structure may be provided between the bit line 23 and the storage node contact plug 33, and a NKN structure may be provided between the bit line contact plug 22 and the storage node contact plug 33.

[0172] According to another embodiment of the present invention, the low-k spacer 30 may be omitted. In this case, a NKON (nitride-low-k-oxide-nitride) structure may be provided between the bit line 23 and the storage node contact plug 33, and a NKN structure may be provided between the bit line contact plug 22 and the storage node contact plug 33. In addition, when the low-k spacer 30 is omitted and the protection spacer 29 is replaced by an air gap, a NKAN (nitride-low-k-air gap-nitride) may be provided between the bit line 23 and the storage node contact plug 33, and a NKN structure may be provided between the bit line contact plug 22 and the storage node contact plug 33.

[0173] Fig.23 FIG. 2 is a cross-sectional view showing a semiconductor device 300 according to another embodiment of the present invention. Fig.23 In, also appears Figures 5 to 6B The same reference numerals in the drawings may denote the same constituent elements, and their detailed descriptions may be omitted.

[0174] refer to Fig.23 , the semiconductor device 300 may include a plurality of memory cells. Each memory cell may include a cell transistor including a buried word line 207, a bit line 213, and a memory element 230. Other constituent elements except the second spacer structure 215UA may be connected to Figures 5 to 6BThe constituent elements are the same. The first spacer structure 215L may be formed between the bit line contact plug 212 and the storage node contact plug 221A. The second spacer structure 215UA may be formed between the bit line 213 and the storage node contact plug 221A. The first spacer structure 215L may include a seed liner 216, a conformal spacer 217, and a gap filling spacer 218. The second spacer structure 215UA may include a seed liner 216, a conformal spacer 217, a protective spacer 219′, and a low-k spacer 220. The conformal spacer 217 and the low-k spacer 220 may have a lower dielectric constant than the seed liner 216. The conformal spacer 217 and the low-k spacer 220 may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN. The conformal spacer 217 and the low-k spacer 220 may have a lower dielectric constant than silicon nitride, but they may include different low-k materials. The protection spacer 219 ′ may include silicon oxide. The dielectric constant of the protection spacer 219 ′ may be lower or higher than the dielectric constants of the conformal spacer 217 and the low-k spacer 220 , and the seed liner 216 may have a higher dielectric constant than the protection spacer 219 ′.

[0175] The seed liner 216 may have a In one embodiment, the seed liner 216 may have a thickness of about 1 to about The seed liner 216 may be used as a seed for uniformly depositing the conformal spacer 217. The conformal spacer 217 and the seed liner 216 may be in direct contact with each other. According to another embodiment of the present invention, the total thickness of the conformal spacer 217 and the protection spacer 219' may be greater than the thickness of the seed liner 216.

[0176] The second spacer structure 215UA may have a NKOK structure and may be disposed between the bit line 213 and the storage node contact plug 221 A. The first spacer structure 215L of a NKN structure may be disposed between the bit line contact plug 212 and the storage node contact plug 221A.

[0177] The storage node contact plug 221A of the semiconductor device 300 may be formed between adjacent bit line structures. The storage node contact plug 221A may be coupled to the second impurity region 210. The storage node contact plug 221A may include a lower plug 222 and an upper plug 224A. The storage node contact plug 221A may also include an ohmic contact layer 223 between the lower plug 222 and the upper plug 224A. The ohmic contact layer 223 may include a metal silicide. For example, the lower plug 222 may include polysilicon, and the upper plug 224A may include a metal nitride, a metal material, or a combination thereof.

[0178] The upper plug 224A may include a head 224H. The head 224H of the upper plug 224A may be located at a higher level than the upper surface of the protection spacer 219'. In one embodiment, the head 224H of the upper plug 224A may partially overlap the upper surface of the protection spacer 219'.

[0179] The head 224H may be a bonding pad, and the memory element 230 may be formed on the head 224H of the upper plug 224A. The memory element 230 may include a capacitor having a storage node. The bonding surface area between the upper plug 224A and the memory element 230 may be increased due to the head 224H.

[0180] According to another embodiment of the present invention, the protection spacer 219′ may be replaced by an air gap. In this case, a second spacer structure 215UA having an NKAK (nitride-low-k-air gap-low-k) structure may be disposed between the bit line 213 and the storage node contact plug 221A, and a first spacer structure 215L having an NKN structure may be disposed between the bit line contact plug 212 and the storage node contact plug 221A.

[0181] In the following, reference will be made to Figure 24 to Figure 27 Description for manufacturing Fig.23 An example of a method of manufacturing a semiconductor device 300 is shown.

[0182] Figure 24 to Figure 27 FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. Figure 24 to Figure 27 In, also appears Figures 7 to 19 The same figure marks in the drawings may denote the same constituent elements, and a detailed description thereof may be omitted below.

[0183] By executing the reference Figures 7 to 15 After forming the bit line contact plug 22 and the bit line 23 on the substrate 11 by the described process, a seed layer 26A, a conformal layer 27A, and a gap-filling spacer 28 may be formed. Subsequently, a protective material 29A may be deposited over the gap-filling spacer 28.

[0184] refer to Fig.24 , a protection spacer 29B may be formed by etching the protection material 29A. A bottom surface of the protection spacer 29B may be located at a level lower than a bottom surface of the bit line 23. An upper surface of the protection spacer 29B may be located at a level lower than an upper surface of the bit line hard mask 24.

[0185] The protection spacer 29B may prevent the conformal layer 27A on both sidewalls of the bit line 23 from being damaged in subsequent processes.

[0186] refer to Fig.25, you can Fig.24 A low-k spacer layer 30B is formed on the exposed surface of the structure including the protective spacer 29B. The low-k spacer layer 30B may have a lower dielectric constant than the seed layer 26A. The dielectric constant of the low-k spacer layer 30B may be the same as the dielectric constant of the conformal layer 27A. The low-k spacer layer 30B and the conformal layer 27A may be the same material. The low-k spacer layer 30B may include a low-k material, and the low-k spacer layer 30B may have a dielectric constant lower than silicon nitride. The low-k spacer layer 30B may have a dielectric constant of about 4.4 or less. The low-k spacer layer 30B may include a silicon-based material. The low-k spacer layer 30B may include at least one chemical selected from carbon and boron. The low-k spacer layer 30B may include a carbon-doped silicon-based material or a boron-doped silicon-based material. The low-k spacer layer 30B may include SiC, SiCO, SiCN, SiOCN, SiBN or SiBCN.

[0187] The low-k spacer layer 30B may be formed, for example, by atomic layer deposition (ALD). Since the protective spacer 29B and the low-k spacer layer 30B are sequentially formed on the conformal layer 27A having improved step coverage, the step coverage of the low-k spacer layer 30B may also be improved. According to another embodiment of the present invention, the low-k spacer layer 30B may have a step coverage worse than that of the conformal layer 27A.

[0188] As described above, since the low-k spacer layer 30B is formed on the protection spacer 29B having a reduced height, the protection spacer 29B may be prevented from being exposed to a subsequent process.

[0189] refer to Fig.26 , a plurality of plug isolation layers 31 may be formed on the low-k spacer layer 30B. The plug isolation layer 31 may separate each linear opening LO between the bit line structures into a plurality of contact openings CO. Figure 5 As shown, the plug isolation layer 31 may vertically overlap the buried word line 17 in the AA′ direction above the buried word line 17. The plug isolation layer 31 may include silicon nitride. According to another embodiment of the present invention, a portion of the bit line hard mask 24 may be consumed while forming the plug isolation layer 31.

[0190] From the perspective of the top view, the contact openings CO and the plug isolation layers 31 may be alternately formed between adjacent bit lines 23 in the direction in which the bit lines 23 extend. Adjacent contact openings CO may be arranged in a shape isolated by the bit line structure and the plug isolation layers 31. From the perspective of the top view, the contact openings CO may have a rectangular hole shape.

[0191] The lower material may be etched to be self-aligned with the contact opening CO. Thus, a plurality of recessed regions 32 exposing a portion of the active region 13 may be formed between the bit line structures. The recessed regions 32 may be formed using an anisotropic etching process or a combination of an anisotropic etching process and an isotropic etching process. For example, in a structure exposed by the contact opening CO between the bit line structures, the low-k spacer layer 30B, the conformal layer 27A, and the seed layer 26A may be anisotropically etched sequentially. Then, the portion of the active region 13 exposed thereafter may be isotropically etched. According to another embodiment of the present invention, the hard mask layer 14 may also be isotropically etched. Portions of the active region 13 and the gap-filling spacer 28 may be exposed by the recessed region 32.

[0192] The recessed region 32 may extend into the substrate 11. While forming the recessed region 32, the isolation layer 12, the gate cap layer 18, and the second impurity region 20 may be recessed to a predetermined depth. The bottom surface of the recessed region 32 may be located at a level lower than the upper surface of the bit line contact plug 22. The bottom surface of the recessed region 32 may be located at a level higher than the bottom surface of the bit line contact plug 22. The contact opening CO and the recessed region 32 may be coupled to each other. The vertical structure of the contact opening CO and the recessed region 32 may be referred to as a "storage node contact hole".

[0193] A dielectric structure (or spacer structure) may be formed on the sidewall of the bit line structure by performing an etching process to form the recessed region 32. The dielectric structure may include materials having different dielectric constants.

[0194] The dielectric structure may include a seed liner 26, a conformal spacer 27, a protection spacer 29′, and a low-k spacer 30′. The seed liner 26 may directly contact the sidewalls of the bit line contact plug 22 and the bit line 23. The conformal spacer 27 may cover the seed liner 26. The protection spacer 29′ may cover the conformal spacer 27, and the low-k spacer 30′ may cover the protection spacer 29′. The seed liner 26 may be located between the conformal spacer 27 and the bit line contact plug 22, and the seed liner 26 may extend to be located between the conformal spacer 27 and the bit line 23. The conformal spacer 27 may be located between the protection spacer 29′ and the seed liner 26, and the conformal spacer 27 may extend to be located between the gap filling spacer 28 and the seed liner 26. The protection spacer 29′ may be located between the low-k spacer 30′ and the conformal spacer 27, and a bottom surface of the protection spacer 29′ may contact an upper surface of the gap-filling spacer 28. A bottom surface of the low-k spacer 30′ may contact an upper surface of the gap-filling spacer 28. An upper surface of the protection spacer 29′ may be covered by the low-k spacer 30′.

[0195] The seed liner 26, the conformal spacer 27, the protection spacer 29′, and the low-k spacer 30′ may be sequentially stacked on the sidewalls of the bit line 23. The seed liner 26, the conformal spacer 27, the gap-filling spacer 28 may be stacked on the sidewalls of the bit line contact plug 22. The sidewalls and bottom surfaces of the gap-filling spacer 28 may be covered by the stack of the seed liner 26 and the conformal spacer 27.

[0196] refer to Fig. 27 , a storage node contact plug 33 may be formed. The storage node contact plug 33 may fill the contact opening CO and the recessed region 32. The storage node contact plug 33 may contact the second impurity region 20. The storage node contact plug 33 may be adjacent to the bit line structure. From the perspective of the top view, a plurality of storage node contact plugs 33 may be located between a plurality of bit line structures. In a direction parallel to the bit line 23, a plurality of storage node contact plugs 33 and a plurality of plug isolation layers 31 may be alternately located between adjacent bit lines 23.

[0197] In the storage node contact plug 33 , a lower plug 33L, an ohmic contact layer 33M, and an upper plug 33U may be sequentially stacked. The upper plug 33U may include a head 33H partially overlapping an upper surface of the protection spacer 29 ′.

[0198] As described above, seed liner 26, conformal spacer 27, and gap-filling spacer 28 may be located between bit line contact plug 22 and lower plug 33L. Seed liner 26, conformal spacer 27, protection spacer 29', and low-k spacer 30' may be located between bit line 23 and lower plug 33L.

[0199] The seed liner 26 and the gap filling spacer 28 may include silicon nitride, and the conformal spacer 27 and the low-k spacer 30′ may include a low-k material. The protection spacer 29′ may include silicon oxide. Therefore, a dielectric structure of an NKOK structure may be disposed between the bit line 23 and the lower plug 33L, and a dielectric structure of an NKN structure may be disposed between the bit line contact plug 22 and the lower plug 33L. According to another embodiment of the present invention, the protection spacer 29′ may be replaced with an air gap. In this case, an NKAK (nitride-low-k-air gap-low-k) structure may be disposed between the bit line 23 and the storage node contact plug 33.

[0200] The parasitic capacitance between the bit line 23 and the lower plug 33L can be reduced by the conformal spacer 27 and the low-k spacer 30'. The step coverage of the conformal spacer 27 can be improved by the seed liner 26. The protection spacer 29' can prevent the conformal spacer 27 from being lost.

[0201] Since the low-k spacer 30 ′ completely covers the protection spacer 29 ′, a short circuit or a bridge between the storage node contact plug 33 and the bit line 23 may be prevented.

[0202] Figure 28 to Figure 32 FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. Figure 28 to Figure 32 In, also appears Figures 7 to 27 The same reference numerals in the drawings may denote the same constituent elements, and a detailed description thereof may be omitted below.

[0203] By executing the above reference Figures 7 to 15 After forming the bit line contact plug 22 and the bit line 23 on the substrate 11 by the described process, a seed layer 26A, a conformal layer 27A, and a gap-filling spacer 28 may be formed. Subsequently, a protective material 29A may be deposited on the gap-filling spacer 28.

[0204] refer to Fig.28 , a protection spacer 29B may be formed by etching the protection material 29A. A bottom surface of the protection spacer 29B may be located at a level lower than a bottom surface of the bit line 23. An upper surface of the protection spacer 29B may be located at a level lower than an upper surface of the bit line hard mask 24.

[0205] The protection spacer 29B can prevent the conformal layer 27A on both sidewalls of the bit line 23 from being damaged during subsequent processes.

[0206] Subsequently, an additional sacrificial protection material 29C may be formed on the protection spacers 29B having a reduced height. The additional sacrificial protection material 29C may have an etch selectivity with respect to the protection spacers 29B. The additional sacrificial protection material 29C may include titanium nitride.

[0207] Subsequently, by selectively etching the additional sacrificial protection material 29C, the upper portion of the protection spacer 29B may be exposed. An upper surface of the additional sacrificial protection material 29C may be located at a lower level than an upper surface of the protection spacer 29B.

[0208] According to another embodiment of the present invention, additional sacrificial protective material 29C is deposited on Fig.15 After the protective material 29A is formed, the protective spacer 29B having a reduced height may be formed by sequentially etching the additional sacrificial protective material 29C and the protective material 29A. Subsequently, the additional sacrificial protective material 29C may be further etched to expose the upper portion of the protective spacer 29B.

[0209] refer to Fig.29 By selectively removing the upper portion of the exposed protection spacer 29B, a protection spacer 29B′ having a lower height may be formed.

[0210] An upper surface of the protection spacer 29B′ may be located at a lower level than an upper surface of the protection spacer 29B.

[0211] As described above, the protection spacer 29B′ having a lower height may be protected from subsequent processes.

[0212] refer to Fig.30 , the additional sacrificial protective material 29C may be removed. Subsequently, a low-k spacer layer 30B may be formed on the protective spacer 29B′. The low-k spacer layer 30B may have a lower dielectric constant than the seed layer 26A. The dielectric constant of the low-k spacer layer 30B may be the same as the dielectric constant of the conformal layer 27A. The low-k spacer layer 30B and the conformal layer 27A may be the same material. The low-k spacer layer 30B may include a low-k material, and the low-k spacer layer 30B may have a lower dielectric constant than silicon nitride. The low-k spacer layer 30B may have a dielectric constant of about 4.4 or less. The low-k spacer layer 30B may include a silicon-based material. The low-k spacer layer 30B may include at least one chemical selected from carbon and boron. The low-k spacer layer 30B may include a carbon-doped silicon-based material or a boron-doped silicon-based material. The low-k spacer layer 30B may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0213] The low-k spacer layer 30B may be formed, for example, by an atomic layer deposition (ALD) process. Since the protective spacer 29B′ and the low-k spacer layer 30B are sequentially formed on the conformal layer 27A having improved step coverage, the step coverage of the low-k spacer layer 30B may also be improved. According to another embodiment of the present invention, the low-k spacer layer 30B may have a worse step coverage than the conformal layer 27A.

[0214] As described above, since the low-k spacer layer 30B is formed on the protection spacer 29B′ having a lower height, the protection spacer 29B′ may be further prevented from being exposed during a subsequent process.

[0215] refer to Fig.31 , a plurality of plug isolation layers 31 may be formed on the low-k spacer layer 30B. The plug isolation layer 31 may separate each line-type opening LO between the bit line structures into a plurality of contact openings CO. Figure 5 As shown, the plug isolation layer 31 may vertically overlap the buried word line 17 in the AA′ direction above the buried word line 17. The plug isolation layer 31 may include silicon nitride. According to another embodiment of the present invention, a portion of the bit line hard mask 24 may be consumed while forming the plug isolation layer 31.

[0216] From the perspective of the top view, the contact openings CO and the plug isolation layers 31 may be alternately formed between adjacent bit lines 23 in the direction in which the bit lines 23 extend. Adjacent contact openings CO may be arranged in an isolated shape by the bit line structure and the plug isolation layers 31. From the perspective of the top view, the contact openings CO may have a rectangular hole shape.

[0217] The lower material may be etched to be self-aligned with the contact opening CO. As a result, a plurality of recessed regions 32 exposing a portion of the active region 13 between the bit line structures may be formed. The recessed regions 32 may be formed using an anisotropic etching process or a combination of an anisotropic etching process and an isotropic etching process. For example, in a structure exposed by the contact opening CO between the bit line structures, the low-k spacer layer 30B, the conformal layer 27A, and the seed layer 26A may be sequentially anisotropically etched, and then the portion of the active region 13 exposed thereafter may be isotropically etched. According to another embodiment of the present invention, the hard mask layer 14 may also be isotropically etched. Portions of the active region 13 and the gap-filling spacer 28 may be exposed by the recessed regions 32.

[0218] The recessed region 32 may extend into the substrate 11. While forming the recessed region 32, the isolation layer 12, the gate cap layer 18, and the second impurity region 20 may be recessed to a predetermined depth. The bottom surface of the recessed region 32 may be located at a level lower than the upper surface of the bit line contact plug 22. The bottom surface of the recessed region 32 may be located at a level higher than the bottom surface of the bit line contact plug 22. The contact opening CO and the recessed region 32 may be coupled to each other. The vertical structure of the contact opening CO and the recessed region 32 may be referred to as a "storage node contact hole".

[0219] A dielectric structure (or spacer structure) may be formed on the sidewalls of the bit line structure by performing an etching process to form the recessed region 32. The dielectric structure may include materials having different dielectric constants.

[0220] The dielectric structure may include a seed liner 26, a conformal spacer 27, a protection spacer 29″, and a low-k spacer 30′. The seed liner 26 may directly contact the sidewalls of the bit line contact plug 22 and the bit line 23. The conformal spacer 27 may cover the seed liner 26. The protection spacer 29″ may cover the conformal spacer 27, and the low-k spacer 30′ may cover the protection spacer 29″. The seed liner 26 may be located between the conformal spacer 27 and the bit line contact plug 22. In addition, the seed liner 26 may extend to be located between the conformal spacer 27 and the bit line 23. The conformal spacer 27 may be located between the protection spacer 29″ and the seed liner 26, and the conformal spacer 27 may extend to be located between the gap filling spacer 28 and the seed liner 26. The protection spacer 29″ may be located between the low-k spacer 30′ and the conformal spacer 27, and a bottom surface of the protection spacer 29″ may contact an upper surface of the gap-filling spacer 28. The bottom surface of the low-k spacer 30′ may contact an upper surface of the gap-filling spacer 28. An upper surface of the protection spacer 29″ may be covered by the low-k spacer 30′.

[0221] The seed liner 26, the conformal spacer 27, the protection spacer 29″ and the low-k spacer 30′ may be sequentially stacked on the sidewalls of the bit line 23. The seed liner 26, the conformal spacer 27 and the gap-filling spacer 28 may be stacked on the sidewalls of the bit line contact plug 22. The sidewalls and the bottom surface of the gap-filling spacer 28 may be covered by the stack of the seed liner 26 and the conformal spacer 27.

[0222] refer to Fig.32 , a storage node contact plug 33 may be formed. The storage node contact plug 33 may fill the contact opening CO and the recessed region 32. The storage node contact plug 33 may contact the second impurity region 20. The storage node contact plug 33 may be adjacent to the bit line structure. From the perspective of the top view, a plurality of storage node contact plugs 33 may be located between a plurality of bit line structures. In a direction parallel to the bit line 23, a plurality of storage node contact plugs 33 and a plurality of plug isolation layers 31 may be alternately located between adjacent bit lines 23.

[0223] In the storage node contact plug 33 , a lower plug 33L, an ohmic contact layer 33M, and an upper plug 33U may be sequentially stacked.

[0224] As described above, seed liner 26, conformal spacer 27, and gap-filling spacer 28 may be located between bit line contact plug 22 and lower plug 33L. Seed liner 26, conformal spacer 27, protection spacer 29″, and low-k spacer 30′ may be located between bit line 23 and lower plug 33L.

[0225] The seed liner 26 and the gap-filling spacer 28 may include silicon nitride, and the conformal spacer 27 and the low-k spacer 30′ may include a low-k material. The protection spacer 29″ may include silicon oxide. Therefore, the dielectric structure may have an NKOK structure and may be disposed between the bit line 23 and the lower plug 33L, and a dielectric structure having an NKN structure may be disposed between the bit line contact plug 22 and the lower plug 33L.

[0226] According to another embodiment of the present invention, the protection spacer 29 ″ may be replaced with an air gap. In this case, a NKAK (nitride-low-k-air gap-low-k) structure may be provided between the bit line 23 and the lower plug 33L.

[0227] According to another embodiment of the present invention, a silicon nitride liner may be further formed on the low-k spacer 30', and thus a NKOKN (nitride-low-k-oxide-low-k-nitride) structure may be provided. The NKOKN structure may be converted into a NKAKN structure by replacing the protection spacer 29" with an air gap.

[0228] The parasitic capacitance between the bit line 23 and the lower plug 33L may be reduced by the conformal spacer 27 and the low-k spacer 30 ′. The step coverage of the conformal spacer 27 may be improved by the seed liner 26 . The protection spacer 29 ″ may prevent the loss of the conformal spacer 27 .

[0229] Since the low-k spacer 30 ′ completely covers the protection spacer 29 ″, a short circuit or bridge between the storage node contact plug 33 and the bit line 23 may be prevented.

[0230] Fig.33 FIG. 4 is a diagram showing a semiconductor device 400 according to another embodiment of the present invention. Fig.33 In, also appears Figures 5 to 6B The same reference numerals in the drawings may denote the same constituent elements, and a detailed description thereof may be omitted below.

[0231] refer to Fig.33 , the semiconductor device 400 may include a plurality of memory cells. Each memory cell may include a cell transistor including a buried word line 207, a bit line 213, and a memory element 230. Other constituent elements except the storage node contact plug 221B may be connected to Figures 5 to 6BThe constituent elements are the same. The first spacer structure 215L may be formed between the bit line contact plug 212 and the storage node contact plug 221B. The second spacer structure 215UB may be formed between the bit line 213 and the storage node contact plug 221B. The first spacer structure 215L may include a seed liner 216, a conformal spacer 217, and a gap filling spacer 218. The second spacer structure 215UB may include a seed liner 216, a conformal spacer 217, a protective spacer 219, and a low-k spacer 220. The conformal spacer 217 and the low-k spacer 220 may have a lower dielectric constant than the seed liner 216. The conformal spacer 217 and the low-k spacer 220 may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN. The conformal spacer 217 and the low-k spacer 220 may have a lower dielectric constant than silicon nitride, and they may include different low-k materials. The protection spacer 219 may include silicon oxide.

[0232] The seed liner 216 may have a In one embodiment, the seed liner 216 may have a thickness of about 1 to about The seed liner 216 may be used as a seed for uniformly depositing the conformal spacer 217. The conformal spacer 217 and the seed liner 216 may be in direct contact with each other. The total thickness of the conformal spacer 217 and the protection spacer 219 may be greater than the thickness of the seed liner 216.

[0233] The second spacer structure 215UB may have a NKOK structure and may be disposed between the bit line 213 and the storage node contact plug 221B, and the first spacer structure 215L having a NKN structure may be disposed between the bit line contact plug 212 and the storage node contact plug 221B.

[0234] According to another embodiment of the present invention, Figure 6C As shown, the protection spacer 219 may be replaced with an air gap. In this case, a second spacer structure 215UB having an NKAK (nitride-low-k-air gap-low-k) structure may be disposed between the bit line 213 and the storage node contact plug 221B, and a first spacer structure 215L having an NKN structure may be disposed between the bit line contact plug 212 and the storage node contact plug 221B.

[0235] The storage node contact plug 221B of the semiconductor device 400 may be formed between adjacent bit line structures. The storage node contact plug 221B may be coupled to the second impurity region 210. The storage node contact plug 221B may include a lower plug 222 and an upper plug 224B. The storage node contact plug 221B may also include an ohmic contact layer 223 between the lower plug 222 and the upper plug 224B. The ohmic contact layer 223 may include a metal-containing material, such as, for example, a metal silicide. The lower plug 222 may include a silicon-containing material, such as, for example, polysilicon. The upper plug 224B may include a metal-containing material, such as, for example, a metal nitride, a metal material, or a combination thereof.

[0236] The upper plug 224B may include an extension portion 224E extending to overlap the upper surface of the bit line hard mask 214. The extension portion 224E may be a bonding pad, and the memory element 230 may be formed on the extension portion 224E of the upper plug 224B. The memory element 230 may include a capacitor having a storage node.

[0237] Fig.34 FIG. 5 is a view showing a semiconductor device 500 according to another embodiment of the present invention. Fig.34 In, also appears Figures 5 to 6C and Fig.33 The same reference numerals in the drawings may denote the same constituent elements. Detailed description of the same elements may be omitted.

[0238] Reference now Fig.34 , the semiconductor device 500 may include a plurality of memory cells. Each memory cell may include a cell transistor including a buried word line 207 (see Figure 6B ), bit line 213 and storage element 230. Other constituent elements except air gap AG and air gap cover layer AGC may be Fig.33The constituent elements in are the same. The first spacer structure 215L may be formed between the bit line contact plug 212 and the storage node contact plug 221B. The second spacer structure 215UC may be formed between the bit line 213 and the storage node contact plug 221B. The first spacer structure 215L may include a seed liner 216, a conformal spacer 217, and a gap filling spacer 218. The second spacer structure 215UC may include a seed liner 216, a conformal spacer 217, an air gap AG, an air gap cover layer AGC, and a low-k spacer 220. The conformal spacer 217 and the low-k spacer 220 may have a lower dielectric constant than the seed liner 216. The conformal spacer 217 and the low-k spacer 220 may include SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN. The conformal spacer 217 and the low-k spacer 220 may have a lower dielectric constant than silicon nitride, and they may include different low-k materials. The protection spacer 219 may include silicon oxide.

[0239] The seed liner 216 may have a In one embodiment, the seed liner 216 may have a thickness of about 1 to about The seed liner 216 may be used as a seed for uniformly depositing the conformal spacer 217. The conformal spacer 217 and the seed liner 216 may be in direct contact with each other.

[0240] The second spacer structure 215UC having the NKAK structure may be disposed between the bit line 213 and the storage node contact plug 221B. The first spacer structure 215L having the NKN structure may be disposed between the bit line contact plug 212 and the storage node contact plug 221B. The upper side of the air gap AG may be sealed by an air gap cover layer AGC. The air gap cover layer AGC may include silicon nitride, silicon oxide, silicon oxycarbide, or a combination thereof. The air gap AG may be parallel to both sidewalls of the bit line 213. A pair of air gaps AG may be formed.

[0241] The storage node contact plug 221B of the semiconductor device 500 may be formed between adjacent bit line structures. The storage node contact plug 221B may be coupled to the second impurity region 210. The storage node contact plug 221B may include a lower plug 222 and an upper plug 224B separated by an ohmic contact layer 223, and the ohmic contact layer 223 is formed between the lower plug 222 and the upper plug 224B. The ohmic contact layer 223 may include a metal silicide. For example, the lower plug 222 may include polysilicon, and the upper plug 224B may include a metal nitride, a metal material, or a combination thereof.

[0242] The upper plug 224B may include an extension portion 224E extending to overlap the upper surface of the bit line hard mask 214. The extension portion 224E may be a bonding pad, and the memory element 230 may be formed on the extension portion 224E of the upper plug 224B. The memory element 230 may include a capacitor having a storage node.

[0243] The pair of air gaps AG may be completely covered by the air gap cover layer AGC. According to another embodiment of the present invention, one of the pair of air gaps AG may be completely covered by the air gap cover layer AGC, while the other air gap AG may be partially covered by the extension portion 224E of the upper plug 224B.

[0244] According to an embodiment of the present invention, since the low-k material is deposited by using a thin seed liner, the step coverage of the low-k material can be improved.

[0245] According to an embodiment of the present invention, an increase in parasitic capacitance can be suppressed by reducing the thickness of silicon nitride occupied in the spacer structure.

[0246] According to an embodiment of the present invention, parasitic capacitance between a bit line contact plug and a storage node contact plug may be reduced by forming a low-k material between the bit line contact plug and the storage node contact plug.

[0247] According to an embodiment of the present invention, parasitic capacitance between a bit line and a storage node contact plug may be reduced by forming a low-k material between the bit line and the storage node contact plug.

[0248] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A semiconductor device, comprising: A bit line structure comprising a bit line contact plug, a bit line and a bit line hard mask sequentially stacked on a substrate; a storage node contact plug spaced apart from the bit line structure; a conformal spacer located between the bit line and the storage node contact plug and comprising a low-k material; a seed liner between the conformal spacer and the bit line; a gap-filling spacer located between the bit line contact plug and the storage node contact plug, wherein the seed liner and the conformal spacer cover sidewalls of the gap-filling spacer, Wherein, the seed liner is thinner than the conformal spacer.

2. The semiconductor device according to claim 1, wherein: The conformal spacer and the seed liner are in direct contact with each other.

3. The semiconductor device according to claim 1, wherein: The conformal spacer has a lower dielectric constant than the seed liner.

4. The semiconductor device according to claim 1, wherein: The conformal spacer includes an impure silicon-based dielectric material including an impurity of at least one of carbon or boron.

5. The semiconductor device according to claim 1, wherein: The conformal spacer includes at least one of SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN.

6. The semiconductor device according to claim 1, wherein: The seed liner includes silicon nitride.

7. The semiconductor device according to claim 1, wherein: The seed lining has to Thickness.

8. The semiconductor device according to claim 1, wherein: The seed liner directly contacts the bit line and the bit line contact plug.

9. The semiconductor device according to claim 1, wherein: Each of the seed liner and the conformal spacer extends to be located between the bit line contact plug and the storage node contact plug.

10. The semiconductor device according to claim 9, in, The seed liner and the conformal spacer cover a bottom surface of the gap-filling spacer.

11. The semiconductor device according to claim 1, wherein: The seed liner and the gap-fill spacer include silicon nitride, and The conformal spacer has a lower dielectric constant than silicon nitride.

12. The semiconductor device according to claim 1, wherein: The seed liner and the conformal spacer have a linear shape contacting both sidewalls of the bit line.

13. The semiconductor device according to claim 1, further comprising: a protection spacer located between the conformal spacer and the storage node contact plug, the protection spacer being in contact with the conformal spacer; as well as a low-k spacer located between the protection spacer and the storage node contact plug, Wherein, the low-k spacer is thinner than the protection spacer.

14. The semiconductor device according to claim 13, wherein: The low-k spacer and the protection spacer include different materials.

15. The semiconductor device according to claim 13, wherein: The conformal spacer and the low-k spacer include the same material.

16. The semiconductor device according to claim 13, wherein: The protection spacer includes silicon oxide, and The low-k spacer includes at least one of SiC, SiCO, SiCN, SiOCN, SiBN or SiBCN.

17. The semiconductor device according to claim 13, wherein: An upper surface of the protection spacer is located at a lower level than an upper surface of the bit line structure, and The low-k spacer completely covers the protection spacer.

18. The semiconductor device according to claim 13, wherein: The total thickness of the conformal spacer and the protection spacer is greater than the thickness of the seed liner.

19. The semiconductor device according to claim 13, further comprising: A protection liner is located between the low-k spacer and the storage node contact plug and contacts the low-k spacer.

20. The semiconductor device according to claim 19, wherein The low-k spacer has a lower dielectric constant than the protection liner.

21. The semiconductor device according to claim 19, wherein: The protective liner includes silicon nitride.

22. The semiconductor device according to claim 1, further comprising: a low-k spacer located between the conformal spacer and the storage node contact plug; as well as An air gap is between the conformal spacer and the low-k spacer.

23. The semiconductor device according to claim 22, further comprising: A protection liner is located between the low-k spacer and the storage node contact plug and contacts the low-k spacer.

24. A semiconductor device comprising: bit lines spaced apart from each other over the substrate by line-shaped openings; bit line contact plugs, which are respectively located under the bit lines; a plurality of plug isolation layers, which divide the linear opening into a plurality of contact openings; storage node contact plugs, which respectively fill the plurality of contact openings; a first spacer structure disposed between the storage node contact plug and the bit line and comprising a stack of a first silicon nitride, a first low-k material, a silicon oxide, and a second low-k material; as well as a second spacer structure disposed between the bit line contact plug and the storage node contact plug and comprising a stack of a second silicon nitride, a third low-k material and a third silicon nitride, The second silicon nitride extends from the first silicon nitride, and the third low-k material extends from the first low-k material.

25. The semiconductor device of claim 24, wherein: The first silicon nitride is located between the bit line and the first low-k material, and The first silicon nitride is thinner than the first low-k material.

26. The semiconductor device according to claim 24, wherein: The first low-k material, the second low-k material, and the third low-k material have a lower dielectric constant than the first silicon nitride and the second silicon nitride.

27. The semiconductor device according to claim 24, wherein: The first low-k material, the second low-k material, and the third low-k material include the same material.

28. The semiconductor device according to claim 24, wherein: The first low-k material, the second low-k material, and the third low-k material include at least one of SiC, SiCO, SiCN, SiOCN, SiBN, or SiBCN.

29. The semiconductor device according to claim 24, wherein: The first spacer structure further includes additional silicon nitride over the second low-k material, The additional silicon nitride is located between the second low-k material and the storage node contact plug.

30. The semiconductor device according to claim 24, wherein: The plug isolation layer has the same material as at least one of the first low-k material, the second low-k material, and the third low-k material.

31. The semiconductor device according to claim 24, wherein: The plug isolation layer includes a low-k material containing boron, and The first low-k material, the second low-k material, and the third low-k material include low-k materials containing carbon.

32. The semiconductor device according to claim 24, wherein: A total thickness of the first low-k material and silicon oxide is formed to be greater than a thickness of the first silicon nitride.

33. The semiconductor device according to claim 24, wherein: The first silicon nitride is formed to have to Thickness.

34. A method for manufacturing a semiconductor device, comprising: forming a plurality of bit line structures over a substrate, the bit line structures comprising bit line contact plugs and bit lines over the bit line contact plugs; forming a spacer structure on a sidewall of the bit line structure; as well as forming a storage node contact plug contacting the spacer structure between the bit line structures, Wherein, the step of forming the spacer structure comprises: forming a nitrogen-containing seed liner on sidewalls of the bit line structure; and conformally forming a first low-k spacer on the nitrogen-containing seed liner, the first low-k spacer having a lower dielectric constant than the nitrogen-containing seed liner, Wherein, the step of forming the spacer structure further comprises: A gap-filling spacer is formed on the first low-k spacer adjacent to the bit line contact plug.

35. The method of claim 34, wherein: The nitrogen-containing seed liner is thinner than the first low-k spacer.

36. The method of claim 34, wherein: The step of forming the spacer structure further includes: forming a protection spacer on the gap-fill spacer and the first low-k spacer parallel to a sidewall of the bit line structure; and A second low-k spacer is formed on the protection spacer.

37. The method of claim 36, wherein: The step of forming the spacer structure further includes forming a nitrogen-containing liner on the second low-k spacer.

38. The method of claim 36, wherein: The protection spacer includes silicon oxide, and The gap-fill spacer includes silicon nitride.

39. The method of claim 36, wherein: The second low-k spacer has a lower dielectric constant than the nitrogen-containing seed liner.

40. The method of claim 36, wherein: The first low-k spacer and the second low-k spacer include a same material.

41. The method of claim 36, wherein: A total thickness of the protection spacer and the first low-k spacer is greater than a thickness of the nitrogen-containing seed liner.

42. The method of claim 34, wherein: The nitrogen-containing seed liner is formed to have to Thickness.

43. The method of claim 34, wherein: The nitrogen-containing seed liner includes silicon nitride, and The first low-k spacer includes SiC, SiCO, SiCN, SiOCN, SiBN or SiBCN.

44. The method of claim 34, wherein: The step of forming the storage node contact plug includes: forming a plug isolation layer including a plurality of contact openings between the bit line structures, the plurality of contact openings exposing a surface of the substrate; and The contact opening is filled with a conductive material to form the storage node contact plug.

45. The method of claim 44, wherein: The dielectric constant of the plug isolation layer is equal to the dielectric constant of the first low-k spacer.

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