Hybrid gate field effect transistor and method of manufacture, switching circuit

Abstract

This application provides a hybrid gate field-effect transistor (GFFET), its fabrication method, and a switching circuit. The hybrid gate GFFET includes a channel layer and source, drain, and gate structures stacked on top of the channel layer. The gate structure employs a hybrid gate structure, which is fabricated from two materials. The gate structure includes a first structural layer and a second structural layer. The second structural layer encapsulates the first structural layer. The first structural layer is an N-type gallium nitride (GaN) layer or an intrinsic GaN layer; the second structural layer is a P-type GaN layer. A gate metal layer is disposed on the side of the gate structure facing away from the channel layer, and the gate metal layer and the first structural layer can make ohmic contact. As can be seen from the above description, by adopting a hybrid gate structure, the gate structure is fabricated from two different materials, and the material located in the middle of the hybrid gate can make ohmic contact with the gate metal layer, thereby improving the reliability of the connection between the gate metal layer and the gate structure, and thus improving the reliability of the hybrid gate GFFET.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a hybrid gate field-effect transistor and its fabrication method, and a switching circuit. Background Technology

[0002] Field-effect transistors (FETs) are widely used as circuit switching components in various scenarios. GaN (gallium nitride) FETs, due to their material properties, have high mobility and high chemical stability, making them suitable for higher frequency switching applications.

[0003] GaN field-effect transistors (FETs) achieve switching by controlling the on / off state of a two-dimensional electron gas in the channel. GaN FETs are generally divided into two types: normally-on FETs, also known as depletion-mode FETs, and normally-off FETs, also known as enhancement-mode FETs. However, for the safety considerations of power systems, switching devices are generally required to be normally-off devices. Currently, there are several ways to achieve normally-off switching.

[0004] Existing GaN field-effect transistors include a source, a drain, a gate structure, and a gate metal layer. In operation, the gate metal layer supplies power to the gate structure, and the gate structure controls the conduction of the source and drain. However, the gate metal layer and the gate structure typically form a Schottky contact, and long-term hot electron bombardment of the Schottky junction can lead to failure, resulting in low reliability of GaN field-effect transistors. Summary of the Invention

[0005] This application provides a hybrid gate field-effect transistor, its fabrication method, and a switching circuit, aiming to improve the reliability of the hybrid gate field-effect transistor.

[0006] Firstly, a hybrid gate field-effect transistor (HFET) is provided. This HFET is used in switching circuits as a primary device to control the switching circuit's on and off states. The HFET includes a channel layer and source, drain, and gate structures stacked on top of the channel layer. The source, drain, and gate structures are disposed on the same layer, with the gate structure located between the source and drain. In this application, the gate structure employs a hybrid gate structure, fabricated from two materials. Specifically, the gate structure includes a first structural layer and a second structural layer. The first and second structural layers are disposed on the same layer and are respectively connected to the channel layer. Furthermore, the second structural layer encloses the first structural layer. The first structural layer is located in the middle of the gate structure, and the second structural layer is located on the periphery of the gate structure. In this application, the first structural layer is an N-type gallium nitride layer or an intrinsic gallium nitride layer; the second structural layer is a P-type gallium nitride layer. The HFET also includes a gate metal layer, which is disposed on the side of the gate structure facing away from the channel layer, and the gate metal layer and the first structural layer can be connected via an ohmic contact. As can be seen from the above description, by adopting a hybrid gate structure, the gate structure is made of two different materials, and the material located in the middle of the hybrid gate can make ohmic contact with the gate metal layer, thereby improving the reliability of the connection between the gate metal layer and the gate structure, and thus improving the reliability of the hybrid gate field-effect transistor.

[0007] In one specific implementation, the channel layer includes a stacked gallium nitride (GaN) layer and an aluminum gallium nitride (AGaN) barrier layer; the source, drain, and gate structures are disposed on the AGaN barrier layer. A channel is formed between the GaN layer and the AGaN barrier layer.

[0008] In one specific embodiment, the system further includes a substrate and a buffer layer disposed on the substrate; the gallium nitride layer is formed in the buffer layer. The buffer layer allows the gallium nitride layer to be supported on the substrate.

[0009] In one specific implementation, the substrate material can be silicon, sapphire, silicon carbide, or gallium nitride bulk material. The substrate can be fabricated using different materials.

[0010] In one specific implementation, a passivation layer is further included, which is stacked with the aluminum gallium nitride barrier layer; the source, drain, and gate structures pass through the passivation layer and are exposed outside the passivation layer. The passivation layer protects the structural layers of the hybrid gate field-effect transistor.

[0011] In one specific implementation, the first structural layer is a cylindrical, square, or elliptical column. The shape of the first structural layer can be chosen from different shapes.

[0012] In one specific implementation, the number of the first structural layers may be at least one. For example, the number of the first structural layers may be one, two, three, or other different numbers.

[0013] In a specific feasible implementation, when there are multiple first structural layers, the multiple first structural layers can be arranged in a single row, an array, or other arrangements.

[0014] In one specific implementation, a Schottky contact is used between the gate metal layer and the second structural layer. The gate metal layer is connected to the first and second structural layers of the gate structure through two different connection methods.

[0015] Secondly, a method for fabricating a hybrid gate field-effect transistor is provided, the method comprising the following steps:

[0016] A first structural layer and a second structural layer are formed on the channel layer; wherein the first structural layer and the second structural layer are disposed on the same layer, and the second structural layer encloses the first structural layer; the first structural layer and the second structural layer constitute a gate structure;

[0017] The source and drain are formed on the channel layer.

[0018] As can be seen from the above description, by adopting a hybrid gate structure, the gate structure is made of two different materials, and the material located in the middle of the hybrid gate can make ohmic contact with the gate metal layer, thereby improving the reliability of the connection between the gate metal layer and the gate structure, and thus improving the reliability of the hybrid gate field-effect transistor.

[0019] In one specific implementation, forming the first and second structural layers on the channel layer specifically involves: forming an etched layer on the channel layer; etching an annular hole in the etched layer; forming a second structural layer within the annular hole; etching a via in the etched layer, wherein the inner sidewall of the second structural layer serves as the sidewall of the via; forming the first structural layer within the via, with the second structural layer enclosing the first structural layer; and etching away the remaining portion of the etched layer. A gate structure is thus formed through etching.

[0020] In one specific implementation, forming the first and second structural layers on the channel layer specifically involves: forming an etched layer on the channel layer; etching a via in the etched layer; forming the first structural layer within the via; etching an annular hole in the etched layer, with the outer wall of the first structural layer exposed in the annular hole; forming the second structural layer within the annular hole, and the second structural layer enclosing the first structural layer; and etching away the remaining portion of the etched layer. The gate structure is thus formed by etching.

[0021] In one specific implementation, forming the first structural layer and the second structural layer on the channel layer specifically involves: forming a material layer on the channel layer that is the same material as the first structural layer; etching the material layer to form the first structural layer; and forming the second structural layer by ion implantation, wherein the second structural layer encapsulates the first structural layer. The gate structure is formed by ion implantation.

[0022] In one specific implementation, forming the first structural layer and the second structural layer on the channel layer specifically involves: forming a material layer on the channel layer that is the same material as the second structural layer; etching the material layer to form the second structural layer; forming the first structural layer by ion implantation, with the second structural layer encapsulating the first structural layer. The gate structure is formed by ion implantation.

[0023] In one specific implementation, the method further includes: forming a buffer layer on a substrate; and forming the channel layer in the buffer layer.

[0024] Thirdly, a switching circuit is provided, comprising a motherboard and a hybrid gate field-effect transistor as described above, disposed on the motherboard. As can be seen from the above description, by employing a hybrid gate structure, where the gate structure is made of two different materials, and the material located in the middle of the hybrid gate can achieve ohmic contact with the gate metal layer, the reliability of the connection between the gate metal layer and the gate structure is improved, thereby enhancing the reliability of the hybrid gate field-effect transistor. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a hybrid gate field-effect transistor provided in an embodiment of this application;

[0026] Figure 2 This is a top view of the gate structure of a hybrid gate field-effect transistor provided in an embodiment of this application;

[0027] Figure 3 Another top view of the gate structure of the hybrid gate field-effect transistor provided in the embodiments of this application;

[0028] Figure 4 Another top view of the gate structure of the hybrid gate field-effect transistor provided in the embodiments of this application;

[0029] Figures 5a to 5g A flowchart illustrating the fabrication process of a hybrid gate field-effect transistor provided in an embodiment of this application;

[0030] Figures 6a to 6g Another fabrication flowchart of the hybrid gate field-effect transistor provided in this application embodiment;

[0031] Figures 7a to 7dA flowchart illustrating the fabrication process of a hybrid gate field-effect transistor provided in an embodiment of this application;

[0032] Figures 8a to 8d Another fabrication flowchart of the hybrid gate field-effect transistor provided in this application embodiment. Detailed Implementation

[0033] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0034] First, let me explain the hybrid gate field-effect transistor provided in this application embodiment. Field-effect transistors are widely used in various scenarios as circuit switching components. Due to their material properties, GaN (gallium nitride) field-effect transistors have high mobility and high chemical stability, and can be used as higher frequency switches, so they are widely used in high frequency circuit switches.

[0035] GaN field-effect transistors (FETs) achieve switching by controlling the on / off state of the two-dimensional electron gas in the channel. GaN FETs are generally classified into two types: normally-on (NOT) FETs, also known as depletion-mode FETs, and normally-off (NOT) FETs, also known as enhancement-mode FETs. However, for the safety of power systems, normally-off devices are generally required. Several methods exist for achieving NOT. Currently, GaN FETs typically use a Schottky junction to connect the gate metal and the gate structure. However, long-term hot electron bombardment of the Schottky junction can lead to failure, resulting in low reliability. Therefore, this application provides a hybrid-gate FET to improve the reliability of FETs, which will be described in detail below with reference to specific figures and embodiments.

[0036] Figure 1 This diagram illustrates the structural layers of a hybrid gate field-effect transistor (HFET) provided in an embodiment of this application. The HFET includes multiple stacked structural layers. For ease of description, it is referred to as... Figure 1 The placement direction of the hybrid gate field-effect transistor shown is the reference direction. The hybrid gate field-effect transistor includes a substrate 10, a buffer layer 20, a channel layer 30, and a source / drain structure layer 50 arranged sequentially along direction a. The above structure layers are described in detail below with reference to the specific accompanying drawings.

[0037] Substrate 10 is the basic component of the hybrid gate field-effect transistor (HFET), used to support the various functional layers of the HFET. In specific configurations, substrate 10 can be made of different materials, as long as it possesses sufficient supporting strength. For example, substrate 10 can be a structural layer made of different materials such as silicon, sapphire, silicon carbide, or gallium nitride. Substrate 10 can be fabricated using different materials.

[0038] As an optional solution, the substrate 10 may be a rectangular structure layer. However, it should be understood that the shape of the substrate 10 provided in the embodiments of this application is not limited to a rectangular structure, and other shapes may also be adopted, such as elliptical, polygonal and other different shapes, as long as it has sufficient area to support other functional layers of the hybrid gate field-effect transistor.

[0039] A buffer layer 20 is disposed on the substrate 10, and can be formed on the surface of the substrate 10 through processes such as chemical vapor deposition or epitaxial growth. The buffer layer 20 is an optional structural layer. It can be configured as needed. For example, if the substrate 10 can directly support the channel layer 30, the buffer layer 20 is not required, and the channel layer 30 can be directly formed on the substrate 10. When the materials of the channel layer 30 and the substrate 10 conflict, and the channel layer 30 cannot be directly formed on the substrate 10, the buffer layer 20 is provided to isolate the substrate 10 from the channel layer 30. In this case, the buffer layer 20 serves as the support layer for the channel layer 30. While the buffer layer 20 supports the channel layer 30, it serves as a structural layer supporting the channel. Furthermore, the buffer layer 20 also possesses certain elastic deformation properties, protecting the channel layer 30 disposed on its surface and improving the reliability and safety of the hybrid gate field-effect transistor provided in this embodiment.

[0040] As an alternative, the buffer layer 20 can be a structural layer made of different materials such as gradient aluminum gallium nitride, superlattice, and low-temperature aluminum nitride. When specifically fabricating a hybrid gate field-effect transistor, different materials can be selected to fabricate the buffer layer 20 as needed.

[0041] The channel layer 30 is the functional layer of the hybrid gate field-effect transistor (HFET) and is used to form the two-dimensional electron gas of the HFET. Alternatively, the channel layer 30 includes a gallium nitride (GaN) layer 32 and an aluminum gallium nitride (AGaN) barrier layer 31 stacked along direction a. A channel can be formed at the interface between the GaN layer 32 and the AGaN barrier layer 31, and the two-dimensional electron gas is located at the interface between the GaN layer 32 and the AGaN barrier layer 31.

[0042] When specifically configuring the channel layer 30, the gallium nitride layer 32 can be disposed on the buffer layer 20, such as by etching or ion implantation. When the substrate 10 can directly support the channel layer 30, the gallium nitride layer 32 can be directly fabricated on the substrate 10 using etching or ion implantation. The aluminum gallium nitride barrier layer 31 is disposed on the surface of the gallium nitride layer 32 facing away from the substrate 10, and can also be fabricated using the aforementioned etching or ion implantation processes.

[0043] In addition to the structure described above, the channel layer 30 can also adopt other structures, such as a three-layer structure comprising a gallium nitride layer, an aluminum gallium nitride barrier layer, and an aluminum nitride layer located between the gallium nitride layer and the aluminum gallium nitride barrier layer. A channel can also be formed using a three-layer structure.

[0044] The source-drain layer is the functional layer of the hybrid gate field-effect transistor, comprising a source 40, a drain 50, and a gate structure layer 60. For example... Figure 1 As shown, the source 40, gate structure layer 60, and drain 50 are disposed on the same layer of the channel layer 30 and electrically connected to the channel layer 30. The source 40 and drain 50 are used to connect to external circuits, and the gate structure layer 60 is used to control the opening and closing of the channel. When the gate structure layer 60 controls the channel to be on, the hybrid gate field-effect transistor is in a closed state, and the circuit connected to the source 40 and drain 50 is conductive; when the gate structure layer 60 controls the channel to be off, the hybrid gate field-effect transistor is in an off state, and the circuit connected to the source 40 and drain 50 is disconnected.

[0045] The gate structure layer 60, source 40, and drain 50 are connected to the aluminum gallium nitride (AGaN) barrier layer 31, and the source 40 and drain 50 are connected to the channel through the AGaN barrier layer 31. The gate structure layer 60 is connected to the channel through the AGaN barrier layer 31 and can absorb electrons located in the channel. When the gate structure layer 60 controls the channel to conduct, electrons are located in the channel, and the source 40 and drain 50 can conduct through the electrons in the channel; when the gate structure layer 60 controls the channel to disconnect, electrons are absorbed by the gate structure layer 60, there are no free electrons in the channel, and the source 40 and drain 50 are disconnected.

[0046] In the specific configuration of the source 40, drain 50, and gate structure layer 60, the gate structure layer 60 is located between the source 40 and drain 50, separating the source 40 and drain 50. It should be understood that, in the specific configuration of the gate structure layer 60, drain 50, and source 40, there is a gap between the gate structure layer 60 and the source 40 and drain 50 to ensure electrical isolation between the gate structure layer 60, source 40, and drain 50.

[0047] The gate structure layer 60 provided in this embodiment adopts a hybrid gate structure, which is composed of two materials. Exemplarily, the gate structure layer 60 includes a first structure layer 62 and a second structure layer 61. The first structure layer 62 and the second structure layer 61 are disposed in the same layer and are respectively connected to the channel layer 30. In this embodiment, the first structure layer 62 and the second structure layer 61 are made of different materials. The first structure layer 62 is an N-type gallium nitride layer or an intrinsic gallium nitride layer, and the second structure layer 61 is a P-type gallium nitride layer. Therefore, the materials constituting the hybrid gate structure can be: P-type gallium nitride + N-type gallium nitride; or P-type gallium nitride + intrinsic gallium nitride. In specific fabrication, any combination can be selected as needed to fabricate the hybrid gate structure.

[0048] The hybrid gate field-effect transistor also includes a gate metal layer 70, which is used to connect to the gate structure layer 60 and to apply a control voltage to the gate structure layer 60 to control the opening and closing of the channel.

[0049] Continue to refer to Figure 1 A gate metal layer 70 is stacked on top of a gate structure layer 60 and is located on the surface of the gate structure layer 60 facing away from the channel layer 30. For ease of description, the surface of the gate structure layer 60 facing away from the channel layer 30 is referred to as the top surface of the gate structure layer 60. On the top surface of the gate structure layer 60, the first structural layer 62 is exposed outside the second structural layer 61; that is, the top surface of the gate structure layer 60 is composed of the surfaces of the first structural layer 62 and the second structural layer 61. When the gate structure layer 60 is connected to the gate metal layer, the top surface of the gate structure layer 60 is the surface where the gate structure layer 60 and the gate metal layer 70 are connected. When connected to the gate structure layer 60, the gate metal layer 70 is at least in ohmic contact with the first structural layer 62. The gate metal layer 70 can be made of common conductive metals such as copper and aluminum. When the first structural layer 62 uses an N-type gallium nitride layer or an intrinsic gallium nitride layer, the gate metal layer 70 can directly make ohmic contact with the semiconductor material such as the N-type gallium nitride layer or the intrinsic gallium nitride layer. An ohmic contact between a metal and a semiconductor means that there is a pure resistance at the contact point, and the smaller the resistance, the better. This ensures that during device operation, most of the voltage is applied to the active region rather than the contact surface. Furthermore, ohmic contacts do not suffer from long-term hot electron bombardment, resulting in higher reliability. By using an ohmic contact between the gate metal layer 70 and the gate structural layer 60, the reliability of the connection between the gate metal layer 70 and the gate structural layer 60 is improved, thereby enhancing the reliability of the hybrid gate field-effect transistor.

[0050] The aforementioned gate metal layer 70 is connected to the first structural layer 62 via an ohmic contact, including but not limited to the following two specific connection methods:

[0051] 1) The gate metal layer 70 is in ohmic contact only with the first structural layer 62. The ohmic contact between the gate metal layer 70 and the first structural layer 62 allows the current from the gate metal layer 70 to be applied more effectively to the first structural layer 62.

[0052] 2) The gate metal layer 70 is in ohmic contact with the first structural layer 62, and the gate metal layer 70 is in Schottky contact with the second structural layer 61. The gate metal layer 70 is connected to the first structural layer 62 and the second structural layer 61 of the gate structural layer 60 through two different connection methods. Although the gate metal layer 70 is electrically connected to the first structural layer 62 and the second structural layer 61 through different contact methods, the voltage is still applied to the gate structural layer 60 through the ohmic contact due to the higher resistance of the Schottky contact.

[0053] The hybrid gate field-effect transistor also includes a passivation layer 80, which protects the various functional layers within the transistor. During installation, the passivation layer 80 is stacked with the aluminum gallium nitride barrier layer 31. It should be understood that, to ensure the source 40, drain 50, and gate structure layer 60 can be connected to external circuits and control circuits, the source 40, drain 50, and gate structure layer 60 pass through the passivation layer 80 and are exposed outside of it. The exposed portions of the source 40, drain 50, and gate structure layer 60 can be used for connection to external circuits and control circuits.

[0054] As an alternative, the passivation layer 80 can be made of silicon nitride, aluminum oxide, silicon oxynitride, or other common materials.

[0055] It should be understood that the passivation layer 80 is an optional structural layer for hybrid gate field-effect transistors. When the application environment of the hybrid gate field-effect transistor is relatively safe, the passivation layer 80 may not be required.

[0056] Specifically, in fabricating the first structural layer 62 and the second structural layer 61, the first structural layer 62 is located in the middle of the gate structural layer 60, and the second structural layer 61 is located on the periphery of the gate structural layer 60, and the second structural layer 61 encloses the first structural layer 62. However, the first structural layer 62 can be selected from different shapes and structures. The specific structural forms of the first structural layer 62 and the second structural layer 61 will be described below with reference to the accompanying drawings.

[0057] refer to Figure 2 , Figure 2 A top view of the gate structure layer is shown. A second structural layer 61 surrounds a first structural layer 62, with the first structural layer 62 located in the middle of the gate structure layer 60 and the second structural layer 61 located around the gate structure layer 60. There are two first structural layers 62, each of which is rectangular. When two first structural layers 62 are specifically arranged, they are spaced apart, and each first structural layer 62 is surrounded by a second structural layer 61.

[0058] refer to Figure 3 , Figure 3 A top view of another gate structure layer is shown. A second structure layer 61 surrounds a first structure layer 62, with the first structure layer 62 located in the middle of the gate structure layer 60 and the second structure layer 61 located around the periphery of the gate structure layer 60. There are two first structure layers 62, each of which is circular. When two first structure layers 62 are specifically arranged, they are spaced apart, and each first structure layer 62 is surrounded by a second structure layer 61.

[0059] refer to Figure 4 , Figure 4A top view of another gate structure layer 60 is shown. A second structure layer 61 surrounds a first structure layer 62, with the first structure layer 62 located in the middle of the gate structure layer 60 and the second structure layer 61 located on the periphery of the gate structure layer 60. There are two first structure layers 62, one circular and the other rectangular. In the specific arrangement of the two first structure layers 62, they are spaced apart, with each first structure layer 62 surrounded by a second structure layer 61.

[0060] Depend on Figure 2 , Figure 3 and Figure 4 It can be seen that the first structural layer 62 provided in this application embodiment can adopt a columnar structure with a cross-section of different shapes. Figure 2 , Figure 3 and Figure 4 The examples only illustrate a few specific cross-sectional shapes of the first structural layer 62. Other cross-sectional shapes of the first structural layer 62 provided in this application embodiment may also be selected, and no specific limitation is made here.

[0061] It should be understood that, in the embodiments of this application, the number of the first structural layers 62 is not limited, and can be adopted in various ways, such as... Figure 2 , Figure 3 or Figure 4 In addition to the two first structural layers 62 shown, different numbers of first structural layers 62, such as one, three, or four, can also be used. The specific number of first structural layers 62 can be set as needed.

[0062] Furthermore, when multiple first structural layers 62 are used, the arrangement of the first structural layers 62 is not specifically limited in this embodiment. The first structural layers 62 can be arranged in different ways, such as single row, array, triangular, X-shaped, or circular arrangements. It is only necessary to ensure that ohmic contact can be achieved with the gate metal layer 70.

[0063] As an optional solution, the cross-sectional area of ​​the first structural layer 62 accounts for between 5% and 50% of the cross-sectional area of ​​the gate structure 60. For example, the cross-sectional area of ​​the first structural layer 62 can be any percentage of the cross-sectional area of ​​the gate structure 60, such as 5%, 10%, 15%, 25%, 30%, 35%, or 50%. It should be understood that when there are multiple first structural layers 62, the cross-sectional area of ​​the first structural layer 62 refers to the sum of the cross-sectional areas of all the first structural layers 62.

[0064] As can be seen from the above description, the hybrid gate field-effect transistor provided in this application uses a first structural layer 62 and a second structural layer 61 to form the gate structure layer 60 of the hybrid gate field-effect transistor, so that the gate metal layer 70 can be connected to the gate structure layer 60 through an ohmic contact with relatively low resistance, thereby improving the reliability of the hybrid gate field-effect transistor.

[0065] To facilitate understanding of the hybrid gate field-effect transistor provided in the embodiments of this application, its fabrication method is described in detail below with reference to the accompanying drawings. In the embodiments of this application, the hybrid gate field-effect transistor can be fabricated using different methods, which will be described one by one below.

[0066] First refer to Figures 5a to 5g , Figures 5a to 5g A specific method for fabricating a hybrid gate field-effect transistor is shown. The method includes the following steps:

[0067] Step 001: Form an etched layer on the channel layer.

[0068] refer to Figure 5a The substrate 10, buffer layer 20, gallium nitride layer 32, and aluminum gallium nitride barrier layer 31 are stacked together through epitaxial growth, deposition, and other processes. When forming the etching layer 100 on the aluminum gallium nitride barrier layer 31, it can be formed directly on the aluminum gallium nitride barrier layer 31 by means of coating or deposition. It should be understood that the thickness of the etching layer 100 should not be less than the thickness of the gate structure layer 60.

[0069] Step 002: Etch an annular hole in the etching layer.

[0070] refer to Figure 5b An annular hole 101 is formed in the etched layer 100 through an etching process, and the annular hole 101 penetrates the etched layer 100, exposing the aluminum gallium nitride barrier layer 31 in the annular hole 101. The shape of the annular hole 101 matches the shape of the second structural layer 61 and is used to form the second structural layer 61 in the annular hole 101. In addition, the solid structure (the remaining etched layer 100) within the annular hole 101 matches the shape of the first structural layer 62, so as to leave space for the first structural layer 62 when the second structural layer 61 is formed.

[0071] Step 003: Form a second structural layer inside the annular hole.

[0072] refer to Figure 5c A second structural layer 61 is formed within the annular hole 101 through epitaxial growth and deposition. The formed second structural layer 61 is in contact with the aluminum gallium nitride barrier layer 31.

[0073] Step 004: Etch through holes in the etching layer.

[0074] refer to Figure 5dThe etching layer 100 surrounding the second structural layer 61 is etched away, leaving only the etching layer within the second structural layer 61. (Reference) Figure 5e A new etched layer 200 is formed, which covers the second structural layer 61 and the remaining structure of the original etched layer 200. A via 201 is etched within the newly formed etched layer 200. The via 201 is located in the second structural layer 61, and the inner sidewall of the second structural layer 61 serves as the sidewall of the via 201, while the top surface of the aluminum gallium nitride barrier layer 31 serves as the bottom wall of the via 201.

[0075] Step 005: Form the first structural layer inside the through hole.

[0076] refer to Figure 5f A first structural layer 62 is formed within the via by epitaxial growth or deposition. The first structural layer 62 is in contact with the second structural layer 61 and the aluminum gallium nitride barrier layer 31.

[0077] Furthermore, during the formation of the first structural layer 62, since the newly formed etched layer covers the second structural layer 61, the formed first structural layer 62 will not cover the second structural layer 61. After fabrication, the first structural layer 62 and the second structural layer 61 are disposed in the same layer, and the second structural layer 61 encapsulates the first structural layer 62.

[0078] After the first structural layer 62 is formed, the remaining part of the etched layer is etched away, so that the gate structural layer 60 composed of the first structural layer 62 and the second structural layer 61 is exposed.

[0079] Step 006: Form other layered structures on the channel layer.

[0080] refer to Figure 5g Source 40 and drain 50 are formed on the channel layer 30. Specifically, source 40 and drain 50 can be formed on the aluminum gallium nitride barrier layer 31 by deposition or epitaxial growth.

[0081] First, a passivation layer 80 is prepared, and then the passivation layer 80 is etched to form vias corresponding to the source 40, drain 50, and gate metal layer 70. The gate metal layer 70, source 40, and drain 50 are formed within these vias, respectively. The formed gate metal layer 70 is in ohmic contact with the first structural layer 62 and in Schottky contact with the second structural layer 61.

[0082] As can be seen from the above fabrication process, the gate structure layer 60 can be formed by etching and deposition. In addition, by using the first structure layer 62 and the second structure layer 61 to form the gate structure layer 60 of the hybrid gate field effect transistor, the gate metal layer 70 can be connected to the gate structure layer 60 through an ohmic contact with relatively low resistance, thereby improving the reliability of the hybrid gate field effect transistor.

[0083] refer to Figures 6a to 6g, Figures 6a to 6g Another specific method for fabricating a hybrid gate field-effect transistor is shown. This method includes the following steps:

[0084] Step 001: Form an etched layer on the channel layer.

[0085] refer to Figure 6a The substrate 10, buffer layer 20, gallium nitride layer 32, and aluminum gallium nitride barrier layer 31 are stacked together through epitaxial growth, deposition, and other processes. When forming the etching layer 100 on the aluminum gallium nitride barrier layer 31, it can be formed directly on the aluminum gallium nitride barrier layer 31 by means of coating or deposition. It should be understood that the thickness of the etching layer 100 should not be less than the thickness of the gate structure layer 60.

[0086] Step 002: Etch through holes in the etching layer.

[0087] refer to Figure 6b An etching process is used to form a via 103 in the etched layer 100. The via 103 penetrates the etched layer 100, exposing the aluminum gallium nitride barrier layer 31 in the via 103. The shape of the via 103 matches the shape of the first structural layer 62 and is used to form the first structural layer 62 in the via 103.

[0088] Step 003: Form the first structural layer inside the through hole.

[0089] refer to Figure 6c A first structural layer 62 is formed within the via 103 by epitaxial growth and deposition. The formed first structural layer 62 is in contact with the aluminum gallium nitride barrier layer 31.

[0090] Step 004: Etch annular holes in the etching layer.

[0091] refer to Figure 6d The etched layer 100 around the first structural layer 62 is etched away to form an annular hole 104. The outer wall of the first structural layer 62 is exposed in the annular hole 104 so that the second structural layer 61, which is subsequently prepared, can contact the first structural layer 62.

[0092] Step 005: Form a second structural layer inside the annular hole.

[0093] refer to Figure 6e A second structural layer 61 is formed within the annular hole 104 by epitaxial growth or deposition. The second structural layer 61 is in contact with the first structural layer 62 and the aluminum gallium nitride barrier layer 31.

[0094] refer to Figure 6f After the second structural layer 61 is formed, the remaining part of the etched layer 100 is etched away, so that the gate structural layer 60 composed of the first structural layer 62 and the second structural layer 61 is exposed.

[0095] Step 006: Form other layered structures on the channel layer.

[0096] refer to Figure 6g Source 40 and drain 50 are formed on the channel layer 30. Specifically, source 40 and drain 50 can be formed on the aluminum gallium nitride barrier layer 31 by deposition or epitaxial growth.

[0097] First, a passivation layer 80 is prepared. The passivation layer 80 is then etched to form vias 103 corresponding to the source 40, drain 50, and gate metal layer 70. The gate metal layer 70, source 40, and drain 50 are formed within the vias 103, respectively. The formed gate metal layer 70 is in ohmic contact with the first structural layer 62 and in Schottky contact with the second structural layer 61.

[0098] As can be seen from the above fabrication process, the gate structure layer 60 can be formed by etching and deposition. In addition, by using the first structure layer 62 and the second structure layer 61 to form the gate structure layer 60 of the hybrid gate field effect transistor, the gate metal layer 70 can be connected to the gate structure layer 60 through an ohmic contact with relatively low resistance, thereby improving the reliability of the hybrid gate field effect transistor.

[0099] refer to Figures 7a to 7d , Figures 7a to 7d Another specific method for fabricating a hybrid gate field-effect transistor is shown. This method includes the following steps:

[0100] Step 001: Form a material layer on the channel layer that is the same material as the second structural layer.

[0101] refer to Figure 7a The substrate 10, buffer layer 20, gallium nitride layer 32, and aluminum gallium nitride barrier layer 31 are stacked together through epitaxial growth, deposition, and other processes. When forming the material layer 300 in the aluminum gallium nitride barrier layer 31, it can be formed directly on the aluminum gallium nitride barrier layer 31 using methods such as epitaxial growth or deposition. It should be understood that the thickness of the material layer 300 should not be less than the thickness of the gate structure layer 60.

[0102] Step 002: Etch the material layer to form the second structural layer.

[0103] refer to Figure 7b A second structural layer 61 of the same size as the gate structure layer 60 is formed by etching the material layer 300.

[0104] Step 003: Form the first structural layer by ion implantation.

[0105] refer to Figure 7cThe first structural layer 62 is formed by ion implantation of inverted ions into the second structural layer 61. The portion of the second structural layer 61 implanted with inverted ions serves as the first structural layer 62, while the portion not implanted with inverted ions serves as the second structural layer 61 of the gate structural layer 60. The second structural layer 61 encloses the first structural layer 62, and the shape of the first structural layer 62 can be referenced. Figures 2-4 The relevant description in the document.

[0106] Step 004: Form other layered structures on the channel layer.

[0107] refer to Figure 7d Source 40 and drain 50 are formed on the channel layer 30. Specifically, source 40 and drain 50 can be formed on the aluminum gallium nitride barrier layer 31 by deposition or epitaxial growth.

[0108] First, a passivation layer 80 is prepared, and then the passivation layer 80 is etched to form vias corresponding to the source 40, drain 50, and gate metal layer 70. The gate metal layer 70, source 40, and drain 50 are formed within these vias, respectively. The formed gate metal layer 70 is in ohmic contact with the first structural layer 62 and in Schottky contact with the second structural layer 61.

[0109] As can be seen from the above fabrication process, the gate structure layer 60 can be formed by ion implantation. In addition, by using the first structure layer 62 and the second structure layer 61 to form the gate structure layer 60 of the hybrid gate field-effect transistor, the gate metal layer 70 can be connected to the gate structure layer 60 through an ohmic contact with relatively low resistance, thereby improving the reliability of the hybrid gate field-effect transistor.

[0110] refer to Figures 8a to 8d , Figures 8a to 8d Another specific method for fabricating a hybrid gate field-effect transistor is shown. This method includes the following steps:

[0111] Step 001: Form a material layer on the channel layer that is the same material as the first structural layer.

[0112] refer to Figure 8a The substrate 10, buffer layer 20, gallium nitride layer 32, and aluminum gallium nitride barrier layer 31 are stacked together through epitaxial growth, deposition, and other processes. When forming the material layer 400 in the aluminum gallium nitride barrier layer 31, it can be directly formed on the aluminum gallium nitride barrier layer 31 using methods such as epitaxial growth or deposition. It should be understood that the thickness of the material layer 400 should not be less than the thickness of the gate structure layer 60.

[0113] Step 002: Etch the material layer to form the first structural layer.

[0114] refer to Figure 8b A first structural layer 62 of the same size as the gate structure layer 60 is formed by etching the material layer 400.

[0115] Step 003: Form the second structural layer by ion implantation.

[0116] refer to Figure 8c The second structural layer 61 is formed by ion implantation of inverted ions into the first structural layer 62. The portion of the first structural layer 62 implanted with inverted ions serves as the second structural layer 61, while the portion not implanted with inverted ions serves as the first structural layer 62 of the gate structural layer 60. The second structural layer 61 encloses the first structural layer 62, and the shape of the first structural layer 62 can be referenced. Figures 2-4 The relevant description in the document.

[0117] Step 004: Form other layered structures on the channel layer.

[0118] refer to Figure 8d Source 40 and drain 50 are formed on the channel layer 30. Specifically, source 40 and drain 50 can be formed on the aluminum gallium nitride barrier layer 31 by deposition or epitaxial growth.

[0119] First, a passivation layer 80 is prepared, and then the passivation layer 80 is etched to form vias corresponding to the source 40, drain 50, and gate metal layer 70. The gate metal layer 70, source 40, and drain 50 are formed within these vias, respectively. The formed gate metal layer 70 is in ohmic contact with the first structural layer 62 and in Schottky contact with the second structural layer 61.

[0120] As can be seen from the above fabrication process, the gate structure layer 60 can be formed by ion implantation. In addition, by using the first structure layer 62 and the second structure layer 61 to form the gate structure layer 60 of the hybrid gate field-effect transistor, the gate metal layer 70 can be connected to the gate structure layer 60 through an ohmic contact with relatively low resistance, thereby improving the reliability of the hybrid gate field-effect transistor.

[0121] As can be seen from the above description, the hybrid gate field-effect transistor provided in this application embodiment can be fabricated in different ways, and the hybrid gate field-effect transistor formed by using a first structural layer 62 and a second structural layer 61 to form the gate structure layer 60 of the hybrid gate field-effect transistor allows the gate metal layer 70 to be connected to the gate structure layer 60 through an ohmic contact with relatively low resistance, thereby improving the reliability of the hybrid gate field-effect transistor.

[0122] This application embodiment also provides a switching circuit, which can be a switching circuit in an AC-DC conversion circuit, a high-voltage conversion circuit, or a half-bridge rectifier circuit. The switching circuit includes a motherboard and a hybrid gate field-effect transistor disposed on the motherboard according to any of the above-mentioned methods. As can be seen from the above description, by adopting a hybrid gate structure in the gate structure layer 60, the gate structure layer 60 is made of two different materials, and the material located in the middle of the hybrid gate can achieve ohmic contact with the gate metal layer 70, thereby improving the reliability of the connection between the gate metal layer 70 and the gate structure layer 60, and thus improving the reliability of the hybrid gate field-effect transistor.

[0123] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A hybrid gate field-effect transistor, characterized in that, include: A channel layer, and source, drain, and gate structures stacked on top of the channel layer; wherein the source, drain, and gate structures are disposed in the same layer; The gate structure includes a first structural layer and a second structural layer disposed in the same layer, wherein the second structural layer encapsulates the first structural layer; wherein the first structural layer is an N-type gallium nitride layer or an intrinsic gallium nitride layer; and the second structural layer is a P-type gallium nitride layer; The hybrid gate field-effect transistor further includes a gate metal layer, which is in ohmic contact with the first structural layer and in Schottky contact with the second structural layer; It also includes a passivation layer, through which the source, drain and gate structures pass and are exposed outside the passivation layer.

2. The hybrid gate field-effect transistor as described in claim 1, characterized in that, The channel layer comprises stacked gallium nitride layers and aluminum gallium nitride barrier layers; The source, drain, and gate structures are disposed on the surface of the aluminum gallium nitride barrier layer.

3. The hybrid gate field-effect transistor as described in claim 2, characterized in that, It also includes a substrate and a buffer layer disposed on the substrate; The gallium nitride layer is formed in the buffer layer.

4. The hybrid gate field-effect transistor as described in claim 3, characterized in that, The substrate is made of silicon, sapphire, silicon carbide, or gallium nitride bulk material.

5. The hybrid gate field-effect transistor as described in claim 2, characterized in that, The passivation layer is stacked with the aluminum gallium nitride barrier layer.

6. The hybrid gate field-effect transistor as described in claim 1, characterized in that, The first structural layer is a circular column, a square column, or an elliptical column.

7. A method for fabricating a hybrid gate field-effect transistor, characterized in that, The method includes the following steps: A passivation layer is formed on the channel layer; A first structural layer and a second structural layer are formed in the passivation layer; wherein the first structural layer and the second structural layer are disposed in the same layer, and the second structural layer encapsulates the first structural layer; the first structural layer and the second structural layer constitute a gate structure; the first structural layer is an N-type gallium nitride layer or an intrinsic gallium nitride layer, and the second structural layer is a P-type gallium nitride layer; A source and a drain are formed in the passivation layer; the source, drain, and gate structures pass through the passivation layer and are exposed outside the passivation layer. A gate metal layer is formed; the gate metal layer is in ohmic contact with the first structural layer and in Schottky contact with the second structural layer.

8. The preparation method according to claim 7, characterized in that, The formation of the first structural layer and the second structural layer on the channel layer specifically refers to: An etched layer is formed on the channel layer; An annular hole is etched in the etching layer; A second structural layer is formed within the annular hole; A through-hole is etched in the etching layer, and the inner sidewall of the second structural layer is the sidewall of the through-hole; A first structural layer is formed within the through hole, and a second structural layer encapsulates the first structural layer; The remaining portion of the etched layer is etched away.

9. The preparation method according to claim 7, characterized in that, The formation of the first structural layer and the second structural layer on the channel layer specifically refers to: An etched layer is formed on the channel layer; Etch through-holes in the etching layer; A first structural layer is formed within the through-hole; An annular hole is etched in the etching layer, and the outer wall of the first structural layer is exposed in the annular hole; A second structural layer is formed inside the annular hole, and the second structural layer wraps around the first structural layer; The remaining portion of the etched layer is etched away.

10. The preparation method according to claim 7, characterized in that, The formation of the first structural layer and the second structural layer on the channel layer specifically refers to: A material layer of the same material as the first structural layer is formed on the channel layer; The material layer is etched to form the first structural layer; The second structural layer is formed by ion implantation, and the second structural layer encapsulates the first structural layer.

11. The preparation method according to claim 7, characterized in that, The formation of the first structural layer and the second structural layer on the channel layer specifically refers to: A material layer of the same material as the second structural layer is formed on the channel layer; The material layer is etched to form the second structural layer; The first structural layer is formed by ion implantation, and the second structural layer encapsulates the first structural layer.

12. The preparation method according to any one of claims 7 to 11, characterized in that, Also includes: A buffer layer is formed on the substrate; The channel layer is formed in the buffer layer.

13. A switching circuit, characterized in that, It includes a motherboard and a hybrid gate field-effect transistor as described in any one of claims 1 to 6 disposed on the motherboard.

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