Charge control clamper for mems readout circuit

Abstract

Various embodiments of this disclosure relate to charge control clamps for MEMS readout circuits. One device includes readout circuitry coupled between an input node and an output node; a microelectromechanical system (MEMS) device coupled to the input node; and a first charge control clamping circuitry coupled between the input node and a first bias node.

Description

Technical Field

[0001] The present invention generally relates to a charge control clamp for microelectromechanical systems (MEMS) circuits, and in a particular embodiment relates to a corresponding method. Background Technology

[0002] The DC operating point of the readout amplifier in a capacitive MEMS device (i.e., a capacitive MEMS microphone) shifts after an overload condition. Because the input bias typically has a very low roll-off frequency (in the range of a few hertz or tens of hertz for acoustic applications), the disturbed DC operating point can take up to several seconds to recover. During the settling-off period, system performance is severely affected, including impaired sensitivity, increased noise, and increased distortion. Summary of the Invention

[0003] According to an embodiment of the present invention, a device includes: a readout circuit coupled between an input node and an output node; a microelectromechanical system (MEMS) device coupled to the input node; and a first charge control clamping circuit coupled between the input node and a first bias node.

[0004] According to another embodiment of the present invention, a clamping circuit includes: a first charge control clamp coupled between an input node and a first bias node, the first charge control clamp being configured to store a first charge associated with the input node during a first voltage clamping mode and to return the first charge to the input node after the first voltage clamping mode; and a second charge control clamp coupled between the input node and a second bias node, the second charge control clamp being configured to store a second charge associated with the input node during a second voltage clamping mode and to return the second charge to the input node after the second voltage clamping mode.

[0005] According to another embodiment of the present invention, a method of operating a microelectromechanical system (MEMS) device includes: clamping a node of the MEMS device to a first voltage during a first overload operation mode; storing a first charge associated with a node of the MEMS device during the first overload operation mode; and returning the first charge to a node of the MEMS device after the first overload operation mode.

[0006] According to another embodiment of the present invention, a circuit includes: a first capacitor; a first transistor having a load path coupled between the first capacitor and a clamping node; and a first amplifier having a negative input coupled to the clamping node, a positive input coupled to a first clamping voltage reference node, and an output coupled to a control node of the first transistor. Attached Figure Description

[0007] To gain a more complete understanding of the invention and its advantages, the following description is now taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a circuit diagram of an exemplary capacitive MEMS readout front end;

[0009] Figure 2A This is a circuit diagram of a charge control clamping circuit for a MEMS readout front end according to an embodiment;

[0010] Figure 2B It is a comparison Figure 1 circuit and Figure 2A Timing diagram of the circuit response;

[0011] Figure 3 This is a circuit diagram of an embodiment of a charge-controlled clamp;

[0012] Figure 4 This is a circuit diagram of an embodiment of a charge-controlled clamper including a single transistor regulating switch;

[0013] Figure 5 This is a circuit diagram of an embodiment of a charge control clamp including a first transistor regulating switch and a second transistor regulating switch;

[0014] Figure 6 This is a circuit diagram of an embodiment of a charge control clamp including a first regulating switch, a second regulating switch, and a Schmitt trigger circuit for controlling the operation of the second regulating switch;

[0015] Figure 7 Is with Figure 6 Timing diagrams related to the charge control clamp; and

[0016] Figure 8 This is a circuit diagram of a charge control clamp that includes a first transistor and a second transistor. Detailed Implementation

[0017] Embodiments of the present invention relate to circuitry and methods for rapidly restoring the DC operating point of a capacitive MEMS device after an overload condition has ended. In embodiments, the DC operating point recovers substantially immediately after an AC or DC overload condition has ended. Therefore, system performance is improved by minimizing settling time, increasing sensitivity, reducing noise, and reducing distortion. In one embodiment of the invention, a method of operating a MEMS device includes: clamping a node of the MEMS device to a first voltage during a first overload operating mode; storing a first charge associated with a node of the MEMS device during the first overload operating mode; and returning the first charge to the node of the MEMS device after the first overload operating mode. In other embodiments, circuitry for restoring the DC operating point of a capacitive MEMS device after an overload condition includes one or more charge control clamping circuits and associated circuitry, which are described in detail below.

[0018] Figure 1 The components of an exemplary MEMS readout circuit 100 are shown, including a capacitive MEMS device 102 coupled between a bias node 110 designated as “Vbias_mems” and a circuit node 112, an electrostatic discharge (ESD) protection circuit 104 coupled to the circuit node 112, a high-value bias resistor (Rbias) 106 coupled between a bias node 114 designated as “Vbias_asic” and the circuit node 112, and a readout amplifier (AMP) 108 having an input coupled to the circuit node 112.

[0019] The bias resistor 106 and the ESD protection circuit 104 can be implemented using one or more diodes or diode-connected transistors that can be implemented in different ways. Furthermore, at least the bias resistor 106 can be implemented using an actual resistor made of a high-resistivity material. Under high signal levels or overload conditions, the bias resistor 106 may begin to leak, and thus the capacitors of the MEMS device 102 will lose charge. For extremely high signal overload conditions, the clamping circuitry in the ESD protection circuit 104 may also cause additional charge loss. This additional charge loss can be significant, causing a DC offset at circuit node 112 and requiring a long stabilization time to recover.

[0020] A high signal level under overload conditions will cause a corresponding high-level AC or DC voltage to appear at the output of the capacitive MEMS device 102 (without clamping). This high-level AC or DC voltage will charge the capacitor of the MEMS device 102 coupled to circuit node 112. If the high-level AC or DC voltage is clamped, the charge associated with the voltage difference between the peak high-level voltage and the clamping voltage will be lost to ground or to the bias voltage associated with the clamping circuitry. The lost charge will correspondingly cause a DC voltage offset at circuit node 112, which in Figure 2B The waveform in 904 is best seen at 20ms. Figure 2B As shown, the DC offset on circuit node 112 can persist for a long time, but remains unresolved after 50ms. Once the capacitor inside the capacitive MEMS device 102 is recharged to replace the expired lost charge through circuit components such as the ESD protection circuit 104 coupled to circuit node 112, the DC offset on the circuit node eventually recovers to the original DC operating point after a long period of time. Figure 2B A solution for DC voltage offset according to an embodiment of the present invention is proposed and described in further detail below.

[0021] The DC operating point offset of the readout circuit 100 can be prevented by storing the charge lost at circuit node 112 during clamping and returning the stored charge to circuit node 112 after clamping. A charge-controlled clamping circuit using one or more charge-controlled clampers according to an embodiment can be used to voltage-clamp circuit node 112 to store the charge lost at circuit node 112 during clamping and return the stored charge to the circuit node after clamping. According to one embodiment, the charge-controlled clamping circuit for a MEMS readout front end... Figure 2A It is shown in the figure and described in detail below.

[0022] Figure 2A This is a circuit diagram of a charge control clamping circuit for a MEMS readout circuit 200 according to an embodiment. According to one embodiment, the MEMS readout circuit 200 includes a MEMS device 102, a bias resistor 106, and a readout amplifier 108, as previously described in... Figure 1As described, the ESD protection circuit 104 has been removed, and charge control clamps 116 and 118 have been added. Charge control clamp 116 is coupled between a bias node 120, designated as "Vbias_asic + V_threshold", and circuit node 112. Charge control clamp 118 is coupled between a second bias node 122, designated as "Vbias_asic - V_threshold", and circuit node 112. Circuit node 112 is the output node of MEMS device 102, but also the input node of the sense amplifier 108, charge control clamp 116, and charge control clamp 118. Embodiments of charge control clamps 116 and 118 are described in detail below.

[0023] MEMS device 102 may include a microphone, but other types of MEMS devices may also be used. If the input of the MEMS device is exposed to a high-level sound source, resulting in a large AC voltage at circuit node 112, an overload condition may occur at circuit node 112. Once the high-level sound source is turned off, the large AC voltage at the circuit node returns to normal levels as the overload condition is removed. If the input of the MEMS device is exposed to environmental hazards such as dust or other environmental factors, causing a large AC or DC voltage at circuit node 112, an overload condition may also occur at circuit node 112. Once the environmental exposure ends or is resolved, the large AC or DC voltage at the circuit node returns to normal levels as the overload condition is removed.

[0024] In the readout circuit 200, after the overload condition is removed, the DC operating point will recover immediately (within milliseconds) because the charge associated with the overload condition stored in charge control clamps 116 and 118 is immediately and completely restored to circuit node 112. Therefore, normal operation can be restored with very little or virtually no settling time.

[0025] Figure 2B This is timing diagram 900, which compares the use of conventional ESD clamps. Figure 1 The circuit and the use of the charge control clamp according to the embodiment Figure 2AThe waveform 902 represents the input signal of the charge control clamping circuit at circuit node 112, which is also the output of MEMS device 102. Waveform 902 includes an AC overload condition occurring between 10 ms and 20 ms, extending between -4.5 V and +4.5 V (unclamped). Waveform 904 represents the response (Vinp) of readout circuit 100 at circuit node 112. Using a conventional ESD clamping circuit, the overload condition is clamped between -0.8 V and 2.4 V from 10 ms to 20 ms, but the DC operating point has been lowered and does not recover between 20 ms and 50 ms after the overload condition is removed. Waveform 906 represents the response (Vinp) of readout circuit 200 at circuit node 112. Using the charge control clamps 118 and 116 described herein, the voltage at circuit node 112 is clamped between -0.7 volts (negative peak for AC overload) and 1.5 volts (positive peak for AC overload) from 10 ms to 20 ms; however, the DC operating point does not decrease and recovers almost immediately to the original DC operating point.

[0026] Figure 3 Is with Figure 2A A schematic diagram of an embodiment of charge control clamp 116A corresponding to the charge control clamp 116 shown. Figure 3 It can also be used as Figure 2A The schematic diagram of charge-controlled clamp 118 shown differs in that the bias voltage is changed to "Vbias-0.8V". Circuit node 112 is designated as "vinp" as the input node of the sense amplifier and is associated with the positive clamp voltage. Charge-controlled clamp 116A here includes an adjustment switch 311 and an integrator 315 for charge storage. The adjustment switch 311 includes an operational amplifier 302, which has a positive input coupled to circuit node 112 and is coupled to the positive input of the sense amplifier. Figure 3 In this embodiment, the negative input of bias node 120 is designated as "Vbias+0.8V". Integrator 315 includes operational amplifier 304, which has a positive input coupled to bias node 120. Capacitor 306 is coupled between the negative input and output of operational amplifier 304.

[0027] During operation, switch 308A is initially open. When the VNP voltage is higher than Vbias + 0.8V, the charge from circuit node 112 (in...) Figure 3The voltage (designated as "vinp" as the input voltage of charge control clamp 116A) is stored on capacitor 306, and the charge flows through closed switch 308A. When the overload condition is removed and the input voltage vimp begins to drop, the charge returns to circuit node 112 through closed switch 308A. When the voltage vimp at circuit node 112 returns to its initial voltage, switch 308A opens.

[0028] For example, if Vbias equals 0.2V, the voltage at circuit node 112 will be less than 1 volt before the overload condition, causing switch 308A to open (turn off). This is because the positive input of operational amplifier 302 is less than its negative input, and the output of the operational amplifier will be forced to a low voltage applied to the control terminal of switch 308A, thus turning off the switch. During the overload condition, the AC voltage at circuit node 112 will have peaks tending to be greater than 1 volt, but these peaks will be clamped at or near a 1-volt clamping voltage. Since the positive input of operational amplifier 302 is greater than its negative input, switch 308A will close (turn on) during these peaks, and the output of the operational amplifier will be forced to a high voltage applied to the control terminal of switch 308A, thus turning on the switch. Integrator 315 is used to store all the charge flowing through switch 308A into capacitor 306. In the integrator configuration, integrator 315 has a positive input coupled to bias node 120, a negative input that will also bear a voltage (1 volt in this case) on the positive input, and an output that will bear the necessary voltage to regulate the amount of charge flowing into capacitor 306. As the AC voltage at node 112 continues to rise above the clamping voltage (1 volt in this case), charge will be continuously stored in capacitor 306. As the AC voltage at node 112 begins to drop to the clamping voltage (1 volt in this case), charge will continuously return to the MEMS capacitor through node 112. When the AC voltage at node 112 continues to decrease below the clamping voltage (1 volt in this case), indicating that the overload condition has disappeared, switch 308 will open (turn off) because the positive input of operational amplifier 302 is smaller than the negative input, and the output of the operational amplifier will be forced to a low voltage applied to the control terminal of switch 308A, thereby turning off the switch.

[0029] Figure 4 This is a circuit diagram of an embodiment of a charge control clamp 116B including a single transistor regulating switch, where the integrator 315 is replaced by a single capacitor 306. A single capacitor implementation can be effectively replaced if the capacitor 306 is a sufficiently large capacitor (larger than the MEMS device capacitor and 15 times or more larger) for storing charge at circuit node 112. Figure 3The integrator 315 is shown. In one embodiment, the value of the capacitor 306 is shown as 25pF, but other values ​​may be used in embodiments. Figure 4 The diagram also shows a precharge switch 312, which is used to precharge the voltage on capacitor 306 to the DC operating voltage of circuit node 120. The precharge switch 312 can be implemented as a transistor having a gate activated by a precharge control signal. Figure 4 (Not shown in the image). Figure 4 The regulating switch 311 continues to be used. Figure 3 The operational amplifier 302 is shown, but the switch 308A is replaced by a P-channel transistor 308B, which has a drain coupled to circuit node 112, a source coupled to circuit node 310 designated as "Vclamp", and a gate coupled to the output of the operational amplifier 302.

[0030] In operation, charge control clamp 116B is similar to charge control clamp 116A, except that charge is transferred from and to capacitor 306 via transistor 308B, which is configured as a switch. Before an overload condition, transistor 308B is turned off; during the overload condition, transistor 308B is selectively turned on (assuming an AC overload condition); and after the overload condition ends, transistor 308B is turned off, as previously discussed. Figure 3 The switch 308A is discussed below. Before an overload condition, such as at the start of an operating cycle, the precharge switch 312 can be opened and then closed to equalize the voltage between bias node 120 and capacitor node 310. In this way, the voltage on capacitor 306 will be precharged to the clamping voltage. Therefore, since the reference voltage of capacitor 306 is equal to the clamping voltage, the exact amount of charge lost during the clamping period of circuit node 112 will be stored on capacitor 306. After the voltage (Vbias + 0.8V) on the bias node equals the voltage on capacitor node 310, the precharge switch 312 can be opened. The control node of the precharge switch 312 can be integrated with... Figure 2A The readout circuit 200 shown is the same integrated circuit in the microprocessor (in...) Figure 4 (Not shown in the diagram) can be controlled, or it can be controlled by signals generated outside the integrated circuit.

[0031] Figure 5 This is a circuit diagram of an embodiment of a charge control clamp 116C, including a first regulating switch and a second regulating switch. All circuit components of the charge control clamp 116C are related to... Figure 4The charge control clamp 116C is the same as that shown in the charge control clamp 116B, except that it includes an additional regulating switch 313 to improve the performance of the charge control clamp 116C. The regulating switch 313 includes a second operational amplifier 314 having a positive input coupled to a bias node 120, a negative input coupled to a Vclamp circuit node 310, and an output coupled to the gate of a P-channel transistor 316. The drain of transistor 316 is coupled to circuit node 112, and the source of transistor 316 is coupled to Vclamp circuit node 310.

[0032] In operation, regulating switch 313 provides a second path for charge to flow into and out of capacitor 306. In some cases, any residual charge on capacitor 306 after an overload condition is removed can be completely transferred to circuit node 112 via transistor 316. This is because regulating switches 311 and 313 each include an operational amplifier with negative inputs referenced to two different circuit path nodes of transistor 308B. Note that regulating switch 311 includes operational amplifier 302, which has inputs referenced to the drain (circuit node 112) and bias node 120 of transistor 308B. Conversely, regulating switch 313 includes operational amplifier 313, which has inputs referenced to the source (capacitor node 310) and bias node 120 of transistor 308B. In this way, the voltages at the source and drain of transistor 308B are monitored and regulated when compared to the voltage at bias node 120.

[0033] Figure 6 It is similar to Figure 5 The circuit diagram shown is an embodiment of the charge control clamp 116D of the charge control clamp 116C, differing in that a Schmitt trigger circuit 318 and a switch 320 are added to control the operation of the second regulating switch 313. Furthermore, the voltage at the gate of transistor 308B is labeled "vop1," and the voltage at the gate of transistor 316 is labeled "vop2," to further illustrate the following description. Figure 7The operation of charge control clamp 116D in the timing diagram. In one embodiment, Schmitt trigger circuit 318 includes a positive input coupled to Vclamp circuit node 310, a negative input coupled to bias node 120, and an output for providing a "vctrl" control signal to control the operation of switch 320. Switch 320 is coupled between VDD at circuit node 322 and the gate of transistor 316, which is the VOP2 voltage. In one embodiment, Schmitt trigger circuit 318 has a hysteresis of approximately 40 mV, wherein a differential input voltage greater than 50 mV switches the output of the Schmitt trigger circuit to logic 1, and wherein a differential input voltage less than 10 mV switches the output of the Schmitt trigger circuit to logic 0.

[0034] During operation, the Schmitt trigger circuit 318 is used to safely disconnect the adjusted second regulating switch 316, as described below. Figure 7 The timing diagram explains this.

[0035] Figure 7 It shows Figure 6 The timing diagram 700 for the charge control clamp 116D is shown. Timing diagram 700 includes waveform 702, which is the VNP voltage at circuit node 120; waveform 704, which is the VOP1 voltage at the gate of transistor 308B; waveform 706, which is the VOP2 voltage at the gate of transistor 316; and waveform 708, which is the bias voltage Vbias + 800mV at bias node 120. In operation, when the value of VNP decreases from a high value under positive overload conditions to a lower value within the normal operating range, the first operational amplifier circuit (first regulating switch 311) is turned off first by the rise of voltage VOP1, as shown in waveform 704. However, since the discharge through the first circuit via regulating switch 311 may not be fast enough, a delay mechanism using Schmitt trigger circuit 318 is designed in the second operational amplifier circuit (second regulating switch 313) such that the VOP2 voltage rises later than the VOP1 voltage, as can be seen in the comparison of the corresponding waveforms 704 and 706. Therefore, the storage capacitor 306 can be fully discharged and the initial conditions at circuit node 112 can be completely restored without any residual error. Although Figure 7A specific hysteresis voltage is shown, but other hysteresis levels may be used for specific applications. In addition to the delay mechanism that helps fully recover the charge at node 112, switch 320 also helps to safely turn off transistor 316 for the following reasons. Even if the voltage at node 310 is below the clamping voltage (vbias + 0.8V in this case), transistor 316 will not be completely turned off by the operation of operational amplifier 314 via the action of node VOP2. To switch node VOP2 from low (during overload) to high (after the overload has subsided), the voltage at node 310 must be sufficiently lower than the voltage at node 120 due to the limited dynamic range of operational amplifier 314. However, once the voltage at node 310 drops to slightly below the voltage at node 120, operational amplifier 314 begins to react weakly, causing the voltage at node VOP2 to rise to a value sufficient to turn off PMOS transistor 316, but unsafely high (VDD). In such a case, the voltage at node 310 is at a value not sufficiently lower than the voltage at node 120, so that VOP2 never reaches VDD or takes a very long time to do so. In summary, with the help of the Schmitt trigger 318 and the switch 320, the transistor 316 is able to be safely turned off with the necessary delay.

[0036] Figure 3 , 4 Figures 5 and 6 show what can be used for Figure 2A The example shown is a charge-controlled clamp of charge-controlled clamp 116. In this embodiment, a bias voltage of Vbias + 0.8V is used with these charge-controlled clamps. Figure 2A The diagram illustrates a charge control clamp 118 associated with different bias voltages. In this embodiment, a bias voltage of Vbias-0.8V is used with the charge control clamp 118. Figure 3 , 4 The circuits shown in 5 and 6 can be used for the charge control clamp 118, the difference being that the bias voltage should be changed to a lower bias voltage. In an embodiment, this bias voltage can be Vbias-0.8V.

[0037] Figure 8 This shows what can be used to implement Figure 2A The charge control clamping circuit 800, representing different embodiments of charge control clampers 116 and 118, also provides charge control clamping functionality, allowing the DC operating point 112 of the circuit node to recover quickly after an overload condition is removed. The PMOS transistor M1 provides positive clamping. Figure 3 The function of the regulating switch 311 is defined by NMOS transistor M2, which provides the regulating switch function for negative clamping. Capacitor C1 provides... Figure 3The capacitor 306 provides charge storage. Capacitor C2 provides charge storage for the negative branch. The gate of transistor M1 (in...) Figure 8 The gate of transistor M2 (referred to as Vclamp_p) is connected to a reference voltage source, which sets the positive clamp voltage together with the threshold voltage of M1. Figure 8 The negative clamping voltage (referred to as Vclamp_n) is connected to a reference voltage source, which sets the negative clamping voltage together with the threshold voltage of M2. In operation, the drain terminal 802 of transistor M1 (also the top plate of C1) is initially pre-charged to Vclamp_p via reset switch sw1. Similarly, the drain terminal 804 of transistor M2 (also the top plate of C2) is initially pre-charged to Vclamp_n via reset switch sw2. When the input voltage (vinp) rises above Vclamp_p + Vth_M1 (where Vth_M1 is the threshold voltage of M1), the charge control clamping circuit 800 enters the positive overload region, and transistor M1 begins to conduct to store charge on C1, similar to... Figure 3 The regulating switch 311 is used. When the input voltage (vinp) begins to decrease from its positive peak, the charge stored on C1 returns from the input node to the MEMS capacitor (vinp). When the input voltage (vinp) eventually falls below Vclamp_p + Vth_M1, the charge control clamp circuit 800 returns to the normal operating region, and transistor M1 is turned off. When the input voltage (vinp) drops below Vclamp_n - Vth_M2 (Vth_M2 is the threshold voltage of M2), the charge control clamp circuit 800 enters the negative overload region and repeats a similar process described for the positive overload case.

[0038] In one embodiment, transistor M1 and switch sw1 of charge control clamping circuit 800 can be replaced with a diode-connected transistor (by replacing switch sw1 with a short circuit) or a diode. Similarly, transistor M2 and switch sw2 of charge control clamping circuit 800 can be replaced with a diode-connected transistor (by replacing switch sw2 with a short circuit) or a diode.

[0039] Advantages of using the readout circuit of the charge control clamp according to the embodiments described herein include: improved performance for overload events across the entire audio frequency band, improved performance for overload events in the subsonic frequency band and for DC overdrive events, no impact on performance within the normal signal range and therefore no degradation in total harmonic distortion (THD) and signal-to-noise ratio (SNR), and the ability to easily extend the desired accuracy of charge control using die area and power. For example, a larger capacitor relative to the output capacitance of the corresponding MEMS device will result in more charge being stored in the capacitor.

[0040] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the description and the claims set forth herein.

[0041] Example 1. According to one embodiment, a device includes: a readout circuit coupled between an input node and an output node; a microelectromechanical system (MEMS) device coupled to the input node; and a first charge control clamping circuit coupled between the input node and a first bias node.

[0042] Example 2. The device according to Example 1, wherein the first charge control clamping circuit is configured to clamp the input node to a first clamping voltage, store a first charge available at the input node during an overload condition, and return the first charge to the input node after the overload condition is removed.

[0043] Example 3. The device according to Example 1, wherein the first charge control clamping circuit includes a first transistor circuit or a first diode circuit.

[0044] Example 4. The device according to any of the preceding examples further includes a second charge control clamping circuit coupled between the input node and the second bias node.

[0045] Example 5. A device according to any of the preceding examples, wherein the second charge control clamping circuit is configured to clamp the input node to a second clamping voltage, store a second charge available at the input node during an overload condition, and return the second charge to the input node after the overload condition is removed.

[0046] Example 6. A device according to any of the preceding examples, wherein the second charge control clamping circuit includes a second transistor circuit or a second diode circuit.

[0047] Example 7. A device according to any of the preceding examples, wherein the first charge control clamping circuit includes a first switching circuit coupled to the first capacitor.

[0048] Example 8. A device according to any of the preceding examples, wherein the first switching circuit includes a first transistor coupled to a first operational amplifier, and wherein the input of the first operational amplifier is coupled to an input node.

[0049] Example 9. A device according to any of the preceding examples, wherein the value of the first capacitor is configured to be greater than the value of the capacitance associated with the MEMS device.

[0050] Example 10. The device according to any of the preceding examples, wherein the first charge control clamping circuit further includes a second switching circuit coupled to the first capacitor.

[0051] Example 11. A device according to any of the preceding examples, wherein the second switching circuit includes a second transistor coupled to a second operational amplifier, and wherein the input of the second operational amplifier is coupled to a first capacitor.

[0052] Example 12. The device according to any of the preceding examples further includes a Schmitt trigger circuit coupled to the first capacitor and the first bias node, the Schmitt trigger circuit being configured to operatively control the second operational amplifier.

[0053] Example 13. A device according to any of the preceding examples, wherein the readout circuitry includes amplifier circuitry.

[0054] Example 14. The device according to any of the preceding examples further includes a bias resistor coupled between the input node and the resistor bias node.

[0055] Example 15. According to one embodiment, a clamping circuit includes: a first charge-controlled clamp coupled between an input node and a first bias node, the first charge-controlled clamp being configured to store a first charge associated with the input node during a first voltage clamping mode and to return the first charge to the input node after the first voltage clamping mode; and a second charge-controlled clamp coupled between the input node and a second bias node, the second charge-controlled clamp being configured to store a second charge associated with the input node during a second voltage clamping mode and to return the second charge to the input node after the second voltage clamping mode.

[0056] Example 16. The clamping circuit according to Example 15, wherein the first charge control clamp includes a first switching circuit coupled to a first capacitor, and wherein the second charge control clamp includes a second switching circuit coupled to a second capacitor.

[0057] Example 17. A clamping circuit according to any of the preceding examples, wherein the value of the first capacitor is greater than the capacitance associated with the input node, and wherein the value of the second capacitor is greater than the capacitance associated with the input node.

[0058] Example 18. A clamping circuit according to any of the preceding examples, wherein the first charge control clamp includes a first additional switching circuit coupled to the first capacitor, and wherein the second charge control clamp includes a second additional switching circuit.

[0059] Example 19. A clamping circuit according to any of the preceding examples, wherein a first voltage clamping mode includes a positive voltage clamping mode, and wherein a second voltage clamping mode includes a negative clamping mode.

[0060] Example 20. According to one embodiment, a method of operating a microelectromechanical system (MEMS) includes: clamping a node of the MEMS device to a first voltage during a first overload operation mode; storing a first charge associated with a node of the MEMS device during the first overload operation mode; and returning the first charge to a node of the MEMS device after the first overload operation mode.

[0061] Example 21. The method according to Example 20 further includes restoring the DC operating point of the MEMS device immediately after returning the first charge to the node of the MEMS device.

[0062] Example 22. The method according to any of the preceding examples further includes: clamping a node of the MEMS device to a second voltage during a second overload operation mode; storing a second charge associated with a node of the MEMS device during the second overload operation mode; and returning the second charge to a node of the MEMS device after the first overload operation mode.

[0063] Example 23. The method according to any of the preceding examples further includes restoring the DC operating point of the MEMS device immediately after returning the second charge to the node of the MEMS device.

[0064] Example 24. The method according to any of the preceding examples, wherein the first overload operation mode includes an AC overload operation mode or a DC overload operation mode.

[0065] Example 25. According to one embodiment, a circuit includes: a first capacitor; a first transistor having a load path coupled between the first capacitor and a clamping node; and a first amplifier having a negative input coupled to the clamping node, a positive input coupled to a first clamping voltage reference node, and an output coupled to a control node of the first transistor.

[0066] Example 26. The circuit according to Example 25 further includes: a second transistor having a load path coupled between the first capacitor and the clamping node; and a second amplifier having a negative input coupled to the first capacitor, a positive input coupled to the first clamping voltage reference node, and an output coupled to the control node of the second transistor.

[0067] Example 27. The circuit according to any of the preceding examples further includes a Schmitt trigger having an input coupled to a clamping node, the Schmitt trigger being configured to operatively control a second amplifier.

[0068] Example 28. The circuit according to any of the preceding examples further includes a microelectromechanical (MEMS) device having an output coupled to a clamping node.

[0069] Example 29. The circuit according to any of the preceding examples further includes: a second capacitor; a third transistor having a load path coupled between the second capacitor and the clamping node; and a third amplifier having a negative input coupled to the clamping node, a positive input coupled to the second clamping voltage reference node, and an output coupled to the control node of the third transistor.

[0070] Example 30. The circuit according to any of the preceding examples further includes: a fourth transistor having a load path coupled between the second capacitor and the clamping node; and a fourth amplifier having a negative input coupled to the second capacitor, a positive input coupled to the second clamping voltage reference node, and an output coupled to the control node of the fourth transistor.

[0071] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Referring to the specification, those skilled in the art will clearly understand various modifications and combinations of the illustrative embodiments and other embodiments of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An apparatus for operating a microelectromechanical system (MEMS) device, comprising: The readout circuit is coupled between the input node and the output node; Microelectromechanical systems (MEMS) devices are coupled to the input node; as well as A first charge-controlled clamping circuit is coupled to the input node. The first charge control clamping circuit is configured to clamp the input node to a first clamping voltage, store a first charge available at the input node during an overload condition, and return the first charge to the input node after the overload condition is removed.

2. The device according to claim 1, wherein the first charge control clamping circuit comprises a first transistor circuit or a first diode circuit.

3. The device of claim 1 further includes a second charge control clamping circuit coupled to the input node.

4. The device of claim 3, wherein the second charge control clamping circuit is configured to clamp the input node to a second clamping voltage, store a second charge available at the input node during an overload condition, and return the second charge to the input node after the overload condition is removed.

5. The device according to claim 3, wherein the second charge control clamping circuit comprises a second transistor circuit or a second diode circuit.

6. The device of claim 1, wherein the first charge control clamping circuit includes a first switching circuit coupled to the first capacitor.

7. The device of claim 6, wherein the first switching circuit includes a first transistor coupled to a first operational amplifier, and wherein the input of the first operational amplifier is coupled to the input node.

8. The device of claim 6, wherein the value of the first capacitor is configured to be greater than the value of the capacitance associated with the MEMS device.

9. The device of claim 6, wherein the first charge control clamping circuit further comprises a second switching circuit coupled to the first capacitor.

10. The device of claim 9, wherein the second switching circuit includes a second transistor coupled to a second operational amplifier, and wherein the input of the second operational amplifier is coupled to the first capacitor.

11. The device of claim 10, further comprising a Schmitt trigger circuit coupled to the first capacitor and configured to operatively control the second operational amplifier.

12. The device of claim 1, wherein the readout circuit includes an amplifier circuit.

13. The device of claim 1, further comprising a bias resistor coupled to the input node.

14. A clamping circuit, comprising: A first charge control clamp is coupled to the input node, and the first charge control clamp is configured to store a first charge associated with the input node during a first voltage clamping mode, and to return the first charge to the input node after the first voltage clamping mode. as well as A second charge control clamp is coupled to the input node and is configured to store a second charge associated with the input node during a second voltage clamping mode and to return the second charge to the input node after the second voltage clamping mode.

15. The clamping circuit of claim 14, wherein the first charge control clamp includes a first switching circuit coupled to a first capacitor, and wherein the second charge control clamp includes a second switching circuit coupled to a second capacitor.

16. The clamping circuit of claim 15, wherein the value of the first capacitor is greater than the capacitance associated with the input node, and wherein the value of the second capacitor is greater than the capacitance associated with the input node.

17. The clamping circuit of claim 15, wherein the first charge control clamp includes a first additional switching circuit coupled to the first capacitor, and wherein the second charge control clamp includes a second additional switching circuit.

18. The clamping circuit of claim 14, wherein the first voltage clamping mode includes a positive voltage clamping mode, and wherein the second voltage clamping mode includes a negative clamping mode.

19. A method for operating a microelectromechanical system (MEMS) device, the method comprising: During the first overload operation mode, the output node of the MEMS device is clamped to a first voltage; During the first overload operation mode, a first charge associated with the output node of the MEMS device is stored; as well as After the first overload operation mode, the first charge is returned to the output node of the MEMS device.

20. The method of claim 19, further comprising immediately restoring the DC operating point of the MEMS device after returning the first charge to the output node of the MEMS device.

21. The method of claim 19, further comprising: During the second overload operation mode, the output node of the MEMS device is clamped to a second voltage; During the second overload operation mode, a second charge associated with the output node of the MEMS device is stored; as well as After the first overload operation mode, the second charge is returned to the output node of the MEMS device.

22. The method of claim 21, further comprising immediately restoring the DC operating point of the MEMS device after returning the second charge to the output node of the MEMS device.

23. The method of claim 19, wherein the first overload operation mode includes an AC overload operation mode or a DC overload operation mode.

24. A circuit comprising: First capacitor; The first transistor has a load path coupled between the first capacitor and the clamping node; as well as The first amplifier has a negative input coupled to the clamping node, a positive input coupled to the first clamping voltage reference node, and an output coupled to the control node of the first transistor. The circuit is configured to store charge available at the clamping node to the first capacitor during an overload condition, and to return the charge from the first capacitor to the clamping node after the overload condition is removed.

25. The circuit of claim 24, further comprising: The second transistor has a load path coupled between the first capacitor and the clamping node; as well as The second amplifier has a negative input coupled to the first capacitor, a positive input coupled to the first clamp voltage reference node, and an output coupled to the control node of the second transistor.

26. The circuit of claim 25 further includes a Schmitt trigger having an input coupled to the clamping node, the Schmitt trigger being configured to operatively control the second amplifier.

27. The circuit of claim 24, further comprising a microelectromechanical system (MEMS) device having an output coupled to the clamping node.

28. The circuit according to claim 24, further comprising: Second capacitor; The third transistor has a load path coupled between the second capacitor and the clamping node; as well as The third amplifier has a negative input coupled to the clamping node, a positive input coupled to the second clamping voltage reference node, and an output coupled to the control node of the third transistor.

29. The circuit of claim 28, further comprising: The fourth transistor has a load path coupled between the second capacitor and the clamping node; as well as The fourth amplifier has a negative input coupled to the second capacitor, a positive input coupled to the second clamp voltage reference node, and an output coupled to the control node of the fourth transistor.

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