Three-dimensional memory and methods of making the same

Abstract

The present disclosure relates to a three-dimensional memory and a method of manufacturing the same, the three-dimensional memory comprising: a gate stack structure comprising a core region and a step region arranged side by side along a first direction and directly contacting each other; a dummy separation structure penetrating through the step region along the first direction; and a gate separation structure penetrating through the core region along the first direction, the gate separation structure having a first end portion contacting the dummy separation structure along the first direction, the dummy separation structure having a second end portion contacting the gate separation structure along the first direction, and the first end portion being located within the second end portion.

Description

[0001] Cross-referencing of related applications

[0002] This application claims priority to Chinese Patent Application No. 202011338956.4, filed on November 25, 2020, entitled "Three-dimensional memory and method of fabrication thereof," the contents of which are expressly incorporated herein by reference. [Technical Field]

[0003] This disclosure relates to a three-dimensional memory and a method for manufacturing the same. [Background Technology]

[0004] With the development of technology, the semiconductor industry is constantly seeking new production methods to enable each memory die in a memory device to have a greater number of memory cells. Among them, 3D NAND (three-dimensional NAND gate) memory has become a cutting-edge and highly promising three-dimensional memory technology due to its advantages such as high storage density and low cost. [Summary of the Invention]

[0005] Embodiments of this disclosure provide a three-dimensional memory, the three-dimensional memory comprising: a gate stack structure, the gate stack structure including a core region and a step region arranged side by side and in direct contact along a first direction; a virtual partition structure penetrating the step region in the first direction; a gate partition structure penetrating the core region in the first direction, the gate partition structure having a first end that contacts the virtual partition structure in the first direction, the virtual partition structure having a second end that contacts the gate partition structure in the first direction, and the first end being located within the second end.

[0006] For example, the second end includes two clamping parts, and the first end is located between the two clamping parts in a second direction perpendicular to the first direction and is in direct contact with the two clamping parts.

[0007] For example, the width of the clamping part in the second direction perpendicular to the first direction gradually increases from the step area to the core area along the first direction.

[0008] For example, the second end also includes a connecting part, which is connected to two clamping parts.

[0009] For example, the connecting part is in direct contact with the first end.

[0010] For example, the virtual partition structure also includes a second extension that is arranged side-by-side with and in direct contact with the second end.

[0011] For example, the second extension extends along the first direction.

[0012] For example, the width of the second end in the second direction perpendicular to the first direction is greater than the width of the second extension in the second direction.

[0013] For example, the width of the second end in the second direction gradually increases along the first direction from the step area to the core area.

[0014] For example, the width of the second end in the second direction gradually increases and then gradually decreases along the first direction from the step area to the core area.

[0015] For example, the material of the virtual partition structure is an insulating material.

[0016] For example, the gate separation structure also includes a first extension that is arranged in parallel with and in direct contact with the first end, and the first end is surrounded by the first extension and the second end together.

[0017] For example, the first extension extends along a first direction.

[0018] For example, at least a portion of the first end has a width in a second direction perpendicular to the first direction that is greater than the width of the first extension in the second direction.

[0019] For example, the width of the first end in the second direction gradually increases along the first direction from the core area to the step area.

[0020] For example, the width of the first end in the second direction gradually increases and then gradually decreases along the first direction from the core area to the step area.

[0021] For example, the first end extends into the step area along the first direction.

[0022] For example, the maximum width of the first end in the second direction perpendicular to the first direction is not greater than the minimum width of the second end in the second direction.

[0023] For example, the gate separation structure includes a conductive structure and an electrically insulating layer located between the conductive structure and the gate stack structure in a second direction perpendicular to the first direction.

[0024] For example, the second end includes two clamping sub-parts, the first end is located between the two clamping sub-parts in a second direction perpendicular to the first direction and is in direct contact with the two clamping sub-parts, and the three-dimensional memory also includes: a plurality of channel structures located in the core region, the plurality of channel structures penetrating the core region in a third direction intersecting the first and second directions;

[0025] Multiple virtual channel structures are located in the stepped area, and these virtual channel structures penetrate the stepped area in a third direction.

[0026] For example, virtual partition structures and gate partition structures are used in a third-party through-gate stack structure.

[0027] For example, a three-dimensional memory also includes a substrate, on which a gate stack structure is located, with a third direction perpendicular to the first and second directions.

[0028] For example, a virtual partition structure is used to divide the step region into multiple block step regions in a second direction perpendicular to the first direction, and a gate partition structure is used to divide the core region into multiple block core regions in the second direction.

[0029] The embodiments of this disclosure also provide a method for fabricating a three-dimensional memory. The method includes: forming a gate stack structure, the gate stack structure including a core region and a step region arranged side by side and in direct contact along a first direction; forming a virtual partition structure and a gate partition structure, the virtual partition structure penetrating the step region in the first direction, the gate partition structure penetrating the core region in the first direction, the gate partition structure having a first end that contacts the virtual partition structure in the first direction, the virtual partition structure having a second end that contacts the gate partition structure in the first direction, and the first end being located within the second end.

[0030] For example, forming a virtual partition structure and a gate partition structure includes: forming a virtual gate partition in a step region, the virtual gate partition penetrating the step region in a first direction; filling the virtual gate partition with insulating material to form a virtual partition structure; forming a gate partition in a core region and a second end of the virtual partition structure, the gate partition penetrating the core region and a portion of the second end in a first direction; and forming a gate partition structure in the gate partition. [Attached Image Description]

[0031] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a top view of the three-dimensional memory provided in an embodiment of this disclosure;

[0033] Figure 2 It is along Figure 1 A schematic diagram of the cross-sectional structure taken by line O-O' in the diagram;

[0034] Figure 3 It is along Figure 1 A schematic diagram of the cross-sectional structure taken by line P-P' in the diagram;

[0035] Figure 4 It is along Figure 1 A schematic diagram of the cross-sectional structure intercepted by line Q-Q' in the diagram;

[0036] Figure 5 This is a schematic diagram of the structure after the gate separation structure and the virtual separation structure are connected according to the embodiments of this disclosure;

[0037] Figure 6 These are schematic diagrams of the four virtual partition structures provided in the embodiments of this disclosure;

[0038] Figure 7 This is a schematic flowchart of a method for fabricating a three-dimensional memory provided in an embodiment of this disclosure.

Detailed Implementation Methods

[0039] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the disclosure. Similarly, the following embodiments are only some, not all, embodiments of the present disclosure, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this disclosure.

[0040] Furthermore, the directional terms used in this disclosure, such as [up], [down], [front], [back], [left], [right], [inside], [outside], and [side], are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and interpretative purposes only, and not for limiting the scope of this disclosure. In the various figures, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the figures are not drawn to scale. Additionally, some well-known parts may not be shown in the figures.

[0041] 3D NAND flash memory typically includes one or more chip memory regions. A stepped region for leading out the gate is typically provided on at least one side of the chip memory region. The stepped region has a stepped shape. The chip memory region and the stepped region are typically divided into multiple blocks to obtain multiple block memory regions.

[0042] However, existing 3D NAND memories use gate slots (or gate separation structures) to separate blocks. Due to the stress in the step region, the gate slots located in the step region are prone to deformation or even breakage, which in turn affects the performance of the 3D NAND memory.

[0043] For example, by using a virtual partition structure and a gate partition structure to separate the step region and the core region of the gate stack structure respectively, and making the gate partition structure have a first end that contacts the virtual partition structure in a first direction, and the virtual partition structure has a second end that contacts the gate partition structure in a first direction, with the first end located inside the second end, the problem that the gate partition structure is prone to deformation or even breakage in the step region due to the stress in the step region when using the gate partition structure to separate the step region can be solved, thereby improving the performance of the three-dimensional memory.

[0044] Please see Figures 1 to 4 , Figure 1 This is a top view schematic diagram of the three-dimensional memory provided in an embodiment of this disclosure. Figure 2 It is along Figure 1 A schematic diagram of the cross-sectional structure taken by line O-O' in the diagram. Figure 3 It is along Figure 1 A schematic diagram of the cross-sectional structure taken by line P-P' in the diagram. Figure 4 It is along Figure 1 The diagram shows a cross-sectional view of the structure taken by line Q-Q'. This three-dimensional memory includes a gate stack structure 12, a virtual separator structure 13, and a gate separator structure 14. For example, the gate stack structure 12 includes a core region 12A and a stepped region 12B arranged side-by-side and in direct contact along a first direction X. The virtual separator structure 13 penetrates the stepped region 12B in the first direction X. The gate separator structure 14 penetrates the core region 12A in the first direction X.

[0045] In some embodiments of this disclosure, such as Figure 5 As shown, the gate separation structure 14 has a first end 14A that contacts the virtual separation structure 13 in the first direction X, and the virtual separation structure 13 has a second end 13A that contacts the gate separation structure 14 in the first direction X. The first end 14A is located inside the second end 13A to ensure that the virtual separation structure 13 and the gate separation structure 14 can play a good isolation role after they are connected together. Furthermore, compared with the scheme of using a gate separator structure to separate the step region in the related technology, some embodiments of this disclosure use a virtual separator structure 13 to separate the step region 12B. The virtual separator structure 13 can not only support the step region 12B of the gate stack structure 12 so that the step region 12B is not easy to collapse, but also separate the first end 14A of the gate separator structure 14 extending into the step region 12B from the gate separator structure 12. This allows the first end 14A to be surrounded by the same film layer (i.e., the virtual separator structure 13) from bottom to top, avoiding leakage problems caused by deformation of the gate separator structure 14 due to different film layer stresses from bottom to top.

[0046] For example, such as Figure 2As shown, the gate stack structure 12 may include multiple alternating layers of gate layer 121 and gate insulating layer 122 stacked in a longitudinal direction Z perpendicular to the first direction X. Figure 1 As shown, the virtual partition structure 13 can be used to divide the step region 12B of the gate stack structure 12 into multiple block step regions K1 / K2 in the second direction Y perpendicular to the first direction X, and the gate partition structure 14 can be used to divide the core region 12A of the gate stack structure 12 into multiple block core regions K3 / K4 in the second direction Y.

[0047] For example, such as Figure 2 As shown, in the gate stack structure 12 described above, the gate layer 121 is located between two adjacent gate insulating layers 122. The gate layer 121 can be made of conductive materials such as tungsten, cobalt, copper, or aluminum. The gate insulating layer 122 can be made of any one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The number of gate layers 121 can be determined based on the number of memory cells to be formed in the vertical Z direction. The virtual separator structure 13 can specifically be an insulating layer, and its material can be any one of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. Figure 4 As shown, the gate separation structure 14 may specifically include a conductive structure 142 and an electrically insulating layer 141 located between the conductive structure 142 and the gate stack structure 12 in a second direction Y perpendicular to the first direction X. For example, the conductive structure 142 may include conductive materials such as titanium or titanium nitride, polycrystalline silicon, and / or tungsten. The electrically insulating layer 141 is used to electrically isolate the conductive structure 142 and the gate stack structure 12, and may specifically be an oxide layer. Furthermore, the conductive structure 142 may serve as a common source to provide a conductive channel for source connection in a three-dimensional memory.

[0048] In one specific embodiment, such as Figure 1 and Figure 5 As shown, the second end portion 13A may include two clamping sub-parts 13A-1 / 13A-2 (that is, the first clamping sub-part 13A-1 and the second clamping sub-part 13A-2). The first end portion 14A may be located between the two clamping sub-parts 13A-1 / 13A-2 in the second direction Y perpendicular to the first direction X, and may be in direct contact with the two clamping sub-parts 13A-1 / 13A-2, so as to ensure that the second end portion 13A of the virtual separation structure 13 can isolate the first end portion 14A of the gate separation structure 14 from the gate stack structure 12 located on both sides of the second direction Y of the first end portion 14A.

[0049] For example, such as Figure 1 and Figure 5As shown, the width of the first clamping sub-part 13A-1 and the second clamping sub-part 13A-2 in the direction perpendicular to the second direction Y can be gradually increased along the first direction X from the step region 12B to the core region 12A, so as to increase the process window when forming the gate separation structure 14, thereby reducing the manufacturing process difficulty of the three-dimensional memory.

[0050] In some embodiments, such as Figure 5 As shown, the second end portion 13A may further include a connecting sub-portion 13A-3, which is connected to the first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2. For example, the connecting sub-portion 13A-3 may be in direct contact with the first end portion 14A.

[0051] In one specific embodiment, such as Figure 5 As shown, the virtual partition structure 13 may further include a second extension 13B arranged parallel to and in direct contact with the second end portion 13A. This second extension 13B can extend along the first direction X. Furthermore, the width W1 of the second end portion 13A in the second direction Y, perpendicular to the first direction X, is greater than the width W2 of the second extension 13B in the second direction Y. Thus, by only widening a portion of the virtual partition structure 13, the tolerance for manufacturing deviations in forming the virtual partition structure 13 and the gate partition structure 14 can be improved, which helps to reduce process difficulty.

[0052] Furthermore, in specific implementation, such as Figure 1 and Figure 5 As shown, the width W2 of the second extension 13B in the second direction Y can be a fixed value V1, while the width W1 of the second end portion 13A in the second direction Y can gradually increase along the first direction X from the stepped area 12B towards the core area 12A. For example, as Figure 6 As shown in (a) and (b), the width W1 of the second end 13A in the second direction Y can increase from the middle to both sides in a non-linear increasing pattern (e.g., a broken line or an arc), or, as ...b) and (c), the width W Figure 6 As shown in (c), the increase can also proceed linearly (e.g., a straight line) from the middle outwards. In some alternative embodiments, such as... Figure 1 , Figure 5 and Figure 6As shown in (d), the width W1 of the second end 13A in the second direction Y can gradually increase and then gradually decrease along the first direction X from the stepped region 12B to the core region 12A, and the minimum width of the second end 13A in the second direction Y is not less than the fixed value V1. Thus, by designing the second end 13A of the virtual partition structure 13 as a large-head structure, it can be ensured that the virtual partition structure 13 and the gate partition structure 14 can play a good isolation role after being connected together, thereby avoiding leakage problems between adjacent memory blocks.

[0053] It should be noted that the above Figure 6 This is a schematic diagram of the structure of a virtual partition structure 13 in which the second end 13A does not surround the first end 14A of the gate partition structure 14, as provided in some embodiments of this disclosure. That is, the above... Figure 6 The virtual partition structure 13 shown is an intermediate structure obtained during the fabrication of the three-dimensional memory after the formation of the virtual partition structure 13 and before the formation of the gate partition structure 14.

[0054] In the above embodiments, such as Figure 5 As shown, the gate separation structure 14 may further include a first extension 14B arranged parallel to and in direct contact with the first end portion 14A, and the first end portion 14A is surrounded by the first extension 14B and the second end portion 13A of the virtual separation structure 13. For example, the second extension 13B may extend along the first direction X. Furthermore, at least a portion of the first end portion 14A has a width W3 in the second direction Y perpendicular to the first direction X that is greater than the width W4 of the first extension 14B in the second direction Y. Thus, by only widening a portion of the gate separation structure 14, the manufacturing tolerance of the virtual separation structure 13 and the gate separation structure 14 can be further improved, thereby helping to further reduce the process difficulty.

[0055] In specific implementation, such as Figure 1 and Figure 5As shown, the width W4 of the first extension 14B in the second direction Y can also be a fixed value V2, and this fixed value V2 can be less than the fixed value V1. That is, the width W4 of the first extension 14B in the second direction Y is less than the width W2 of the second extension 13B in the second direction Y. Further, the width W3 of the first end portion 14A in the second direction Y can gradually increase along the first direction X from the core region 12A to the step region 12B. Similar to the specific implementation where the width W3 of the second end portion 13A gradually increases in the second direction Y, the width W3 of the first end portion 14A in the second direction Y can also increase from the middle to both sides in a non-linear increasing pattern (e.g., a broken line or an arc), or it can increase from the middle to both sides in a linear increasing pattern (a straight line), or it can gradually increase and then gradually decrease along the first direction X from the core region 12A to the step region 12B. At the same time, the minimum width of the first end portion 14A in the second direction Y can be made not less than the fixed value V2.

[0056] Thus, by designing the first end 14A of the gate separation structure 14 as a large-head structure, it can be further ensured that the virtual separation structure 13 and the gate separation structure 14 can play a good isolation role after being connected together, thereby better avoiding leakage problems between two adjacent block memory areas.

[0057] Furthermore, in order to better encompass the first end portion 14A with the second end portion 13A, the width variation pattern of the second end portion 13A in the second direction Y can match the width variation pattern of the first end portion 14A in the second direction Y. For example, the widths W1 / W3 of both the second end portion 13A and the first end portion 14A in the second direction Y can increase from the middle to both sides in a non-linear increasing pattern (e.g., a broken line). In some specific embodiments, the maximum width of the first end portion 14A along the second direction Y can be designed to be no greater than the minimum width of the second end portion 13A along the second direction Y, so that the first end portion 14A is more easily encompassed by the second end portion 13A.

[0058] It should be noted that some embodiments of this disclosure only increase the side width of the virtual partition structure 13 and / or the gate partition structure 14, so that the main width of the virtual partition structure 13 and the gate partition structure 14 can still be maintained at a small value. Compared with the scheme of increasing the overall width of the partition structure, the process requirements of the etching step and the filling step can be reduced.

[0059] Furthermore, in some embodiments of this disclosure, only one core region 12A and one step region 12B are given as examples. In some embodiments, there may be two step regions 12B, with the core region 12A located between these two step regions 12B. In other embodiments, there may be two core regions 12A, with the step region 12B located between these two core regions 12A. Accordingly, the internal structure of the three-dimensional memory on one side in the first direction X can refer to the internal structure on the other side. It is understood that some embodiments of this disclosure only specifically describe the internal structure of the three-dimensional memory on one side in the first direction X.

[0060] In the above embodiments, such as Figure 1 and Figure 5 As shown, the first end 14A of the gate separator structure 14 can extend along the first direction X into the stepped region 12B of the gate stack structure 12. Therefore, without the virtual separator structure 13 extending into the core region 12A of the gate stack structure 12, the virtual separator structure 13 can surround the first end 14A of the gate separator structure 14 from three directions, avoiding the impact on the performance of the 3D memory caused by the virtual separator structure 13 extending into the core region 12A of the gate stack structure 12.

[0061] In the above embodiments, such as Figures 1 to 4 As shown, the aforementioned three-dimensional memory may further include multiple channel structures 16 and multiple virtual channel structures 17. For example, the multiple channel structures 16 are located in the core region 12A and can penetrate the core region 12A in a third direction (e.g., the longitudinal direction Z) intersecting the first direction X and the second direction Y. The multiple virtual channel structures 17 are located in the step region 12B and can penetrate the step region 12B in the third direction. For example, the channel structure 16 may specifically include a dielectric pillar, a channel layer surrounding the dielectric pillar, and a charge storage layer surrounding the channel layer. The charge storage layer may include a tunneling oxide layer surrounding the channel layer, a charge trapping layer surrounding the tunneling oxide layer, and a barrier oxide layer surrounding the charge trapping layer. For example, the charge trapping layer may be made of silicon nitride, and the channel layer may be made of polysilicon. The virtual separator structure 13 and the gate separator structure 14 can penetrate the gate stack structure 12 in the third direction.

[0062] Furthermore, it is understood that, for the aforementioned three-dimensional memory, one channel structure 16 in the core region 12A is shared by multiple memory cells in a memory string. The multiple virtual channel structures in the stepped region 12B do not provide storage functionality but are used to provide mechanical support to prevent the memory device from collapsing. Moreover, in specific implementations, the virtual channel structures can have the same structure as the aforementioned channel structures, so this will not be elaborated further here.

[0063] For example, such as Figures 1 to 4 As shown, the aforementioned three-dimensional memory may further include a semiconductor layer, for example, a substrate 11. The aforementioned gate stack structure 12 is located on the semiconductor layer (e.g., on the substrate 11), and the semiconductor layer (e.g., substrate 11) may be made of single-crystal silicon, single-crystal germanium, or silicon-on-insulator (SOI). In some examples, the semiconductor layer may include polycrystalline silicon. For example, the semiconductor layer may be made of polycrystalline silicon or other suitable materials. For example, for ease of description, subsequent semiconductor layers are described using the substrate. For example, the gate stack structure 12 may be formed after the semiconductor layer is formed. Alternatively, the gate stack structure 12 may be formed before the semiconductor layer is formed.

[0064] For example, the aforementioned third direction can be perpendicular to the aforementioned first direction X and second direction Y, that is, the aforementioned third direction can be perpendicular to the longitudinal direction Z of the substrate 11. Accordingly, the aforementioned virtual partition structure 13 and gate partition structure 14 can be perpendicular to the aforementioned substrate 11.

[0065] In some specific embodiments, such as Figures 1 to 4 As shown, the aforementioned three-dimensional memory may further include a dielectric layer 15 covering the step region 12B, and the aforementioned virtual partition structure 13 sequentially penetrates the dielectric layer 15 and the step region 12B in the longitudinal Z direction. For example, the dielectric layer 15 may be made of an insulating material such as silicon oxide. Furthermore, in specific implementations, the material of the aforementioned virtual partition structure 13 may be the same as that of the dielectric layer 15, for example, both being silicon oxide, so that the virtual partition structure 14 is not affected by the stress of the dielectric layer 15, thereby preventing the virtual partition structure 14 from undergoing lateral bending or torsional deformation.

[0066] In one specific embodiment, such as Figure 1As shown, the aforementioned three-dimensional memory may further include at least one first sub-gate partition structure 18 and at least one second sub-gate partition structure 19. The at least one first sub-gate partition structure 18 is located in the block core regions K3 / K4 and extends in the first direction X, and is not connected to the second sub-gate partition structure 19. The at least one second sub-gate partition structure 19 is located in the block step regions K1 / K2 and extends in the first direction X, and is not connected to the first sub-gate partition structure 18. In the aforementioned three-dimensional memory, the block core region K3 and the block step region K1 connected in the first direction X constitute one block storage region, and the block core region K4 and the block step region K2 connected in the first direction X constitute another block storage region. The purpose of providing the first sub-gate partition structure 18 and the second sub-gate partition structure 19 in the block storage regions is to reduce the manufacturing difficulty. This is because the more steps there are, the greater the manufacturing difficulty. To reduce manufacturing complexity, when the number of gates is large, the block memory can be divided into several parts by setting the first sub-gate partition structure 18 and the second sub-gate partition structure 19, with each part exposing each step layer. For example, when the number of gate layers 121 is 32, if the block memory is divided into four parts, the first part can expose gate layers 1, 5, 9, 13, 17, 21, 25, and 29 respectively; the second part can expose gate layers 2, 6, 10, 14, 18, 22, 26, and 30 respectively; the third part can expose steps 3, 7, 11, 15, 19, 23, 27, and 31 respectively; and the fourth part can expose steps 4, 8, 12, 16, 20, 24, 28, and 32 respectively. Each part has only eight steps, with at least one step including four gate layers 121. Compared to directly forming 32 continuous steps, the process is simpler. Furthermore, the first sub-gate line separation structure 18 and the second sub-gate line separation structure 19 are staggered and not connected to each other, allowing the gate layers 121 located on the same layer to be electrically connected to each other. Moreover, the specific structures of the first sub-gate line separation structure 18 and the second sub-gate line separation structure 19 are largely the same as those of the gate separation structure 14, and therefore will not be described in detail here.

[0067] Unlike related technologies, the three-dimensional memory in some embodiments of this disclosure uses a virtual separator structure and a gate separator structure to separate the step region and the core region of the gate stack structure, respectively. The gate separator structure has a first end that contacts the virtual separator structure in a first direction, and the virtual separator structure has a second end that contacts the gate separator structure in a first direction. The first end is located inside the second end. This avoids the problem that the gate separator structure is prone to deformation or even breakage in the step region due to the stress in the step region when using the gate separator structure to separate the step region, thereby improving the performance of the three-dimensional memory.

[0068] Please see Figure 7 as well as Figures 1 to 6 , Figure 7 This is a schematic flowchart of a method for fabricating a three-dimensional memory provided in an embodiment of this disclosure. Figures 1 to 6 The diagram below illustrates the structure of a three-dimensional memory or a portion thereof provided in an embodiment of this application. The specific process for manufacturing this three-dimensional memory is as follows:

[0069] Step S11: Form a gate stack structure 12, which includes a core region 12A and a step region 12B arranged side by side and in direct contact along the first direction X.

[0070] For example, the gate stack structure 12 described above includes multiple alternating layers of gate sacrificial layers and gate insulating layers 122 stacked in a longitudinal direction Z perpendicular to the first direction X. The gate sacrificial layers can be made of silicon nitride, and the gate insulating layers 122 can be made of silicon oxide. The number of gate sacrificial layers can be determined according to the number of memory cells to be formed in the longitudinal direction. In a specific implementation, the gate stack structure 12 can be formed on a substrate 11, and then the gate stack structure 12 can be etched so that one end of the gate stack structure 12 in the first direction X is stepped. For example, the substrate 11 can be made of single-crystal silicon, single-crystal germanium, or silicon-on-insulator (SOI).

[0071] Step S12: Form a virtual partition structure 13 and a gate partition structure 14. The virtual partition structure 13 penetrates the step region 12B in the first direction X, and the gate partition structure 14 penetrates the core region 12A in the first direction X. The gate partition structure 14 has a first end 14A that contacts the virtual partition structure 13 in the first direction X, and the virtual partition structure 13 has a second end 13A that contacts the gate partition structure 14 in the first direction X, and the first end 14A is located within the second end 13A.

[0072] For example, the virtual partition structure 13 can be used to divide the stepped region 12B of the gate stack structure 12 into multiple block stepped regions K1 / K2 in the second direction Y, which is perpendicular to the first direction X. The gate partition structure 14 can be used to divide the core region 12A of the gate stack structure 12 into multiple block core regions K3 / K4 in the second direction Y.

[0073] For example, step S12 above may include:

[0074] Step S121: A virtual gate spacer 13 is formed in the step region 12B, and the virtual gate spacer 13 penetrates the step region 12B in the first direction X.

[0075] For example, before step S121, it may also include: forming a dielectric layer 15 covering the step region 12B, and the virtual gate trench sequentially penetrates the dielectric layer 15 and the step region 12B in the longitudinal direction Z. For example, the dielectric layer 15 may be made of an insulating material such as silicon oxide.

[0076] Step S122: Fill the virtual gate spacer with an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide) to obtain the virtual spacer structure 13.

[0077] Step S123: A gate spacer is formed in the core region 12A and the second end 13A of the virtual partition structure 13, the gate spacer penetrating the core region 12A and part of the second end 13A in the first direction X.

[0078] Step S124: Form a gate partition structure 14 in the gate partition trench.

[0079] For example, an electrically insulating layer 141 (e.g., an oxide layer) and a conductive structure 142 serving as a common source can be sequentially formed on the sidewall of the aforementioned gate spacer to obtain the aforementioned gate separation structure 14. For example, the conductive structure 142 may include conductive materials such as titanium or titanium nitride, polycrystalline silicon, and / or tungsten.

[0080] In one embodiment, such as Figure 5 As shown, the second end portion 13A may include two clamping sub-parts 13A-1 / 13A-2 (that is, the first clamping sub-part 13A-1 and the second clamping sub-part 13A-2). The first end portion 14A may be located between the first clamping sub-part 13A-1 and the second clamping sub-part 13A-2 in the second direction Y perpendicular to the first direction X, and may be in direct contact with the first clamping sub-part 13A-1 and the second clamping sub-part 13A-2.

[0081] For example, such as Figure 1 and Figure 5 As shown, the width of the first clamping sub-part 13A-1 and the second clamping sub-part 13A-2 in the direction perpendicular to the second direction Y can gradually increase along the first direction X from the step area 12B to the core area 12A.

[0082] In one specific embodiment, such as Figure 5 As shown, the second end portion 13A may further include a connecting sub-portion 13A-3, which is connected to the first clamping sub-portion 13A-1 and the second clamping sub-portion 13A-2. For example, the connecting sub-portion 13A-3 may be in direct contact with the first end portion 14A.

[0083] In one embodiment, such as Figure 5As shown, the virtual partition structure 13 may further include a second extension 13B arranged parallel to and in direct contact with the second end portion 13A. This second extension 13B may extend along the first direction X. Furthermore, the width W1 of the second end portion 13A in the second direction Y, perpendicular to the first direction X, is greater than the width W2 of the second extension 13B in the second direction Y.

[0084] For example, the width W1 of the second end portion 13A in the second direction Y can gradually increase along the first direction X from the stepped region 12B to the core region 12A. In some alternative embodiments, the width W1 of the second end portion 13A in the second direction Y can also gradually increase and then gradually decrease along the first direction X from the stepped region 12B to the core region 12A.

[0085] In the above embodiments, the gate separation structure 14 may further include a first extension 14B arranged parallel to and in direct contact with the first end portion 14A, and the first end portion 14A is surrounded by the first extension 14B and the second end portion 13A of the virtual separation structure 13. For example, the second extension 13B may extend along the first direction X. Furthermore, at least a portion of the first end portion 14A has a width W3 in the second direction Y perpendicular to the first direction X that is greater than the width W4 of the first extension 14B in the second direction Y.

[0086] For example, the width W3 of the first end portion 14A in the second direction Y can gradually increase along the first direction X from the core region 12A to the step region 12B. In some alternative embodiments, the width W3 of the first end portion 14A in the second direction Y can first gradually increase and then gradually decrease along the first direction X from the core region 12A to the step region 12B.

[0087] In some embodiments, the first end portion 14A may extend along the first direction X into the step region 12B.

[0088] In some embodiments, the maximum width of the first end portion 14A in the second direction Y perpendicular to the first direction X is not greater than the minimum width of the second end portion 13A in the second direction Y.

[0089] In some embodiments, the three-dimensional memory may further include a plurality of channel structures 16 located in the core region 12A and a plurality of virtual channel structures 17 located in the step region 12B. For example, the plurality of channel structures 16 may penetrate the core region 12A in a third direction (e.g., the longitudinal direction Z) intersecting the first direction X and the second direction Y. The plurality of virtual channel structures 17 may penetrate the step region 12B in the third direction.

[0090] For example, the virtual partition structure 13 and the gate partition structure 14 described above can penetrate the gate stack structure 12 in the third direction described above.

[0091] In some specific embodiments, the three-dimensional memory may further include a substrate 11, on which the gate stack structure 12 is located. For example, the third direction may be perpendicular to the first direction X and the second direction Y, that is, the third direction may be the longitudinal direction Z perpendicular to the substrate 11.

[0092] In some embodiments, prior to step S124 described above, the following may also be included:

[0093] Step S125: A gate line slit is formed in the core region 12A, the gate line slit being perpendicular to the substrate 11 and penetrating the core region 12B in the first direction X.

[0094] For example, the gate line slit and the gate spacer can be formed by the same etching process, and the gate line slit is not connected to the virtual partition structure.

[0095] Step S126: Replace the gate sacrificial layer in the gate stack structure 12 with the gate layer 121 through the gate line gap and gate slot.

[0096] For example, a replacement process can be used to replace the gate sacrificial layer in the gate stack structure 12 described above, and a conductive material (e.g., tungsten) can be filled in the same position to form the corresponding gate layer 121.

[0097] Step S127: Form a common source structure in the gate line gap.

[0098] In a specific embodiment, steps S127 and S124 can be executed simultaneously. That is, an electrically insulating layer 141 and a conductive structure 142 serving as a common source electrode can be formed sequentially on the sidewalls of the gate line gap and the gate partition trench, so as to obtain the common source electrode structure and the gate partition structure 14.

[0099] It should be noted that the specific structure of the three-dimensional memory in some embodiments of this disclosure can be referred to the specific implementation methods in the above embodiments of the three-dimensional memory, so it will not be repeated here.

[0100] Unlike related technologies, the fabrication method of the three-dimensional memory in some embodiments of this disclosure forms a gate stack structure, which includes a core region and a step region arranged side by side and in direct contact along a first direction; forms a virtual separator structure and a gate separator structure, wherein the virtual separator structure penetrates the step region in the first direction, and the gate separator structure penetrates the core region in the first direction. The gate separator structure has a first end that contacts the virtual separator structure in the first direction, and the virtual separator structure has a second end that contacts the gate separator structure in the first direction, with the first end located inside the second end. This avoids the problem that the gate separator structure is prone to deformation or even breakage in the step region due to the stress in the step region when using the gate separator structure to separate the step region, thereby improving the performance of the three-dimensional memory.

[0101] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A three-dimensional memory, comprising: A gate stack structure, the gate stack structure comprising a core region and a step region arranged side by side and in direct contact along a first direction; A virtual partition structure extends through the stepped area in the first direction; A gate separator structure extends through the core region in the first direction, the gate separator structure having a first end that contacts the virtual separator structure in the first direction, the virtual separator structure having a second end that contacts the gate separator structure in the first direction, and the first end being surrounded by the second end.

2. The three-dimensional memory according to claim 1, wherein, The second end includes two clamping parts, and the first end is located between the two clamping parts in a second direction perpendicular to the first direction and is in direct contact with the two clamping parts.

3. The three-dimensional memory according to claim 2, wherein, The width of the clamping part in the second direction perpendicular to the first direction gradually increases along the first direction from the stepped area toward the core area.

4. The three-dimensional memory according to claim 2, wherein, The second end also includes a connecting sub-part, which is connected to the two clamping sub-parts.

5. The three-dimensional memory according to claim 4, wherein, The connecting sub-part is in direct contact with the first end.

6. The three-dimensional memory according to claim 1, wherein, The virtual partition structure also includes a second extension that is arranged side-by-side with and in direct contact with the second end.

7. The three-dimensional memory according to claim 6, wherein, The second extension extends along the first direction.

8. The three-dimensional memory according to claim 6, wherein, The width of the second end portion in the second direction perpendicular to the first direction is greater than the width of the second extension portion in the second direction.

9. The three-dimensional memory according to claim 8, wherein, The width of the second end in the second direction gradually increases along the first direction from the stepped area toward the core area.

10. The three-dimensional memory according to claim 8, wherein, The width of the second end in the second direction gradually increases and then gradually decreases along the first direction from the stepped area toward the core area.

11. The three-dimensional memory according to claim 1, wherein, The virtual partition structure is made of insulating material.

12. The three-dimensional memory according to any one of claims 1-11, wherein, The gate separation structure further includes a first extension that is arranged in parallel with and in direct contact with the first end, and the first end is surrounded by the first extension and the second end together.

13. The three-dimensional memory according to claim 12, wherein, The first extension extends along the first direction.

14. The three-dimensional memory according to claim 12, wherein, At least a portion of the first end portion has a width in a second direction perpendicular to the first direction that is greater than the width of the first extension portion in the second direction.

15. The three-dimensional memory according to claim 14, wherein, The width of the first end in the second direction gradually increases along the first direction from the core area to the step area.

16. The three-dimensional memory according to claim 14, wherein, The width of the first end in the second direction gradually increases and then gradually decreases along the first direction from the core area to the step area.

17. The three-dimensional memory according to any one of claims 1-11, wherein, The first end extends into the stepped area along the first direction.

18. The three-dimensional memory according to any one of claims 1-11, wherein, The maximum width of the first end in the second direction perpendicular to the first direction is not greater than the minimum width of the second end in the second direction.

19. The three-dimensional memory according to any one of claims 1-11, wherein, The gate separation structure includes a conductive structure and an electrically insulating layer located between the conductive structure and the gate stack structure in a second direction perpendicular to the first direction.

20. The three-dimensional memory according to any one of claims 1-11, wherein, The second end includes two clamping sub-parts, and the first end is located between the two clamping sub-parts in a second direction perpendicular to the first direction and is in direct contact with the two clamping sub-parts. The three-dimensional memory further includes: Multiple channel structures located in the core area, the multiple channel structures penetrating the core area in a third direction intersecting the first direction and the second direction; Multiple virtual channel structures are located in the stepped area, and the multiple virtual channel structures penetrate the stepped area in a third direction.

21. The three-dimensional memory according to claim 20, wherein, The virtual partition structure and the gate partition structure penetrate the gate stack structure in the third direction.

22. The three-dimensional memory according to claim 21, wherein, The three-dimensional memory also includes a substrate, the gate stack structure is located on the substrate, and the third direction is perpendicular to the first direction and the second direction.

23. The three-dimensional memory according to any one of claims 1-11, wherein, The virtual partition structure is used to divide the step region into multiple block step regions in a second direction perpendicular to the first direction, and the gate partition structure is used to divide the core region into multiple block core regions in the second direction.

24. A method for fabricating a three-dimensional memory, comprising: A gate stack structure is formed, the gate stack structure including a core region and a step region arranged side by side and in direct contact along a first direction; A virtual partition structure and a gate partition structure are formed. The virtual partition structure penetrates the stepped region in the first direction, and the gate partition structure penetrates the core region in the first direction. The gate partition structure has a first end that contacts the virtual partition structure in the first direction, and the virtual partition structure has a second end that contacts the gate partition structure in the first direction, and the first end is surrounded by the second end.

25. The method for manufacturing a three-dimensional memory according to claim 24, wherein, The formation of the virtual partition structure and the gate partition structure specifically includes: A virtual gate spacer is formed in the stepped region, and the virtual gate spacer penetrates the stepped region in the first direction; Insulating material is filled into the virtual gate spacer to form a virtual partition structure; A gate spacer is formed in the core region and the second end of the virtual partition structure, the gate spacer penetrating the core region and a portion of the second end in the first direction; A gate separation structure is formed in the gate spacer.

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